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authorDave Airlie <airlied@starflyer.(none)>2005-07-30 14:37:43 +1000
committerDave Airlie <airlied@linux.ie>2005-07-30 14:37:43 +1000
commitbdf242eeb0f69567fe43eba93889d80ecacbfe94 (patch)
treedc402eeeb75fd51e92b4f4a63712c6e64ac4c2fb /include/asm-cris/arch-v32/tlb.h
parent836cf0465c422ee6d654060edd7c620d9cf0c09c (diff)
parentb0825488a642cadcf39709961dde61440cb0731c (diff)
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Merge ../linux-2.6/
Diffstat (limited to 'include/asm-cris/arch-v32/tlb.h')
-rw-r--r--include/asm-cris/arch-v32/tlb.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/include/asm-cris/arch-v32/tlb.h b/include/asm-cris/arch-v32/tlb.h
new file mode 100644
index 00000000000..4effb125366
--- /dev/null
+++ b/include/asm-cris/arch-v32/tlb.h
@@ -0,0 +1,14 @@
+#ifndef _CRIS_ARCH_TLB_H
+#define _CRIS_ARCH_TLB_H
+
+/*
+ * The TLB is a 64-entry cache. Each entry has a 8-bit page_id that is used
+ * to store the "process" it belongs to (=> fast mm context switch). The
+ * last page_id is never used so we can make TLB entries that never matches.
+ */
+#define NUM_TLB_ENTRIES 64
+#define NUM_PAGEID 256
+#define INVALID_PAGEID 255
+#define NO_CONTEXT -1
+
+#endif /* _CRIS_ARCH_TLB_H */