diff options
| author | Clifford Wolf <clifford@clifford.at> | 2007-07-17 04:04:06 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-07-17 10:23:04 -0700 |
| commit | 698ca47e8dba93f4b001b06b4c7037b09ac6eb09 (patch) | |
| tree | 2e1f817e847d37b7397171d7fe15dc5ee0a79d07 /drivers | |
| parent | 78961a5740374a8143f8fe120300f2ed160dd276 (diff) | |
| download | kernel-crypto-698ca47e8dba93f4b001b06b4c7037b09ac6eb09.tar.gz kernel-crypto-698ca47e8dba93f4b001b06b4c7037b09ac6eb09.tar.xz kernel-crypto-698ca47e8dba93f4b001b06b4c7037b09ac6eb09.zip | |
spi_mpc83xx.c underclocking hotfix
The MPC83xx SPI controller clock divider can divide the system clock by not
more then 1024. The spi_mpc83xx driver does not check this and silently
writes garbage to the SPI controller registers when asked to run at lower
frequencies. I've tried to run the SPI on a 266MHz MPC8349E with 100kHz
for debugging a bus problem and suddenly was confronted with a 2nd problem
to debug.. ;-)
The patch adds an additional check which avoids writing garbage to the SPI
controller registers and warn the user about it. This might help others to
avoid simmilar problems.
Cc: Kumar Gala <galak@gate.crashing.org>
Cc: David Brownell <david-b@pacbell.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/spi/spi_mpc83xx.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/spi/spi_mpc83xx.c b/drivers/spi/spi_mpc83xx.c index 9cdbc12278e..bbd51bc88a6 100644 --- a/drivers/spi/spi_mpc83xx.c +++ b/drivers/spi/spi_mpc83xx.c @@ -158,6 +158,12 @@ static void mpc83xx_spi_chipselect(struct spi_device *spi, int value) if ((mpc83xx_spi->sysclk / spi->max_speed_hz) >= 64) { u8 pm = mpc83xx_spi->sysclk / (spi->max_speed_hz * 64); + if (pm > 0x0f) { + printk(KERN_WARNING "MPC83xx SPI: SPICLK can't be less then a SYSCLK/1024!\n" + "Requested SPICLK is %d Hz. Will use %d Hz instead.\n", + spi->max_speed_hz, mpc83xx_spi->sysclk / 1024); + pm = 0x0f; + } regval |= SPMODE_PM(pm) | SPMODE_DIV16; } else { u8 pm = mpc83xx_spi->sysclk / (spi->max_speed_hz * 4); |