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authorJesse Brandeburg <jesse.brandeburg@intel.com>2006-11-01 08:47:42 -0800
committerJeff Garzik <jeff@garzik.org>2006-12-02 00:11:59 -0500
commit2ce9047f5d8464039da8ff986e71be5546e229c0 (patch)
tree4e888a376bb97c9688d8ebb70d1ffef144b5529f /drivers
parent21c4d5e07859a6fc0f62be37da15b161e142c8d1 (diff)
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e1000: add mmiowb() for IA64 to sync tail writes
IA64 SMP systems were seeing TX issues with multiple cpu's attempting to write tail registers unordered. This mmiowb() fixes the issue. Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/e1000/e1000_main.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c
index 93b97c6b8a6..681b738c6da 100644
--- a/drivers/net/e1000/e1000_main.c
+++ b/drivers/net/e1000/e1000_main.c
@@ -2867,6 +2867,9 @@ e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
tx_ring->next_to_use = i;
writel(i, adapter->hw.hw_addr + tx_ring->tdt);
+ /* we need this if more than one processor can write to our tail
+ * at a time, it syncronizes IO on IA64/Altix systems */
+ mmiowb();
}
/**