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| author | Hyok S. Choi <hyok.choi@samsung.com> | 2006-09-28 21:46:34 +0900 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-09-28 20:17:30 +0100 |
| commit | 6afd6fae1d5f7e7129a10c4f3e32018966eeac1c (patch) | |
| tree | 4b7470f0f771c4e97b18f83db0bd4ca3d529684b /arch | |
| parent | 0f45d7f36b766cb668cebfb5d4d2f67b4a8676ba (diff) | |
| download | kernel-crypto-6afd6fae1d5f7e7129a10c4f3e32018966eeac1c.tar.gz kernel-crypto-6afd6fae1d5f7e7129a10c4f3e32018966eeac1c.tar.xz kernel-crypto-6afd6fae1d5f7e7129a10c4f3e32018966eeac1c.zip | |
[ARM] nommu: confirms the CR_V bit in nommu mode
In nommu mode, the exception vector location depends on the platforms.
Some of the implementations may have some special exception control
forwarding method in their ROM/flash and for some of them has its own
re-mapping mechanism by the h/w.
This patch introduces a special configuration CONFIG_CPU_HIGH_VECTOR which
turns on the CR_V bit in nommu mode. The CR_V bit is turned off by default.
This feature depends on CP15 and does not supported by ARM740.
Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/Kconfig | 2 | ||||
| -rw-r--r-- | arch/arm/kernel/head-nommu.S | 5 | ||||
| -rw-r--r-- | arch/arm/mm/Kconfig | 12 |
3 files changed, 18 insertions, 1 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2673fee3281..ea7640af0f1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -95,7 +95,7 @@ config ARCH_MTD_XIP config VECTORS_BASE hex - default 0xffff0000 if MMU + default 0xffff0000 if MMU || CPU_HIGH_VECTOR default DRAM_BASE if REMAP_VECTORS_TO_RAM default 0x00000000 help diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S index 698a537915d..f359a189dcf 100644 --- a/arch/arm/kernel/head-nommu.S +++ b/arch/arm/kernel/head-nommu.S @@ -77,6 +77,11 @@ __after_proc_init: #ifdef CONFIG_CPU_ICACHE_DISABLE bic r0, r0, #CR_I #endif +#ifdef CONFIG_CPU_HIGH_VECTOR + orr r0, r0, #CR_V +#else + bic r0, r0, #CR_V +#endif mcr p15, 0, r0, c1, c0, 0 @ write control reg #endif /* CONFIG_CPU_CP15 */ diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 6c1bd424ea6..c0bfb8212b7 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -524,6 +524,18 @@ config CPU_BIG_ENDIAN port must properly enable any big-endian related features of your chipset/board/processor. +config CPU_HIGH_VECTOR + depends !MMU && CPU_CP15 && !CPU_ARM740T + bool "Select the High exception vector" + default n + help + Say Y here to select high exception vector(0xFFFF0000~). + The exception vector can be vary depending on the platform + design in nommu mode. If your platform needs to select + high exception vector, say Y. + Otherwise or if you are unsure, say N, and the low exception + vector (0x00000000~) will be used. + config CPU_ICACHE_DISABLE bool "Disable I-Cache (I-bit)" depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) |