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authorShaohua Li <shaohua.li@intel.com>2006-03-23 02:59:52 -0800
committerLinus Torvalds <torvalds@g5.osdl.org>2006-03-23 07:38:06 -0800
commitf2d0d263b51d13efe55f0aae9254b69ba2855f1c (patch)
treea392ca227a460b22fe90cc5bca73e18e0b70cbdb /arch/mips/tx4927
parent75874d5cc8efef22457072e14103dc55f164e64e (diff)
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[PATCH] x86: cpuid.4 doesn't need cpu level 5
Detecting cache line using cpuid.4, cpuid level 4 is enough. Signed-off-by: Shaohua Li<shaohua.li@intel.com> Cc: Dave Jones <davej@codemonkey.org.uk> Cc: "Seth, Rohit" <rohit.seth@intel.com> Cc: Andi Kleen <ak@muc.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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