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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2009-03-30 14:04:53 +1100 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2009-03-30 14:04:53 +1100 |
| commit | 9ff9a26b786c35ee8d2a66222924a807ec851a9f (patch) | |
| tree | db432a17bccca1ca2c16907f0ee83ac449ed4012 /arch/mips/kernel/traps.c | |
| parent | 0a3108beea9143225119d5e7c72a8e2c64f3eb7d (diff) | |
| parent | 0d34fb8e93ceba7b6dad0062dbb4a0813bacd75b (diff) | |
| download | kernel-crypto-9ff9a26b786c35ee8d2a66222924a807ec851a9f.tar.gz kernel-crypto-9ff9a26b786c35ee8d2a66222924a807ec851a9f.tar.xz kernel-crypto-9ff9a26b786c35ee8d2a66222924a807ec851a9f.zip | |
Merge commit 'origin/master' into next
Manual merge of:
arch/powerpc/include/asm/elf.h
drivers/i2c/busses/i2c-mpc.c
Diffstat (limited to 'arch/mips/kernel/traps.c')
| -rw-r--r-- | arch/mips/kernel/traps.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index b2d7041341b..29fadaccecd 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1520,7 +1520,9 @@ void __cpuinit per_cpu_trap_init(void) #endif /* CONFIG_MIPS_MT_SMTC */ if (cpu_has_veic || cpu_has_vint) { + unsigned long sr = set_c0_status(ST0_BEV); write_c0_ebase(ebase); + write_c0_status(sr); /* Setting vector spacing enables EI/VI mode */ change_c0_intctl(0x3e0, VECTORSPACING); } @@ -1602,8 +1604,6 @@ void __cpuinit set_uncached_handler(unsigned long offset, void *addr, #ifdef CONFIG_64BIT unsigned long uncached_ebase = TO_UNCAC(ebase); #endif - if (cpu_has_mips_r2) - uncached_ebase += (read_c0_ebase() & 0x3ffff000); if (!addr) panic(panic_null_cerr); @@ -1635,9 +1635,11 @@ void __init trap_init(void) return; /* Already done */ #endif - if (cpu_has_veic || cpu_has_vint) - ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); - else { + if (cpu_has_veic || cpu_has_vint) { + unsigned long size = 0x200 + VECTORSPACING*64; + ebase = (unsigned long) + __alloc_bootmem(size, 1 << fls(size), 0); + } else { ebase = CAC_BASE; if (cpu_has_mips_r2) ebase += (read_c0_ebase() & 0x3ffff000); |