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| author | Nicolas Pitre <nico@cam.org> | 2006-02-01 19:26:01 +0000 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-02-01 19:26:01 +0000 |
| commit | 8a052e0bc25ff52f17b3dff150846ca9eb969162 (patch) | |
| tree | 607355bc9ce1ac2d6f5611287cf89fa473d48d02 | |
| parent | 62500d1f8eadff078cca462dc4df035a29180383 (diff) | |
| download | kernel-crypto-8a052e0bc25ff52f17b3dff150846ca9eb969162.tar.gz kernel-crypto-8a052e0bc25ff52f17b3dff150846ca9eb969162.tar.xz kernel-crypto-8a052e0bc25ff52f17b3dff150846ca9eb969162.zip | |
[ARM] 3293/1: don't invalidate the whole I-cache with xscale_coherent_user_range
Patch from Nicolas Pitre
The mini I-cache issue is valid only for kernel space since debuggers
would not fly if they used user space addresses for their stubs.
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| -rw-r--r-- | arch/arm/mm/proc-xscale.S | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 861b3594728..2d3823ec315 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -241,7 +241,15 @@ ENTRY(xscale_flush_user_cache_range) * it also trashes the mini I-cache used by JTAG debuggers. */ ENTRY(xscale_coherent_kern_range) - /* FALLTHROUGH */ + bic r0, r0, #CACHELINESIZE - 1 +1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry + add r0, r0, #CACHELINESIZE + cmp r0, r1 + blo 1b + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB + mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer + mov pc, lr /* * coherent_user_range(start, end) @@ -252,18 +260,16 @@ ENTRY(xscale_coherent_kern_range) * * - start - virtual start address * - end - virtual end address - * - * Note: single I-cache line invalidation isn't used here since - * it also trashes the mini I-cache used by JTAG debuggers. */ ENTRY(xscale_coherent_user_range) bic r0, r0, #CACHELINESIZE - 1 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry + mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry add r0, r0, #CACHELINESIZE cmp r0, r1 blo 1b mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB + mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer mov pc, lr |