diff options
95 files changed, 9132 insertions, 11947 deletions
diff --git a/0001-ideapad-laptop-Change-Lenovo-Yoga-2-series-rfkill-ha.patch b/0001-ideapad-laptop-Change-Lenovo-Yoga-2-series-rfkill-ha.patch deleted file mode 100644 index aab1c4e3..00000000 --- a/0001-ideapad-laptop-Change-Lenovo-Yoga-2-series-rfkill-ha.patch +++ /dev/null @@ -1,138 +0,0 @@ -Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1021036 -Upstream-status: Send upstream for 3.17 - -From 0ad19912cb324f0a356a212433ec0b2a31f61acc Mon Sep 17 00:00:00 2001 -From: Hans de Goede <hdegoede@redhat.com> -Date: Fri, 20 Jun 2014 10:29:16 +0200 -Subject: [PATCH] ideapad-laptop: Change Lenovo Yoga 2 series rfkill handling - -It seems that the same problems which lead to adding an rfkill blacklist and -putting the Lenovo Yoga 2 11 on it are also present on the Lenovo Yoga 2 13 -and Lenovo Yoga 2 Pro too: -https://bugzilla.redhat.com/show_bug.cgi?id=1021036 -https://forums.lenovo.com/t5/Linux-Discussion/Yoga-2-13-not-Pro-Linux-Warning/m-p/1517612 - -Testing has shown that the firmware rfkill settings are persistent over -reboots. So blacklisting the driver is not good enough, if the wifi is blocked -at the firmware level the wifi needs to be explictly unblocked through the -ideapad-laptop interface. - -And at least on the Lenovo Yoga 2 13 the VPCCMD_RF register which on devices -with hardware kill switch reports the hardware switch state, needs to be -explictly set to 1 (radio enabled / not blocked). - -So this patch does 3 things to get proper rfkill handling on these models: - -1) Instead of blacklisting the rfkill functionality, which means that people -with a firmware blocked wifi get stuck in that situation, ignore the value -reported by the not present hardware rfkill switch, as this is what is causing -ideapad-laptop to wrongly report all radios as hardware blocks. But do register -the rfkill interfaces so that the user can soft [un]block them. - -2) On models without a hardware rfkill switch, explictly set VPCCMD_RF to 1 - -3) Drop the " 11" postfix from the dmi match string, as the entire Yoga 2 -series is affected. - -Yoga 2 11: -Reported-and-tested-by: Vincent Gerris <vgerris@gmail.com> - -Yoga 2 13: -Tested-by: madls05 <http://ubuntuforums.org/showthread.php?t=2215044> - -Yoga 2 Pro: -Reported-and-tested-by: Peter F. Patel-Schneider <pfpschneider@gmail.com> - -Signed-off-by: Hans de Goede <hdegoede@redhat.com> ---- - drivers/platform/x86/ideapad-laptop.c | 41 +++++++++++++++++++++++------------ - 1 file changed, 27 insertions(+), 14 deletions(-) - -diff --git a/drivers/platform/x86/ideapad-laptop.c b/drivers/platform/x86/ideapad-laptop.c -index b4c495a..b0e3a2e 100644 ---- a/drivers/platform/x86/ideapad-laptop.c -+++ b/drivers/platform/x86/ideapad-laptop.c -@@ -87,6 +87,7 @@ struct ideapad_private { - struct backlight_device *blightdev; - struct dentry *debug; - unsigned long cfg; -+ bool has_hw_rfkill_switch; - }; - - static bool no_bt_rfkill; -@@ -473,12 +474,14 @@ static struct rfkill_ops ideapad_rfk_ops = { - - static void ideapad_sync_rfk_state(struct ideapad_private *priv) - { -- unsigned long hw_blocked; -+ unsigned long hw_blocked = 0; - int i; - -- if (read_ec_data(priv->adev->handle, VPCCMD_R_RF, &hw_blocked)) -- return; -- hw_blocked = !hw_blocked; -+ if (priv->has_hw_rfkill_switch) { -+ if (read_ec_data(priv->adev->handle, VPCCMD_R_RF, &hw_blocked)) -+ return; -+ hw_blocked = !hw_blocked; -+ } - - for (i = 0; i < IDEAPAD_RFKILL_DEV_NUM; i++) - if (priv->rfk[i]) -@@ -821,14 +824,17 @@ static void ideapad_acpi_notify(acpi_handle handle, u32 event, void *data) - } - } - --/* Blacklist for devices where the ideapad rfkill interface does not work */ --static struct dmi_system_id rfkill_blacklist[] = { -- /* The Lenovo Yoga 2 11 always reports everything as blocked */ -+/* -+ * Some ideapads don't have a hardware rfkill switch, reading VPCCMD_R_RF -+ * always results in 0 on these models, causing ideapad_laptop to wrongly -+ * report all radios as hardware-blocked. -+ */ -+static struct dmi_system_id no_hw_rfkill_list[] = { - { -- .ident = "Lenovo Yoga 2 11", -+ .ident = "Lenovo Yoga 2 11 / 13 / Pro", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), -- DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo Yoga 2 11"), -+ DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo Yoga 2"), - }, - }, - {} -@@ -856,6 +862,7 @@ static int ideapad_acpi_add(struct platform_device *pdev) - priv->cfg = cfg; - priv->adev = adev; - priv->platform_device = pdev; -+ priv->has_hw_rfkill_switch = !dmi_check_system(no_hw_rfkill_list); - - ret = ideapad_sysfs_init(priv); - if (ret) -@@ -869,11 +876,17 @@ static int ideapad_acpi_add(struct platform_device *pdev) - if (ret) - goto input_failed; - -- if (!dmi_check_system(rfkill_blacklist)) { -- for (i = 0; i < IDEAPAD_RFKILL_DEV_NUM; i++) -- if (test_bit(ideapad_rfk_data[i].cfgbit, &priv->cfg)) -- ideapad_register_rfkill(priv, i); -- } -+ /* -+ * On some models without a hw-switch (the yoga 2 13 at least) -+ * VPCCMD_W_RF must be explicitly set to 1 for the wifi to work. -+ */ -+ if (!priv->has_hw_rfkill_switch) -+ write_ec_cmd(priv->adev->handle, VPCCMD_W_RF, 1); -+ -+ for (i = 0; i < IDEAPAD_RFKILL_DEV_NUM; i++) -+ if (test_bit(ideapad_rfk_data[i].cfgbit, &priv->cfg)) -+ ideapad_register_rfkill(priv, i); -+ - ideapad_sync_rfk_state(priv); - ideapad_sync_touchpad_state(priv); - --- -2.0.0 - diff --git a/ACPI-Limit-access-to-custom_method.patch b/ACPI-Limit-access-to-custom_method.patch new file mode 100644 index 00000000..636c25b4 --- /dev/null +++ b/ACPI-Limit-access-to-custom_method.patch @@ -0,0 +1,30 @@ +From: Matthew Garrett <matthew.garrett@nebula.com> +Date: Fri, 9 Mar 2012 08:39:37 -0500 +Subject: [PATCH] ACPI: Limit access to custom_method + +custom_method effectively allows arbitrary access to system memory, making +it possible for an attacker to circumvent restrictions on module loading. +Disable it if any such restrictions have been enabled. + +Signed-off-by: Matthew Garrett <matthew.garrett@nebula.com> +--- + drivers/acpi/custom_method.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/acpi/custom_method.c b/drivers/acpi/custom_method.c +index c68e72414a67..4277938af700 100644 +--- a/drivers/acpi/custom_method.c ++++ b/drivers/acpi/custom_method.c +@@ -29,6 +29,9 @@ static ssize_t cm_write(struct file *file, const char __user * user_buf, + struct acpi_table_header table; + acpi_status status; + ++ if (secure_modules()) ++ return -EPERM; ++ + if (!(*ppos)) { + /* parse the table header to get the table length */ + if (count <= sizeof(struct acpi_table_header)) +-- +1.9.3 + diff --git a/ARM-tegra-usb-no-reset.patch b/ARM-tegra-usb-no-reset.patch new file mode 100644 index 00000000..2f3dd687 --- /dev/null +++ b/ARM-tegra-usb-no-reset.patch @@ -0,0 +1,31 @@ +From: Peter Robinson <pbrobinson@gmail.com> +Date: Thu, 3 May 2012 20:27:11 +0100 +Subject: [PATCH] ARM: tegra: usb no reset + +Patch for disconnect issues with storage attached to a + tegra-ehci controller +--- + drivers/usb/core/hub.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c +index d481c99a20d7..6050143ce7ec 100644 +--- a/drivers/usb/core/hub.c ++++ b/drivers/usb/core/hub.c +@@ -5036,6 +5036,13 @@ static void hub_events(void) + (u16) hub->change_bits[0], + (u16) hub->event_bits[0]); + ++ /* Don't disconnect USB-SATA on TrimSlice */ ++ if (strcmp(dev_name(hdev->bus->controller), "tegra-ehci.0") == 0) { ++ if ((hdev->state == 7) && (hub->change_bits[0] == 0) && ++ (hub->event_bits[0] == 0x2)) ++ hub->event_bits[0] = 0; ++ } ++ + /* Lock the device, then check to see if we were + * disconnected while waiting for the lock to succeed. */ + usb_lock_device(hdev); +-- +1.9.3 + diff --git a/Add-EFI-signature-data-types.patch b/Add-EFI-signature-data-types.patch new file mode 100644 index 00000000..b6df877a --- /dev/null +++ b/Add-EFI-signature-data-types.patch @@ -0,0 +1,56 @@ +From: Dave Howells <dhowells@redhat.com> +Date: Tue, 23 Oct 2012 09:30:54 -0400 +Subject: [PATCH] Add EFI signature data types + +Add the data types that are used for containing hashes, keys and certificates +for cryptographic verification. + +Bugzilla: N/A +Upstream-status: Fedora mustard for now + +Signed-off-by: David Howells <dhowells@redhat.com> +--- + include/linux/efi.h | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/include/linux/efi.h b/include/linux/efi.h +index ebe6a24cc1e1..5ce40e215f15 100644 +--- a/include/linux/efi.h ++++ b/include/linux/efi.h +@@ -581,6 +581,12 @@ void efi_native_runtime_setup(void); + #define DEVICE_TREE_GUID \ + EFI_GUID( 0xb1b621d5, 0xf19c, 0x41a5, 0x83, 0x0b, 0xd9, 0x15, 0x2c, 0x69, 0xaa, 0xe0 ) + ++#define EFI_CERT_SHA256_GUID \ ++ EFI_GUID( 0xc1c41626, 0x504c, 0x4092, 0xac, 0xa9, 0x41, 0xf9, 0x36, 0x93, 0x43, 0x28 ) ++ ++#define EFI_CERT_X509_GUID \ ++ EFI_GUID( 0xa5c059a1, 0x94e4, 0x4aa7, 0x87, 0xb5, 0xab, 0x15, 0x5c, 0x2b, 0xf0, 0x72 ) ++ + typedef struct { + efi_guid_t guid; + u64 table; +@@ -796,6 +802,20 @@ typedef struct _efi_file_io_interface { + + #define EFI_INVALID_TABLE_ADDR (~0UL) + ++typedef struct { ++ efi_guid_t signature_owner; ++ u8 signature_data[]; ++} efi_signature_data_t; ++ ++typedef struct { ++ efi_guid_t signature_type; ++ u32 signature_list_size; ++ u32 signature_header_size; ++ u32 signature_size; ++ u8 signature_header[]; ++ /* efi_signature_data_t signatures[][] */ ++} efi_signature_list_t; ++ + /* + * All runtime access to EFI goes through this structure: + */ +-- +1.9.3 + diff --git a/Add-an-EFI-signature-blob-parser-and-key-loader.patch b/Add-an-EFI-signature-blob-parser-and-key-loader.patch new file mode 100644 index 00000000..e78b065c --- /dev/null +++ b/Add-an-EFI-signature-blob-parser-and-key-loader.patch @@ -0,0 +1,178 @@ +From: Dave Howells <dhowells@redhat.com> +Date: Tue, 23 Oct 2012 09:36:28 -0400 +Subject: [PATCH] Add an EFI signature blob parser and key loader. + +X.509 certificates are loaded into the specified keyring as asymmetric type +keys. + +Signed-off-by: David Howells <dhowells@redhat.com> +--- + crypto/asymmetric_keys/Kconfig | 8 +++ + crypto/asymmetric_keys/Makefile | 1 + + crypto/asymmetric_keys/efi_parser.c | 109 ++++++++++++++++++++++++++++++++++++ + include/linux/efi.h | 4 ++ + 4 files changed, 122 insertions(+) + create mode 100644 crypto/asymmetric_keys/efi_parser.c + +diff --git a/crypto/asymmetric_keys/Kconfig b/crypto/asymmetric_keys/Kconfig +index 4870f28403f5..4a1b50d73b80 100644 +--- a/crypto/asymmetric_keys/Kconfig ++++ b/crypto/asymmetric_keys/Kconfig +@@ -67,4 +67,12 @@ config SIGNED_PE_FILE_VERIFICATION + This option provides support for verifying the signature(s) on a + signed PE binary. + ++config EFI_SIGNATURE_LIST_PARSER ++ bool "EFI signature list parser" ++ depends on EFI ++ select X509_CERTIFICATE_PARSER ++ help ++ This option provides support for parsing EFI signature lists for ++ X.509 certificates and turning them into keys. ++ + endif # ASYMMETRIC_KEY_TYPE +diff --git a/crypto/asymmetric_keys/Makefile b/crypto/asymmetric_keys/Makefile +index e47fcd9ac5e8..6512f6596785 100644 +--- a/crypto/asymmetric_keys/Makefile ++++ b/crypto/asymmetric_keys/Makefile +@@ -8,6 +8,7 @@ asymmetric_keys-y := asymmetric_type.o signature.o + + obj-$(CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE) += public_key.o + obj-$(CONFIG_PUBLIC_KEY_ALGO_RSA) += rsa.o ++obj-$(CONFIG_EFI_SIGNATURE_LIST_PARSER) += efi_parser.o + + # + # X.509 Certificate handling +diff --git a/crypto/asymmetric_keys/efi_parser.c b/crypto/asymmetric_keys/efi_parser.c +new file mode 100644 +index 000000000000..424896a0b169 +--- /dev/null ++++ b/crypto/asymmetric_keys/efi_parser.c +@@ -0,0 +1,109 @@ ++/* EFI signature/key/certificate list parser ++ * ++ * Copyright (C) 2012 Red Hat, Inc. All Rights Reserved. ++ * Written by David Howells (dhowells@redhat.com) ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public Licence ++ * as published by the Free Software Foundation; either version ++ * 2 of the Licence, or (at your option) any later version. ++ */ ++ ++#define pr_fmt(fmt) "EFI: "fmt ++#include <linux/module.h> ++#include <linux/printk.h> ++#include <linux/err.h> ++#include <linux/efi.h> ++#include <keys/asymmetric-type.h> ++ ++static __initdata efi_guid_t efi_cert_x509_guid = EFI_CERT_X509_GUID; ++ ++/** ++ * parse_efi_signature_list - Parse an EFI signature list for certificates ++ * @data: The data blob to parse ++ * @size: The size of the data blob ++ * @keyring: The keyring to add extracted keys to ++ */ ++int __init parse_efi_signature_list(const void *data, size_t size, struct key *keyring) ++{ ++ unsigned offs = 0; ++ size_t lsize, esize, hsize, elsize; ++ ++ pr_devel("-->%s(,%zu)\n", __func__, size); ++ ++ while (size > 0) { ++ efi_signature_list_t list; ++ const efi_signature_data_t *elem; ++ key_ref_t key; ++ ++ if (size < sizeof(list)) ++ return -EBADMSG; ++ ++ memcpy(&list, data, sizeof(list)); ++ pr_devel("LIST[%04x] guid=%pUl ls=%x hs=%x ss=%x\n", ++ offs, ++ list.signature_type.b, list.signature_list_size, ++ list.signature_header_size, list.signature_size); ++ ++ lsize = list.signature_list_size; ++ hsize = list.signature_header_size; ++ esize = list.signature_size; ++ elsize = lsize - sizeof(list) - hsize; ++ ++ if (lsize > size) { ++ pr_devel("<--%s() = -EBADMSG [overrun @%x]\n", ++ __func__, offs); ++ return -EBADMSG; ++ } ++ if (lsize < sizeof(list) || ++ lsize - sizeof(list) < hsize || ++ esize < sizeof(*elem) || ++ elsize < esize || ++ elsize % esize != 0) { ++ pr_devel("- bad size combo @%x\n", offs); ++ return -EBADMSG; ++ } ++ ++ if (efi_guidcmp(list.signature_type, efi_cert_x509_guid) != 0) { ++ data += lsize; ++ size -= lsize; ++ offs += lsize; ++ continue; ++ } ++ ++ data += sizeof(list) + hsize; ++ size -= sizeof(list) + hsize; ++ offs += sizeof(list) + hsize; ++ ++ for (; elsize > 0; elsize -= esize) { ++ elem = data; ++ ++ pr_devel("ELEM[%04x]\n", offs); ++ ++ key = key_create_or_update( ++ make_key_ref(keyring, 1), ++ "asymmetric", ++ NULL, ++ &elem->signature_data, ++ esize - sizeof(*elem), ++ (KEY_POS_ALL & ~KEY_POS_SETATTR) | ++ KEY_USR_VIEW, ++ KEY_ALLOC_NOT_IN_QUOTA | ++ KEY_ALLOC_TRUSTED); ++ ++ if (IS_ERR(key)) ++ pr_err("Problem loading in-kernel X.509 certificate (%ld)\n", ++ PTR_ERR(key)); ++ else ++ pr_notice("Loaded cert '%s' linked to '%s'\n", ++ key_ref_to_ptr(key)->description, ++ keyring->description); ++ ++ data += esize; ++ size -= esize; ++ offs += esize; ++ } ++ } ++ ++ return 0; ++} +diff --git a/include/linux/efi.h b/include/linux/efi.h +index 5ce40e215f15..41359e548bcb 100644 +--- a/include/linux/efi.h ++++ b/include/linux/efi.h +@@ -906,6 +906,10 @@ extern bool efi_poweroff_required(void); + (md) <= (efi_memory_desc_t *)((m)->map_end - (m)->desc_size); \ + (md) = (void *)(md) + (m)->desc_size) + ++struct key; ++extern int __init parse_efi_signature_list(const void *data, size_t size, ++ struct key *keyring); ++ + /** + * efi_range_is_wc - check the WC bit on an address range + * @start: starting kvirt address +-- +1.9.3 + diff --git a/Add-option-to-automatically-enforce-module-signature.patch b/Add-option-to-automatically-enforce-module-signature.patch new file mode 100644 index 00000000..8e2789aa --- /dev/null +++ b/Add-option-to-automatically-enforce-module-signature.patch @@ -0,0 +1,185 @@ +From: Matthew Garrett <matthew.garrett@nebula.com> +Date: Fri, 9 Aug 2013 18:36:30 -0400 +Subject: [PATCH] Add option to automatically enforce module signatures when in + Secure Boot mode + +UEFI Secure Boot provides a mechanism for ensuring that the firmware will +only load signed bootloaders and kernels. Certain use cases may also +require that all kernel modules also be signed. Add a configuration option +that enforces this automatically when enabled. + +Signed-off-by: Matthew Garrett <matthew.garrett@nebula.com> +--- + Documentation/x86/zero-page.txt | 2 ++ + arch/x86/Kconfig | 10 ++++++++++ + arch/x86/boot/compressed/eboot.c | 36 +++++++++++++++++++++++++++++++++++ + arch/x86/include/uapi/asm/bootparam.h | 3 ++- + arch/x86/kernel/setup.c | 6 ++++++ + include/linux/module.h | 6 ++++++ + kernel/module.c | 7 +++++++ + 7 files changed, 69 insertions(+), 1 deletion(-) + +diff --git a/Documentation/x86/zero-page.txt b/Documentation/x86/zero-page.txt +index 199f453cb4de..ec38acf00b40 100644 +--- a/Documentation/x86/zero-page.txt ++++ b/Documentation/x86/zero-page.txt +@@ -30,6 +30,8 @@ Offset Proto Name Meaning + 1E9/001 ALL eddbuf_entries Number of entries in eddbuf (below) + 1EA/001 ALL edd_mbr_sig_buf_entries Number of entries in edd_mbr_sig_buffer + (below) ++1EB/001 ALL kbd_status Numlock is enabled ++1EC/001 ALL secure_boot Secure boot is enabled in the firmware + 1EF/001 ALL sentinel Used to detect broken bootloaders + 290/040 ALL edd_mbr_sig_buffer EDD MBR signatures + 2D0/A00 ALL e820_map E820 memory map table +diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig +index 36327438caf0..61542c282e70 100644 +--- a/arch/x86/Kconfig ++++ b/arch/x86/Kconfig +@@ -1566,6 +1566,16 @@ config EFI_MIXED + + If unsure, say N. + ++config EFI_SECURE_BOOT_SIG_ENFORCE ++ def_bool n ++ prompt "Force module signing when UEFI Secure Boot is enabled" ++ ---help--- ++ UEFI Secure Boot provides a mechanism for ensuring that the ++ firmware will only load signed bootloaders and kernels. Certain ++ use cases may also require that all kernel modules also be signed. ++ Say Y here to automatically enable module signature enforcement ++ when a system boots with UEFI Secure Boot enabled. ++ + config SECCOMP + def_bool y + prompt "Enable seccomp to safely compute untrusted bytecode" +diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c +index de8eebd6f67c..975d11bfaf5b 100644 +--- a/arch/x86/boot/compressed/eboot.c ++++ b/arch/x86/boot/compressed/eboot.c +@@ -12,6 +12,7 @@ + #include <asm/efi.h> + #include <asm/setup.h> + #include <asm/desc.h> ++#include <asm/bootparam_utils.h> + + #undef memcpy /* Use memcpy from misc.c */ + +@@ -814,6 +815,37 @@ out: + return status; + } + ++static int get_secure_boot(void) ++{ ++ u8 sb, setup; ++ unsigned long datasize = sizeof(sb); ++ efi_guid_t var_guid = EFI_GLOBAL_VARIABLE_GUID; ++ efi_status_t status; ++ ++ status = efi_early->call((unsigned long)sys_table->runtime->get_variable, ++ L"SecureBoot", &var_guid, NULL, &datasize, &sb); ++ ++ if (status != EFI_SUCCESS) ++ return 0; ++ ++ if (sb == 0) ++ return 0; ++ ++ ++ status = efi_early->call((unsigned long)sys_table->runtime->get_variable, ++ L"SetupMode", &var_guid, NULL, &datasize, ++ &setup); ++ ++ if (status != EFI_SUCCESS) ++ return 0; ++ ++ if (setup == 1) ++ return 0; ++ ++ return 1; ++} ++ ++ + /* + * See if we have Graphics Output Protocol + */ +@@ -1389,6 +1421,10 @@ struct boot_params *efi_main(struct efi_config *c, + else + setup_boot_services32(efi_early); + ++ sanitize_boot_params(boot_params); ++ ++ boot_params->secure_boot = get_secure_boot(); ++ + setup_graphics(boot_params); + + setup_efi_pci(boot_params); +diff --git a/arch/x86/include/uapi/asm/bootparam.h b/arch/x86/include/uapi/asm/bootparam.h +index 225b0988043a..90dbfb73e11f 100644 +--- a/arch/x86/include/uapi/asm/bootparam.h ++++ b/arch/x86/include/uapi/asm/bootparam.h +@@ -133,7 +133,8 @@ struct boot_params { + __u8 eddbuf_entries; /* 0x1e9 */ + __u8 edd_mbr_sig_buf_entries; /* 0x1ea */ + __u8 kbd_status; /* 0x1eb */ +- __u8 _pad5[3]; /* 0x1ec */ ++ __u8 secure_boot; /* 0x1ec */ ++ __u8 _pad5[2]; /* 0x1ed */ + /* + * The sentinel is set to a nonzero value (0xff) in header.S. + * +diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c +index 41ead8d3bc0b..5a5cf7395724 100644 +--- a/arch/x86/kernel/setup.c ++++ b/arch/x86/kernel/setup.c +@@ -1142,6 +1142,12 @@ void __init setup_arch(char **cmdline_p) + + io_delay_init(); + ++#ifdef CONFIG_EFI_SECURE_BOOT_SIG_ENFORCE ++ if (boot_params.secure_boot) { ++ enforce_signed_modules(); ++ } ++#endif ++ + /* + * Parse the ACPI tables for possible boot-time SMP configuration. + */ +diff --git a/include/linux/module.h b/include/linux/module.h +index 341a73ecea2e..cca08ac450e2 100644 +--- a/include/linux/module.h ++++ b/include/linux/module.h +@@ -188,6 +188,12 @@ const struct exception_table_entry *search_exception_tables(unsigned long add); + + struct notifier_block; + ++#ifdef CONFIG_MODULE_SIG ++extern void enforce_signed_modules(void); ++#else ++static inline void enforce_signed_modules(void) {}; ++#endif ++ + #ifdef CONFIG_MODULES + + extern int modules_disabled; /* for sysctl */ +diff --git a/kernel/module.c b/kernel/module.c +index 1f7b4664300e..866417ecc76a 100644 +--- a/kernel/module.c ++++ b/kernel/module.c +@@ -3843,6 +3843,13 @@ void module_layout(struct module *mod, + EXPORT_SYMBOL(module_layout); + #endif + ++#ifdef CONFIG_MODULE_SIG ++void enforce_signed_modules(void) ++{ ++ sig_enforce = true; ++} ++#endif ++ + bool secure_modules(void) + { + #ifdef CONFIG_MODULE_SIG +-- +1.9.3 + diff --git a/Add-secure_modules-call.patch b/Add-secure_modules-call.patch new file mode 100644 index 00000000..ecf5b894 --- /dev/null +++ b/Add-secure_modules-call.patch @@ -0,0 +1,63 @@ +From: Matthew Garrett <matthew.garrett@nebula.com> +Date: Fri, 9 Aug 2013 17:58:15 -0400 +Subject: [PATCH] Add secure_modules() call + +Provide a single call to allow kernel code to determine whether the system +has been configured to either disable module loading entirely or to load +only modules signed with a trusted key. + +Bugzilla: N/A +Upstream-status: Fedora mustard. Replaced by securelevels, but that was nak'd + +Signed-off-by: Matthew Garrett <matthew.garrett@nebula.com> +--- + include/linux/module.h | 7 +++++++ + kernel/module.c | 10 ++++++++++ + 2 files changed, 17 insertions(+) + +diff --git a/include/linux/module.h b/include/linux/module.h +index 71f282a4e307..341a73ecea2e 100644 +--- a/include/linux/module.h ++++ b/include/linux/module.h +@@ -516,6 +516,8 @@ int unregister_module_notifier(struct notifier_block *nb); + + extern void print_modules(void); + ++extern bool secure_modules(void); ++ + #else /* !CONFIG_MODULES... */ + + /* Given an address, look for it in the exception tables. */ +@@ -626,6 +628,11 @@ static inline int unregister_module_notifier(struct notifier_block *nb) + static inline void print_modules(void) + { + } ++ ++static inline bool secure_modules(void) ++{ ++ return false; ++} + #endif /* CONFIG_MODULES */ + + #ifdef CONFIG_SYSFS +diff --git a/kernel/module.c b/kernel/module.c +index 03214bd288e9..1f7b4664300e 100644 +--- a/kernel/module.c ++++ b/kernel/module.c +@@ -3842,3 +3842,13 @@ void module_layout(struct module *mod, + } + EXPORT_SYMBOL(module_layout); + #endif ++ ++bool secure_modules(void) ++{ ++#ifdef CONFIG_MODULE_SIG ++ return (sig_enforce || modules_disabled); ++#else ++ return modules_disabled; ++#endif ++} ++EXPORT_SYMBOL(secure_modules); +-- +1.9.3 + diff --git a/sysrq-secure-boot.patch b/Add-sysrq-option-to-disable-secure-boot-mode.patch index 1b139934..414fe6e3 100644 --- a/sysrq-secure-boot.patch +++ b/Add-sysrq-option-to-disable-secure-boot-mode.patch @@ -1,11 +1,9 @@ -Bugzilla: N/A -Upstream-status: Fedora mustard - -From 603230771bdbca78e6530d29dbe8b239cdcc8473 Mon Sep 17 00:00:00 2001 From: Kyle McMartin <kyle@redhat.com> Date: Fri, 30 Aug 2013 09:28:51 -0400 Subject: [PATCH] Add sysrq option to disable secure boot mode +Bugzilla: N/A +Upstream-status: Fedora mustard --- arch/x86/kernel/setup.c | 36 ++++++++++++++++++++++++++++++++++++ drivers/input/misc/uinput.c | 1 + @@ -17,7 +15,7 @@ Subject: [PATCH] Add sysrq option to disable secure boot mode 7 files changed, 65 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c -index 5ce785fc9f05..2024cbb7169b 100644 +index fb282ff6a802..d291d16ba257 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -70,6 +70,11 @@ @@ -71,10 +69,10 @@ index 5ce785fc9f05..2024cbb7169b 100644 .notifier_call = dump_kernel_offset }; diff --git a/drivers/input/misc/uinput.c b/drivers/input/misc/uinput.c -index 856936247500..1e87a1ea704b 100644 +index 421e29e4cd81..61c1eb97806c 100644 --- a/drivers/input/misc/uinput.c +++ b/drivers/input/misc/uinput.c -@@ -353,6 +353,7 @@ static int uinput_allocate_device(struct uinput_device *udev) +@@ -366,6 +366,7 @@ static int uinput_allocate_device(struct uinput_device *udev) if (!udev->dev) return -ENOMEM; @@ -83,7 +81,7 @@ index 856936247500..1e87a1ea704b 100644 input_set_drvdata(udev->dev, udev); diff --git a/drivers/tty/sysrq.c b/drivers/tty/sysrq.c -index 454b65898e2c..19d67594a3b8 100644 +index 42bad18c66c9..496e073b09d7 100644 --- a/drivers/tty/sysrq.c +++ b/drivers/tty/sysrq.c @@ -463,6 +463,7 @@ static struct sysrq_key_op *sysrq_key_table[36] = { @@ -217,7 +215,7 @@ index 387fa7d05c98..4b07e30b3279 100644 int unregister_sysrq_key(int key, struct sysrq_key_op *op); struct sysrq_key_op *__sysrq_get_key_op(int key); diff --git a/kernel/debug/kdb/kdb_main.c b/kernel/debug/kdb/kdb_main.c -index 2f7c760305ca..abb29d9811af 100644 +index 379650b984f8..070f29fefdc2 100644 --- a/kernel/debug/kdb/kdb_main.c +++ b/kernel/debug/kdb/kdb_main.c @@ -1924,7 +1924,7 @@ static int kdb_sr(int argc, const char **argv) @@ -230,10 +228,10 @@ index 2f7c760305ca..abb29d9811af 100644 return 0; diff --git a/kernel/module.c b/kernel/module.c -index 452079124fb7..37dabbc1e902 100644 +index 866417ecc76a..d7ca95c5a349 100644 --- a/kernel/module.c +++ b/kernel/module.c -@@ -109,9 +109,9 @@ struct list_head *kdb_modules = &modules; /* kdb needs the list of modules */ +@@ -108,9 +108,9 @@ struct list_head *kdb_modules = &modules; /* kdb needs the list of modules */ #ifdef CONFIG_MODULE_SIG #ifdef CONFIG_MODULE_SIG_FORCE diff --git a/HID-i2c-hid-call-the-hid-driver-s-suspend-and-resume.patch b/HID-i2c-hid-call-the-hid-driver-s-suspend-and-resume.patch deleted file mode 100644 index 9fdc11b7..00000000 --- a/HID-i2c-hid-call-the-hid-driver-s-suspend-and-resume.patch +++ /dev/null @@ -1,76 +0,0 @@ -From 109571cf3ec78a39477eedd6b11927f52cbcb1e8 Mon Sep 17 00:00:00 2001 -From: Andrew Duggan <aduggan@synaptics.com> -Date: Fri, 11 Jul 2014 16:34:18 -0700 -Subject: [PATCH] HID: i2c-hid: call the hid driver's suspend and resume - callbacks - -Currently, the i2c-hid driver does not call the suspend, resume, and -reset_resume callbacks in the hid_driver struct when those events occur. -This means that HID drivers for i2c-hid devices will not be able to execute -commands which may be needed during suspend or resume. One example is when a -touchpad using the hid-multitouch driver gets reset by i2c-hid coming out of -resume. Since the reset_resume callback never gets called the device is never -put back into the correct input mode. This patch calls the suspend and resume -callbacks and tries to duplicate the functionality of the usb-hid driver. - -Bugzilla: 1143812 -Upstream-status: 3.17 - -Signed-off-by: Andrew Duggan <aduggan@synaptics.com> -Signed-off-by: Vincent Huang <vincent.huang@tw.synaptics.com> -Reviewed-by: Benjamin Tissoires <benjamin.tissoires@redhat.com> -Signed-off-by: Jiri Kosina <jkosina@suse.cz> ---- - drivers/hid/i2c-hid/i2c-hid.c | 15 ++++++++++++++- - 1 file changed, 14 insertions(+), 1 deletion(-) - -diff --git a/drivers/hid/i2c-hid/i2c-hid.c b/drivers/hid/i2c-hid/i2c-hid.c -index 21aafc8f48c8..747d54421e73 100644 ---- a/drivers/hid/i2c-hid/i2c-hid.c -+++ b/drivers/hid/i2c-hid/i2c-hid.c -@@ -1054,21 +1054,29 @@ static int i2c_hid_remove(struct i2c_client *client) - static int i2c_hid_suspend(struct device *dev) - { - struct i2c_client *client = to_i2c_client(dev); -+ struct i2c_hid *ihid = i2c_get_clientdata(client); -+ struct hid_device *hid = ihid->hid; -+ int ret = 0; - - disable_irq(client->irq); - if (device_may_wakeup(&client->dev)) - enable_irq_wake(client->irq); - -+ if (hid->driver && hid->driver->suspend) -+ ret = hid->driver->suspend(hid, PMSG_SUSPEND); -+ - /* Save some power */ - i2c_hid_set_power(client, I2C_HID_PWR_SLEEP); - -- return 0; -+ return ret; - } - - static int i2c_hid_resume(struct device *dev) - { - int ret; - struct i2c_client *client = to_i2c_client(dev); -+ struct i2c_hid *ihid = i2c_get_clientdata(client); -+ struct hid_device *hid = ihid->hid; - - enable_irq(client->irq); - ret = i2c_hid_hwreset(client); -@@ -1078,6 +1086,11 @@ static int i2c_hid_resume(struct device *dev) - if (device_may_wakeup(&client->dev)) - disable_irq_wake(client->irq); - -+ if (hid->driver && hid->driver->reset_resume) { -+ ret = hid->driver->reset_resume(hid); -+ return ret; -+ } -+ - return 0; - } - #endif --- -2.1.0 - diff --git a/HID-magicmouse-sanity-check-report-size-in-raw_event.patch b/HID-magicmouse-sanity-check-report-size-in-raw_event.patch deleted file mode 100644 index 32863aff..00000000 --- a/HID-magicmouse-sanity-check-report-size-in-raw_event.patch +++ /dev/null @@ -1,51 +0,0 @@ -From c54def7bd64d7c0b6993336abcffb8444795bf38 Mon Sep 17 00:00:00 2001 -From: Jiri Kosina <jkosina@suse.cz> -Date: Wed, 27 Aug 2014 09:12:24 +0200 -Subject: [PATCH] HID: magicmouse: sanity check report size in raw_event() - callback - -The report passed to us from transport driver could potentially be -arbitrarily large, therefore we better sanity-check it so that -magicmouse_emit_touch() gets only valid values of raw_id. - -Bugzilla: 1141179 -Upstream-status: 3.17 and CC'd stable - -Cc: stable@vger.kernel.org -Reported-by: Steven Vittitoe <scvitti@google.com> -Signed-off-by: Jiri Kosina <jkosina@suse.cz> ---- - drivers/hid/hid-magicmouse.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/drivers/hid/hid-magicmouse.c b/drivers/hid/hid-magicmouse.c -index ecc2cbf300cc..29a74c1efcb8 100644 ---- a/drivers/hid/hid-magicmouse.c -+++ b/drivers/hid/hid-magicmouse.c -@@ -290,6 +290,11 @@ static int magicmouse_raw_event(struct hid_device *hdev, - if (size < 4 || ((size - 4) % 9) != 0) - return 0; - npoints = (size - 4) / 9; -+ if (npoints > 15) { -+ hid_warn(hdev, "invalid size value (%d) for TRACKPAD_REPORT_ID\n", -+ size); -+ return 0; -+ } - msc->ntouches = 0; - for (ii = 0; ii < npoints; ii++) - magicmouse_emit_touch(msc, ii, data + ii * 9 + 4); -@@ -307,6 +312,11 @@ static int magicmouse_raw_event(struct hid_device *hdev, - if (size < 6 || ((size - 6) % 8) != 0) - return 0; - npoints = (size - 6) / 8; -+ if (npoints > 15) { -+ hid_warn(hdev, "invalid size value (%d) for MOUSE_REPORT_ID\n", -+ size); -+ return 0; -+ } - msc->ntouches = 0; - for (ii = 0; ii < npoints; ii++) - magicmouse_emit_touch(msc, ii, data + ii * 8 + 6); --- -2.1.0 - diff --git a/HID-picolcd-sanity-check-report-size-in-raw_event-ca.patch b/HID-picolcd-sanity-check-report-size-in-raw_event-ca.patch deleted file mode 100644 index 456d91c9..00000000 --- a/HID-picolcd-sanity-check-report-size-in-raw_event-ca.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 844817e47eef14141cf59b8d5ac08dd11c0a9189 Mon Sep 17 00:00:00 2001 -From: Jiri Kosina <jkosina@suse.cz> -Date: Wed, 27 Aug 2014 09:13:15 +0200 -Subject: [PATCH] HID: picolcd: sanity check report size in raw_event() - callback - -The report passed to us from transport driver could potentially be -arbitrarily large, therefore we better sanity-check it so that raw_data -that we hold in picolcd_pending structure are always kept within proper -bounds. - -Bugzilla: 1141410 -Upstream-status: 3.17 and CC'd to stable - -Cc: stable@vger.kernel.org -Reported-by: Steven Vittitoe <scvitti@google.com> -Signed-off-by: Jiri Kosina <jkosina@suse.cz> ---- - drivers/hid/hid-picolcd_core.c | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/drivers/hid/hid-picolcd_core.c b/drivers/hid/hid-picolcd_core.c -index acbb021065ec..020df3c2e8b4 100644 ---- a/drivers/hid/hid-picolcd_core.c -+++ b/drivers/hid/hid-picolcd_core.c -@@ -350,6 +350,12 @@ static int picolcd_raw_event(struct hid_device *hdev, - if (!data) - return 1; - -+ if (size > 64) { -+ hid_warn(hdev, "invalid size value (%d) for picolcd raw event\n", -+ size); -+ return 0; -+ } -+ - if (report->id == REPORT_KEY_STATE) { - if (data->input_keys) - ret = picolcd_raw_keypad(data, report, raw_data+1, size-1); --- -2.1.0 - diff --git a/HID-wacom-Add-support-for-the-Cintiq-Companion.patch b/HID-wacom-Add-support-for-the-Cintiq-Companion.patch new file mode 100644 index 00000000..276fa103 --- /dev/null +++ b/HID-wacom-Add-support-for-the-Cintiq-Companion.patch @@ -0,0 +1,46 @@ +From: Benjamin Tissoires <benjamin.tissoires@redhat.com> +Date: Wed, 3 Sep 2014 15:43:25 -0400 +Subject: [PATCH] HID: wacom: Add support for the Cintiq Companion + +The Wacom Cintiq Companion shares the same sensor than the Cintiq +Companion Hybrid, with the exception of the different PIDs. + +Bugzilla: 1134969 +Upstream-status: Queued for 3.18 + +Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com> +--- + drivers/hid/wacom_wac.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/drivers/hid/wacom_wac.c b/drivers/hid/wacom_wac.c +index aa6a08eb7ad6..c3cbbfb5811f 100644 +--- a/drivers/hid/wacom_wac.c ++++ b/drivers/hid/wacom_wac.c +@@ -2573,6 +2573,14 @@ static const struct wacom_features wacom_features_0x309 = + { "Wacom ISDv5 309", .type = WACOM_24HDT, /* Touch */ + .oVid = USB_VENDOR_ID_WACOM, .oPid = 0x0307, .touch_max = 10, + .check_for_hid_type = true, .hid_type = HID_TYPE_USBNONE }; ++static const struct wacom_features wacom_features_0x30A = ++ { "Wacom ISDv5 30A", 59352, 33648, 2047, 63, ++ CINTIQ_HYBRID, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES, 200, 200, ++ .oVid = USB_VENDOR_ID_WACOM, .oPid = 0x30C }; ++static const struct wacom_features wacom_features_0x30C = ++ { "Wacom ISDv5 30C", .type = WACOM_24HDT, /* Touch */ ++ .oVid = USB_VENDOR_ID_WACOM, .oPid = 0x30A, .touch_max = 10, ++ .check_for_hid_type = true, .hid_type = HID_TYPE_USBNONE }; + + #define USB_DEVICE_WACOM(prod) \ + HID_DEVICE(BUS_USB, HID_GROUP_WACOM, USB_VENDOR_ID_WACOM, prod),\ +@@ -2708,6 +2716,8 @@ const struct hid_device_id wacom_ids[] = { + { USB_DEVICE_WACOM(0x304) }, + { USB_DEVICE_WACOM(0x307) }, + { USB_DEVICE_WACOM(0x309) }, ++ { USB_DEVICE_WACOM(0x30A) }, ++ { USB_DEVICE_WACOM(0x30C) }, + { USB_DEVICE_WACOM(0x30E) }, + { USB_DEVICE_WACOM(0x314) }, + { USB_DEVICE_WACOM(0x315) }, +-- +1.9.3 + diff --git a/Input-wacom-Add-support-for-the-Cintiq-Companion.patch b/Input-wacom-Add-support-for-the-Cintiq-Companion.patch deleted file mode 100644 index 33691ccf..00000000 --- a/Input-wacom-Add-support-for-the-Cintiq-Companion.patch +++ /dev/null @@ -1,46 +0,0 @@ -From bdfffc320102278edac2db5a397ffbfd89faeab3 Mon Sep 17 00:00:00 2001 -From: Benjamin Tissoires <benjamin.tissoires@redhat.com> -Date: Wed, 3 Sep 2014 15:43:25 -0400 -Subject: [PATCH] Input: wacom: Add support for the Cintiq Companion - -The Wacom Cintiq Companion shares the same sensor than the Cintiq -Companion Hybrid, with the exception of the different PIDs. - -Bugzilla: 1134969 -Upstream-status: Queued for 3.18 - -Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com> ---- - drivers/input/tablet/wacom_wac.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/drivers/input/tablet/wacom_wac.c b/drivers/input/tablet/wacom_wac.c -index e73cf2c71f35..7f6caf8c85fb 100644 ---- a/drivers/input/tablet/wacom_wac.c -+++ b/drivers/input/tablet/wacom_wac.c -@@ -2332,6 +2332,13 @@ static const struct wacom_features wacom_features_0x0307 = - static const struct wacom_features wacom_features_0x0309 = - { "Wacom ISDv5 309", .type = WACOM_24HDT, /* Touch */ - .oVid = USB_VENDOR_ID_WACOM, .oPid = 0x0307, .touch_max = 10 }; -+static const struct wacom_features wacom_features_0x030A = -+ { "Wacom ISDv5 30A", WACOM_PKGLEN_INTUOS, 59352, 33648, 2047, -+ 63, CINTIQ_HYBRID, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES, 200, 200, -+ .oVid = USB_VENDOR_ID_WACOM, .oPid = 0x30C }; -+static const struct wacom_features wacom_features_0x030C = -+ { "Wacom ISDv5 30C", .type = WACOM_24HDT, /* Touch */ -+ .oVid = USB_VENDOR_ID_WACOM, .oPid = 0x030A, .touch_max = 10 }; - - #define USB_DEVICE_WACOM(prod) \ - USB_DEVICE(USB_VENDOR_ID_WACOM, prod), \ -@@ -2478,6 +2485,8 @@ const struct usb_device_id wacom_ids[] = { - { USB_DEVICE_WACOM(0xFA) }, - { USB_DEVICE_WACOM(0xFB) }, - { USB_DEVICE_WACOM(0x0307) }, -+ { USB_DEVICE_WACOM(0x030A) }, -+ { USB_DEVICE_DETAILED(0x030C, USB_CLASS_HID, 0, 0) }, - { USB_DEVICE_DETAILED(0x0309, USB_CLASS_HID, 0, 0) }, - { USB_DEVICE_LENOVO(0x6004) }, - { } --- -1.9.3 - diff --git a/KEYS-Add-a-system-blacklist-keyring.patch b/KEYS-Add-a-system-blacklist-keyring.patch new file mode 100644 index 00000000..17ef25bf --- /dev/null +++ b/KEYS-Add-a-system-blacklist-keyring.patch @@ -0,0 +1,111 @@ +From: Josh Boyer <jwboyer@fedoraproject.org> +Date: Fri, 26 Oct 2012 12:36:24 -0400 +Subject: [PATCH] KEYS: Add a system blacklist keyring + +This adds an additional keyring that is used to store certificates that +are blacklisted. This keyring is searched first when loading signed modules +and if the module's certificate is found, it will refuse to load. This is +useful in cases where third party certificates are used for module signing. + +Signed-off-by: Josh Boyer <jwboyer@fedoraproject.org> +--- + include/keys/system_keyring.h | 4 ++++ + init/Kconfig | 9 +++++++++ + kernel/module_signing.c | 12 ++++++++++++ + kernel/system_keyring.c | 17 +++++++++++++++++ + 4 files changed, 42 insertions(+) + +diff --git a/include/keys/system_keyring.h b/include/keys/system_keyring.h +index 72665eb80692..2c7b80d31366 100644 +--- a/include/keys/system_keyring.h ++++ b/include/keys/system_keyring.h +@@ -28,4 +28,8 @@ static inline struct key *get_system_trusted_keyring(void) + } + #endif + ++#ifdef CONFIG_SYSTEM_BLACKLIST_KEYRING ++extern struct key *system_blacklist_keyring; ++#endif ++ + #endif /* _KEYS_SYSTEM_KEYRING_H */ +diff --git a/init/Kconfig b/init/Kconfig +index 80a6907f91c5..dfdd7f738247 100644 +--- a/init/Kconfig ++++ b/init/Kconfig +@@ -1723,6 +1723,15 @@ config SYSTEM_TRUSTED_KEYRING + + Keys in this keyring are used by module signature checking. + ++config SYSTEM_BLACKLIST_KEYRING ++ bool "Provide system-wide ring of blacklisted keys" ++ depends on KEYS ++ help ++ Provide a system keyring to which blacklisted keys can be added. ++ Keys in the keyring are considered entirely untrusted. Keys in this ++ keyring are used by the module signature checking to reject loading ++ of modules signed with a blacklisted key. ++ + config PROFILING + bool "Profiling support" + help +diff --git a/kernel/module_signing.c b/kernel/module_signing.c +index be5b8fac4bd0..fed815fcdaf2 100644 +--- a/kernel/module_signing.c ++++ b/kernel/module_signing.c +@@ -158,6 +158,18 @@ static struct key *request_asymmetric_key(const char *signer, size_t signer_len, + + pr_debug("Look up: \"%s\"\n", id); + ++#ifdef CONFIG_SYSTEM_BLACKLIST_KEYRING ++ key = keyring_search(make_key_ref(system_blacklist_keyring, 1), ++ &key_type_asymmetric, id); ++ if (!IS_ERR(key)) { ++ /* module is signed with a cert in the blacklist. reject */ ++ pr_err("Module key '%s' is in blacklist\n", id); ++ key_ref_put(key); ++ kfree(id); ++ return ERR_PTR(-EKEYREJECTED); ++ } ++#endif ++ + key = keyring_search(make_key_ref(system_trusted_keyring, 1), + &key_type_asymmetric, id); + if (IS_ERR(key)) +diff --git a/kernel/system_keyring.c b/kernel/system_keyring.c +index 875f64e8935b..c15e93f5a418 100644 +--- a/kernel/system_keyring.c ++++ b/kernel/system_keyring.c +@@ -20,6 +20,9 @@ + + struct key *system_trusted_keyring; + EXPORT_SYMBOL_GPL(system_trusted_keyring); ++#ifdef CONFIG_SYSTEM_BLACKLIST_KEYRING ++struct key *system_blacklist_keyring; ++#endif + + extern __initconst const u8 system_certificate_list[]; + extern __initconst const unsigned long system_certificate_list_size; +@@ -41,6 +44,20 @@ static __init int system_trusted_keyring_init(void) + panic("Can't allocate system trusted keyring\n"); + + set_bit(KEY_FLAG_TRUSTED_ONLY, &system_trusted_keyring->flags); ++ ++#ifdef CONFIG_SYSTEM_BLACKLIST_KEYRING ++ system_blacklist_keyring = keyring_alloc(".system_blacklist_keyring", ++ KUIDT_INIT(0), KGIDT_INIT(0), ++ current_cred(), ++ (KEY_POS_ALL & ~KEY_POS_SETATTR) | ++ KEY_USR_VIEW | KEY_USR_READ, ++ KEY_ALLOC_NOT_IN_QUOTA, NULL); ++ if (IS_ERR(system_blacklist_keyring)) ++ panic("Can't allocate system blacklist keyring\n"); ++ ++ set_bit(KEY_FLAG_TRUSTED_ONLY, &system_blacklist_keyring->flags); ++#endif ++ + return 0; + } + +-- +1.9.3 + diff --git a/KEYS-Reinstate-EPERM-for-a-key-type-name-beginning-w.patch b/KEYS-Reinstate-EPERM-for-a-key-type-name-beginning-w.patch new file mode 100644 index 00000000..cd141ea8 --- /dev/null +++ b/KEYS-Reinstate-EPERM-for-a-key-type-name-beginning-w.patch @@ -0,0 +1,44 @@ +From: David Howells <dhowells@redhat.com> +Date: Tue, 16 Sep 2014 17:29:03 +0100 +Subject: [PATCH] KEYS: Reinstate EPERM for a key type name beginning with a + '.' + +Reinstate the generation of EPERM for a key type name beginning with a '.' in +a userspace call. Types whose name begins with a '.' are internal only. + +The test was removed by: + + commit a4e3b8d79a5c6d40f4a9703abf7fe3abcc6c3b8d + Author: Mimi Zohar <zohar@linux.vnet.ibm.com> + Date: Thu May 22 14:02:23 2014 -0400 + Subject: KEYS: special dot prefixed keyring name bug fix + +I think we want to keep the restriction on type name so that userspace can't +add keys of a special internal type. + +Note that removal of the test causes several of the tests in the keyutils +testsuite to fail. + +Signed-off-by: David Howells <dhowells@redhat.com> +Acked-by: Vivek Goyal <vgoyal@redhat.com> +cc: Mimi Zohar <zohar@linux.vnet.ibm.com> +--- + security/keys/keyctl.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/security/keys/keyctl.c b/security/keys/keyctl.c +index e26f860e5f2e..eff88a5f5d40 100644 +--- a/security/keys/keyctl.c ++++ b/security/keys/keyctl.c +@@ -37,6 +37,8 @@ static int key_get_type_from_user(char *type, + return ret; + if (ret == 0 || ret >= len) + return -EINVAL; ++ if (type[0] == '.') ++ return -EPERM; + type[len - 1] = '\0'; + return 0; + } +-- +1.9.3 + diff --git a/MODSIGN-Import-certificates-from-UEFI-Secure-Boot.patch b/MODSIGN-Import-certificates-from-UEFI-Secure-Boot.patch new file mode 100644 index 00000000..a23a15cd --- /dev/null +++ b/MODSIGN-Import-certificates-from-UEFI-Secure-Boot.patch @@ -0,0 +1,185 @@ +From: Josh Boyer <jwboyer@fedoraproject.org> +Date: Fri, 26 Oct 2012 12:42:16 -0400 +Subject: [PATCH] MODSIGN: Import certificates from UEFI Secure Boot + +Secure Boot stores a list of allowed certificates in the 'db' variable. +This imports those certificates into the system trusted keyring. This +allows for a third party signing certificate to be used in conjunction +with signed modules. By importing the public certificate into the 'db' +variable, a user can allow a module signed with that certificate to +load. The shim UEFI bootloader has a similar certificate list stored +in the 'MokListRT' variable. We import those as well. + +In the opposite case, Secure Boot maintains a list of disallowed +certificates in the 'dbx' variable. We load those certificates into +the newly introduced system blacklist keyring and forbid any module +signed with those from loading. + +Signed-off-by: Josh Boyer <jwboyer@fedoraproject.org> +--- + include/linux/efi.h | 6 ++++ + init/Kconfig | 9 +++++ + kernel/Makefile | 3 ++ + kernel/modsign_uefi.c | 92 +++++++++++++++++++++++++++++++++++++++++++++++++++ + 4 files changed, 110 insertions(+) + create mode 100644 kernel/modsign_uefi.c + +diff --git a/include/linux/efi.h b/include/linux/efi.h +index 41359e548bcb..db9e6118575e 100644 +--- a/include/linux/efi.h ++++ b/include/linux/efi.h +@@ -587,6 +587,12 @@ void efi_native_runtime_setup(void); + #define EFI_CERT_X509_GUID \ + EFI_GUID( 0xa5c059a1, 0x94e4, 0x4aa7, 0x87, 0xb5, 0xab, 0x15, 0x5c, 0x2b, 0xf0, 0x72 ) + ++#define EFI_IMAGE_SECURITY_DATABASE_GUID \ ++ EFI_GUID( 0xd719b2cb, 0x3d3a, 0x4596, 0xa3, 0xbc, 0xda, 0xd0, 0x0e, 0x67, 0x65, 0x6f ) ++ ++#define EFI_SHIM_LOCK_GUID \ ++ EFI_GUID( 0x605dab50, 0xe046, 0x4300, 0xab, 0xb6, 0x3d, 0xd8, 0x10, 0xdd, 0x8b, 0x23 ) ++ + typedef struct { + efi_guid_t guid; + u64 table; +diff --git a/init/Kconfig b/init/Kconfig +index dfdd7f738247..3c866db603a7 100644 +--- a/init/Kconfig ++++ b/init/Kconfig +@@ -1877,6 +1877,15 @@ config MODULE_SIG_ALL + comment "Do not forget to sign required modules with scripts/sign-file" + depends on MODULE_SIG_FORCE && !MODULE_SIG_ALL + ++config MODULE_SIG_UEFI ++ bool "Allow modules signed with certs stored in UEFI" ++ depends on MODULE_SIG && SYSTEM_BLACKLIST_KEYRING && EFI ++ select EFI_SIGNATURE_LIST_PARSER ++ help ++ This will import certificates stored in UEFI and allow modules ++ signed with those to be loaded. It will also disallow loading ++ of modules stored in the UEFI dbx variable. ++ + choice + prompt "Which hash algorithm should modules be signed with?" + depends on MODULE_SIG +diff --git a/kernel/Makefile b/kernel/Makefile +index dc5c77544fd6..95bdf3398880 100644 +--- a/kernel/Makefile ++++ b/kernel/Makefile +@@ -45,6 +45,7 @@ obj-$(CONFIG_UID16) += uid16.o + obj-$(CONFIG_SYSTEM_TRUSTED_KEYRING) += system_keyring.o system_certificates.o + obj-$(CONFIG_MODULES) += module.o + obj-$(CONFIG_MODULE_SIG) += module_signing.o ++obj-$(CONFIG_MODULE_SIG_UEFI) += modsign_uefi.o + obj-$(CONFIG_KALLSYMS) += kallsyms.o + obj-$(CONFIG_BSD_PROCESS_ACCT) += acct.o + obj-$(CONFIG_KEXEC) += kexec.o +@@ -99,6 +100,8 @@ obj-$(CONFIG_TORTURE_TEST) += torture.o + + $(obj)/configs.o: $(obj)/config_data.h + ++$(obj)/modsign_uefi.o: KBUILD_CFLAGS += -fshort-wchar ++ + # config_data.h contains the same information as ikconfig.h but gzipped. + # Info from config_data can be extracted from /proc/config* + targets += config_data.gz +diff --git a/kernel/modsign_uefi.c b/kernel/modsign_uefi.c +new file mode 100644 +index 000000000000..94b0eb38a284 +--- /dev/null ++++ b/kernel/modsign_uefi.c +@@ -0,0 +1,92 @@ ++#include <linux/kernel.h> ++#include <linux/sched.h> ++#include <linux/cred.h> ++#include <linux/err.h> ++#include <linux/efi.h> ++#include <linux/slab.h> ++#include <keys/asymmetric-type.h> ++#include <keys/system_keyring.h> ++#include "module-internal.h" ++ ++static __init void *get_cert_list(efi_char16_t *name, efi_guid_t *guid, unsigned long *size) ++{ ++ efi_status_t status; ++ unsigned long lsize = 4; ++ unsigned long tmpdb[4]; ++ void *db = NULL; ++ ++ status = efi.get_variable(name, guid, NULL, &lsize, &tmpdb); ++ if (status != EFI_BUFFER_TOO_SMALL) { ++ pr_err("Couldn't get size: 0x%lx\n", status); ++ return NULL; ++ } ++ ++ db = kmalloc(lsize, GFP_KERNEL); ++ if (!db) { ++ pr_err("Couldn't allocate memory for uefi cert list\n"); ++ goto out; ++ } ++ ++ status = efi.get_variable(name, guid, NULL, &lsize, db); ++ if (status != EFI_SUCCESS) { ++ kfree(db); ++ db = NULL; ++ pr_err("Error reading db var: 0x%lx\n", status); ++ } ++out: ++ *size = lsize; ++ return db; ++} ++ ++/* ++ * * Load the certs contained in the UEFI databases ++ * */ ++static int __init load_uefi_certs(void) ++{ ++ efi_guid_t secure_var = EFI_IMAGE_SECURITY_DATABASE_GUID; ++ efi_guid_t mok_var = EFI_SHIM_LOCK_GUID; ++ void *db = NULL, *dbx = NULL, *mok = NULL; ++ unsigned long dbsize = 0, dbxsize = 0, moksize = 0; ++ int rc = 0; ++ ++ /* Check if SB is enabled and just return if not */ ++ if (!efi_enabled(EFI_SECURE_BOOT)) ++ return 0; ++ ++ /* Get db, MokListRT, and dbx. They might not exist, so it isn't ++ * an error if we can't get them. ++ */ ++ db = get_cert_list(L"db", &secure_var, &dbsize); ++ if (!db) { ++ pr_err("MODSIGN: Couldn't get UEFI db list\n"); ++ } else { ++ rc = parse_efi_signature_list(db, dbsize, system_trusted_keyring); ++ if (rc) ++ pr_err("Couldn't parse db signatures: %d\n", rc); ++ kfree(db); ++ } ++ ++ mok = get_cert_list(L"MokListRT", &mok_var, &moksize); ++ if (!mok) { ++ pr_info("MODSIGN: Couldn't get UEFI MokListRT\n"); ++ } else { ++ rc = parse_efi_signature_list(mok, moksize, system_trusted_keyring); ++ if (rc) ++ pr_err("Couldn't parse MokListRT signatures: %d\n", rc); ++ kfree(mok); ++ } ++ ++ dbx = get_cert_list(L"dbx", &secure_var, &dbxsize); ++ if (!dbx) { ++ pr_info("MODSIGN: Couldn't get UEFI dbx list\n"); ++ } else { ++ rc = parse_efi_signature_list(dbx, dbxsize, ++ system_blacklist_keyring); ++ if (rc) ++ pr_err("Couldn't parse dbx signatures: %d\n", rc); ++ kfree(dbx); ++ } ++ ++ return rc; ++} ++late_initcall(load_uefi_certs); +-- +1.9.3 + diff --git a/MODSIGN-Support-not-importing-certs-from-db.patch b/MODSIGN-Support-not-importing-certs-from-db.patch new file mode 100644 index 00000000..6ed99e62 --- /dev/null +++ b/MODSIGN-Support-not-importing-certs-from-db.patch @@ -0,0 +1,83 @@ +From: Josh Boyer <jwboyer@fedoraproject.org> +Date: Thu, 3 Oct 2013 10:14:23 -0400 +Subject: [PATCH] MODSIGN: Support not importing certs from db + +If a user tells shim to not use the certs/hashes in the UEFI db variable +for verification purposes, shim will set a UEFI variable called MokIgnoreDB. +Have the uefi import code look for this and not import things from the db +variable. + +Signed-off-by: Josh Boyer <jwboyer@fedoraproject.org> +--- + kernel/modsign_uefi.c | 40 +++++++++++++++++++++++++++++++--------- + 1 file changed, 31 insertions(+), 9 deletions(-) + +diff --git a/kernel/modsign_uefi.c b/kernel/modsign_uefi.c +index 94b0eb38a284..ae28b974d49a 100644 +--- a/kernel/modsign_uefi.c ++++ b/kernel/modsign_uefi.c +@@ -8,6 +8,23 @@ + #include <keys/system_keyring.h> + #include "module-internal.h" + ++static __init int check_ignore_db(void) ++{ ++ efi_status_t status; ++ unsigned int db = 0; ++ unsigned long size = sizeof(db); ++ efi_guid_t guid = EFI_SHIM_LOCK_GUID; ++ ++ /* Check and see if the MokIgnoreDB variable exists. If that fails ++ * then we don't ignore DB. If it succeeds, we do. ++ */ ++ status = efi.get_variable(L"MokIgnoreDB", &guid, NULL, &size, &db); ++ if (status != EFI_SUCCESS) ++ return 0; ++ ++ return 1; ++} ++ + static __init void *get_cert_list(efi_char16_t *name, efi_guid_t *guid, unsigned long *size) + { + efi_status_t status; +@@ -47,23 +64,28 @@ static int __init load_uefi_certs(void) + efi_guid_t mok_var = EFI_SHIM_LOCK_GUID; + void *db = NULL, *dbx = NULL, *mok = NULL; + unsigned long dbsize = 0, dbxsize = 0, moksize = 0; +- int rc = 0; ++ int ignore_db, rc = 0; + + /* Check if SB is enabled and just return if not */ + if (!efi_enabled(EFI_SECURE_BOOT)) + return 0; + ++ /* See if the user has setup Ignore DB mode */ ++ ignore_db = check_ignore_db(); ++ + /* Get db, MokListRT, and dbx. They might not exist, so it isn't + * an error if we can't get them. + */ +- db = get_cert_list(L"db", &secure_var, &dbsize); +- if (!db) { +- pr_err("MODSIGN: Couldn't get UEFI db list\n"); +- } else { +- rc = parse_efi_signature_list(db, dbsize, system_trusted_keyring); +- if (rc) +- pr_err("Couldn't parse db signatures: %d\n", rc); +- kfree(db); ++ if (!ignore_db) { ++ db = get_cert_list(L"db", &secure_var, &dbsize); ++ if (!db) { ++ pr_err("MODSIGN: Couldn't get UEFI db list\n"); ++ } else { ++ rc = parse_efi_signature_list(db, dbsize, system_trusted_keyring); ++ if (rc) ++ pr_err("Couldn't parse db signatures: %d\n", rc); ++ kfree(db); ++ } + } + + mok = get_cert_list(L"MokListRT", &mok_var, &moksize); +-- +1.9.3 + diff --git a/PCI-Lock-down-BAR-access-when-module-security-is-ena.patch b/PCI-Lock-down-BAR-access-when-module-security-is-ena.patch new file mode 100644 index 00000000..2fc17c0b --- /dev/null +++ b/PCI-Lock-down-BAR-access-when-module-security-is-ena.patch @@ -0,0 +1,116 @@ +From: Matthew Garrett <matthew.garrett@nebula.com> +Date: Thu, 8 Mar 2012 10:10:38 -0500 +Subject: [PATCH] PCI: Lock down BAR access when module security is enabled + +Any hardware that can potentially generate DMA has to be locked down from +userspace in order to avoid it being possible for an attacker to modify +kernel code, allowing them to circumvent disabled module loading or module +signing. Default to paranoid - in future we can potentially relax this for +sufficiently IOMMU-isolated devices. + +Signed-off-by: Matthew Garrett <matthew.garrett@nebula.com> +--- + drivers/pci/pci-sysfs.c | 10 ++++++++++ + drivers/pci/proc.c | 8 +++++++- + drivers/pci/syscall.c | 3 ++- + 3 files changed, 19 insertions(+), 2 deletions(-) + +diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c +index 9ff0a901ecf7..8d0d5d92b8d9 100644 +--- a/drivers/pci/pci-sysfs.c ++++ b/drivers/pci/pci-sysfs.c +@@ -30,6 +30,7 @@ + #include <linux/vgaarb.h> + #include <linux/pm_runtime.h> + #include <linux/of.h> ++#include <linux/module.h> + #include "pci.h" + + static int sysfs_initialized; /* = 0 */ +@@ -704,6 +705,9 @@ static ssize_t pci_write_config(struct file *filp, struct kobject *kobj, + loff_t init_off = off; + u8 *data = (u8 *) buf; + ++ if (secure_modules()) ++ return -EPERM; ++ + if (off > dev->cfg_size) + return 0; + if (off + count > dev->cfg_size) { +@@ -998,6 +1002,9 @@ static int pci_mmap_resource(struct kobject *kobj, struct bin_attribute *attr, + resource_size_t start, end; + int i; + ++ if (secure_modules()) ++ return -EPERM; ++ + for (i = 0; i < PCI_ROM_RESOURCE; i++) + if (res == &pdev->resource[i]) + break; +@@ -1099,6 +1106,9 @@ static ssize_t pci_write_resource_io(struct file *filp, struct kobject *kobj, + struct bin_attribute *attr, char *buf, + loff_t off, size_t count) + { ++ if (secure_modules()) ++ return -EPERM; ++ + return pci_resource_io(filp, kobj, attr, buf, off, count, true); + } + +diff --git a/drivers/pci/proc.c b/drivers/pci/proc.c +index 3f155e78513f..4265ea07e3b0 100644 +--- a/drivers/pci/proc.c ++++ b/drivers/pci/proc.c +@@ -116,6 +116,9 @@ static ssize_t proc_bus_pci_write(struct file *file, const char __user *buf, + int size = dev->cfg_size; + int cnt; + ++ if (secure_modules()) ++ return -EPERM; ++ + if (pos >= size) + return 0; + if (nbytes >= size) +@@ -195,6 +198,9 @@ static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd, + #endif /* HAVE_PCI_MMAP */ + int ret = 0; + ++ if (secure_modules()) ++ return -EPERM; ++ + switch (cmd) { + case PCIIOC_CONTROLLER: + ret = pci_domain_nr(dev->bus); +@@ -233,7 +239,7 @@ static int proc_bus_pci_mmap(struct file *file, struct vm_area_struct *vma) + struct pci_filp_private *fpriv = file->private_data; + int i, ret; + +- if (!capable(CAP_SYS_RAWIO)) ++ if (!capable(CAP_SYS_RAWIO) || secure_modules()) + return -EPERM; + + /* Make sure the caller is mapping a real resource for this device */ +diff --git a/drivers/pci/syscall.c b/drivers/pci/syscall.c +index b91c4da68365..98f5637304d1 100644 +--- a/drivers/pci/syscall.c ++++ b/drivers/pci/syscall.c +@@ -10,6 +10,7 @@ + #include <linux/errno.h> + #include <linux/pci.h> + #include <linux/syscalls.h> ++#include <linux/module.h> + #include <asm/uaccess.h> + #include "pci.h" + +@@ -92,7 +93,7 @@ SYSCALL_DEFINE5(pciconfig_write, unsigned long, bus, unsigned long, dfn, + u32 dword; + int err = 0; + +- if (!capable(CAP_SYS_ADMIN)) ++ if (!capable(CAP_SYS_ADMIN) || secure_modules()) + return -EPERM; + + dev = pci_get_bus_and_slot(bus, dfn); +-- +1.9.3 + diff --git a/Restrict-dev-mem-and-dev-kmem-when-module-loading-is.patch b/Restrict-dev-mem-and-dev-kmem-when-module-loading-is.patch new file mode 100644 index 00000000..003bfec7 --- /dev/null +++ b/Restrict-dev-mem-and-dev-kmem-when-module-loading-is.patch @@ -0,0 +1,41 @@ +From: Matthew Garrett <matthew.garrett@nebula.com> +Date: Fri, 9 Mar 2012 09:28:15 -0500 +Subject: [PATCH] Restrict /dev/mem and /dev/kmem when module loading is + restricted + +Allowing users to write to address space makes it possible for the kernel +to be subverted, avoiding module loading restrictions. Prevent this when +any restrictions have been imposed on loading modules. + +Signed-off-by: Matthew Garrett <matthew.garrett@nebula.com> +--- + drivers/char/mem.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/char/mem.c b/drivers/char/mem.c +index cdf839f9defe..c63cf93b00eb 100644 +--- a/drivers/char/mem.c ++++ b/drivers/char/mem.c +@@ -164,6 +164,9 @@ static ssize_t write_mem(struct file *file, const char __user *buf, + if (p != *ppos) + return -EFBIG; + ++ if (secure_modules()) ++ return -EPERM; ++ + if (!valid_phys_addr_range(p, count)) + return -EFAULT; + +@@ -502,6 +505,9 @@ static ssize_t write_kmem(struct file *file, const char __user *buf, + char *kbuf; /* k-addr because vwrite() takes vmlist_lock rwlock */ + int err = 0; + ++ if (secure_modules()) ++ return -EPERM; ++ + if (p < (unsigned long) high_memory) { + unsigned long to_write = min_t(unsigned long, count, + (unsigned long)high_memory - p); +-- +1.9.3 + diff --git a/Revert-Revert-ACPI-video-change-acpi-video-brightnes.patch b/Revert-Revert-ACPI-video-change-acpi-video-brightnes.patch index 2f44032c..0f3a7015 100644 --- a/Revert-Revert-ACPI-video-change-acpi-video-brightnes.patch +++ b/Revert-Revert-ACPI-video-change-acpi-video-brightnes.patch @@ -1,23 +1,24 @@ -Bugzilla: N/A -Upstream-status: Sigh. We almost got to drop this. - -From 20e3f1e1b9341d233a11734c07c076caac9936ef Mon Sep 17 00:00:00 2001 From: Josh Boyer <jwboyer@fedoraproject.org> Date: Mon, 28 Jul 2014 12:59:48 -0400 Subject: [PATCH] Revert "Revert "ACPI / video: change acpi-video brightness_switch_enabled default to 0"" This reverts commit 2843768b701971ab10e62c77d5c75ad7c306f1bd. + +Bugzilla: N/A +Upstream-status: Sigh. We almost got to drop this. + +Signed-off-by: Josh Boyer <jwboyer@fedoraproject.org> --- Documentation/kernel-parameters.txt | 2 +- drivers/acpi/video.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt -index b7fa2f599459..e8db409a7e3a 100644 +index 10d51c2f10d7..5b6ebe8b519e 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt -@@ -3532,7 +3532,7 @@ bytes respectively. Such letter suffixes can also be entirely omitted. +@@ -3596,7 +3596,7 @@ bytes respectively. Such letter suffixes can also be entirely omitted. the allocated input device; If set to 0, video driver will only send out the event without touching backlight brightness level. @@ -27,7 +28,7 @@ index b7fa2f599459..e8db409a7e3a 100644 virtio_mmio.device= [VMMIO] Memory mapped virtio (platform) device. diff --git a/drivers/acpi/video.c b/drivers/acpi/video.c -index 350d52a8f781..44c89f705018 100644 +index 8e7e18567ae6..a3d293806f96 100644 --- a/drivers/acpi/video.c +++ b/drivers/acpi/video.c @@ -68,7 +68,7 @@ MODULE_AUTHOR("Bruno Ducrot"); diff --git a/acpi-Ignore-acpi_rsdp-kernel-parameter-when-module-l.patch b/acpi-Ignore-acpi_rsdp-kernel-parameter-when-module-l.patch new file mode 100644 index 00000000..cea06c30 --- /dev/null +++ b/acpi-Ignore-acpi_rsdp-kernel-parameter-when-module-l.patch @@ -0,0 +1,38 @@ +From: Josh Boyer <jwboyer@redhat.com> +Date: Mon, 25 Jun 2012 19:57:30 -0400 +Subject: [PATCH] acpi: Ignore acpi_rsdp kernel parameter when module loading + is restricted + +This option allows userspace to pass the RSDP address to the kernel, which +makes it possible for a user to circumvent any restrictions imposed on +loading modules. Disable it in that case. + +Signed-off-by: Josh Boyer <jwboyer@redhat.com> +--- + drivers/acpi/osl.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c +index 3abe9b223ba7..ee8f11cf65da 100644 +--- a/drivers/acpi/osl.c ++++ b/drivers/acpi/osl.c +@@ -44,6 +44,7 @@ + #include <linux/list.h> + #include <linux/jiffies.h> + #include <linux/semaphore.h> ++#include <linux/module.h> + + #include <asm/io.h> + #include <asm/uaccess.h> +@@ -245,7 +246,7 @@ early_param("acpi_rsdp", setup_acpi_rsdp); + acpi_physical_address __init acpi_os_get_root_pointer(void) + { + #ifdef CONFIG_KEXEC +- if (acpi_rsdp) ++ if (acpi_rsdp && !secure_modules()) + return acpi_rsdp; + #endif + +-- +1.9.3 + diff --git a/0001-acpi-video-Add-4-new-models-to-the-use_native_backli.patch b/acpi-video-Add-4-new-models-to-the-use_native_backli.patch index dd7f2736..4411248f 100644 --- a/0001-acpi-video-Add-4-new-models-to-the-use_native_backli.patch +++ b/acpi-video-Add-4-new-models-to-the-use_native_backli.patch @@ -1,8 +1,7 @@ -From 5573624261ab5d54f2dea2a3e09a98729db9ecd9 Mon Sep 17 00:00:00 2001 From: Hans de Goede <hdegoede@redhat.com> Date: Wed, 30 Apr 2014 15:24:19 +0200 -Subject: [PATCH 1/2] acpi-video: Add 4 new models to the use_native_backlight - dmi list +Subject: [PATCH] acpi-video: Add 4 new models to the use_native_backlight dmi + list Acer Aspire V5-171 https://bugzilla.redhat.com/show_bug.cgi?id=983342 @@ -21,10 +20,10 @@ Signed-off-by: Hans de Goede <hdegoede@redhat.com> 1 file changed, 32 insertions(+) diff --git a/drivers/acpi/video.c b/drivers/acpi/video.c -index 8b6990e..48146fc 100644 +index a3d293806f96..5c8ce8c699fc 100644 --- a/drivers/acpi/video.c +++ b/drivers/acpi/video.c -@@ -488,6 +488,14 @@ static struct dmi_system_id video_dmi_table[] __initdata = { +@@ -556,6 +556,14 @@ static struct dmi_system_id video_dmi_table[] __initdata = { }, }, { @@ -39,7 +38,7 @@ index 8b6990e..48146fc 100644 .callback = video_set_use_native_backlight, .ident = "Thinkpad Helix", .matches = { -@@ -513,6 +521,14 @@ static struct dmi_system_id video_dmi_table[] __initdata = { +@@ -597,6 +605,14 @@ static struct dmi_system_id video_dmi_table[] __initdata = { }, { .callback = video_set_use_native_backlight, @@ -54,7 +53,7 @@ index 8b6990e..48146fc 100644 .ident = "Acer Aspire V5-431", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "Acer"), -@@ -520,6 +536,14 @@ static struct dmi_system_id video_dmi_table[] __initdata = { +@@ -644,6 +660,14 @@ static struct dmi_system_id video_dmi_table[] __initdata = { }, }, { @@ -69,7 +68,7 @@ index 8b6990e..48146fc 100644 .callback = video_set_use_native_backlight, .ident = "HP ProBook 4340s", .matches = { -@@ -571,6 +595,14 @@ static struct dmi_system_id video_dmi_table[] __initdata = { +@@ -720,6 +744,14 @@ static struct dmi_system_id video_dmi_table[] __initdata = { }, { .callback = video_set_use_native_backlight, @@ -85,5 +84,5 @@ index 8b6990e..48146fc 100644 .matches = { DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), -- -1.9.0 +1.9.3 diff --git a/acpi-video-Add-use-native-backlight-quirk-for-the-Th.patch b/acpi-video-Add-use-native-backlight-quirk-for-the-Th.patch index f3d36889..fb77e564 100644 --- a/acpi-video-Add-use-native-backlight-quirk-for-the-Th.patch +++ b/acpi-video-Add-use-native-backlight-quirk-for-the-Th.patch @@ -1,11 +1,7 @@ -Bugzilla: 1093171 -Upstream-status: Queued for 3.16 - -From 7ac976d0109433d1ad0812f4f6889a904d9a0c40 Mon Sep 17 00:00:00 2001 From: Hans de Goede <hdegoede@redhat.com> Date: Mon, 2 Jun 2014 17:41:10 +0200 -Subject: [PATCH 13/14] acpi-video: Add use native backlight quirk for the - ThinkPad W530 +Subject: [PATCH] acpi-video: Add use native backlight quirk for the ThinkPad + W530 Like all of the other *30 ThinkPad models, the W530 has a broken acpi-video backlight control. Note in order for this to actually fix things on the @@ -15,6 +11,9 @@ is also needed. https://bugzilla.redhat.com/show_bug.cgi?id=1093171 +Bugzilla: 1093171 +Upstream-status: Queued for 3.16 + Cc: stable@vger.kernel.org Signed-off-by: Hans de Goede <hdegoede@redhat.com> --- @@ -22,10 +21,10 @@ Signed-off-by: Hans de Goede <hdegoede@redhat.com> 1 file changed, 8 insertions(+) diff --git a/drivers/acpi/video.c b/drivers/acpi/video.c -index ab7cd65ce21e..dcb0ef4c22f6 100644 +index 5c8ce8c699fc..d8a6ecb0b2b2 100644 --- a/drivers/acpi/video.c +++ b/drivers/acpi/video.c -@@ -468,6 +468,14 @@ static struct dmi_system_id video_dmi_table[] __initdata = { +@@ -469,6 +469,14 @@ static struct dmi_system_id video_dmi_table[] __initdata = { }, { .callback = video_set_use_native_backlight, @@ -41,5 +40,5 @@ index ab7cd65ce21e..dcb0ef4c22f6 100644 .matches = { DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), -- -1.9.0 +1.9.3 diff --git a/acpi-video-Add-use_native_backlight-quirk-for-HP-Pro.patch b/acpi-video-Add-use_native_backlight-quirk-for-HP-Pro.patch index c8c1f7aa..33a26383 100644 --- a/acpi-video-Add-use_native_backlight-quirk-for-HP-Pro.patch +++ b/acpi-video-Add-use_native_backlight-quirk-for-HP-Pro.patch @@ -1,16 +1,15 @@ -Bugzilla: 1025690 -Upstream-status: Waiting for feedback from reporter - -From dfe2c6722a6f6cb45f6b336b094b26a77acd8393 Mon Sep 17 00:00:00 2001 From: Hans de Goede <hdegoede@redhat.com> Date: Mon, 2 Jun 2014 17:41:11 +0200 -Subject: [PATCH 14/14] acpi-video: Add use_native_backlight quirk for HP - ProBook 4540s +Subject: [PATCH] acpi-video: Add use_native_backlight quirk for HP ProBook + 4540s As reported here: https://bugzilla.redhat.com/show_bug.cgi?id=1025690 This is yet another model which needs this quirk. +Bugzilla: 1025690 +Upstream-status: Waiting for feedback from reporter + Cc: stable@vger.kernel.org Signed-off-by: Hans de Goede <hdegoede@redhat.com> --- @@ -18,10 +17,10 @@ Signed-off-by: Hans de Goede <hdegoede@redhat.com> 1 file changed, 8 insertions(+) diff --git a/drivers/acpi/video.c b/drivers/acpi/video.c -index dcb0ef4c22f6..3db16753f88a 100644 +index d8a6ecb0b2b2..8dbf009521c7 100644 --- a/drivers/acpi/video.c +++ b/drivers/acpi/video.c -@@ -548,6 +548,14 @@ static struct dmi_system_id video_dmi_table[] __initdata = { +@@ -693,6 +693,14 @@ static struct dmi_system_id video_dmi_table[] __initdata = { }, { .callback = video_set_use_native_backlight, @@ -37,5 +36,5 @@ index dcb0ef4c22f6..3db16753f88a 100644 .matches = { DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), -- -1.9.0 +1.9.3 diff --git a/arm-beagle.patch b/arm-beagle.patch deleted file mode 100644 index 5e2d8abd..00000000 --- a/arm-beagle.patch +++ /dev/null @@ -1,460 +0,0 @@ -Bugzilla: 1012025 -Upstream-status: In beagle github repository https://github.com/beagleboard/kernel - -From b5a2528c89fc8049b2a6a750634c14983e33d00f Mon Sep 17 00:00:00 2001 -From: Robert Nelson <robertcnelson@gmail.com> -Date: Fri, 27 Dec 2013 13:05:09 -0600 -Subject: [PATCH] arm: dts: am335x-boneblack: lcdc add panel-info - -Signed-off-by: Robert Nelson <robertcnelson@gmail.com> ---- - arch/arm/boot/dts/am335x-boneblack.dts | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - -diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts -index 6b71ad9..09ffbd8 100644 ---- a/arch/arm/boot/dts/am335x-boneblack.dts -+++ b/arch/arm/boot/dts/am335x-boneblack.dts -@@ -74,5 +74,18 @@ - pinctrl-0 = <&nxp_hdmi_bonelt_pins>; - pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; - status = "okay"; -+ -+ panel-info { -+ bpp = <16>; -+ ac-bias = <255>; -+ ac-bias-intrpt = <0>; -+ dma-burst-sz = <16>; -+ fdd = <16>; -+ sync-edge = <1>; -+ sync-ctrl = <1>; -+ raster-order = <0>; -+ fifo-th = <0>; -+ invert-pxl-clk; -+ }; - }; - }; --- -1.8.5.1 - -From 1da083a002581520dd358b8b8e097078000d12b9 Mon Sep 17 00:00:00 2001 -From: Robert Nelson <robertcnelson@gmail.com> -Date: Fri, 27 Dec 2013 13:14:19 -0600 -Subject: [PATCH 2/2] arm: dts: am335x-boneblack: add cpu0 opp points - -Signed-off-by: Robert Nelson <robertcnelson@gmail.com> ---- - arch/arm/boot/dts/am335x-boneblack.dts | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - -diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts -index 09ffbd8..f213ccd 100644 ---- a/arch/arm/boot/dts/am335x-boneblack.dts -+++ b/arch/arm/boot/dts/am335x-boneblack.dts -@@ -67,6 +67,24 @@ - }; - - / { -+ cpus { -+ cpu@0 { -+ cpu0-supply = <&dcdc2_reg>; -+ /* -+ * To consider voltage drop between PMIC and SoC, -+ * tolerance value is reduced to 2% from 4% and -+ * voltage value is increased as a precaution. -+ */ -+ operating-points = < -+ /* kHz uV */ -+ 1000000 1325000 -+ 800000 1300000 -+ 600000 1112000 -+ 300000 969000 -+ >; -+ }; -+ }; -+ - hdmi { - compatible = "ti,tilcdc,slave"; - i2c = <&i2c0>; --- -1.8.5.1 - -From 8551d8aa7d3e002da2097e7e902fb96fceb8694e Mon Sep 17 00:00:00 2001 -From: Robert Nelson <robertcnelson@gmail.com> -Date: Tue, 31 Dec 2013 11:17:45 -0600 -Subject: [PATCH 3/3] arm: dts: am335x-bone-common: enable and use i2c2 - -Signed-off-by: Robert Nelson <robertcnelson@gmail.com> ---- - arch/arm/boot/dts/am335x-bone-common.dtsi | 39 +++++++++++++++++++++++++++++++ - 1 file changed, 39 insertions(+) - -diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi -index e3f27ec..54366b6 100644 ---- a/arch/arm/boot/dts/am335x-bone-common.dtsi -+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi -@@ -84,6 +84,13 @@ - >; - }; - -+ i2c2_pins: pinmux_i2c2_pins { -+ pinctrl-single,pins = < -+ 0x178 0x73 /* (SLEWCTRL_SLOW | PIN_INPUT_PULLUP | MUX_MODE3) uart1_ctsn.i2c2_sda */ -+ 0x17c 0x73 /* (SLEWCTRL_SLOW | PIN_INPUT_PULLUP | MUX_MODE3) uart1_rtsn.i2c2_scl */ -+ >; -+ }; -+ - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ -@@ -220,6 +227,38 @@ - reg = <0x24>; - }; - -+ baseboard_eeprom: baseboard_eeprom@50 { -+ compatible = "at,24c256"; -+ reg = <0x50>; -+ }; -+}; -+ -+&i2c2 { -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c2_pins>; -+ -+ clock-frequency = <100000>; -+ -+ cape_eeprom0: cape_eeprom0@54 { -+ compatible = "at,24c256"; -+ reg = <0x54>; -+ }; -+ -+ cape_eeprom1: cape_eeprom1@55 { -+ compatible = "at,24c256"; -+ reg = <0x55>; -+ }; -+ -+ cape_eeprom2: cape_eeprom2@56 { -+ compatible = "at,24c256"; -+ reg = <0x56>; -+ }; -+ -+ cape_eeprom3: cape_eeprom3@57 { -+ compatible = "at,24c256"; -+ reg = <0x57>; -+ }; - }; - - /include/ "tps65217.dtsi" --- -1.8.5.2 - -From a3099dc53a47d1694a5b575580ec3406dc429bf8 Mon Sep 17 00:00:00 2001 -From: Robert Nelson <robertcnelson@gmail.com> -Date: Tue, 31 Dec 2013 14:18:00 -0600 -Subject: [PATCH 4/4] arm: dts: am335x-bone-common: setup default pinmux - http://elinux.org/Basic_Proto_Cape - -Signed-off-by: Robert Nelson <robertcnelson@gmail.com> ---- - arch/arm/boot/dts/am335x-bone-common.dtsi | 130 ++++++++++++++++++++++++++++++ - 1 file changed, 130 insertions(+) - -diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi -index e4571af..f85cabc 100644 ---- a/arch/arm/boot/dts/am335x-bone-common.dtsi -+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi -@@ -98,6 +98,13 @@ - >; - }; - -+ uart1_pins: pinmux_uart1_pins { -+ pinctrl-single,pins = < -+ 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ -+ 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ -+ >; -+ }; -+ - clkout2_pin: pinmux_clkout2_pin { - pinctrl-single,pins = < - 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ -@@ -178,6 +185,33 @@ - 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ - >; - }; -+ -+ spi0_pins: pinmux_spi0_pins { -+ pinctrl-single,pins = < -+ 0x150 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */ -+ 0x154 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */ -+ 0x158 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ -+ 0x15c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ -+ >; -+ }; -+ -+ ehrpwm1_pin_p9_14: pinmux_ehrpwm1_pin_p9_14 { -+ pinctrl-single,pins = < -+ 0x048 0x6 /* P9_14 (ZCZ ball U14) | MODE 6 */ -+ >; -+ }; -+ -+ ehrpwm1_pin_p9_16: pinmux_ehrpwm1_pin_p9_16 { -+ pinctrl-single,pins = < -+ 0x04c 0x6 /* P9_16 (ZCZ ball T14) | MODE 6 */ -+ >; -+ }; -+ -+ ecap0_pin_p9_42: pinmux_ecap0_pin_p9_42 { -+ pinctrl-single,pins = < -+ 0x164 0x0 /* P9_42 (ZCZ ball C18) | MODE 0 */ -+ >; -+ }; - }; - - &uart0 { -@@ -187,6 +221,13 @@ - status = "okay"; - }; - -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+ -+ status = "okay"; -+}; -+ - &usb { - status = "okay"; - -@@ -261,6 +302,56 @@ - }; - }; - -+&epwmss0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ecap0_pin_p9_42>; -+ status = "okay"; -+ -+ ecap@48300100 { -+ status = "okay"; -+ }; -+}; -+ -+&epwmss1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = < -+ &ehrpwm1_pin_p9_14 -+ &ehrpwm1_pin_p9_16 -+ >; -+ -+ status = "okay"; -+ -+ ehrpwm@48302200 { -+ status = "okay"; -+ }; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; -+ status = "okay"; -+ -+ spidev0: spi@0 { -+ compatible = "spidev"; -+ reg = <0>; -+ spi-max-frequency = <16000000>; -+ spi-cpha; -+ }; -+ -+ spidev1: spi@1 { -+ compatible = "spidev"; -+ reg = <1>; -+ spi-max-frequency = <16000000>; -+ }; -+}; -+ -+&tscadc { -+ status = "okay"; -+ adc { -+ ti,adc-channels = <4 5 6>; -+ }; -+}; -+ - /include/ "tps65217.dtsi" - - &tps { -@@ -336,3 +427,42 @@ - cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; - cd-inverted; - }; -+ -+/ { -+ ocp { -+ //FIXME: these pwm's still need work, this guild isn't working.. -+ //http://elinux.org/EBC_Exercise_13_Pulse_Width_Modulation -+ pwm_test_P9_14@0 { -+ compatible = "pwm_test"; -+ pwms = <&ehrpwm1 0 500000 1>; -+ pwm-names = "PWM_P9_14"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ehrpwm1_pin_p9_14>; -+ enabled = <1>; -+ duty = <0>; -+ status = "okay"; -+ }; -+ -+ pwm_test_P9_16@0 { -+ compatible = "pwm_test"; -+ pwms = <&ehrpwm1 0 500000 1>; -+ pwm-names = "PWM_P9_16"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ehrpwm1_pin_p9_16>; -+ enabled = <1>; -+ duty = <0>; -+ status = "okay"; -+ }; -+ -+ pwm_test_P9_42 { -+ compatible = "pwm_test"; -+ pwms = <&ecap0 0 500000 1>; -+ pwm-names = "PWM_P9_42"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ecap0_pin_p9_42>; -+ enabled = <1>; -+ duty = <0>; -+ status = "okay"; -+ }; -+ }; -+}; --- -1.8.5.2 - -From b6e2c817edfc6d73874cf833daffe1be6c7ed8bb Mon Sep 17 00:00:00 2001 -From: Robert Nelson <robertcnelson@gmail.com> -Date: Thu, 13 Mar 2014 14:18:52 -0500 -Subject: [PATCH] arm: dts: am335x-bone-common: add - uart2_pins/uart4_pins/uart5_pins - -Signed-off-by: Robert Nelson <robertcnelson@gmail.com> ---- - arch/arm/boot/dts/am335x-bone-common.dtsi | 21 +++++++++++++++++++++ - 1 file changed, 21 insertions(+) - -diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi -index f85cabc..5270d18 100644 ---- a/arch/arm/boot/dts/am335x-bone-common.dtsi -+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi -@@ -105,6 +105,27 @@ - >; - }; - -+ uart2_pins: pinmux_uart2_pins { -+ pinctrl-single,pins = < -+ 0x150 0x21 /* spi0_sclk.uart2_rxd | MODE1 */ -+ 0x154 0x01 /* spi0_d0.uart2_txd | MODE1 */ -+ >; -+ }; -+ -+ uart4_pins: pinmux_uart4_pins { -+ pinctrl-single,pins = < -+ 0x070 0x26 /* gpmc_wait0.uart4_rxd | MODE6 */ -+ 0x074 0x06 /* gpmc_wpn.uart4_txd | MODE6 */ -+ >; -+ }; -+ -+ uart5_pins: pinmux_uart5_pins { -+ pinctrl-single,pins = < -+ 0x0C4 0x24 /* lcd_data9.uart5_rxd | MODE4 */ -+ 0x0C0 0x04 /* lcd_data8.uart5_txd | MODE4 */ -+ >; -+ }; -+ - clkout2_pin: pinmux_clkout2_pin { - pinctrl-single,pins = < - 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ --- -1.9.0 - -From 72567452d5d6007010597158f6afd00e2bf07579 Mon Sep 17 00:00:00 2001 -From: Pantelis Antoniou <panto@antoniou-consulting.com> -Date: Sat, 15 Sep 2012 12:00:41 +0300 -Subject: [PATCH] pinctrl: pinctrl-single must be initialized early. - -When using pinctrl-single to handle i2c initialization, it has -to be done early. Whether this is the best way to do so, is an -exercise left to the reader. ---- - drivers/pinctrl/pinctrl-single.c | 12 +++++++++++- - 1 file changed, 11 insertions(+), 1 deletion(-) - -diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c -index 829b98c..5107dcf 100644 ---- a/drivers/pinctrl/pinctrl-single.c -+++ b/drivers/pinctrl/pinctrl-single.c -@@ -2039,7 +2039,17 @@ static struct platform_driver pcs_driver = { - #endif - }; - --module_platform_driver(pcs_driver); -+static int __init pcs_init(void) -+{ -+ return platform_driver_register(&pcs_driver); -+} -+postcore_initcall(pcs_init); -+ -+static void __exit pcs_exit(void) -+{ -+ platform_driver_unregister(&pcs_driver); -+} -+module_exit(pcs_exit); - - MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>"); - MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver"); --- -1.8.5.2 - -From b6e2c817edfc6d73874cf833daffe1be6c7ed8bb Mon Sep 17 00:00:00 2001 -From: Robert Nelson <robertcnelson@gmail.com> -Date: Thu, 13 Mar 2014 14:18:52 -0500 -Subject: [PATCH] arm: dts: am335x-bone-common: add - uart2_pins/uart4_pins/uart5_pins - -Signed-off-by: Robert Nelson <robertcnelson@gmail.com> ---- - arch/arm/boot/dts/am335x-bone-common.dtsi | 21 +++++++++++++++++++++ - 1 file changed, 21 insertions(+) - -diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi -index f85cabc..5270d18 100644 ---- a/arch/arm/boot/dts/am335x-bone-common.dtsi -+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi -@@ -105,6 +105,27 @@ - >; - }; - -+ uart2_pins: pinmux_uart2_pins { -+ pinctrl-single,pins = < -+ 0x150 0x21 /* spi0_sclk.uart2_rxd | MODE1 */ -+ 0x154 0x01 /* spi0_d0.uart2_txd | MODE1 */ -+ >; -+ }; -+ -+ uart4_pins: pinmux_uart4_pins { -+ pinctrl-single,pins = < -+ 0x070 0x26 /* gpmc_wait0.uart4_rxd | MODE6 */ -+ 0x074 0x06 /* gpmc_wpn.uart4_txd | MODE6 */ -+ >; -+ }; -+ -+ uart5_pins: pinmux_uart5_pins { -+ pinctrl-single,pins = < -+ 0x0C4 0x24 /* lcd_data9.uart5_rxd | MODE4 */ -+ 0x0C0 0x04 /* lcd_data8.uart5_txd | MODE4 */ -+ >; -+ }; -+ - clkout2_pin: pinmux_clkout2_pin { - pinctrl-single,pins = < - 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ --- -1.9.0 diff --git a/arm-dts-am335x-bone-common-add-uart2_pins-uart4_pins.patch b/arm-dts-am335x-bone-common-add-uart2_pins-uart4_pins.patch new file mode 100644 index 00000000..e95955de --- /dev/null +++ b/arm-dts-am335x-bone-common-add-uart2_pins-uart4_pins.patch @@ -0,0 +1,45 @@ +From: Robert Nelson <robertcnelson@gmail.com> +Date: Thu, 13 Mar 2014 14:18:52 -0500 +Subject: [PATCH] arm: dts: am335x-bone-common: add + uart2_pins/uart4_pins/uart5_pins + +Signed-off-by: Robert Nelson <robertcnelson@gmail.com> +--- + arch/arm/boot/dts/am335x-bone-common.dtsi | 21 +++++++++++++++++++++ + 1 file changed, 21 insertions(+) + +diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi +index 86cdb52dbf8a..db4518ef755d 100644 +--- a/arch/arm/boot/dts/am335x-bone-common.dtsi ++++ b/arch/arm/boot/dts/am335x-bone-common.dtsi +@@ -105,6 +105,27 @@ + >; + }; + ++ uart2_pins: pinmux_uart2_pins { ++ pinctrl-single,pins = < ++ 0x150 0x21 /* spi0_sclk.uart2_rxd | MODE1 */ ++ 0x154 0x01 /* spi0_d0.uart2_txd | MODE1 */ ++ >; ++ }; ++ ++ uart4_pins: pinmux_uart4_pins { ++ pinctrl-single,pins = < ++ 0x070 0x26 /* gpmc_wait0.uart4_rxd | MODE6 */ ++ 0x074 0x06 /* gpmc_wpn.uart4_txd | MODE6 */ ++ >; ++ }; ++ ++ uart5_pins: pinmux_uart5_pins { ++ pinctrl-single,pins = < ++ 0x0C4 0x24 /* lcd_data9.uart5_rxd | MODE4 */ ++ 0x0C0 0x04 /* lcd_data8.uart5_txd | MODE4 */ ++ >; ++ }; ++ + clkout2_pin: pinmux_clkout2_pin { + pinctrl-single,pins = < + 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ +-- +1.9.3 + diff --git a/arm-dts-am335x-bone-common-enable-and-use-i2c2.patch b/arm-dts-am335x-bone-common-enable-and-use-i2c2.patch new file mode 100644 index 00000000..04efe225 --- /dev/null +++ b/arm-dts-am335x-bone-common-enable-and-use-i2c2.patch @@ -0,0 +1,69 @@ +From: Robert Nelson <robertcnelson@gmail.com> +Date: Tue, 31 Dec 2013 11:17:45 -0600 +Subject: [PATCH] arm: dts: am335x-bone-common: enable and use i2c2 + +Signed-off-by: Robert Nelson <robertcnelson@gmail.com> +--- + arch/arm/boot/dts/am335x-bone-common.dtsi | 39 +++++++++++++++++++++++++++++++ + 1 file changed, 39 insertions(+) + +diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi +index bde1777b62be..c7357bcc7d5c 100644 +--- a/arch/arm/boot/dts/am335x-bone-common.dtsi ++++ b/arch/arm/boot/dts/am335x-bone-common.dtsi +@@ -84,6 +84,13 @@ + >; + }; + ++ i2c2_pins: pinmux_i2c2_pins { ++ pinctrl-single,pins = < ++ 0x178 0x73 /* (SLEWCTRL_SLOW | PIN_INPUT_PULLUP | MUX_MODE3) uart1_ctsn.i2c2_sda */ ++ 0x17c 0x73 /* (SLEWCTRL_SLOW | PIN_INPUT_PULLUP | MUX_MODE3) uart1_rtsn.i2c2_scl */ ++ >; ++ }; ++ + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ +@@ -220,6 +227,38 @@ + reg = <0x24>; + }; + ++ baseboard_eeprom: baseboard_eeprom@50 { ++ compatible = "at,24c256"; ++ reg = <0x50>; ++ }; ++}; ++ ++&i2c2 { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins>; ++ ++ clock-frequency = <100000>; ++ ++ cape_eeprom0: cape_eeprom0@54 { ++ compatible = "at,24c256"; ++ reg = <0x54>; ++ }; ++ ++ cape_eeprom1: cape_eeprom1@55 { ++ compatible = "at,24c256"; ++ reg = <0x55>; ++ }; ++ ++ cape_eeprom2: cape_eeprom2@56 { ++ compatible = "at,24c256"; ++ reg = <0x56>; ++ }; ++ ++ cape_eeprom3: cape_eeprom3@57 { ++ compatible = "at,24c256"; ++ reg = <0x57>; ++ }; + }; + + /include/ "tps65217.dtsi" +-- +1.9.3 + diff --git a/arm-dts-am335x-bone-common-setup-default-pinmux-http.patch b/arm-dts-am335x-bone-common-setup-default-pinmux-http.patch new file mode 100644 index 00000000..180055d4 --- /dev/null +++ b/arm-dts-am335x-bone-common-setup-default-pinmux-http.patch @@ -0,0 +1,179 @@ +From: Robert Nelson <robertcnelson@gmail.com> +Date: Tue, 31 Dec 2013 14:18:00 -0600 +Subject: [PATCH] arm: dts: am335x-bone-common: setup default pinmux + http://elinux.org/Basic_Proto_Cape + +Signed-off-by: Robert Nelson <robertcnelson@gmail.com> +--- + arch/arm/boot/dts/am335x-bone-common.dtsi | 130 ++++++++++++++++++++++++++++++ + 1 file changed, 130 insertions(+) + +diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi +index c7357bcc7d5c..86cdb52dbf8a 100644 +--- a/arch/arm/boot/dts/am335x-bone-common.dtsi ++++ b/arch/arm/boot/dts/am335x-bone-common.dtsi +@@ -98,6 +98,13 @@ + >; + }; + ++ uart1_pins: pinmux_uart1_pins { ++ pinctrl-single,pins = < ++ 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ ++ 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ ++ >; ++ }; ++ + clkout2_pin: pinmux_clkout2_pin { + pinctrl-single,pins = < + 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ +@@ -178,6 +185,33 @@ + 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + >; + }; ++ ++ spi0_pins: pinmux_spi0_pins { ++ pinctrl-single,pins = < ++ 0x150 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */ ++ 0x154 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */ ++ 0x158 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ ++ 0x15c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ ++ >; ++ }; ++ ++ ehrpwm1_pin_p9_14: pinmux_ehrpwm1_pin_p9_14 { ++ pinctrl-single,pins = < ++ 0x048 0x6 /* P9_14 (ZCZ ball U14) | MODE 6 */ ++ >; ++ }; ++ ++ ehrpwm1_pin_p9_16: pinmux_ehrpwm1_pin_p9_16 { ++ pinctrl-single,pins = < ++ 0x04c 0x6 /* P9_16 (ZCZ ball T14) | MODE 6 */ ++ >; ++ }; ++ ++ ecap0_pin_p9_42: pinmux_ecap0_pin_p9_42 { ++ pinctrl-single,pins = < ++ 0x164 0x0 /* P9_42 (ZCZ ball C18) | MODE 0 */ ++ >; ++ }; + }; + + &uart0 { +@@ -187,6 +221,13 @@ + status = "okay"; + }; + ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ ++ status = "okay"; ++}; ++ + &usb { + status = "okay"; + }; +@@ -261,6 +302,56 @@ + }; + }; + ++&epwmss0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ecap0_pin_p9_42>; ++ status = "okay"; ++ ++ ecap@48300100 { ++ status = "okay"; ++ }; ++}; ++ ++&epwmss1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = < ++ &ehrpwm1_pin_p9_14 ++ &ehrpwm1_pin_p9_16 ++ >; ++ ++ status = "okay"; ++ ++ ehrpwm@48302200 { ++ status = "okay"; ++ }; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++ status = "okay"; ++ ++ spidev0: spi@0 { ++ compatible = "spidev"; ++ reg = <0>; ++ spi-max-frequency = <16000000>; ++ spi-cpha; ++ }; ++ ++ spidev1: spi@1 { ++ compatible = "spidev"; ++ reg = <1>; ++ spi-max-frequency = <16000000>; ++ }; ++}; ++ ++&tscadc { ++ status = "okay"; ++ adc { ++ ti,adc-channels = <4 5 6>; ++ }; ++}; ++ + /include/ "tps65217.dtsi" + + &tps { +@@ -337,3 +428,42 @@ + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; + cd-inverted; + }; ++ ++/ { ++ ocp { ++ //FIXME: these pwm's still need work, this guild isn't working.. ++ //http://elinux.org/EBC_Exercise_13_Pulse_Width_Modulation ++ pwm_test_P9_14@0 { ++ compatible = "pwm_test"; ++ pwms = <&ehrpwm1 0 500000 1>; ++ pwm-names = "PWM_P9_14"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ehrpwm1_pin_p9_14>; ++ enabled = <1>; ++ duty = <0>; ++ status = "okay"; ++ }; ++ ++ pwm_test_P9_16@0 { ++ compatible = "pwm_test"; ++ pwms = <&ehrpwm1 0 500000 1>; ++ pwm-names = "PWM_P9_16"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ehrpwm1_pin_p9_16>; ++ enabled = <1>; ++ duty = <0>; ++ status = "okay"; ++ }; ++ ++ pwm_test_P9_42 { ++ compatible = "pwm_test"; ++ pwms = <&ecap0 0 500000 1>; ++ pwm-names = "PWM_P9_42"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ecap0_pin_p9_42>; ++ enabled = <1>; ++ duty = <0>; ++ status = "okay"; ++ }; ++ }; ++}; +-- +1.9.3 + diff --git a/arm-dts-am335x-boneblack-add-cpu0-opp-points.patch b/arm-dts-am335x-boneblack-add-cpu0-opp-points.patch new file mode 100644 index 00000000..2c10bfa4 --- /dev/null +++ b/arm-dts-am335x-boneblack-add-cpu0-opp-points.patch @@ -0,0 +1,41 @@ +From: Robert Nelson <robertcnelson@gmail.com> +Date: Fri, 27 Dec 2013 13:14:19 -0600 +Subject: [PATCH] arm: dts: am335x-boneblack: add cpu0 opp points + +Signed-off-by: Robert Nelson <robertcnelson@gmail.com> +--- + arch/arm/boot/dts/am335x-boneblack.dts | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts +index bf5349165542..acfff3befff5 100644 +--- a/arch/arm/boot/dts/am335x-boneblack.dts ++++ b/arch/arm/boot/dts/am335x-boneblack.dts +@@ -66,6 +66,24 @@ + }; + + / { ++ cpus { ++ cpu@0 { ++ cpu0-supply = <&dcdc2_reg>; ++ /* ++ * To consider voltage drop between PMIC and SoC, ++ * tolerance value is reduced to 2% from 4% and ++ * voltage value is increased as a precaution. ++ */ ++ operating-points = < ++ /* kHz uV */ ++ 1000000 1325000 ++ 800000 1300000 ++ 600000 1112000 ++ 300000 969000 ++ >; ++ }; ++ }; ++ + hdmi { + compatible = "ti,tilcdc,slave"; + i2c = <&i2c0>; +-- +1.9.3 + diff --git a/arm-dts-am335x-boneblack-lcdc-add-panel-info.patch b/arm-dts-am335x-boneblack-lcdc-add-panel-info.patch new file mode 100644 index 00000000..00511f50 --- /dev/null +++ b/arm-dts-am335x-boneblack-lcdc-add-panel-info.patch @@ -0,0 +1,38 @@ +From: Robert Nelson <robertcnelson@gmail.com> +Date: Fri, 27 Dec 2013 13:05:09 -0600 +Subject: [PATCH] arm: dts: am335x-boneblack: lcdc add panel-info + +Bugzilla: 1012025 +Upstream-status: In beagle github repository https://github.com/beagleboard/kernel + +Signed-off-by: Robert Nelson <robertcnelson@gmail.com> +--- + arch/arm/boot/dts/am335x-boneblack.dts | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts +index 305975d3f531..bf5349165542 100644 +--- a/arch/arm/boot/dts/am335x-boneblack.dts ++++ b/arch/arm/boot/dts/am335x-boneblack.dts +@@ -73,5 +73,18 @@ + pinctrl-0 = <&nxp_hdmi_bonelt_pins>; + pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; + status = "okay"; ++ ++ panel-info { ++ bpp = <16>; ++ ac-bias = <255>; ++ ac-bias-intrpt = <0>; ++ dma-burst-sz = <16>; ++ fdd = <16>; ++ sync-edge = <1>; ++ sync-ctrl = <1>; ++ raster-order = <0>; ++ fifo-th = <0>; ++ invert-pxl-clk; ++ }; + }; + }; +-- +1.9.3 + diff --git a/arm-dts-sun7i-bananapi.patch b/arm-dts-sun7i-bananapi.patch new file mode 100644 index 00000000..94cbc9eb --- /dev/null +++ b/arm-dts-sun7i-bananapi.patch @@ -0,0 +1,213 @@ +From: Hans de Goede <hdegoede@redhat.com> +Date: Tue, 30 Sep 2014 14:29:26 +0100 +Subject: [PATCH] arm: dts sun7i bananapi + +The Banana Pi is an A20 based development board using Raspberry Pi compatible +IO headers. It comes with 1 GB RAM, 1 Gb ethernet, 2x USB host, sata, hdmi +and stereo audio out + various expenansion headers: + +Signed-off-by: Hans de Goede <hdegoede@xxxxxxxxxx> +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/sun7i-a20-bananapi.dts | 177 +++++++++++++++++++++++++++++++ + 2 files changed, 178 insertions(+) + create mode 100644 arch/arm/boot/dts/sun7i-a20-bananapi.dts + +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index b8c5cd3ddeb9..c3003a4460f5 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -414,6 +414,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \ + sun6i-a31-hummingbird.dtb \ + sun6i-a31-m9.dtb + dtb-$(CONFIG_MACH_SUN7I) += \ ++ sun7i-a20-bananapi.dtb \ + sun7i-a20-cubieboard2.dtb \ + sun7i-a20-cubietruck.dtb \ + sun7i-a20-i12-tvbox.dtb \ +diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/sun7i-a20-bananapi.dts +new file mode 100644 +index 000000000000..7214475a3c36 +--- /dev/null ++++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts +@@ -0,0 +1,177 @@ ++/* ++ * Copyright 2014 Hans de Goede <hdegoede@xxxxxxxxxx> ++ * ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++/dts-v1/; ++/include/ "sun7i-a20.dtsi" ++/include/ "sunxi-common-regulators.dtsi" ++ ++/ { ++ model = "LeMaker Banana Pi"; ++ compatible = "lemaker,bananapi", "allwinner,sun7i-a20"; ++ ++ soc@01c00000 { ++ mmc0: mmc@01c0f000 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 7 10 0>; /* PH10 */ ++ cd-inverted; ++ status = "okay"; ++ }; ++ ++ usbphy: phy@01c13400 { ++ usb1_vbus-supply = <®_usb1_vbus>; ++ usb2_vbus-supply = <®_usb2_vbus>; ++ status = "okay"; ++ }; ++ ++ ehci0: usb@01c14000 { ++ status = "okay"; ++ }; ++ ++ ohci0: usb@01c14400 { ++ status = "okay"; ++ }; ++ ++ ahci: sata@01c18000 { ++ status = "okay"; ++ }; ++ ++ ehci1: usb@01c1c000 { ++ status = "okay"; ++ }; ++ ++ ohci1: usb@01c1c400 { ++ status = "okay"; ++ }; ++ ++ pinctrl@01c20800 { ++ uart3_pins_bananapi: uart3_pin@0 { ++ allwinner,pins = "PH0", "PH1"; ++ allwinner,function = "uart3"; ++ allwinner,drive = <0>; ++ allwinner,pull = <0>; ++ }; ++ ++ mmc0_cd_pin_bananapi: mmc0_cd_pin@0 { ++ allwinner,pins = "PH10"; ++ allwinner,function = "gpio_in"; ++ allwinner,drive = <0>; ++ allwinner,pull = <1>; ++ }; ++ ++ gmac_power_pin_bananapi: gmac_power_pin@0 { ++ allwinner,pins = "PH23"; ++ allwinner,function = "gpio_out"; ++ allwinner,drive = <0>; ++ allwinner,pull = <0>; ++ }; ++ ++ led_pins_bananapi: led_pins@0 { ++ allwinner,pins = "PH24"; ++ allwinner,function = "gpio_out"; ++ allwinner,drive = <0>; ++ allwinner,pull = <0>; ++ }; ++ }; ++ ++ ir0: ir@01c21800 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ir0_pins_a>; ++ status = "okay"; ++ }; ++ ++ uart0: serial@01c28000 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++ }; ++ ++ uart3: serial@01c28c00 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pins_bananapi>; ++ status = "okay"; ++ }; ++ ++ uart7: serial@01c29c00 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart7_pins_a>; ++ status = "okay"; ++ }; ++ ++ i2c0: i2c@01c2ac00 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins_a>; ++ status = "okay"; ++ ++ axp209: pmic@34 { ++ compatible = "x-powers,axp209"; ++ reg = <0x34>; ++ interrupt-parent = <&nmi_intc>; ++ interrupts = <0 8>; ++ ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ i2c2: i2c@01c2b400 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins_a>; ++ status = "okay"; ++ }; ++ ++ gmac: ethernet@01c50000 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac_pins_rgmii_a>; ++ phy = <&phy1>; ++ phy-mode = "rgmii"; ++ phy-supply = <®_gmac_3v3>; ++ status = "okay"; ++ ++ phy1: ethernet-phy@1 { ++ reg = <1>; ++ }; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_pins_bananapi>; ++ ++ green { ++ label = "bananapi:green:usr"; ++ gpios = <&pio 7 24 0>; ++ }; ++ }; ++ ++ reg_usb1_vbus: usb1-vbus { ++ status = "okay"; ++ }; ++ ++ reg_usb2_vbus: usb2-vbus { ++ status = "okay"; ++ }; ++ ++ reg_gmac_3v3: gmac-3v3 { ++ compatible = "regulator-fixed"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac_power_pin_bananapi>; ++ regulator-name = "gmac-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <50000>; ++ enable-active-high; ++ gpio = <&pio 7 23 0>; ++ }; ++}; +-- +1.9.3 + diff --git a/arm-highbank-l2-reverts.patch b/arm-highbank-l2-reverts.patch new file mode 100644 index 00000000..f1e6d45d --- /dev/null +++ b/arm-highbank-l2-reverts.patch @@ -0,0 +1,60 @@ +From: Kyle McMartin <kmcmartin@redhat.com> +Date: Tue, 30 Sep 2014 16:19:47 -0400 +Subject: [PATCH] arm: highbank l2 reverts + +Revert some v3.16 changes to mach-highbank which broke L2 cache enablement. +Will debug upstream separately, but we need F22/21 running there. (#1139762) +--- + arch/arm/mach-highbank/highbank.c | 21 ++++++++++++--------- + 1 file changed, 12 insertions(+), 9 deletions(-) + +diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c +index 8c35ae4ff176..38e1dc3b4c6e 100644 +--- a/arch/arm/mach-highbank/highbank.c ++++ b/arch/arm/mach-highbank/highbank.c +@@ -51,13 +51,11 @@ static void __init highbank_scu_map_io(void) + } + + +-static void highbank_l2c310_write_sec(unsigned long val, unsigned reg) ++static void highbank_l2x0_disable(void) + { +- if (reg == L2X0_CTRL) +- highbank_smc1(0x102, val); +- else +- WARN_ONCE(1, "Highbank L2C310: ignoring write to reg 0x%x\n", +- reg); ++ outer_flush_all(); ++ /* Disable PL310 L2 Cache controller */ ++ highbank_smc1(0x102, 0x0); + } + + static void __init highbank_init_irq(void) +@@ -66,6 +64,14 @@ static void __init highbank_init_irq(void) + + if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9")) + highbank_scu_map_io(); ++ ++ /* Enable PL310 L2 Cache controller */ ++ if (IS_ENABLED(CONFIG_CACHE_L2X0) && ++ of_find_compatible_node(NULL, NULL, "arm,pl310-cache")) { ++ highbank_smc1(0x102, 0x1); ++ l2x0_of_init(0, ~0); ++ outer_cache.disable = highbank_l2x0_disable; ++ } + } + + static void highbank_power_off(void) +@@ -179,9 +185,6 @@ DT_MACHINE_START(HIGHBANK, "Highbank") + #if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE) + .dma_zone_size = (4ULL * SZ_1G), + #endif +- .l2c_aux_val = 0, +- .l2c_aux_mask = ~0, +- .l2c_write_sec = highbank_l2c310_write_sec, + .init_irq = highbank_init_irq, + .init_machine = highbank_init, + .dt_compat = highbank_match, +-- +1.9.3 + diff --git a/arm-imx6-utilite.patch b/arm-i.MX6-Utilite-device-dtb.patch index bb074720..0354f754 100644 --- a/arm-imx6-utilite.patch +++ b/arm-i.MX6-Utilite-device-dtb.patch @@ -1,5 +1,13 @@ +From: Peter Robinson <pbrobinson@gmail.com> +Date: Fri, 11 Jul 2014 00:10:56 +0100 +Subject: [PATCH] arm: i.MX6 Utilite device dtb + +--- + arch/arm/boot/dts/imx6q-cm-fx6.dts | 38 ++++++++++++++++++++++++++++++++++++++ + 1 file changed, 38 insertions(+) + diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts -index 99b46f8..8b6ddd1 100644 +index 99b46f8030ad..8b6ddd16dcc5 100644 --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts @@ -97,11 +97,49 @@ @@ -52,3 +60,6 @@ index 99b46f8..8b6ddd1 100644 + pinctrl-0 = <&pinctrl_usdhc3>; + status = "okay"; +}; +-- +1.9.3 + diff --git a/arm-qemu-fixdisplay.patch b/arm-qemu-fixdisplay.patch deleted file mode 100644 index 090193c2..00000000 --- a/arm-qemu-fixdisplay.patch +++ /dev/null @@ -1,472 +0,0 @@ -commit d10715be03bd8bad59ddc50236cb140c3bd73c7b -Author: Pawel Moll <pawel.moll@arm.com> -Date: Tue Jun 24 12:55:11 2014 +0100 - - video: ARM CLCD: Add DT support - - This patch adds basic DT bindings for the PL11x CLCD cells - and make their fbdev driver use them. - - Signed-off-by: Pawel Moll <pawel.moll@arm.com> - Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> - -diff --git a/Documentation/devicetree/bindings/video/arm,pl11x.txt b/Documentation/devicetree/bindings/video/arm,pl11x.txt -new file mode 100644 -index 0000000..3e3039a ---- /dev/null -+++ b/Documentation/devicetree/bindings/video/arm,pl11x.txt -@@ -0,0 +1,109 @@ -+* ARM PrimeCell Color LCD Controller PL110/PL111 -+ -+See also Documentation/devicetree/bindings/arm/primecell.txt -+ -+Required properties: -+ -+- compatible: must be one of: -+ "arm,pl110", "arm,primecell" -+ "arm,pl111", "arm,primecell" -+ -+- reg: base address and size of the control registers block -+ -+- interrupt-names: either the single entry "combined" representing a -+ combined interrupt output (CLCDINTR), or the four entries -+ "mbe", "vcomp", "lnbu", "fuf" representing the individual -+ CLCDMBEINTR, CLCDVCOMPINTR, CLCDLNBUINTR, CLCDFUFINTR interrupts -+ -+- interrupts: contains an interrupt specifier for each entry in -+ interrupt-names -+ -+- clock-names: should contain "clcdclk" and "apb_pclk" -+ -+- clocks: contains phandle and clock specifier pairs for the entries -+ in the clock-names property. See -+ Documentation/devicetree/binding/clock/clock-bindings.txt -+ -+Optional properties: -+ -+- memory-region: phandle to a node describing memory (see -+ Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) -+ to be used for the framebuffer; if not present, the framebuffer -+ may be located anywhere in the memory -+ -+- max-memory-bandwidth: maximum bandwidth in bytes per second that the -+ cell's memory interface can handle; if not present, the memory -+ interface is fast enough to handle all possible video modes -+ -+Required sub-nodes: -+ -+- port: describes LCD panel signals, following the common binding -+ for video transmitter interfaces; see -+ Documentation/devicetree/bindings/media/video-interfaces.txt; -+ when it is a TFT panel, the port's endpoint must define the -+ following property: -+ -+ - arm,pl11x,tft-r0g0b0-pads: an array of three 32-bit values, -+ defining the way CLD pads are wired up; first value -+ contains index of the "CLD" external pin (pad) used -+ as R0 (first bit of the red component), second value -+ index of the pad used as G0, third value index of the -+ pad used as B0, see also "LCD panel signal multiplexing -+ details" paragraphs in the PL110/PL111 Technical -+ Reference Manuals; this implicitly defines available -+ color modes, for example: -+ - PL111 TFT 4:4:4 panel: -+ arm,pl11x,tft-r0g0b0-pads = <4 15 20>; -+ - PL110 TFT (1:)5:5:5 panel: -+ arm,pl11x,tft-r0g0b0-pads = <1 7 13>; -+ - PL111 TFT (1:)5:5:5 panel: -+ arm,pl11x,tft-r0g0b0-pads = <3 11 19>; -+ - PL111 TFT 5:6:5 panel: -+ arm,pl11x,tft-r0g0b0-pads = <3 10 19>; -+ - PL110 and PL111 TFT 8:8:8 panel: -+ arm,pl11x,tft-r0g0b0-pads = <0 8 16>; -+ - PL110 and PL111 TFT 8:8:8 panel, R & B components swapped: -+ arm,pl11x,tft-r0g0b0-pads = <16 8 0>; -+ -+ -+Example: -+ -+ clcd@10020000 { -+ compatible = "arm,pl111", "arm,primecell"; -+ reg = <0x10020000 0x1000>; -+ interrupt-names = "combined"; -+ interrupts = <0 44 4>; -+ clocks = <&oscclk1>, <&oscclk2>; -+ clock-names = "clcdclk", "apb_pclk"; -+ max-memory-bandwidth = <94371840>; /* Bps, 1024x768@60 16bpp */ -+ -+ port { -+ clcd_pads: endpoint { -+ remote-endpoint = <&clcd_panel>; -+ arm,pl11x,tft-r0g0b0-pads = <0 8 16>; -+ }; -+ }; -+ -+ }; -+ -+ panel { -+ compatible = "panel-dpi"; -+ -+ port { -+ clcd_panel: endpoint { -+ remote-endpoint = <&clcd_pads>; -+ }; -+ }; -+ -+ panel-timing { -+ clock-frequency = <25175000>; -+ hactive = <640>; -+ hback-porch = <40>; -+ hfront-porch = <24>; -+ hsync-len = <96>; -+ vactive = <480>; -+ vback-porch = <32>; -+ vfront-porch = <11>; -+ vsync-len = <2>; -+ }; -+ }; -diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig -index 4a7098f..6f451ad 100644 ---- a/drivers/video/fbdev/Kconfig -+++ b/drivers/video/fbdev/Kconfig -@@ -280,6 +280,7 @@ config FB_ARMCLCD - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT -+ select VIDEOMODE_HELPERS if OF - help - This framebuffer device driver is for the ARM PrimeCell PL110 - Colour LCD controller. ARM PrimeCells provide the building -diff --git a/drivers/video/fbdev/amba-clcd.c b/drivers/video/fbdev/amba-clcd.c -index 14d6b37..23b3519 100644 ---- a/drivers/video/fbdev/amba-clcd.c -+++ b/drivers/video/fbdev/amba-clcd.c -@@ -26,6 +26,13 @@ - #include <linux/amba/clcd.h> - #include <linux/clk.h> - #include <linux/hardirq.h> -+#include <linux/dma-mapping.h> -+#include <linux/of.h> -+#include <linux/of_address.h> -+#include <linux/of_graph.h> -+#include <video/display_timing.h> -+#include <video/of_display_timing.h> -+#include <video/videomode.h> - - #include <asm/sizes.h> - -@@ -543,6 +550,259 @@ static int clcdfb_register(struct clcd_fb *fb) - return ret; - } - -+#ifdef CONFIG_OF -+static int clcdfb_of_get_dpi_panel_mode(struct device_node *node, -+ struct fb_videomode *mode) -+{ -+ int err; -+ struct display_timing timing; -+ struct videomode video; -+ -+ err = of_get_display_timing(node, "panel-timing", &timing); -+ if (err) -+ return err; -+ -+ videomode_from_timing(&timing, &video); -+ -+ err = fb_videomode_from_videomode(&video, mode); -+ if (err) -+ return err; -+ -+ return 0; -+} -+ -+static int clcdfb_snprintf_mode(char *buf, int size, struct fb_videomode *mode) -+{ -+ return snprintf(buf, size, "%ux%u@%u", mode->xres, mode->yres, -+ mode->refresh); -+} -+ -+static int clcdfb_of_get_mode(struct device *dev, struct device_node *endpoint, -+ struct fb_videomode *mode) -+{ -+ int err; -+ struct device_node *panel; -+ char *name; -+ int len; -+ -+ panel = of_graph_get_remote_port_parent(endpoint); -+ if (!panel) -+ return -ENODEV; -+ -+ /* Only directly connected DPI panels supported for now */ -+ if (of_device_is_compatible(panel, "panel-dpi")) -+ err = clcdfb_of_get_dpi_panel_mode(panel, mode); -+ else -+ err = -ENOENT; -+ if (err) -+ return err; -+ -+ len = clcdfb_snprintf_mode(NULL, 0, mode); -+ name = devm_kzalloc(dev, len + 1, GFP_KERNEL); -+ clcdfb_snprintf_mode(name, len + 1, mode); -+ mode->name = name; -+ -+ return 0; -+} -+ -+static int clcdfb_of_init_tft_panel(struct clcd_fb *fb, u32 r0, u32 g0, u32 b0) -+{ -+ static struct { -+ unsigned int part; -+ u32 r0, g0, b0; -+ u32 caps; -+ } panels[] = { -+ { 0x110, 1, 7, 13, CLCD_CAP_5551 }, -+ { 0x110, 0, 8, 16, CLCD_CAP_888 }, -+ { 0x111, 4, 14, 20, CLCD_CAP_444 }, -+ { 0x111, 3, 11, 19, CLCD_CAP_444 | CLCD_CAP_5551 }, -+ { 0x111, 3, 10, 19, CLCD_CAP_444 | CLCD_CAP_5551 | -+ CLCD_CAP_565 }, -+ { 0x111, 0, 8, 16, CLCD_CAP_444 | CLCD_CAP_5551 | -+ CLCD_CAP_565 | CLCD_CAP_888 }, -+ }; -+ int i; -+ -+ /* Bypass pixel clock divider, data output on the falling edge */ -+ fb->panel->tim2 = TIM2_BCD | TIM2_IPC; -+ -+ /* TFT display, vert. comp. interrupt at the start of the back porch */ -+ fb->panel->cntl |= CNTL_LCDTFT | CNTL_LCDVCOMP(1); -+ -+ fb->panel->caps = 0; -+ -+ /* Match the setup with known variants */ -+ for (i = 0; i < ARRAY_SIZE(panels) && !fb->panel->caps; i++) { -+ if (amba_part(fb->dev) != panels[i].part) -+ continue; -+ if (g0 != panels[i].g0) -+ continue; -+ if (r0 == panels[i].r0 && b0 == panels[i].b0) -+ fb->panel->caps = panels[i].caps & CLCD_CAP_RGB; -+ if (r0 == panels[i].b0 && b0 == panels[i].r0) -+ fb->panel->caps = panels[i].caps & CLCD_CAP_BGR; -+ } -+ -+ return fb->panel->caps ? 0 : -EINVAL; -+} -+ -+static int clcdfb_of_init_display(struct clcd_fb *fb) -+{ -+ struct device_node *endpoint; -+ int err; -+ u32 max_bandwidth; -+ u32 tft_r0b0g0[3]; -+ -+ fb->panel = devm_kzalloc(&fb->dev->dev, sizeof(*fb->panel), GFP_KERNEL); -+ if (!fb->panel) -+ return -ENOMEM; -+ -+ endpoint = of_graph_get_next_endpoint(fb->dev->dev.of_node, NULL); -+ if (!endpoint) -+ return -ENODEV; -+ -+ err = clcdfb_of_get_mode(&fb->dev->dev, endpoint, &fb->panel->mode); -+ if (err) -+ return err; -+ -+ err = of_property_read_u32(fb->dev->dev.of_node, "max-memory-bandwidth", -+ &max_bandwidth); -+ if (!err) -+ fb->panel->bpp = 8 * max_bandwidth / (fb->panel->mode.xres * -+ fb->panel->mode.yres * fb->panel->mode.refresh); -+ else -+ fb->panel->bpp = 32; -+ -+#ifdef CONFIG_CPU_BIG_ENDIAN -+ fb->panel->cntl |= CNTL_BEBO; -+#endif -+ fb->panel->width = -1; -+ fb->panel->height = -1; -+ -+ if (of_property_read_u32_array(endpoint, -+ "arm,pl11x,tft-r0g0b0-pads", -+ tft_r0b0g0, ARRAY_SIZE(tft_r0b0g0)) == 0) -+ return clcdfb_of_init_tft_panel(fb, tft_r0b0g0[0], -+ tft_r0b0g0[1], tft_r0b0g0[2]); -+ -+ return -ENOENT; -+} -+ -+static int clcdfb_of_vram_setup(struct clcd_fb *fb) -+{ -+ int err; -+ struct device_node *memory; -+ u64 size; -+ -+ err = clcdfb_of_init_display(fb); -+ if (err) -+ return err; -+ -+ memory = of_parse_phandle(fb->dev->dev.of_node, "memory-region", 0); -+ if (!memory) -+ return -ENODEV; -+ -+ fb->fb.screen_base = of_iomap(memory, 0); -+ if (!fb->fb.screen_base) -+ return -ENOMEM; -+ -+ fb->fb.fix.smem_start = of_translate_address(memory, -+ of_get_address(memory, 0, &size, NULL)); -+ fb->fb.fix.smem_len = size; -+ -+ return 0; -+} -+ -+static int clcdfb_of_vram_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) -+{ -+ unsigned long off, user_size, kernel_size; -+ -+ -+ off = vma->vm_pgoff << PAGE_SHIFT; -+ user_size = vma->vm_end - vma->vm_start; -+ kernel_size = fb->fb.fix.smem_len; -+ -+ if (off >= kernel_size || user_size > (kernel_size - off)) -+ return -ENXIO; -+ -+ return remap_pfn_range(vma, vma->vm_start, -+ __phys_to_pfn(fb->fb.fix.smem_start) + vma->vm_pgoff, -+ user_size, -+ pgprot_writecombine(vma->vm_page_prot)); -+} -+ -+static void clcdfb_of_vram_remove(struct clcd_fb *fb) -+{ -+ iounmap(fb->fb.screen_base); -+} -+ -+static int clcdfb_of_dma_setup(struct clcd_fb *fb) -+{ -+ unsigned long framesize; -+ dma_addr_t dma; -+ int err; -+ -+ err = clcdfb_of_init_display(fb); -+ if (err) -+ return err; -+ -+ framesize = fb->panel->mode.xres * fb->panel->mode.yres * -+ fb->panel->bpp / 8; -+ fb->fb.screen_base = dma_alloc_coherent(&fb->dev->dev, framesize, -+ &dma, GFP_KERNEL); -+ if (!fb->fb.screen_base) -+ return -ENOMEM; -+ -+ fb->fb.fix.smem_start = dma; -+ fb->fb.fix.smem_len = framesize; -+ -+ return 0; -+} -+ -+static int clcdfb_of_dma_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) -+{ -+ return dma_mmap_writecombine(&fb->dev->dev, vma, fb->fb.screen_base, -+ fb->fb.fix.smem_start, fb->fb.fix.smem_len); -+} -+ -+static void clcdfb_of_dma_remove(struct clcd_fb *fb) -+{ -+ dma_free_coherent(&fb->dev->dev, fb->fb.fix.smem_len, -+ fb->fb.screen_base, fb->fb.fix.smem_start); -+} -+ -+static struct clcd_board *clcdfb_of_get_board(struct amba_device *dev) -+{ -+ struct clcd_board *board = devm_kzalloc(&dev->dev, sizeof(*board), -+ GFP_KERNEL); -+ struct device_node *node = dev->dev.of_node; -+ -+ if (!board) -+ return NULL; -+ -+ board->name = of_node_full_name(node); -+ board->caps = CLCD_CAP_ALL; -+ board->check = clcdfb_check; -+ board->decode = clcdfb_decode; -+ if (of_find_property(node, "memory-region", NULL)) { -+ board->setup = clcdfb_of_vram_setup; -+ board->mmap = clcdfb_of_vram_mmap; -+ board->remove = clcdfb_of_vram_remove; -+ } else { -+ board->setup = clcdfb_of_dma_setup; -+ board->mmap = clcdfb_of_dma_mmap; -+ board->remove = clcdfb_of_dma_remove; -+ } -+ -+ return board; -+} -+#else -+static struct clcd_board *clcdfb_of_get_board(struct amba_dev *dev) -+{ -+ return NULL; -+} -+#endif -+ - static int clcdfb_probe(struct amba_device *dev, const struct amba_id *id) - { - struct clcd_board *board = dev_get_platdata(&dev->dev); -@@ -550,6 +810,9 @@ static int clcdfb_probe(struct amba_device *dev, const struct amba_id *id) - int ret; - - if (!board) -+ board = clcdfb_of_get_board(dev); -+ -+ if (!board) - return -EINVAL; - - ret = dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32)); -commit 1d5167b72ca05b2096760e1200fcd53b5f9a7562 -Author: Pawel Moll <pawel.moll@arm.com> -Date: Fri Aug 1 15:43:34 2014 +0100 - - video: ARM CLCD: Fix DT-related build problems - - This patch fixes the following error when !CONFIG_OF: - - drivers/video/fbdev/amba-clcd.c:800:54: warning: ‘struct amba_dev’ declared inside parameter list [enabled by default] - static struct clcd_board *clcdfb_of_get_board(struct amba_dev *dev) - ^ - and adds a missing Kconfig select causing this - when CONFIG_OF && !CONFIG_FB_MODE_HELPERS: - - drivers/video/fbdev/amba-clcd.c:567: undefined reference to `fb_videomode_from_videomode' - - Reported-by: Fengguang Wu <fengguang.wu@intel.com> - Signed-off-by: Pawel Moll <pawel.moll@arm.com> - Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> - -diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig -index 6f451ad..ef94623 100644 ---- a/drivers/video/fbdev/Kconfig -+++ b/drivers/video/fbdev/Kconfig -@@ -280,6 +280,7 @@ config FB_ARMCLCD - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT -+ select FB_MODE_HELPERS if OF - select VIDEOMODE_HELPERS if OF - help - This framebuffer device driver is for the ARM PrimeCell PL110 -diff --git a/drivers/video/fbdev/amba-clcd.c b/drivers/video/fbdev/amba-clcd.c -index 23b3519..beadd3e 100644 ---- a/drivers/video/fbdev/amba-clcd.c -+++ b/drivers/video/fbdev/amba-clcd.c -@@ -797,7 +797,7 @@ static struct clcd_board *clcdfb_of_get_board(struct amba_device *dev) - return board; - } - #else --static struct clcd_board *clcdfb_of_get_board(struct amba_dev *dev) -+static struct clcd_board *clcdfb_of_get_board(struct amba_device *dev) - { - return NULL; - } diff --git a/arm-tegra-drmdetection.patch b/arm-tegra-drmdetection.patch deleted file mode 100644 index d8404051..00000000 --- a/arm-tegra-drmdetection.patch +++ /dev/null @@ -1,111 +0,0 @@ -From: Stephen Warren <swarren@xxxxxxxxxx> - -When tegra-drm.ko is built as a module, these MODULE_DEVICE_TABLEs allow -the module to be auto-loaded since the module will match the devices -instantiated from device tree. - -(Notes for stable: in 3.14+, just git rm any conflicting file, since they -are added in later kernels. For 3.13 and below, manual merging will be -needed) - -Cc: <stable@xxxxxxxxxxxxxxx> -Signed-off-by: Stephen Warren <swarren@xxxxxxxxxx> ---- -v2: Remove change to drm.c, since the match table there isn't used for -probing. ---- - drivers/gpu/drm/tegra/dc.c | 1 + - drivers/gpu/drm/tegra/dpaux.c | 1 + - drivers/gpu/drm/tegra/dsi.c | 1 + - drivers/gpu/drm/tegra/gr2d.c | 1 + - drivers/gpu/drm/tegra/gr3d.c | 1 + - drivers/gpu/drm/tegra/hdmi.c | 1 + - drivers/gpu/drm/tegra/sor.c | 1 + - 7 files changed, 7 insertions(+) - -diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c -index ef40381f3909..48c3bc460eef 100644 ---- a/drivers/gpu/drm/tegra/dc.c -+++ b/drivers/gpu/drm/tegra/dc.c -@@ -1303,6 +1303,7 @@ static const struct of_device_id tegra_dc_of_match[] = { - /* sentinel */ - } - }; -+MODULE_DEVICE_TABLE(of, tegra_dc_of_match); - - static int tegra_dc_parse_dt(struct tegra_dc *dc) - { -diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c -index 3f132e356e9c..708f783ead47 100644 ---- a/drivers/gpu/drm/tegra/dpaux.c -+++ b/drivers/gpu/drm/tegra/dpaux.c -@@ -382,6 +382,7 @@ static const struct of_device_id tegra_dpaux_of_match[] = { - { .compatible = "nvidia,tegra124-dpaux", }, - { }, - }; -+MODULE_DEVICE_TABLE(of, tegra_dpaux_of_match); - - struct platform_driver tegra_dpaux_driver = { - .driver = { -diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c -index bd56f2affa78..97c409f10456 100644 ---- a/drivers/gpu/drm/tegra/dsi.c -+++ b/drivers/gpu/drm/tegra/dsi.c -@@ -982,6 +982,7 @@ static const struct of_device_id tegra_dsi_of_match[] = { - { .compatible = "nvidia,tegra114-dsi", }, - { }, - }; -+MODULE_DEVICE_TABLE(of, tegra_dsi_of_match); - - struct platform_driver tegra_dsi_driver = { - .driver = { -diff --git a/drivers/gpu/drm/tegra/gr2d.c b/drivers/gpu/drm/tegra/gr2d.c -index 7c53941f2a9e..02cd3e37a6ec 100644 ---- a/drivers/gpu/drm/tegra/gr2d.c -+++ b/drivers/gpu/drm/tegra/gr2d.c -@@ -121,6 +121,7 @@ static const struct of_device_id gr2d_match[] = { - { .compatible = "nvidia,tegra20-gr2d" }, - { }, - }; -+MODULE_DEVICE_TABLE(of, gr2d_match); - - static const u32 gr2d_addr_regs[] = { - GR2D_UA_BASE_ADDR, -diff --git a/drivers/gpu/drm/tegra/gr3d.c b/drivers/gpu/drm/tegra/gr3d.c -index 30f5ba9bd6d0..2bea2b2d204e 100644 ---- a/drivers/gpu/drm/tegra/gr3d.c -+++ b/drivers/gpu/drm/tegra/gr3d.c -@@ -130,6 +130,7 @@ static const struct of_device_id tegra_gr3d_match[] = { - { .compatible = "nvidia,tegra20-gr3d" }, - { } - }; -+MODULE_DEVICE_TABLE(of, tegra_gr3d_match); - - static const u32 gr3d_addr_regs[] = { - GR3D_IDX_ATTRIBUTE( 0), -diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c -index a0b8d8539d07..84ea0c8b47f7 100644 ---- a/drivers/gpu/drm/tegra/hdmi.c -+++ b/drivers/gpu/drm/tegra/hdmi.c -@@ -1370,6 +1370,7 @@ static const struct of_device_id tegra_hdmi_of_match[] = { - { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config }, - { }, - }; -+MODULE_DEVICE_TABLE(of, tegra_hdmi_of_match); - - static int tegra_hdmi_probe(struct platform_device *pdev) - { -diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c -index 27c979b50111..061a5c501124 100644 ---- a/drivers/gpu/drm/tegra/sor.c -+++ b/drivers/gpu/drm/tegra/sor.c -@@ -1455,6 +1455,7 @@ static const struct of_device_id tegra_sor_of_match[] = { - { .compatible = "nvidia,tegra124-sor", }, - { }, - }; -+MODULE_DEVICE_TABLE(of, tegra_sor_of_match); - - struct platform_driver tegra_sor_driver = { - .driver = { --- -1.8.1.5 diff --git a/arm-tegra-usb-no-reset-linux33.patch b/arm-tegra-usb-no-reset-linux33.patch deleted file mode 100644 index 342e80f5..00000000 --- a/arm-tegra-usb-no-reset-linux33.patch +++ /dev/null @@ -1,16 +0,0 @@ ---- linux-3.3.4-3.fc17.x86_64_orig/drivers/usb/core/hub.c 2012-05-02 20:08:18.421685932 -0400
-+++ linux-3.3.4-3.fc17.x86_64/drivers/usb/core/hub.c 2012-05-02 20:30:36.565865425 -0400
-@@ -3484,6 +3484,13 @@ static void hub_events(void)
- (u16) hub->change_bits[0],
- (u16) hub->event_bits[0]);
-
-+ /* Don't disconnect USB-SATA on TrimSlice */
-+ if (strcmp(dev_name(hdev->bus->controller), "tegra-ehci.0") == 0) {
-+ if ((hdev->state == 7) && (hub->change_bits[0] == 0) &&
-+ (hub->event_bits[0] == 0x2))
-+ hub->event_bits[0] = 0;
-+ }
-+
- /* Lock the device, then check to see if we were
- * disconnected while waiting for the lock to succeed. */
- usb_lock_device(hdev);
diff --git a/asus-wmi-Add-a-no-backlight-quirk.patch b/asus-wmi-Add-a-no-backlight-quirk.patch deleted file mode 100644 index 3a99afef..00000000 --- a/asus-wmi-Add-a-no-backlight-quirk.patch +++ /dev/null @@ -1,69 +0,0 @@ -Bugzilla: 1097436 -Upstream-status: Sent upstream for 3.16 - -From f6fad201a0e4584e9826a2deb8ebbfccdb8cb13b Mon Sep 17 00:00:00 2001 -From: Hans de Goede <hdegoede@redhat.com> -Date: Mon, 2 Jun 2014 17:41:01 +0200 -Subject: [PATCH 04/14] asus-wmi: Add a no backlight quirk - -Some Asus motherboards for desktop PC-s export an acpi-video and -an asus-wmi interface advertising backlight support. Add a quirk to allow -to blacklist these so that desktop environments such as gnome don't start -showing nonsense brightness controls. - -https://bugzilla.redhat.com/show_bug.cgi?id=1097436 - -Signed-off-by: Hans de Goede <hdegoede@redhat.com> ---- - drivers/platform/x86/asus-wmi.c | 8 ++++++-- - drivers/platform/x86/asus-wmi.h | 1 + - 2 files changed, 7 insertions(+), 2 deletions(-) - -diff --git a/drivers/platform/x86/asus-wmi.c b/drivers/platform/x86/asus-wmi.c -index c5e082fb82fa..6f73dc5125ca 100644 ---- a/drivers/platform/x86/asus-wmi.c -+++ b/drivers/platform/x86/asus-wmi.c -@@ -1272,6 +1272,9 @@ static int asus_wmi_backlight_init(struct asus_wmi *asus) - int max; - int power; - -+ if (asus->driver->quirks->no_backlight) -+ return -ENODEV; -+ - max = read_brightness_max(asus); - - if (max == -ENODEV) -@@ -1370,7 +1373,7 @@ static void asus_wmi_notify(u32 value, void *context) - code = ASUS_WMI_BRN_DOWN; - - if (code == ASUS_WMI_BRN_DOWN || code == ASUS_WMI_BRN_UP) { -- if (!acpi_video_backlight_support()) { -+ if (asus->backlight_device) { - asus_wmi_backlight_notify(asus, orig_code); - goto exit; - } -@@ -1773,7 +1776,8 @@ static int asus_wmi_add(struct platform_device *pdev) - if (err) - goto fail_rfkill; - -- if (asus->driver->quirks->wmi_backlight_power) -+ if (asus->driver->quirks->wmi_backlight_power || -+ asus->driver->quirks->no_backlight) - acpi_video_dmi_promote_vendor(); - if (!acpi_video_backlight_support()) { - pr_info("Disabling ACPI video driver\n"); -diff --git a/drivers/platform/x86/asus-wmi.h b/drivers/platform/x86/asus-wmi.h -index 4da4c8bafe70..cc47efe14974 100644 ---- a/drivers/platform/x86/asus-wmi.h -+++ b/drivers/platform/x86/asus-wmi.h -@@ -42,6 +42,7 @@ struct quirk_entry { - bool scalar_panel_brightness; - bool store_backlight_power; - bool wmi_backlight_power; -+ bool no_backlight; - int wapf; - /* - * For machines with AMD graphic chips, it will send out WMI event --- -1.9.0 - diff --git a/asus-wmi-Restrict-debugfs-interface-when-module-load.patch b/asus-wmi-Restrict-debugfs-interface-when-module-load.patch new file mode 100644 index 00000000..babfe87e --- /dev/null +++ b/asus-wmi-Restrict-debugfs-interface-when-module-load.patch @@ -0,0 +1,53 @@ +From: Matthew Garrett <matthew.garrett@nebula.com> +Date: Fri, 9 Mar 2012 08:46:50 -0500 +Subject: [PATCH] asus-wmi: Restrict debugfs interface when module loading is + restricted + +We have no way of validating what all of the Asus WMI methods do on a +given machine, and there's a risk that some will allow hardware state to +be manipulated in such a way that arbitrary code can be executed in the +kernel, circumventing module loading restrictions. Prevent that if any of +these features are enabled. + +Signed-off-by: Matthew Garrett <matthew.garrett@nebula.com> +--- + drivers/platform/x86/asus-wmi.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/drivers/platform/x86/asus-wmi.c b/drivers/platform/x86/asus-wmi.c +index 21fc932da3a1..c6d42ad95c08 100644 +--- a/drivers/platform/x86/asus-wmi.c ++++ b/drivers/platform/x86/asus-wmi.c +@@ -1590,6 +1590,9 @@ static int show_dsts(struct seq_file *m, void *data) + int err; + u32 retval = -1; + ++ if (secure_modules()) ++ return -EPERM; ++ + err = asus_wmi_get_devstate(asus, asus->debug.dev_id, &retval); + + if (err < 0) +@@ -1606,6 +1609,9 @@ static int show_devs(struct seq_file *m, void *data) + int err; + u32 retval = -1; + ++ if (secure_modules()) ++ return -EPERM; ++ + err = asus_wmi_set_devstate(asus->debug.dev_id, asus->debug.ctrl_param, + &retval); + +@@ -1630,6 +1636,9 @@ static int show_call(struct seq_file *m, void *data) + union acpi_object *obj; + acpi_status status; + ++ if (secure_modules()) ++ return -EPERM; ++ + status = wmi_evaluate_method(ASUS_WMI_MGMT_GUID, + 1, asus->debug.method_id, + &input, &output); +-- +1.9.3 + diff --git a/ath9k_rx_dma_stop_check.patch b/ath9k-rx-dma-stop-check.patch index 606eb1c6..32884eb6 100644 --- a/ath9k_rx_dma_stop_check.patch +++ b/ath9k-rx-dma-stop-check.patch @@ -1,6 +1,16 @@ +From: "kernel-team@fedoraproject.org" <kernel-team@fedoraproject.org> +Date: Wed, 6 Feb 2013 09:57:47 -0500 +Subject: [PATCH] ath9k: rx dma stop check + +--- + drivers/net/wireless/ath/ath9k/mac.c | 12 +++++++++++- + 1 file changed, 11 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c +index 275205ab5f15..bb842623bdf6 100644 --- a/drivers/net/wireless/ath/ath9k/mac.c +++ b/drivers/net/wireless/ath/ath9k/mac.c -@@ -689,7 +689,7 @@ bool ath9k_hw_stopdmarecv(struct ath_hw +@@ -700,7 +700,7 @@ bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset) { #define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */ struct ath_common *common = ath9k_hw_common(ah); @@ -9,7 +19,7 @@ int i; /* Enable access to the DMA observation bus */ -@@ -719,6 +719,16 @@ bool ath9k_hw_stopdmarecv(struct ath_hw +@@ -730,6 +730,16 @@ bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset) } if (i == 0) { @@ -26,3 +36,6 @@ ath_err(common, "DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x DMADBG_7=0x%08x\n", AH_RX_STOP_DMA_TIMEOUT / 1000, +-- +1.9.3 + diff --git a/config-arm-generic b/config-arm-generic index 38a00166..1f07efa9 100644 --- a/config-arm-generic +++ b/config-arm-generic @@ -8,6 +8,7 @@ CONFIG_HW_PERF_EVENTS=y CONFIG_NFS_FS=y CONFIG_CRASH=m +CONFIG_CC_STACKPROTECTOR=y # CONFIG_PID_IN_CONTEXTIDR is not set @@ -42,6 +43,7 @@ CONFIG_HAVE_PERF_USER_STACK_DUMP=y # ARM AMBA generic HW CONFIG_ARM_AMBA=y CONFIG_ARM_CCI=y +CONFIG_ARM_CCN=y CONFIG_ARM_DMA_USE_IOMMU=y CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8 CONFIG_ARM_GIC=y @@ -77,15 +79,12 @@ CONFIG_GENERIC_CPUFREQ_CPU0=m # Device tree CONFIG_DTC=y CONFIG_DMA_OF=y -CONFIG_PROC_DEVICETREE=y CONFIG_OF=y CONFIG_OF_ADDRESS=y -CONFIG_OF_DEVICE=y CONFIG_OF_DYNAMIC=y CONFIG_OF_EARLY_FLATTREE=y CONFIG_OF_FLATTREE=y CONFIG_OF_GPIO=y -CONFIG_OF_I2C=m CONFIG_OF_IOMMU=y CONFIG_OF_IRQ=y CONFIG_OF_MDIO=m @@ -101,14 +100,13 @@ CONFIG_THERMAL_OF=y # External Connectors CONFIG_EXTCON=m -CONFIG_OF_EXTCON=m CONFIG_EXTCON_GPIO=m CONFIG_EXTCON_ADC_JACK=m +# CONFIG_EXTCON_SM5502 is not set # MTD CONFIG_MTD_BLKDEVS=m CONFIG_MTD_BLOCK=m -CONFIG_MTD_CHAR=m CONFIG_MTD_CFI=m CONFIG_MTD_CFI_INTELEXT=m CONFIG_MTD_CFI_AMDSTD=m @@ -177,18 +175,27 @@ CONFIG_CMA_AREAS=7 # CONFIG_CRYPTO_TEST is not set # CONFIG_TRANSPARENT_HUGEPAGE is not set # CONFIG_XEN is not set - -# CONFIG_MMC_DW_SOCFPGA is not set +# CONFIG_DRM_RCAR_DU is not set +# CONFIG_I2C_RCAR is not set +# CONFIG_DRM_SHMOBILE is not set +# CONFIG_I2C_SH_MOBILE is not set # CONFIG_I2C_NOMADIK is not set -# CONFIG_LEDS_RENESAS_TPU is not set +# CONFIG_IRQ_DOMAIN_DEBUG is not set +# CONFIG_LOCK_STAT is not set + # CONFIG_DRM_ARMADA is not set +# CONFIG_DRM_TEGRA is not set +# CONFIG_SHMOBILE_IOMMU is not set + # CONFIG_COMMON_CLK_SI570 is not set # CONFIG_COMMON_CLK_QCOM is not set -# CONFIG_IRQ_DOMAIN_DEBUG is not set # CONFIG_ARM_PTDUMP is not set -### turn off things which make no sense on ARM +# CONFIG_PATA_PLATFORM is not set +# CONFIG_USB_ULPI is not set + +### turn off things which make no sense on embedded SoC # core @@ -201,8 +208,6 @@ CONFIG_CMA_AREAS=7 # CONFIG_ISDN is not set # CONFIG_GAMEPORT is not set # CONFIG_AGP is not set -# CONFIG_PATA_PLATFORM is not set -# CONFIG_USB_ULPI is not set # netdrv @@ -220,7 +225,6 @@ CONFIG_CMA_AREAS=7 # CONFIG_NET_VENDOR_SUN is not set # CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_NET_VENDOR_XIRCOM is not set -# CONFIG_NET_PCMCIA is not set # scsi @@ -241,10 +245,17 @@ CONFIG_CMA_AREAS=7 # CONFIG_SCSI_MPT3SAS is not set # serial -# CONFIG_SERIAL_SH_SCI is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_IFX6X60 is not set # drm # CONFIG_DRM_VMWGFX is not set # CONFIG_IMX_IPUV3_CORE is not set # CONFIG_DEBUG_SET_MODULE_RONX is not set + +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_BMP085_SPI is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_SPI_ROCKCHIP is not set diff --git a/config-arm64 b/config-arm64 index 082ceda8..0310d91c 100644 --- a/config-arm64 +++ b/config-arm64 @@ -9,7 +9,6 @@ CONFIG_SCHED_SMT=y # arm64 only SoCs CONFIG_ARCH_XGENE=y -# CONFIG_ALWAYS_USE_PERSISTENT_CLOCK is not set # CONFIG_AMBA_PL08X is not set CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y CONFIG_ARCH_REQUIRE_GPIOLIB=y @@ -26,11 +25,9 @@ CONFIG_CMDLINE="console=ttyAMA0" # CONFIG_CMDLINE_FORCE is not set CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_GENERIC_ACL=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_CLOCKEVENTS_BUILD=y CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_IO=y CONFIG_GENERIC_PCI_IOMAP=y @@ -81,6 +78,10 @@ CONFIG_CRYPTO_AES_ARM64_CE=m CONFIG_CRYPTO_AES_ARM64_CE_CCM=m CONFIG_CRYPTO_AES_ARM64_CE_BLK=m CONFIG_CRYPTO_AES_ARM64_NEON_BLK=m +CONFIG_CRYPTO_DEV_CCP=y +CONFIG_CRYPTO_DEV_CCP_DD=m +CONFIG_CRYPTO_DEV_CCP_CRYPTO=m + # APM Xgene CONFIG_POWER_RESET_XGENE=y @@ -111,3 +112,27 @@ CONFIG_PCI_XGENE=y CONFIG_HOTPLUG_PCI=y # CONFIG_HOTPLUG_PCI_CPCI is not set # CONFIG_HOTPLUG_PCI_SHPC is not set + +# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set + +# CONFIG_PNP_DEBUG_MESSAGES is not set +CONFIG_NET_SB1000=y +CONFIG_SBSAUART_TTY=y +CONFIG_I2C_SCMI=m +CONFIG_SENSORS_ACPI_POWER=m +CONFIG_IMX_THERMAL=m +CONFIG_PWM_LPSS=m +CONFIG_ACPI=y +CONFIG_ACPI_PROCFS_POWER=y +CONFIG_ACPI_EC_DEBUGFS=y +CONFIG_ACPI_BUTTON=m +CONFIG_ACPI_FAN=m +CONFIG_ACPI_DOCK=y +CONFIG_ACPI_IPMI=y +CONFIG_ACPI_CONTAINER=y +CONFIG_ACPI_HED=m +CONFIG_ACPI_CUSTOM_METHOD=m + +CONFIG_AMD_XGBE=y +CONFIG_AMD_XGBE_PHY=y +# CONFIG_AMD_XGBE_DCB is not set diff --git a/config-armv7 b/config-armv7 index 4ddeea52..133a3106 100644 --- a/config-armv7 +++ b/config-armv7 @@ -10,7 +10,6 @@ CONFIG_ARCH_OMAP4=y CONFIG_ARCH_PICOXCELL=y CONFIG_ARCH_QCOM=y CONFIG_ARCH_ROCKCHIP=y -# CONFIG_ARCH_SOCFPGA is not set CONFIG_ARCH_TEGRA=y CONFIG_ARCH_U8500=y # CONFIG_ARCH_VIRT is not set @@ -23,7 +22,6 @@ CONFIG_ARCH_ZYNQ=y # CONFIG_VIRTUALIZATION is not set # mvebu -CONFIG_MACH_ARMADA_370_XP=y CONFIG_MACH_ARMADA_370=y CONFIG_MACH_ARMADA_375=y CONFIG_MACH_ARMADA_38X=y @@ -39,7 +37,7 @@ CONFIG_MV643XX_ETH=m CONFIG_PINCTRL_MVEBU=y CONFIG_PINCTRL_ARMADA_370=y CONFIG_PINCTRL_ARMADA_XP=y -# CONFIG_ARM_ARMADA_370_XP_CPUIDLE is not set +# CONFIG_ARM_MVEBU_V7_CPUIDLE is not set CONFIG_PINCTRL_DOVE=y CONFIG_EDAC_MV64X60=m CONFIG_RTC_DRV_S35390A=m @@ -50,7 +48,6 @@ CONFIG_MVNETA=m CONFIG_GPIO_MVEBU=y CONFIG_MVEBU_CLK_CORE=y CONFIG_MVEBU_CLK_COREDIV=y -CONFIG_MVEBU_CLK_GATING=y CONFIG_MMC_MVSDIO=m CONFIG_MMC_SDHCI_DOVE=m CONFIG_SPI_ORION=m @@ -81,15 +78,12 @@ CONFIG_SOC_TI81XX=y # CONFIG_MACH_CM_T3517 is not set # CONFIG_MACH_CRANEBOARD is not set # CONFIG_MACH_DEVKIT8000 is not set -# CONFIG_MACH_IGEP0030 is not set # CONFIG_MACH_NOKIA_RX51 is not set # CONFIG_MACH_OMAP_3430SDP is not set -# CONFIG_MACH_OMAP_3630SDP is not set # CONFIG_MACH_OMAP_LDP is not set # CONFIG_MACH_OMAP3_BEAGLE is not set # CONFIG_MACH_OMAP3517EVM is not set # CONFIG_MACH_OMAP3530_LV_SOM is not set -# CONFIG_MACH_OMAP3EVM is not set # CONFIG_MACH_OMAP3_PANDORA is not set # CONFIG_MACH_OMAP3_TORPEDO is not set # CONFIG_MACH_OVERO is not set @@ -103,19 +97,16 @@ CONFIG_OMAP_RESET_CLOCKS=y CONFIG_OMAP_MUX=y CONFIG_OMAP_MUX_WARNINGS=y CONFIG_OMAP_32K_TIMER=y -CONFIG_OMAP_32K_TIMER_HZ=128 CONFIG_OMAP_PACKAGE_CBB=y CONFIG_OMAP_PACKAGE_CUS=y # CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set -CONFIG_OMAP_MCBSP=y CONFIG_OMAP2PLUS_MBOX=m CONFIG_OMAP_MBOX_KFIFO_SIZE=256 CONFIG_OMAP_DM_TIMER=y CONFIG_OMAP_PM_NOOP=y CONFIG_DMA_OMAP=y CONFIG_OMAP_IOMMU=y -CONFIG_OMAP_IOVMM=m CONFIG_HWSPINLOCK_OMAP=m CONFIG_OMAP3_EMU=y # CONFIG_OMAP3_SDRC_AC_TIMING is not set @@ -136,9 +127,9 @@ CONFIG_BATTERY_TWL4030_MADC=m CONFIG_OMAP_USB2=m CONFIG_OMAP_CONTROL_PHY=m CONFIG_TI_PIPE3=m +CONFIG_PCI_DRA7XX=y CONFIG_TWL4030_USB=m CONFIG_TWL6030_USB=m -CONFIG_TWL6030_PWM=m CONFIG_TWL6040_CORE=y CONFIG_CLK_TWL6040=m CONFIG_OMAP_INTERCONNECT=m @@ -151,7 +142,6 @@ CONFIG_USB_EHCI_HCD_OMAP=m CONFIG_USB_OHCI_HCD_OMAP3=m CONFIG_USB_MUSB_AM35X=m CONFIG_USB_MUSB_OMAP2PLUS=m -CONFIG_OMAP_CONTROL_USB=m CONFIG_MMC_OMAP=m CONFIG_MMC_OMAP_HS=y CONFIG_RTC_DRV_MAX8907=m @@ -173,6 +163,7 @@ CONFIG_REGULATOR_PBIAS=m CONFIG_RTC_DRV_PALMAS=m CONFIG_OMAP5_DSS_HDMI=y CONFIG_OMAP5_DSS_HDMI_AUDIO=y +CONFIG_COMMON_CLK_PALMAS=m CONFIG_WL_TI=y CONFIG_WLCORE_SDIO=m @@ -186,7 +177,6 @@ CONFIG_MTD_ONENAND_OMAP2=m CONFIG_MTD_NAND_OMAP2=m CONFIG_MTD_NAND_OMAP_BCH=y CONFIG_SPI_OMAP24XX=m -CONFIG_MFD_TI_SSP=m CONFIG_SPI_TI_QSPI=m CONFIG_INPUT_TWL4030_PWRBUTTON=m @@ -194,10 +184,8 @@ CONFIG_INPUT_TWL4030_VIBRA=m CONFIG_INPUT_TWL6040_VIBRA=m CONFIG_KEYBOARD_OMAP4=m CONFIG_KEYBOARD_TWL4030=m -CONFIG_TOUCHSCREEN_TI_TSCADC=m # OMAP thermal temp. Can likely be built as module but doesn't autoload so build in to ensure performance on PandaES -CONFIG_OMAP_BANDGAP=y CONFIG_TI_SOC_THERMAL=y CONFIG_TI_THERMAL=y CONFIG_OMAP4_THERMAL=y @@ -224,13 +212,10 @@ CONFIG_HW_RANDOM_OMAP3_ROM=m CONFIG_DRM_OMAP=m CONFIG_DRM_OMAP_NUM_CRTCS=2 CONFIG_OMAP2_VRFB=y -# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set -# CONFIG_FB_OMAP_LCD_VGA is not set # CONFIG_FB_OMAP2 is not set # CONFIG_FB_DA8XX is not set CONFIG_OMAP2_DSS=m -# CONFIG_OMAP2_DSS_DEBUG_SUPPORT is not set # CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS is not set CONFIG_OMAP2_DSS_DPI=y CONFIG_OMAP2_DSS_RFBI=y @@ -238,9 +223,7 @@ CONFIG_OMAP2_DSS_VENC=y CONFIG_OMAP4_DSS_HDMI=y CONFIG_OMAP2_DSS_SDI=y CONFIG_OMAP2_DSS_DSI=y -# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 -CONFIG_OMAP2_DSS_SLEEP_BEFORE_RESET=y CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET=y CONFIG_DISPLAY_ENCODER_TFP410=m @@ -263,14 +246,9 @@ CONFIG_V4L_PLATFORM_DRIVERS=y # CONFIG_VIDEO_OMAP2_VOUT is not set CONFIG_VIDEO_OMAP3=m # CONFIG_VIDEO_OMAP4 is not set -# CONFIG_VIDEO_OMAP4_DEBUG is not set # The ones below are for TI Davinci -# CONFIG_VIDEO_VPFE_CAPTURE is not set -# CONFIG_VIDEO_VPSS_SYSTEM is not set # CONFIG_VIDEO_DM6446_CCDC is not set -# CONFIG_VIDEO_DM644X_VPBE is not set # CONFIG_VIDEO_DM355_CCDC is not set -# CONFIG_VIDEO_ISIF is not set # Also enable vivi driver - useful for testing a full kernelspace V4L2 driver CONFIG_V4L_TEST_DRIVERS=y CONFIG_VIDEO_VIVI=m @@ -280,18 +258,13 @@ CONFIG_SND_SOC_I2C_AND_SPI=m CONFIG_SND_OMAP_SOC_AM3517EVM=m CONFIG_SND_OMAP_SOC_DMIC=m CONFIG_SND_OMAP_SOC_HDMI=m -CONFIG_SND_OMAP_SOC_IGEP0020=m CONFIG_SND_OMAP_SOC_MCBSP=m CONFIG_SND_OMAP_SOC_MCPDM=m CONFIG_SND_OMAP_SOC_OMAP_HDMI=m CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m -CONFIG_SND_OMAP_SOC_OMAP3EVM=m -CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE=m CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m -CONFIG_SND_OMAP_SOC_OVERO=m CONFIG_SND_OMAP_SOC_RX51=m -CONFIG_SND_OMAP_SOC_SDP4430=m CONFIG_SND_SOC_TLV320AIC23=m CONFIG_SND_SOC_TLV320AIC3X=m CONFIG_SND_SOC_TWL4030=m @@ -301,7 +274,6 @@ CONFIG_RADIO_WL128X=m CONFIG_OMAP_REMOTEPROC=m -# CONFIG_TIDSPBRIDGE is not set # CONFIG_OMAP2_DSS_DEBUGFS is not set # CONFIG_OMAP_IOMMU_DEBUG is not set # CONFIG_OMAP_MUX_DEBUG is not set @@ -334,6 +306,7 @@ CONFIG_SND_DAVINCI_SOC_I2S=m CONFIG_SND_DAVINCI_SOC_MCASP=m CONFIG_SND_DAVINCI_SOC_VCIF=m CONFIG_SND_DAVINCI_SOC_GENERIC_EVM=m +CONFIG_SND_EDMA_SOC=m CONFIG_SND_AM33XX_SOC_EVM=m CONFIG_REGULATOR_TI_ABB=m CONFIG_TI_ADC081C=m @@ -351,7 +324,6 @@ CONFIG_SERIAL_MSM_CONSOLE=y CONFIG_PINCTRL_APQ8064=m CONFIG_PINCTRL_IPQ8064=m CONFIG_PINCTRL_MSM8960=m -CONFIG_PINCTRL_MSM8960=m CONFIG_COMMON_CLK_QCOM=m CONFIG_APQ_GCC_8084=m CONFIG_APQ_MMCC_8084=m @@ -370,6 +342,9 @@ CONFIG_USB_MSM_OTG=m CONFIG_MMC_SDHCI_MSM=m CONFIG_QCOM_BAM_DMA=m CONFIG_QCOM_GSBI=m +CONFIG_PHY_QCOM_APQ8064_SATA=m +CONFIG_PHY_QCOM_IPQ806X_SATA=m +CONFIG_CRYPTO_DEV_QCE=m CONFIG_MSM_IOMMU=y CONFIG_DRM_MSM=m CONFIG_DRM_MSM_FBDEV=y @@ -377,7 +352,6 @@ CONFIG_USB_EHCI_MSM=m # CONFIG_DRM_MSM_REGISTER_LOGGING is not set # i.MX -CONFIG_MXC_IRQ_PRIOR=y # CONFIG_MXC_DEBUG_BOARD is not set CONFIG_SOC_IMX50=y CONFIG_SOC_IMX51=y @@ -386,7 +360,6 @@ CONFIG_SOC_IMX6Q=y CONFIG_SOC_IMX6SL=y CONFIG_SOC_IMX6SX=y # CONFIG_SOC_VF610 is not set -CONFIG_MACH_IMX51_DT=y CONFIG_ARM_IMX6Q_CPUFREQ=m CONFIG_PCI_IMX6=y CONFIG_IMX_THERMAL=m @@ -414,7 +387,6 @@ CONFIG_STMPE_I2C=y CONFIG_SPI_IMX=m CONFIG_SPI_FSL_QUADSPI=m CONFIG_STMPE_SPI=y -CONFIG_MFD_MC13783=m CONFIG_MFD_MC13XXX_SPI=m CONFIG_MFD_STMPE=y CONFIG_MTD_NAND_GPMI_NAND=m @@ -428,6 +400,7 @@ CONFIG_RTC_DRV_SNVS=m # CONFIG_FB_IMX is not set CONFIG_SND_IMX_SOC=m +CONFIG_SND_SOC_FSL_ASRC=m CONFIG_SND_SOC_FSL_ESAI=m CONFIG_SND_SOC_FSL_SAI=m CONFIG_SND_SOC_FSL_SPDIF=m @@ -442,7 +415,6 @@ CONFIG_SND_SOC_IMX_WM8962=m CONFIG_SND_SOC_IMX_MC13783=m CONFIG_SND_SOC_IMX_SPDIF=m CONFIG_SND_SOC_EUKREA_TLV320=m -CONFIG_SND_SOC_TVL320AIC32X4=m CONFIG_SND_SOC_WM8731=m CONFIG_USB_IMX21_HCD=m @@ -503,10 +475,17 @@ CONFIG_REGULATOR_DA9055=m # picoxcell # CONFIG_CRYPTO_DEV_PICOXCELL is not set -# CONFIG_HW_RANDOM_PICOXCELL is not set + +# Exynos 4 +CONFIG_ARCH_EXYNOS4=y +CONFIG_SOC_EXYNOS4212=y +CONFIG_SOC_EXYNOS4412=y # Rockchips CONFIG_I2C_RK3X=m +CONFIG_SPI_ROCKCHIP=m +CONFIG_SND_SOC_ROCKCHIP=m +CONFIG_PWM_ROCKCHIP=m # ST Ericsson CONFIG_MACH_HREFV60=y @@ -584,7 +563,6 @@ CONFIG_MFD_TPS80031=y CONFIG_KEYBOARD_NVEC=y CONFIG_SERIO_NVEC_PS2=y CONFIG_NVEC_POWER=y -CONFIG_NVEC_LEDS=y CONFIG_NVEC_PAZ00=y CONFIG_MFD_TPS6586X=y CONFIG_GPIO_TPS6586X=y @@ -605,6 +583,8 @@ CONFIG_LATTICE_ECP3_CONFIG=m CONFIG_NET_VENDOR_XILINX=y CONFIG_XILINX_EMACLITE=m CONFIG_GPIO_XILINX=y +# Broken +# CONFIG_GPIO_ZYNQ is not set CONFIG_I2C_XILINX=m CONFIG_SPI_XILINX=m CONFIG_SPI_CADENCE=m diff --git a/config-armv7-generic b/config-armv7-generic index 739a0402..4a96a546 100644 --- a/config-armv7-generic +++ b/config-armv7-generic @@ -35,7 +35,6 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_XZ_DEC_ARMTHUMB=y CONFIG_ARCH_HAS_TICK_BROADCAST=y -CONFIG_ALWAYS_USE_PERSISTENT_CLOCK=y CONFIG_IRQ_CROSSBAR=y # CONFIG_MCPM is not set @@ -60,9 +59,13 @@ CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA=y # CONFIG_ARCH_BCM is not set # CONFIG_ARCH_BERLIN is not set # CONFIG_ARCH_HI3xxx is not set +# CONFIG_ARCH_HISI is not set +# CONFIG_ARCH_MEDIATEK is not set # CONFIG_ARCH_QCOM is not set +# CONFIG_ARCH_S5PV210 is not set # CONFIG_ARCH_SHMOBILE_MULTI is not set # CONFIG_ARCH_SIRF is not set +# CONFIG_ARCH_SOCFPGA is not set # CONFIG_PLAT_SPEAR is not set # CONFIG_ARCH_STI is not set # CONFIG_ARCH_U8500 is not set @@ -122,7 +125,6 @@ CONFIG_LSM_MMAP_MIN_ADDR=32768 CONFIG_XZ_DEC_ARM=y CONFIG_UACCESS_WITH_MEMCPY=y -CONFIG_CC_STACKPROTECTOR=y CONFIG_PCI_HOST_GENERIC=y @@ -165,11 +167,11 @@ CONFIG_ARM_HIGHBANK_CPUFREQ=m # CONFIG_MACH_SUN5I is not set CONFIG_MACH_SUN6I=y CONFIG_MACH_SUN7I=y -CONFIG_PINCTRL_SUNXI=y +# CONFIG_MACH_SUN8I is not set +CONFIG_DMA_SUN6I=m CONFIG_SUNXI_WATCHDOG=m CONFIG_NET_VENDOR_ALLWINNER=y CONFIG_STMMAC_PLATFORM=y -CONFIG_DWMAC_SOCFPGA=y CONFIG_DWMAC_SUNXI=y CONFIG_EEPROM_SUNXI_SID=m CONFIG_RTC_DRV_SUNXI=m @@ -184,18 +186,15 @@ CONFIG_POWER_RESET_SUN6I=y CONFIG_TOUCHSCREEN_SUN4I=m CONFIG_MFD_AXP20X=y CONFIG_REGULATOR_AXP20X=m +CONFIG_IR_SUNXI=m CONFIG_MDIO_SUN4I=m CONFIG_SUN4I_EMAC=m -CONFIG_MDIO_SUN4I=m -CONFIG_SUN4I_EMAC=m # Exynos CONFIG_ARCH_EXYNOS3=y -CONFIG_ARCH_EXYNOS4=y +# CONFIG_ARCH_EXYNOS4 is not set CONFIG_ARCH_EXYNOS5=y CONFIG_SOC_EXYNOS3250=y -CONFIG_SOC_EXYNOS4212=y -CONFIG_SOC_EXYNOS4412=y CONFIG_SOC_EXYNOS5250=y CONFIG_SOC_EXYNOS5420=y CONFIG_SOC_EXYNOS5440=y @@ -304,8 +303,6 @@ CONFIG_TEGRA_IOMMU_SMMU=y CONFIG_MMC_SDHCI_TEGRA=m CONFIG_TEGRA_WATCHDOG=m CONFIG_I2C_TEGRA=m -CONFIG_TEGRA_SYSTEM_DMA=y -CONFIG_TEGRA_EMC_SCALING_ENABLE=y CONFIG_TEGRA_AHB=y CONFIG_TEGRA20_APB_DMA=y CONFIG_SPI_TEGRA114=m @@ -326,6 +323,9 @@ CONFIG_DRM_TEGRA_FBDEV=y # CONFIG_DRM_TEGRA_DEBUG is not set CONFIG_DRM_TEGRA_STAGING=y CONFIG_NOUVEAU_PLATFORM_DRIVER=m +CONFIG_AD525X_DPOT=m +CONFIG_AD525X_DPOT_I2C=m +CONFIG_AD525X_DPOT_SPI=m # Jetson TK1 CONFIG_PINCTRL_AS3722=y @@ -365,7 +365,6 @@ CONFIG_AX88796_93CX6=y # usb gadget CONFIG_USB_OTG=y CONFIG_USB_GADGET=m -CONFIG_USB_GADGET_MUSB_HDRC=m CONFIG_USB_GADGET_VBUS_DRAW=100 CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 CONFIG_USB_MUSB_HDRC=m @@ -382,12 +381,10 @@ CONFIG_USB_CONFIGFS_NCM=y CONFIG_USB_CONFIGFS_OBEX=y # CONFIG_USB_CONFIGFS_RNDIS is not set CONFIG_USB_CONFIGFS_SERIAL=y -CONFIG_USB_CONFIGFS_STORAGE=y # CONFIG_USB_CONFIGFS_F_LB_SS is not set # CONFIG_USB_CONFIGFS_F_FS is not set # CONFIG_MUSB_PIO_ONLY is not set -# CONFIG_USB_MUSB_DEBUG is not set # CONFIG_USB_GADGET_DEBUG is not set # CONFIG_USB_GADGET_DEBUG_FILES is not set # CONFIG_USB_GADGET_DEBUG_FS is not set @@ -427,6 +424,7 @@ CONFIG_MFD_TPS65912_SPI=y # CONFIG_MFD_TPS80031 is not set # CONFIG_TWL4030_CORE is not set # CONFIG_TWL6040_CORE is not set +# # Pin stuff CONFIG_PINMUX=y @@ -435,11 +433,11 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_GENERIC_PINCONF=y # CONFIG_PINCTRL_SAMSUNG is not set -# CONFIG_PINCTRL_CAPRI is not set # CONFIG_PINCTRL_MSM8X74 is not set # CONFIG_PINCTRL_BCM281XX is not set # CONFIG_PINCTRL_APQ8064 is not set # CONFIG_PINCTRL_IPQ8064 is not set +# CONFIG_PINCTRL_MSM8960 is not set # GPIO # CONFIG_GPIO_EM is not set @@ -478,7 +476,6 @@ CONFIG_SPI_OC_TINY=m CONFIG_SPI_SC18IS602=m CONFIG_SPI_TLE62X0=m CONFIG_SPI_XCOMM=m -CONFIG_SPI_XILINX=m # CONFIG_SPI_FSL_SPI is not set # CONFIG_SPI_CADENCE is not set @@ -493,6 +490,8 @@ CONFIG_I2C_MV64XXX=m CONFIG_CRYPTO_SHA1_ARM=m CONFIG_CRYPTO_AES_ARM=m # CONFIG_CRYPTO_AES_ARM_BS is not set +CONFIG_CRYPTO_SHA1_ARM_NEON=m +CONFIG_CRYPTO_SHA512_ARM_NEON=m # DMA CONFIG_TI_PRIV_EDMA=y @@ -504,7 +503,6 @@ CONFIG_EDAC_MM_EDAC=m CONFIG_EDAC_LEGACY_SYSFS=y # Watchdog -CONFIG_MPCORE_WATCHDOG=m # Thermal / powersaving CONFIG_THERMAL=y @@ -550,7 +548,6 @@ CONFIG_MMC_DW_PLTFM=m CONFIG_MMC_DW_PCI=m CONFIG_SPI_DW_MMIO=m CONFIG_SPI_DW_PCI=m -# CONFIG_MMC_DW_SOCFPGA is not set # CONFIG_MMC_DW_IDMAC is not set # CONFIG_MMC_DW_K3 is not set CONFIG_USB_DWC2=y @@ -565,6 +562,7 @@ CONFIG_USB_DWC3_OMAP=m CONFIG_USB_DWC3_PCI=m # CONFIG_USB_DWC3_DEBUG is not set # CONFIG_USB_DWC3_KEYSTONE is not set +# CONFIG_DWC3_HOST_USB3_LPM_ENABLE is not set CONFIG_DW_WATCHDOG=m CONFIG_PCIE_DW=y @@ -579,7 +577,6 @@ CONFIG_SND_DMAENGINE_PCM=m CONFIG_SND_JACK=y CONFIG_SND_SIMPLE_CARD=m CONFIG_SND_SOC_ALL_CODECS=m -CONFIG_SND_SOC_CACHE_LZO=y CONFIG_SND_SOC_DMIC=m CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y CONFIG_SND_SOC_HDMI_CODEC=m @@ -618,15 +615,21 @@ CONFIG_SND_SOC_SPDIF=m # CONFIG_SND_SOC_WM8903 is not set # CONFIG_SND_SOC_WM8962 is not set # CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_SND_SOC_FSL_ASRC is not set +# CONFIG_SND_SOC_FSL_ESAI is not set # CONFIG_SND_SOC_FSL_SAI is not set -# CONFIG_SND_SOC_FSL_SSI is not set # CONFIG_SND_SOC_FSL_SPDIF is not set -# CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_FSL_SSI is not set # CONFIG_SND_SOC_IMX_AUDMUX is not set # CONFIG_SND_SOC_ALC5623 is not set # CONFIG_SND_SOC_CS42L56 is not set # CONFIG_SND_SOC_STA350 is not set # CONFIG_SND_ATMEL_SOC is not set +# CONFIG_SND_SOC_TLV320AIC31XX is not set +# CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_CS4265 is not set +# CONFIG_SND_EDMA_SOC is not set +# CONFIG_SND_SOC_ROCKCHIP is not set # Displays CONFIG_BACKLIGHT_TPS65217=m @@ -652,7 +655,6 @@ CONFIG_RTC_DRV_TPS80031=m # Regulators CONFIG_REGULATOR=y CONFIG_RFKILL_REGULATOR=m -CONFIG_REGULATOR_DUMMY=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_VIRTUAL_CONSUMER=m CONFIG_REGULATOR_USERSPACE_CONSUMER=m @@ -685,6 +687,7 @@ CONFIG_REGULATOR_TPS65912=m CONFIG_REGULATOR_TPS80031=m CONFIG_REGULATOR_LTC3589=m CONFIG_REGULATOR_ANATOP=m +CONFIG_REGULATOR_DA9211=m CONFIG_CHARGER_MANAGER=y CONFIG_CHARGER_BQ2415X=m @@ -771,7 +774,6 @@ CONFIG_UBIFS_FS=m CONFIG_UBIFS_FS_ADVANCED_COMPR=y CONFIG_UBIFS_FS_LZO=y CONFIG_UBIFS_FS_ZLIB=y -# CONFIG_UBIFS_FS_DEBUG is not set # Sensors CONFIG_SENSORS_HTU21=m @@ -792,6 +794,7 @@ CONFIG_BPF_JIT=y # HW Enabled in armv7 not lpae # CONFIG_DRM_TILCDC is not set # CONFIG_DRM_IMX is not set +# CONFIG_DRM_STI is not set # CONFIG_AHCI_IMX is not set # CONFIG_IMX_THERMAL is not set # CONFIG_TI_DAC7512 is not set @@ -828,6 +831,7 @@ CONFIG_BPF_JIT=y # CONFIG_MMC_TMIO is not set # CONFIG_PINCTRL_IMX35 is not set # CONFIG_DVB_USB_PCTV452E is not set +# CONFIG_DWMAC_SOCFPGA is not set # CONFIG_MFD_LP8788 is not set # CONFIG_MFD_MAX77693 is not set diff --git a/config-armv7-lpae b/config-armv7-lpae index b282f5de..661ce368 100644 --- a/config-armv7-lpae +++ b/config-armv7-lpae @@ -11,7 +11,6 @@ CONFIG_ARCH_VIRT=y # CONFIG_SOC_AM43XX is not set # CONFIG_SOC_DRA7XX is not set # CONFIG_ARCH_ROCKCHIP is not set -# CONFIG_ARCH_SOCFPGA is not set # CONFIG_ARCH_ZYNQ is not set # CONFIG_ARCH_AXXIA is not set @@ -62,6 +61,7 @@ CONFIG_TI_AEMIF=m CONFIG_POWER_RESET_KEYSTONE=y CONFIG_DAVINCI_WATCHDOG=m CONFIG_SPI_DAVINCI=m +CONFIG_TI_DAVINCI_MDIO=m # CONFIG_TI_SOC_THERMAL is not set # Tegra (non A15 device options) diff --git a/config-debug b/config-debug index bc9ad26e..467f33a1 100644 --- a/config-debug +++ b/config-debug @@ -31,14 +31,12 @@ CONFIG_LOCK_STAT=y CONFIG_DEBUG_STACK_USAGE=y CONFIG_ACPI_DEBUG=y -# CONFIG_ACPI_DEBUG_FUNC_TRACE is not set CONFIG_DEBUG_SG=y CONFIG_DEBUG_PI_LIST=y # CONFIG_DEBUG_PAGEALLOC is not set -CONFIG_DEBUG_WRITECOUNT=y CONFIG_DEBUG_OBJECTS=y # CONFIG_DEBUG_OBJECTS_SELFTEST is not set CONFIG_DEBUG_OBJECTS_FREE=y @@ -53,7 +51,6 @@ CONFIG_CAN_DEBUG_DEVICES=y CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_DEBUG_NOTIFIERS=y @@ -97,7 +94,6 @@ CONFIG_PM_ADVANCED_DEBUG=y CONFIG_CEPH_LIB_PRETTYDEBUG=y CONFIG_QUOTA_DEBUG=y -CONFIG_PCI_DEFAULT_USE_CRS=y CONFIG_KGDB_KDB=y CONFIG_KDB_KEYBOARD=y @@ -123,6 +119,8 @@ CONFIG_MAC80211_MESSAGE_TRACING=y CONFIG_EDAC_DEBUG=y +CONFIG_SPI_DEBUG=y + CONFIG_X86_DEBUG_STATIC_CPU_HAS=y CONFIG_LATENCYTOP=y CONFIG_SCHEDSTATS=y diff --git a/config-generic b/config-generic index 1958b04d..ab611ccd 100644 --- a/config-generic +++ b/config-generic @@ -44,6 +44,7 @@ CONFIG_TASK_XACCT=y CONFIG_TASK_IO_ACCOUNTING=y CONFIG_SYSCTL=y CONFIG_LOG_BUF_SHIFT=18 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 # CONFIG_IKCONFIG is not set # CONFIG_EMBEDDED is not set # CONFIG_EXPERT is not set @@ -63,7 +64,6 @@ CONFIG_UTS_NS=y CONFIG_IPC_NS=y CONFIG_NET_NS=y CONFIG_USER_NS=y -# CONFIG_UIDGID_STRICT_TYPE_CHECKS is not set CONFIG_POSIX_MQUEUE=y # CONFIG_PREEMPT_NONE is not set @@ -76,8 +76,6 @@ CONFIG_SLUB_CPU_PARTIAL=y # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_AD525X_DPOT is not set -# CONFIG_ATMEL_PWM is not set -# CONFIG_IWMC3200TOP is not set # # Loadable module support @@ -105,7 +103,6 @@ CONFIG_PCIEASPM=y CONFIG_PCIE_ECRC=y CONFIG_PCIEAER_INJECT=m CONFIG_HOTPLUG_PCI_PCIE=y -CONFIG_HOTPLUG_PCI_FAKE=m # CONFIG_SGI_IOC4 is not set @@ -130,7 +127,6 @@ CONFIG_SDIO_UART=m # CONFIG_MMC_TEST is not set # CONFIG_MMC_DEBUG is not set # https://lists.fedoraproject.org/pipermail/kernel/2014-February/004889.html -CONFIG_MMC_UNSAFE_RESUME=y # CONFIG_MMC_CLKGATE is not set CONFIG_MMC_BLOCK=m CONFIG_MMC_BLOCK_MINORS=8 @@ -149,6 +145,7 @@ CONFIG_MMC_USHC=m CONFIG_MMC_REALTEK_PCI=m CONFIG_MMC_REALTEK_USB=m CONFIG_MMC_VUB300=m +# CONFIG_MMC_SPI is not set # CONFIG_MMC_SDHCI_PXAV2 is not set # CONFIG_MMC_SDHCI_PXAV3 is not set # CONFIG_MMC_SDHCI_OF_ARASAN is not set @@ -169,7 +166,6 @@ CONFIG_INFINIBAND_SRP=m CONFIG_INFINIBAND_SRPT=m CONFIG_INFINIBAND_USER_MAD=m CONFIG_INFINIBAND_USER_ACCESS=m -# CONFIG_INFINIBAND_EXPERIMENTAL_UVERBS_FLOW_STEERING is not set #staging CONFIG_INFINIBAND_IPATH=m CONFIG_INFINIBAND_ISER=m CONFIG_INFINIBAND_ISERT=m @@ -208,16 +204,34 @@ CONFIG_BINFMT_MISC=m # Generic Driver Options # CONFIG_FW_LOADER=y +# CONFIG_TEST_FIRMWARE is not set # CONFIG_FIRMWARE_IN_KERNEL is not set CONFIG_EXTRA_FIRMWARE="" # Give this a try in rawhide for now # CONFIG_FW_LOADER_USER_HELPER is not set +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set # CONFIG_CMA is not set # CONFIG_DMA_CMA is not set +# CONFIG_FENCE_TRACE is not set # CONFIG_SPI is not set +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_BUTTERFLY is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_LM70_LLP is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PXA2XX is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_TOPCLIFF_PCH is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI_FSL_SPI is not set # CONFIG_SPMI is not set @@ -233,7 +247,6 @@ CONFIG_MTD=m # # User Modules And Translation Layers # -# CONFIG_MTD_CHAR is not set # CONFIG_MTD_BLKDEVS is not set # CONFIG_MTD_BLOCK is not set # CONFIG_MTD_BLOCK_RO is not set @@ -272,6 +285,8 @@ CONFIG_MTD_CFI_I2=y # CONFIG_MTD_TS5500 is not set # CONFIG_MTD_INTEL_VR_NOR is not set # CONFIG_MTD_PLATRAM is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_DATAFLASH is not set # Self-contained MTD device drivers # CONFIG_MTD_PMC551 is not set @@ -287,9 +302,7 @@ CONFIG_MTD_CFI_I2=y # CONFIG_MTD_DOCG3 is not set # CONFIG_MTD_NAND is not set # CONFIG_MTD_ONENAND is not set -# CONFIG_MTD_NAND_VERIFY_WRITE is not set # CONFIG_MTD_NAND_ECC_BCH is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set # CONFIG_MTD_NAND_DISKONCHIP is not set # CONFIG_MTD_LPDDR is not set CONFIG_MTD_UBI=m @@ -372,7 +385,6 @@ CONFIG_VIRTIO_NET=m CONFIG_HW_RANDOM_VIRTIO=m CONFIG_VIRTIO_CONSOLE=m CONFIG_VHOST_NET=m -CONFIG_TCM_VHOST=m CONFIG_VHOST_SCSI=m # @@ -385,7 +397,6 @@ CONFIG_SCSI_PROC_FS=y CONFIG_SCSI_SCAN_ASYNC=y CONFIG_SCSI_SRP=m CONFIG_SCSI_SRP_ATTRS=m -CONFIG_SCSI_TGT=m CONFIG_SCSI_ISCI=m CONFIG_SCSI_CHELSIO_FCOE=m @@ -409,15 +420,12 @@ CONFIG_CHR_DEV_SCH=m # # Some SCSI devices (e.g. CD jukebox) support multiple LUNs # -CONFIG_SCSI_MULTI_LUN=y CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y CONFIG_SCSI_SPI_ATTRS=m CONFIG_SCSI_FC_ATTRS=m -CONFIG_SCSI_FC_TGT_ATTRS=y CONFIG_SCSI_ISCSI_ATTRS=m CONFIG_SCSI_SAS_ATTRS=m -CONFIG_SCSI_SRP_TGT_ATTRS=y CONFIG_SCSI_SAS_LIBSAS=m CONFIG_SCSI_SAS_ATA=y CONFIG_SCSI_SAS_HOST_SMP=y @@ -436,7 +444,6 @@ CONFIG_SCSI_ACARD=m CONFIG_SCSI_AACRAID=m CONFIG_SCSI_AIC7XXX=m # http://lists.fedoraproject.org/pipermail/kernel/2013-February/004102.html -# CONFIG_SCSI_AIC7XXX_OLD is not set CONFIG_AIC7XXX_CMDS_PER_DEVICE=4 CONFIG_AIC7XXX_RESET_DELAY_MS=15000 # CONFIG_AIC7XXX_BUILD_FIRMWARE is not set @@ -635,10 +642,8 @@ CONFIG_MD_RAID456=m CONFIG_BCACHE=m # CONFIG_BCACHE_DEBUG is not set -# CONFIG_BCACHE_EDEBUG is not set # CONFIG_BCACHE_CLOSURES_DEBUG is not set -# CONFIG_MULTICORE_RAID456 is not set CONFIG_ASYNC_RAID6_TEST=m CONFIG_BLK_DEV_DM=y CONFIG_DM_CRYPT=m @@ -653,7 +658,6 @@ CONFIG_DM_CACHE_MQ=m CONFIG_DM_CACHE_CLEANER=m # CONFIG_DM_ERA is not set # CONFIG_DM_DEBUG_BLOCK_STACK_TRACING is not set -# CONFIG_DM_DEBUG_SPACE_MAPS is not set CONFIG_DM_UEVENT=y CONFIG_DM_ZERO=y CONFIG_DM_LOG_USERSPACE=m @@ -683,10 +687,8 @@ CONFIG_FIREWIRE=m CONFIG_FIREWIRE_OHCI=m CONFIG_FIREWIRE_SBP2=m CONFIG_FIREWIRE_NET=m -CONFIG_FIREWIRE_OHCI_DEBUG=y CONFIG_FIREWIRE_NOSY=m # CONFIG_FIREWIRE_SERIAL is not set -# CONFIG_FIREWIRE_OHCI_REMOTE_DMA is not set # # I2O device support @@ -754,7 +756,6 @@ CONFIG_IP_MROUTE=y CONFIG_IP_MROUTE_MULTIPLE_TABLES=y CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y -CONFIG_ARPD=y CONFIG_SYN_COOKIES=y CONFIG_NET_IPVTI=m CONFIG_INET_AH=m @@ -762,7 +763,6 @@ CONFIG_INET_ESP=m CONFIG_INET_IPCOMP=m CONFIG_NETCONSOLE=m CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_NETPOLL_TRAP=y CONFIG_NET_POLL_CONTROLLER=y # @@ -797,7 +797,6 @@ CONFIG_IP_VS_FTP=m CONFIG_IP_VS_PE_SIP=m CONFIG_IPV6=y -CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y CONFIG_IPV6_ROUTE_INFO=y CONFIG_IPV6_OPTIMISTIC_DAD=y @@ -842,7 +841,6 @@ CONFIG_NETFILTER_NETLINK_ACCT=m CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NETFILTER_NETLINK_QUEUE_CT=y CONFIG_NETFILTER_NETLINK_LOG=m -CONFIG_NETFILTER_TPROXY=m CONFIG_NETFILTER_XTABLES=y CONFIG_NETFILTER_XT_SET=m CONFIG_NETFILTER_XT_MARK=m @@ -860,10 +858,13 @@ CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m CONFIG_NETFILTER_XT_TARGET_LED=m CONFIG_NETFILTER_XT_TARGET_LOG=m CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_NAT=m +CONFIG_NETFILTER_XT_TARGET_NETMAP=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NOTRACK=m CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_REDIRECT=m CONFIG_NETFILTER_XT_TARGET_SECMARK=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m @@ -954,6 +955,11 @@ CONFIG_NF_CT_NETLINK=m CONFIG_NF_CT_NETLINK_HELPER=m CONFIG_NF_CT_PROTO_UDPLITE=m +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_NF_LOG_IPV6=m +CONFIG_NF_LOG_BRIDGE=m + CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_RPFILTER=m @@ -962,18 +968,15 @@ CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_TARGET_NETMAP=m CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_LOG=m -CONFIG_IP_NF_TARGET_ULOG=m CONFIG_IP_NF_TARGET_REJECT=y CONFIG_IP_NF_TARGET_SYNPROXY=m CONFIG_IP_NF_TARGET_TTL=m -CONFIG_NF_NAT_IPV4=m +CONFIG_IP_NF_NAT=m CONFIG_IP_NF_TARGET_MASQUERADE=m CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m -CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_IPTABLES=y @@ -994,14 +997,12 @@ CONFIG_IP6_NF_MATCH_MH=m CONFIG_IP6_NF_MATCH_RPFILTER=m CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_RAW=m CONFIG_IP6_NF_SECURITY=m -CONFIG_IP6_NF_TARGET_LOG=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_TARGET_SYNPROXY=m CONFIG_IP6_NF_TARGET_HL=m -CONFIG_NF_NAT_IPV6=m +CONFIG_IP6_NF_NAT=m CONFIG_IP6_NF_TARGET_MASQUERADE=m # CONFIG_IP6_NF_TARGET_NPT is not set @@ -1055,9 +1056,9 @@ CONFIG_BRIDGE_EBT_SNAT=m CONFIG_BRIDGE_EBT_STP=m CONFIG_BRIDGE_EBT_T_FILTER=m CONFIG_BRIDGE_EBT_T_NAT=m -CONFIG_BRIDGE_EBT_ULOG=m CONFIG_BRIDGE_EBT_VLAN=m CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m CONFIG_XFRM=y CONFIG_XFRM_MIGRATE=y CONFIG_XFRM_SUB_POLICY=y @@ -1093,7 +1094,6 @@ CONFIG_IP_SET_LIST_SET=m # CONFIG_IP_SCTP=m CONFIG_NET_SCTPPROBE=m -# CONFIG_SCTP_DBG_MSG is not set # CONFIG_SCTP_DBG_OBJCNT is not set CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1=y # CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5 is not set @@ -1112,11 +1112,8 @@ CONFIG_ATALK=m CONFIG_DEV_APPLETALK=m CONFIG_IPDDP=m CONFIG_IPDDP_ENCAP=y -CONFIG_IPDDP_DECAP=y # CONFIG_X25 is not set # CONFIG_LAPB is not set -# CONFIG_ECONET is not set -CONFIG_WAN_ROUTER=m CONFIG_IP_DCCP=m CONFIG_IP_DCCP_CCID2=m # CONFIG_IP_DCCP_CCID2_DEBUG is not set @@ -1131,8 +1128,6 @@ CONFIG_IP_DCCP_CCID3=y CONFIG_TIPC=m CONFIG_TIPC_PORTS=8192 # CONFIG_TIPC_MEDIA_IB is not set -# CONFIG_TIPC_ADVANCED is not set -# CONFIG_TIPC_DEBUG is not set CONFIG_NETLABEL=y @@ -1347,6 +1342,7 @@ CONFIG_CHELSIO_T1_1G=y CONFIG_CHELSIO_T3=m CONFIG_CHELSIO_T4=m CONFIG_CHELSIO_T4VF=m +# CONFIG_CHELSIO_T4_DCB is not set CONFIG_NET_VENDOR_CISCO=y CONFIG_ENIC=m @@ -1364,7 +1360,6 @@ CONFIG_TULIP=m # CONFIG_TULIP_NAPI is not set # CONFIG_TULIP_MWI is not set CONFIG_TULIP_MMIO=y -# CONFIG_NI5010 is not set CONFIG_DE4X5=m CONFIG_WINBOND_840=m CONFIG_DM9102=m @@ -1372,8 +1367,6 @@ CONFIG_PCMCIA_XIRCOM=m CONFIG_ULI526X=m CONFIG_NET_VENDOR_DLINK=y -CONFIG_DE600=m -CONFIG_DE620=m CONFIG_DL2K=m CONFIG_SUNDANCE=m # CONFIG_SUNDANCE_MMIO is not set @@ -1398,7 +1391,6 @@ CONFIG_E1000E=m CONFIG_IGB=m CONFIG_IGB_HWMON=y CONFIG_IGB_DCA=y -CONFIG_IGB_PTP=y CONFIG_IGBVF=m CONFIG_IXGB=m CONFIG_IXGBEVF=m @@ -1406,7 +1398,6 @@ CONFIG_IXGBE=m CONFIG_IXGBE_DCA=y CONFIG_IXGBE_DCB=y CONFIG_IXGBE_HWMON=y -CONFIG_IXGBE_PTP=y CONFIG_I40E=m # CONFIG_I40E_VXLAN is not set # CONFIG_I40E_DCB is not set @@ -1425,8 +1416,11 @@ CONFIG_SKY2=m CONFIG_NET_VENDOR_MICREL=y CONFIG_KSZ884X_PCI=m # CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set # CONFIG_KS8851_MLL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_ENC28J60 is not set CONFIG_NET_VENDOR_MYRI=y CONFIG_MYRI10GE=m CONFIG_MYRI10GE_DCA=y @@ -1438,7 +1432,6 @@ CONFIG_NS83820=m CONFIG_NET_VENDOR_8390=y CONFIG_PCMCIA_AXNET=m CONFIG_NE2K_PCI=m -CONFIG_NE3210=m CONFIG_PCMCIA_PCNET=m CONFIG_NET_VENDOR_NVIDIA=y @@ -1446,7 +1439,6 @@ CONFIG_FORCEDETH=m CONFIG_NET_VENDOR_OKI=y # CONFIG_PCH_GBE is not set -# CONFIG_PCH_PTP is not set CONFIG_NET_PACKET_ENGINE=y CONFIG_HAMACHI=m @@ -1487,7 +1479,6 @@ CONFIG_NET_VENDOR_SIS=y CONFIG_SIS900=m CONFIG_SIS190=m -CONFIG_NET_VENDOR_SMC=y CONFIG_NET_VENDOR_SMSC=y CONFIG_PCMCIA_SMC91C92=m @@ -1500,8 +1491,6 @@ CONFIG_STMMAC_ETH=m # CONFIG_STMMAC_PLATFORM is not set # CONFIG_STMMAC_PCI is not set # CONFIG_STMMAC_DA is not set -# CONFIG_STMMAC_DUAL_MAC is not set -# CONFIG_STMMAC_TIMER is not set # CONFIG_STMMAC_DEBUG_FS is not set CONFIG_NET_VENDOR_SUN=y @@ -1550,6 +1539,7 @@ CONFIG_SMSC_PHY=m CONFIG_STE10XP=m CONFIG_VITESSE_PHY=m CONFIG_MICREL_PHY=m +# CONFIG_MICREL_KS8995MA is not set # CONFIG_OMAP_CONTROL_PHY is not set # CONFIG_PHY_SAMSUNG_USB2 is not set @@ -1561,9 +1551,6 @@ CONFIG_TYPHOON=m CONFIG_DNET=m -CONFIG_LNE390=m -CONFIG_ES3210=m -CONFIG_NET_PCI=y CONFIG_B44=m CONFIG_B44_PCI=y CONFIG_BCMGENET=m @@ -1572,7 +1559,6 @@ CONFIG_BNX2X=m CONFIG_BNX2X_SRIOV=y CONFIG_CNIC=m CONFIG_FEALNX=m -CONFIG_NET_POCKET=y CONFIG_ETHOC=m # @@ -1627,7 +1613,6 @@ CONFIG_CFG80211_DEFAULT_PS=y CONFIG_NL80211=y # CONFIG_NL80211_TESTMODE is not set CONFIG_WIRELESS_EXT=y -# CONFIG_WIRELESS_EXT_SYSFS is not set CONFIG_LIB80211=m CONFIG_LIB80211_CRYPT_WEP=m CONFIG_LIB80211_CRYPT_CCMP=m @@ -1636,7 +1621,6 @@ CONFIG_LIB80211_CRYPT_TKIP=m CONFIG_MAC80211=m CONFIG_MAC80211_RC_MINSTREL=y -# CONFIG_MAC80211_RC_DEFAULT_PID is not set CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT="minstrel" CONFIG_MAC80211_MESH=y @@ -1662,12 +1646,10 @@ CONFIG_ATH9K=m CONFIG_ATH9K_PCI=y CONFIG_ATH9K_AHB=y # CONFIG_ATH9K_DEBUG is not set -# CONFIG_ATH9K_MAC_DEBUG is not set CONFIG_ATH9K_DEBUGFS=y CONFIG_ATH9K_HTC=m CONFIG_ATH9K_BTCOEX_SUPPORT=y # CONFIG_ATH9K_HTC_DEBUGFS is not set -# CONFIG_ATH9K_LEGACY_RATE_CONTROL is not set # CONFIG_ATH9K_STATION_STATISTICS is not set # CONFIG_ATH9K_WOW is not set # @@ -1693,13 +1675,12 @@ CONFIG_B43=m CONFIG_B43_PCMCIA=y CONFIG_B43_SDIO=y CONFIG_B43_BCMA=y -# CONFIG_B43_BCMA_EXTRA is not set CONFIG_B43_BCMA_PIO=y # CONFIG_B43_DEBUG is not set CONFIG_B43_PHY_LP=y CONFIG_B43_PHY_N=y CONFIG_B43_PHY_HT=y -# CONFIG_B43_FORCE_PIO is not set +# CONFIG_B43_PHY_G is not set CONFIG_B43LEGACY=m # CONFIG_B43LEGACY_DEBUG is not set CONFIG_B43LEGACY_DMA=y @@ -1710,10 +1691,9 @@ CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y CONFIG_BRCMSMAC=m CONFIG_BRCMFMAC=m CONFIG_BRCMFMAC_SDIO=y -CONFIG_BRCMFMAC_SDIO_OOB=y CONFIG_BRCMFMAC_USB=y +CONFIG_BRCMFMAC_PCIE=y # CONFIG_BRCM_TRACING is not set -# CONFIG_BRCMISCAN is not set # CONFIG_BRCMDBG is not set # CONFIG_SYSTEMPORT is not set CONFIG_HERMES=m @@ -1741,6 +1721,7 @@ CONFIG_LIBERTAS_CS=m CONFIG_LIBERTAS_SDIO=m # CONFIG_LIBERTAS_DEBUG is not set # CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_LIBERTAS_SPI is not set CONFIG_LIBERTAS_MESH=y CONFIG_IWLWIFI=m CONFIG_IWLDVM=m @@ -1748,14 +1729,9 @@ CONFIG_IWLMVM=m # CONFIG_IWLWIFI_BCAST_FILTERING is not set CONFIG_IWLWIFI_DEBUG=y CONFIG_IWLWIFI_DEBUGFS=y -CONFIG_IWLWIFI_DEVICE_SVTOOL=y -# CONFIG_IWLWIFI_EXPERIMENTAL_MFP is not set -CONFIG_IWLWIFI_UCODE16=y -# CONFIG_IWLWIFI_P2P is not set CONFIG_IWLEGACY=m CONFIG_IWLEGACY_DEBUG=y CONFIG_IWLEGACY_DEBUGFS=y -# CONFIG_IWLWIFI_LEGACY_DEVICE_TRACING is not set CONFIG_IWL4965=y CONFIG_IWL3945=m # CONFIG_IWM is not set @@ -1764,6 +1740,7 @@ CONFIG_MAC80211_HWSIM=m CONFIG_P54_COMMON=m CONFIG_P54_USB=m CONFIG_P54_PCI=m +# CONFIG_P54_SPI is not set CONFIG_MWL8K=m # CONFIG_PRISM54 is not set # CONFIG_PCMCIA_WL3501 is not set @@ -1804,8 +1781,6 @@ CONFIG_ZD1211RW=m # CONFIG_ZD1211RW_DEBUG is not set CONFIG_WL12XX=m -CONFIG_WL12XX_SPI=m -CONFIG_WL12XX_SDIO=m CONFIG_WL1251=m CONFIG_WL1251_SPI=m @@ -1826,6 +1801,20 @@ CONFIG_MWIFIEX_SDIO=m CONFIG_MWIFIEX_PCIE=m CONFIG_MWIFIEX_USB=m +CONFIG_IEEE802154=m +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_IEEE802154_DRIVERS=m +CONFIG_IEEE802154_FAKEHARD=m +CONFIG_IEEE802154_FAKELB=m +# CONFIG_IEEE802154_AT86RF230 is not set +# CONFIG_IEEE802154_MRF24J40 is not set +# CONFIG_IEEE802154_CC2520 is not set + +CONFIG_MAC802154=m +CONFIG_NET_MPLS_GSO=m + +CONFIG_6LOWPAN=m + # # Token Ring devices # @@ -1841,7 +1830,6 @@ CONFIG_NET_FC=y # # PCMCIA network device support # -CONFIG_NET_PCMCIA=y CONFIG_PCMCIA_3C589=m CONFIG_PCMCIA_3C574=m CONFIG_PCMCIA_FMVJ18X=m @@ -1874,7 +1862,6 @@ CONFIG_NFC_DIGITAL=m CONFIG_NFC_NCI=m CONFIG_NFC_HCI=m CONFIG_NFC_SHDLC=y -CONFIG_NFC_LLCP=y CONFIG_NFC_SIM=m CONFIG_NFC_MRVL=m @@ -1888,6 +1875,9 @@ CONFIG_NFC_MICROREAD_I2C=m CONFIG_NFC_TRF7970A=m CONFIG_NFC_ST21NFCA=m CONFIG_NFC_ST21NFCA_I2C=m +# CONFIG_NFC_ST21NFCB is not set +# CONFIG_NFC_ST21NFCB_I2C is not set +# CONFIG_NFC_NCI_SPI is not set # @@ -1932,8 +1922,7 @@ CONFIG_WINBOND_FIR=m # Bluetooth support # CONFIG_BT=m -# CONFIG_BT_6LOWPAN is not set -CONFIG_BT_L2CAP=y +CONFIG_BT_6LOWPAN=m CONFIG_BT_SCO=y CONFIG_BT_CMTP=m CONFIG_BT_RFCOMM=m @@ -2057,7 +2046,6 @@ CONFIG_HYSDN_CAPI=y # CONFIG_ISDN_CAPI=m # CONFIG_CAPI_TRACE is not set -CONFIG_ISDN_DRV_AVMB1_VERBOSE_REASON=y CONFIG_ISDN_CAPI_MIDDLEWARE=y CONFIG_ISDN_CAPI_CAPI20=m @@ -2117,7 +2105,7 @@ CONFIG_TABLET_USB_AIPTEK=m CONFIG_TABLET_USB_GTCO=m CONFIG_TABLET_USB_HANWANG=m CONFIG_TABLET_USB_KBTAB=m -CONFIG_TABLET_USB_WACOM=m +CONFIG_TABLET_SERIAL_WACOM4=m CONFIG_INPUT_POWERMATE=m CONFIG_INPUT_YEALINK=m @@ -2180,6 +2168,7 @@ CONFIG_KEYBOARD_ATKBD=y # CONFIG_KEYBOARD_TCA6416 is not set # CONFIG_KEYBOARD_TCA8418 is not set # CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_CAP1106 is not set CONFIG_INPUT_MOUSE=y CONFIG_MOUSE_PS2=y # CONFIG_MOUSE_PS2_TOUCHKIT is not set @@ -2267,6 +2256,9 @@ CONFIG_TOUCHSCREEN_ATMEL_MXT=m CONFIG_TOUCHSCREEN_AUO_PIXCIR=m CONFIG_TOUCHSCREEN_TI_AM335X_TSC=m CONFIG_TOUCHSCREEN_ZFORCE=m +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_TSC2005 is not set CONFIG_INPUT_MISC=y CONFIG_INPUT_PCSPKR=m @@ -2305,7 +2297,6 @@ CONFIG_SYNCLINK_GT=m CONFIG_N_HDLC=m CONFIG_N_GSM=m # CONFIG_TRACE_SINK is not set -# CONFIG_STALDRV is not set # CONFIG_DUMMY_IRQ is not set # CONFIG_IBM_ASM is not set CONFIG_TIFM_CORE=m @@ -2365,6 +2356,9 @@ CONFIG_SERIAL_ARC_NR_PORTS=1 # CONFIG_SERIAL_FSL_LPUART is not set # CONFIG_SERIAL_ST_ASC is not set # CONFIG_SERIAL_PCH_UART is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_IFX6X60 is not set CONFIG_UNIX98_PTYS=y CONFIG_DEVPTS_MULTIPLE_INSTANCES=y @@ -2411,7 +2405,6 @@ CONFIG_I2C_ALGOPCA=m # CONFIG_I2C_I801 is not set # CONFIG_I2C_ISCH is not set # CONFIG_I2C_NFORCE2_S4985 is not set -# CONFIG_I2C_INTEL_MID is not set # CONFIG_I2C_EG20T is not set # CONFIG_I2C_CBUS_GPIO is not set CONFIG_I2C_VIPERBOARD=m @@ -2420,6 +2413,8 @@ CONFIG_EEPROM_AT24=m CONFIG_EEPROM_LEGACY=m CONFIG_EEPROM_93CX6=m CONFIG_EEPROM_MAX6875=m +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_93XX46 is not set CONFIG_I2C_NFORCE2=m # CONFIG_I2C_OCORES is not set @@ -2494,6 +2489,7 @@ CONFIG_SENSORS_K8TEMP=m CONFIG_SENSORS_K10TEMP=m CONFIG_SENSORS_LIS3LV02D=m CONFIG_SENSORS_LIS3_I2C=m +# CONFIG_SENSORS_LIS3_SPI is not set CONFIG_SENSORS_LM63=m CONFIG_SENSORS_LM75=m CONFIG_SENSORS_LM77=m @@ -2585,6 +2581,15 @@ CONFIG_SENSORS_UCD9200=m CONFIG_SENSORS_ZL6100=m CONFIG_SENSORS_EMC6W201=m +CONFIG_SENSORS_TMP103=m +CONFIG_SENSORS_ADS7871=m +CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_LM70=m +CONFIG_SENSORS_ADCXX=m +CONFIG_SENSORS_MAX1111=m +CONFIG_SENSORS_POWR1220=m +CONFIG_SENSORS_AD7314=m + CONFIG_PMBUS=m CONFIG_SENSORS_PMBUS=m CONFIG_SENSORS_MAX16064=m @@ -2594,6 +2599,7 @@ CONFIG_SENSORS_MAX34440=m CONFIG_SENSORS_MAX8688=m CONFIG_SENSORS_MAX1668=m CONFIG_SENSORS_MAX197=m +CONFIG_SENSORS_TPS40422=m # Industrial I/O subsystem configuration CONFIG_IIO=m @@ -2606,7 +2612,6 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 CONFIG_IIO_INTERRUPT_TRIGGER=m CONFIG_HID_SENSOR_IIO_COMMON=m CONFIG_HID_SENSOR_IIO_TRIGGER=m -CONFIG_HID_SENSOR_ENUM_BASE_QUIRKS=y # CONFIG_IIO_SYSFS_TRIGGER is not set # CONFIG_AD5446 is not set # CONFIG_AD5380 is not set @@ -2639,6 +2644,7 @@ CONFIG_HID_SENSOR_INCLINOMETER_3D=m CONFIG_HID_SENSOR_DEVICE_ROTATION=m # CONFIG_ADJD_S311 is not set # CONFIG_SENSORS_TSL2563 is not set +# CONFIG_SENSORS_HMC5843_I2C is not set # CONFIG_VCNL4000 is not set # CONFIG_AK8975 is not set # CONFIG_MAG3110 is not set @@ -2682,6 +2688,13 @@ CONFIG_HID_SENSOR_DEVICE_ROTATION=m # CONFIG_MPL115 is not set # CONFIG_SI7005 is not set # CONFIG_AS3935 is not set +# CONFIG_KXCJK1013 is not set +# CONFIG_ISL29125 is not set +# CONFIG_TCS3414 is not set +# CONFIG_AK09911 is not set +# CONFIG_T5403 is not set +# CONFIG_MCP4922 is not set +# CONFIG_MAX1027 is not set # staging IIO drivers # CONFIG_AD7291 is not set @@ -2696,6 +2709,7 @@ CONFIG_HID_SENSOR_DEVICE_ROTATION=m # CONFIG_SENSORS_ISL29018 is not set # CONFIG_SENSORS_ISL29028 is not set # CONFIG_SENSORS_HMC5843 is not set +# CONFIG_SENSORS_HMC5843_SPI is not set # CONFIG_IIO_PERIODIC_RTC_TRIGGER is not set # CONFIG_IIO_SIMPLE_DUMMY is not set # CONFIG_ADIS16201 is not set @@ -2734,6 +2748,9 @@ CONFIG_HID_SENSOR_DEVICE_ROTATION=m # CONFIG_PCH_PHUB is not set # CONFIG_USB_SWITCH_FSA9480 is not set # CONFIG_SRAM is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_BMP085_SPI is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set CONFIG_W1=m CONFIG_W1_CON=y @@ -2755,6 +2772,7 @@ CONFIG_W1_SLAVE_DS2780=m CONFIG_W1_SLAVE_DS2781=m CONFIG_W1_SLAVE_DS28E04=m CONFIG_W1_SLAVE_BQ27000=m +CONFIG_W1_SLAVE_DS2406=m # # Mice @@ -2811,7 +2829,6 @@ CONFIG_WM8350_WATCHDOG=m CONFIG_WM831X_WATCHDOG=m # CONFIG_MAX63XX_WATCHDOG is not set # CONFIG_DW_WATCHDOG is not set -CONFIG_W83697UG_WDT=m # CONFIG_MEN_A21_WDT is not set # CONFIG_GPIO_WATCHDOG is not set # CONFIG_XILINX_WATCHDOG is not set @@ -2876,6 +2893,20 @@ CONFIG_RTC_DRV_RV3029C2=m CONFIG_RTC_DRV_PCF50633=m CONFIG_RTC_DRV_DS3232=m CONFIG_RTC_DRV_ISL12022=m +CONFIG_RTC_DRV_MCP795=m +CONFIG_RTC_DRV_RX4581=m +CONFIG_RTC_DRV_PCF2123=m +CONFIG_RTC_DRV_DS3234=m +CONFIG_RTC_DRV_RS5C348=m +CONFIG_RTC_DRV_R9701=m +CONFIG_RTC_DRV_MAX6902=m +CONFIG_RTC_DRV_DS1390=m +CONFIG_RTC_DRV_DS1347=m +CONFIG_RTC_DRV_DS1343=m +CONFIG_RTC_DRV_DS1305=m +CONFIG_RTC_DRV_M41T94=m +CONFIG_RTC_DRV_M41T93=m +CONFIG_RTC_DRV_PCF85063=m # CONFIG_RTC_DRV_HID_SENSOR_TIME is not set # CONFIG_RTC_DRV_MOXART is not set # CONFIG_RTC_DRV_ISL12057 is not set @@ -2903,7 +2934,6 @@ CONFIG_AGP_EFFICEON=y CONFIG_VGA_ARB=y CONFIG_VGA_ARB_MAX_GPUS=16 -# CONFIG_STUB_POULSBO is not set CONFIG_DRM=m CONFIG_DRM_LOAD_EDID_FIRMWARE=y @@ -2912,7 +2942,6 @@ CONFIG_DRM_CIRRUS_QEMU=m # do not enable on f17 or older # CONFIG_DRM_TDFX is not set # CONFIG_DRM_R128 is not set CONFIG_DRM_RADEON=m -CONFIG_DRM_RADEON_KMS=y # CONFIG_DRM_RADEON_UMS is not set # CONFIG_DRM_I810 is not set # CONFIG_DRM_MGA is not set @@ -2923,14 +2952,11 @@ CONFIG_DRM_I915=m CONFIG_DRM_I915_KMS=y CONFIG_DRM_I915_FBDEV=y # CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT is not set -# CONFIG_DRM_I915_UMS is not set CONFIG_DRM_VIA=m CONFIG_DRM_NOUVEAU=m CONFIG_NOUVEAU_DEBUG=5 CONFIG_NOUVEAU_DEBUG_DEFAULT=3 CONFIG_DRM_NOUVEAU_BACKLIGHT=y -CONFIG_DRM_NOUVEAU_DEBUG=y -# CONFIG_DRM_PSB is not set CONFIG_DRM_I2C_CH7006=m CONFIG_DRM_I2C_SIL164=m CONFIG_DRM_I2C_NXP_TDA998X=m @@ -2966,9 +2992,9 @@ CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y CONFIG_MEDIA_RADIO_SUPPORT=y CONFIG_MEDIA_RC_SUPPORT=y CONFIG_MEDIA_CONTROLLER=y +# CONFIG_MEDIA_SDR_SUPPORT is not set CONFIG_VIDEO_DEV=m # CONFIG_VIDEO_ADV_DEBUG is not set -CONFIG_VIDEO_HELPER_CHIPS_AUTO=y CONFIG_VIDEO_V4L2=y # CONFIG_VIDEO_V4L2_INT_DEVICE is not set CONFIG_VIDEO_V4L2_SUBDEV_API=y @@ -2985,13 +3011,9 @@ CONFIG_VIDEO_V4L2_SUBDEV_API=y # # Video Adapters # -CONFIG_V4L_USB_DRIVERS=y -CONFIG_VIDEO_CAPTURE_DRIVERS=y -CONFIG_V4L_PCI_DRIVERS=y CONFIG_VIDEO_AU0828=m CONFIG_VIDEO_AU0828_V4L2=y CONFIG_VIDEO_BT848=m -CONFIG_VIDEO_BT848_DVB=y CONFIG_VIDEO_BWQCAM=m CONFIG_VIDEO_SR030PC30=m CONFIG_VIDEO_NOON010PC30=m @@ -3032,6 +3054,7 @@ CONFIG_VIDEO_SAA7134=m CONFIG_VIDEO_SAA7134_ALSA=m CONFIG_VIDEO_SAA7134_DVB=m CONFIG_VIDEO_SAA7134_RC=y +CONFIG_VIDEO_SOLO6X10=m CONFIG_VIDEO_USBVISION=m CONFIG_VIDEO_STK1160_COMMON=m CONFIG_VIDEO_STK1160=m @@ -3056,6 +3079,7 @@ CONFIG_VIDEO_TLG2300=m # CONFIG_VIDEO_M5MOLS is not set # CONFIG_EXYNOS_VIDEO is not set CONFIG_VIDEO_USBTV=m +# CONFIG_VIDEO_AU0828_RC is not set CONFIG_USB_VIDEO_CLASS=m CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y @@ -3073,14 +3097,11 @@ CONFIG_MEDIA_ATTACH=y # # V4L/DVB tuners -# Selected automatically by not setting CONFIG_MEDIA_TUNER_CUSTOMISE # -# CONFIG_MEDIA_TUNER_CUSTOMISE is not set # # Digital Video Broadcasting Devices # -CONFIG_DVB_CAPTURE_DRIVERS=y CONFIG_DVB_CORE=m CONFIG_DVB_NET=y CONFIG_DVB_MAX_ADAPTERS=8 @@ -3088,9 +3109,7 @@ CONFIG_DVB_DYNAMIC_MINORS=y # # DVB frontends -# Selected automatically by not setting CONFIG_DVB_FE_CUSTOMISE # -# CONFIG_DVB_FE_CUSTOMISE is not set # # Supported DVB bridge Modules @@ -3112,7 +3131,6 @@ CONFIG_DVB_USB_DW2102=m CONFIG_DVB_USB_FRIIO=m CONFIG_DVB_USB_EC168=m CONFIG_DVB_USB_PCTV452E=m -CONFIG_DVB_USB_IT913X=m CONFIG_DVB_USB_MXL111SF=m CONFIG_DVB_DM1105=m CONFIG_DVB_FIREDTV=m @@ -3193,7 +3211,6 @@ CONFIG_IR_RC5_DECODER=m CONFIG_IR_RC6_DECODER=m CONFIG_IR_JVC_DECODER=m CONFIG_IR_SONY_DECODER=m -CONFIG_IR_RC5_SZ_DECODER=m CONFIG_IR_SANYO_DECODER=m CONFIG_IR_SHARP_DECODER=m CONFIG_IR_MCE_KBD_DECODER=m @@ -3211,6 +3228,7 @@ CONFIG_IR_WINBOND_CIR=m CONFIG_IR_IGUANA=m CONFIG_IR_TTUSBIR=m CONFIG_IR_GPIO_CIR=m +CONFIG_IR_XMP_DECODER=m CONFIG_V4L_MEM2MEM_DRIVERS=y # CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set @@ -3223,14 +3241,11 @@ CONFIG_V4L_MEM2MEM_DRIVERS=y # # Broadcom Crystal HD video decoder driver # -CONFIG_CRYSTALHD=m # # Graphics support # -CONFIG_DISPLAY_SUPPORT=m -CONFIG_VIDEO_OUTPUT_CONTROL=m CONFIG_FB=y # CONFIG_FB_FOREIGN_ENDIAN is not set @@ -3353,6 +3368,7 @@ CONFIG_SND_RTCTIMER=y CONFIG_SND_DYNAMIC_MINORS=y CONFIG_SND_MAX_CARDS=32 # CONFIG_SND_SUPPORT_OLD_API is not set +# CONFIG_SND_SPI is not set # # Generic devices @@ -3413,7 +3429,6 @@ CONFIG_SND_HDA_INPUT_JACK=y CONFIG_SND_HDA_PATCH_LOADER=y CONFIG_SND_HDA_HWDEP=y CONFIG_SND_HDA_CODEC_REALTEK=y -CONFIG_SND_HDA_ENABLE_REALTEK_QUIRKS=y CONFIG_SND_HDA_CODEC_CA0110=y CONFIG_SND_HDA_CODEC_ANALOG=y CONFIG_SND_HDA_CODEC_SIGMATEL=y @@ -3500,7 +3515,6 @@ CONFIG_USB_SUPPORT=y # CONFIG_USB_DEBUG is not set # DEPRECATED: See bug 362221. Fix udev. -# CONFIG_USB_DEVICE_CLASS is not set # @@ -3508,11 +3522,9 @@ CONFIG_USB_SUPPORT=y # # Deprecated. -# CONFIG_USB_DEVICEFS is not set CONFIG_USB_DEFAULT_PERSIST=y # CONFIG_USB_DYNAMIC_MINORS is not set -CONFIG_USB_SUSPEND=y # # USB Host Controller Drivers @@ -3539,7 +3551,6 @@ CONFIG_USB_SL811_HCD_ISO=y # CONFIG_USB_SL811_CS is not set # CONFIG_USB_R8A66597_HCD is not set CONFIG_USB_XHCI_HCD=y -# CONFIG_USB_XHCI_HCD_DEBUGGING is not set # CONFIG_USB_MAX3421_HCD is not set # @@ -3567,7 +3578,6 @@ CONFIG_USB_STORAGE_KARMA=m CONFIG_USB_STORAGE_REALTEK=m CONFIG_REALTEK_AUTOPM=y CONFIG_USB_STORAGE_ENE_UB6250=m -# CONFIG_USB_LIBUSUAL is not set CONFIG_USB_UAS=m @@ -3576,7 +3586,6 @@ CONFIG_USB_UAS=m # CONFIG_USB_HID=y -CONFIG_HID_SUPPORT=y CONFIG_HID=y CONFIG_I2C_HID=m @@ -3587,12 +3596,10 @@ CONFIG_UHID=m CONFIG_HID_PID=y CONFIG_LOGITECH_FF=y CONFIG_HID_LOGITECH_DJ=m -CONFIG_LOGIWII_FF=y CONFIG_LOGIRUMBLEPAD2_FF=y CONFIG_PANTHERLORD_FF=y CONFIG_THRUSTMASTER_FF=y CONFIG_HID_WACOM=m -CONFIG_HID_WACOM_POWER_SUPPLY=y CONFIG_ZEROPLUS_FF=y CONFIG_USB_HIDDEV=y CONFIG_USB_IDMOUSE=m @@ -3604,9 +3611,7 @@ CONFIG_LOGIWHEELS_FF=y CONFIG_HID_MAGICMOUSE=y CONFIG_HID_MULTITOUCH=m CONFIG_HID_NTRIG=y -CONFIG_HID_QUANTA=y CONFIG_HID_PRIMAX=m -CONFIG_HID_PS3REMOTE=m CONFIG_HID_PRODIKEYS=m CONFIG_HID_DRAGONRISE=m CONFIG_HID_GYRATION=m @@ -3618,7 +3623,6 @@ CONFIG_HID_PETALYNX=m CONFIG_HID_PICOLCD=m CONFIG_HID_RMI=m CONFIG_HID_ROCCAT=m -CONFIG_HID_ROCCAT_KONE=m CONFIG_HID_SAMSUNG=m CONFIG_HID_SONY=m CONFIG_SONY_FF=y @@ -3643,22 +3647,16 @@ CONFIG_HID_ELECOM=m CONFIG_HID_ELO=m CONFIG_HID_UCLOGIC=m CONFIG_HID_WALTOP=m -CONFIG_HID_ROCCAT_PYRA=m -CONFIG_HID_ROCCAT_KONEPLUS=m CONFIG_HID_ACRUX=m CONFIG_HID_ACRUX_FF=y CONFIG_HID_KEYTOUCH=m CONFIG_HID_LCPOWER=m -CONFIG_HID_LENOVO_TPKBD=m -CONFIG_HID_ROCCAT_ARVO=m -CONFIG_HID_ROCCAT_ISKU=m -CONFIG_HID_ROCCAT_KOVAPLUS=m CONFIG_HID_HOLTEK=m CONFIG_HOLTEK_FF=y CONFIG_HID_HUION=m +CONFIG_HID_GT683R=m CONFIG_HID_SPEEDLINK=m CONFIG_HID_WIIMOTE=m -CONFIG_HID_WIIMOTE_EXT=y CONFIG_HID_KYE=m CONFIG_HID_SAITEK=m CONFIG_HID_TIVO=m @@ -3666,6 +3664,7 @@ CONFIG_HID_GENERIC=y CONFIG_HID_AUREAL=m CONFIG_HID_APPLEIR=m # CONFIG_HID_CP2112 is not set +CONFIG_HID_LENOVO=m # @@ -3679,7 +3678,6 @@ CONFIG_USB_MICROTEK=m # CONFIG_USB_DSBR=m -# CONFIG_USB_ET61X251 is not set CONFIG_USB_M5602=m CONFIG_USB_STV06XX=m CONFIG_USB_GSPCA=m @@ -3733,13 +3731,13 @@ CONFIG_USB_GSPCA_SE401=m CONFIG_USB_S2255=m # CONFIG_VIDEO_SH_MOBILE_CEU is not set # CONFIG_VIDEO_SH_MOBILE_CSI2 is not set -# CONFIG_USB_SN9C102 is not set CONFIG_USB_ZR364XX=m # CONFIG_SOC_CAMERA is not set # # USB Network adaptors # +CONFIG_USB_NET_DRIVERS=y CONFIG_USB_CATC=m CONFIG_USB_HSO=m CONFIG_USB_KAWETH=m @@ -3813,9 +3811,7 @@ CONFIG_USB_SERIAL_EDGEPORT_TI=m CONFIG_USB_SERIAL_EMPEG=m # CONFIG_USB_SERIAL_F81232 is not set CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_FUNSOFT=m CONFIG_USB_SERIAL_GARMIN=m -CONFIG_USB_SERIAL_HP4X=m CONFIG_USB_SERIAL_IPAQ=m CONFIG_USB_SERIAL_IPW=m CONFIG_USB_SERIAL_IR=m @@ -3840,11 +3836,9 @@ CONFIG_USB_SERIAL_MCT_U232=m # CONFIG_USB_SERIAL_METRO is not set CONFIG_USB_SERIAL_MOS7720=m CONFIG_USB_SERIAL_MOS7715_PARPORT=y -# CONFIG_USB_SERIAL_ZIO is not set # CONFIG_USB_SERIAL_WISHBONE is not set # CONFIG_USB_SERIAL_ZTE is not set CONFIG_USB_SERIAL_MOS7840=m -CONFIG_USB_SERIAL_MOTOROLA=m # CONFIG_USB_SERIAL_MXUPORT is not set CONFIG_USB_SERIAL_NAVMAN=m CONFIG_USB_SERIAL_OPTION=m @@ -3852,24 +3846,19 @@ CONFIG_USB_SERIAL_OTI6858=m CONFIG_USB_SERIAL_OPTICON=m CONFIG_USB_SERIAL_OMNINET=m CONFIG_USB_SERIAL_PL2303=m -# CONFIG_USB_SERIAL_QUATECH2 is not set CONFIG_USB_SERIAL_SAFE=m CONFIG_USB_SERIAL_SAFE_PADDED=y CONFIG_USB_SERIAL_SIERRAWIRELESS=m -CONFIG_USB_SERIAL_SIEMENS_MPI=m CONFIG_USB_SERIAL_SPCP8X5=m CONFIG_USB_SERIAL_TI=m CONFIG_USB_SERIAL_VISOR=m CONFIG_USB_SERIAL_WHITEHEAT=m CONFIG_USB_SERIAL_XIRCOM=m CONFIG_USB_SERIAL_QCAUX=m -CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m CONFIG_USB_SERIAL_XSENS_MT=m CONFIG_USB_SERIAL_DEBUG=m CONFIG_USB_SERIAL_SSU100=m CONFIG_USB_SERIAL_QT2=m -CONFIG_USB_SERIAL_FLASHLOADER=m -CONFIG_USB_SERIAL_SUUNTO=m CONFIG_USB_SERIAL_CONSOLE=y CONFIG_USB_EZUSB=y @@ -3894,6 +3883,8 @@ CONFIG_USB_PHY=y # CONFIG_GENERIC_PHY is not set # CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set # CONFIG_PHY_EXYNOS_DP_VIDEO is not set +# CONFIG_PHY_ST_SPEAR1310_MIPHY is not set +# CONFIG_PHY_ST_SPEAR1340_MIPHY is not set # CONFIG_AM335X_PHY_USB is not set # CONFIG_SAMSUNG_USBPHY is not set # CONFIG_SAMSUNG_USB2PHY is not set @@ -3906,8 +3897,6 @@ CONFIG_USB_CXACRU=m # CONFIG_USB_CYTHERM is not set CONFIG_USB_EMI26=m CONFIG_USB_FTDI_ELAN=m -CONFIG_USB_FILE_STORAGE=m -# CONFIG_USB_FILE_STORAGE_TEST is not set # CONFIG_USB_GADGET is not set # CONFIG_USB_DWC3 is not set # CONFIG_USB_GADGETFS is not set @@ -3917,6 +3906,7 @@ CONFIG_USB_ISIGHTFW=m CONFIG_USB_YUREX=m CONFIG_USB_EZUSB_FX2=m CONFIG_USB_HSIC_USB3503=m +# CONFIG_USB_LINK_LAYER_TEST is not set CONFIG_USB_LCD=m CONFIG_USB_LD=m CONFIG_USB_LEGOTOWER=m @@ -3944,13 +3934,11 @@ CONFIG_USB_UEAGLEATM=m CONFIG_USB_XUSBATM=m # CONFIG_USB_DWC2 is not set - -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y - # CONFIG_USB_ISP1301 is not set - # CONFIG_USB_OTG is not set +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + # # Sonics Silicon Backplane # @@ -3971,7 +3959,6 @@ CONFIG_PCF50633_GPIO=m CONFIG_INPUT_PCF50633_PMU=m CONFIG_INPUT_GPIO_ROTARY_ENCODER=m -CONFIG_MFD_SUPPORT=y CONFIG_MFD_VX855=m CONFIG_MFD_SM501=m CONFIG_MFD_SM501_GPIO=y @@ -4021,6 +4008,13 @@ CONFIG_MFD_VIPERBOARD=m # CONFIG_MFD_LP3943 is not set # CONFIG_MFD_BCM590XX is not set # CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_INTEL_SOC_PMIC is not set # @@ -4033,7 +4027,6 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_EXT3_FS is not set CONFIG_EXT4_FS=y CONFIG_EXT4_USE_FOR_EXT23=y -CONFIG_EXT4_FS_XATTR=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y CONFIG_JBD2=y @@ -4242,9 +4235,7 @@ CONFIG_GFS2_FS_LOCKING_DLM=y CONFIG_UBIFS_FS=m -CONFIG_UBIFS_FS_XATTR=y # CONFIG_UBIFS_FS_ADVANCED_COMPR is not set -# CONFIG_UBIFS_FS_DEBUG is not set # # Partition Types @@ -4342,6 +4333,9 @@ CONFIG_FRAME_WARN=1024 CONFIG_MAGIC_SYSRQ=y CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x0 CONFIG_DEBUG_INFO=y +# Revisit both of these options +# CONFIG_DEBUG_INFO_SPLIT is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set CONFIG_FRAME_POINTER=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set # CONFIG_DEBUG_DRIVER is not set @@ -4402,7 +4396,6 @@ CONFIG_EARLY_PRINTK_DBGP=y # CONFIG_CRASH_DUMP is not set # CONFIG_CRASH is not set # CONFIG_GCOV_KERNEL is not set -# CONFIG_RAMOOPS is not set CONFIG_KGDB=y CONFIG_KGDB_SERIAL_CONSOLE=y @@ -4435,12 +4428,10 @@ CONFIG_SECURITY_SELINUX_AVC_STATS=y CONFIG_AUDIT=y CONFIG_AUDITSYSCALL=y # http://lists.fedoraproject.org/pipermail/kernel/2013-February/004125.html -CONFIG_AUDIT_LOGINUID_IMMUTABLE=y CONFIG_SECCOMP=y CONFIG_STRICT_DEVMEM=y -# CONFIG_SSBI is not set # # Cryptographic options @@ -4511,6 +4502,7 @@ CONFIG_LIBCRC32C=m CONFIG_CRYPTO_CRC32C_INTEL=m CONFIG_CRYPTO_GHASH=m CONFIG_CRYPTO_ANSI_CPRNG=m +# CONFIG_CRYPTO_DRBG_MENU is not set CONFIG_CRYPTO_DEV_HIFN_795X=m CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y CONFIG_CRYPTO_PCRYPT=m @@ -4553,7 +4545,6 @@ CONFIG_CDROM_PKTCDVD_BUFFERS=8 CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_BACKLIGHT_CLASS_DEVICE=m # CONFIG_BACKLIGHT_GENERIC is not set -CONFIG_BACKLIGHT_PROGEAR=m # CONFIG_BACKLIGHT_ADP8860 is not set # CONFIG_BACKLIGHT_ADP8870 is not set # CONFIG_BACKLIGHT_LM3630 is not set @@ -4573,6 +4564,19 @@ CONFIG_BACKLIGHT_LP855X=m CONFIG_LCD_CLASS_DEVICE=m CONFIG_LCD_PLATFORM=m +# CONFIG_LCD_ILI922X is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +# CONFIG_LCD_S6E63M0 is not set +# CONFIG_LCD_LD9040 is not set +# CONFIG_LCD_AMS369FG06 is not set +# CONFIG_LCD_LMS501KF03 is not set +# CONFIG_LCD_HX8357 is not set +# CONFIG_LCD_L4F00242T03 is not set +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LTV350QV is not set + CONFIG_SCHED_DEBUG=y CONFIG_FAIR_GROUP_SCHED=y @@ -4605,6 +4609,7 @@ CONFIG_BLK_CGROUP=y CONFIG_RELAY=y CONFIG_PRINTK_TIME=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 CONFIG_ENABLE_MUST_CHECK=y # CONFIG_ENABLE_WARN_DEPRECATED is not set @@ -4656,15 +4661,10 @@ CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_TABLE=y CONFIG_CPU_FREQ_STAT=m CONFIG_CPU_FREQ_STAT_DETAILS=y -# CONFIG_IBMTR is not set -# CONFIG_SKISA is not set -# CONFIG_PROTEON is not set -# CONFIG_SMCTR is not set # CONFIG_MOUSE_ATIXL is not set @@ -4707,15 +4707,12 @@ CONFIG_MIGRATION=y CONFIG_BOUNCE=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y -# CONFIG_LEDS_AMS_DELTA is not set # CONFIG_LEDS_LOCOMO is not set # CONFIG_LEDS_NET48XX is not set -# CONFIG_LEDS_NET5501 is not set # CONFIG_LEDS_PCA9532 is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_BD2802 is not set # CONFIG_LEDS_S3C24XX is not set -# CONFIG_LEDS_PCA9633 is not set CONFIG_LEDS_DELL_NETBOOKS=m # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_LM355x is not set @@ -4723,7 +4720,6 @@ CONFIG_LEDS_DELL_NETBOOKS=m # CONFIG_LEDS_PWM is not set # CONFIG_LEDS_LP8501 is not set # CONFIG_LEDS_PCA963X is not set -# CONFIG_LEDS_PCA9685 is not set CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -4734,12 +4730,10 @@ CONFIG_LEDS_TRIGGER_BACKLIGHT=m CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_TRANSIENT=m CONFIG_LEDS_TRIGGER_CAMERA=m -CONFIG_LEDS_ALIX2=m CONFIG_LEDS_CLEVO_MAIL=m CONFIG_LEDS_INTEL_SS4200=m CONFIG_LEDS_LM3530=m # CONFIG_LEDS_LM3642 is not set -CONFIG_LEDS_LM3556=m CONFIG_LEDS_BLINKM=m CONFIG_LEDS_LP3944=m CONFIG_LEDS_LP5521=m @@ -4750,6 +4744,7 @@ CONFIG_LEDS_REGULATOR=m CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_WM8350=m CONFIG_LEDS_WM831X_STATUS=m +# CONFIG_LEDS_DAC124S085 is not set CONFIG_DMADEVICES=y CONFIG_DMA_ENGINE=y @@ -4760,6 +4755,7 @@ CONFIG_DW_DMAC_PCI=m # CONFIG_TIMB_DMA is not set # CONFIG_DMATEST is not set # CONFIG_FSL_EDMA is not set +# CONFIG_NBPFAXI_DMA is not set CONFIG_ASYNC_TX_DMA=y CONFIG_UNUSED_SYMBOLS=y @@ -4799,7 +4795,6 @@ CONFIG_NO_HZ=y CONFIG_TIMER_STATS=y CONFIG_HIGH_RES_TIMERS=y CONFIG_PERF_EVENTS=y -CONFIG_PERF_COUNTERS=y # Auxillary displays CONFIG_KS0108=m @@ -4822,7 +4817,6 @@ CONFIG_APM_POWER=m # CONFIG_BATTERY_DS2781 is not set # CONFIG_BATTERY_DS2782 is not set # CONFIG_BATTERY_SBS is not set -# CONFIG_BATTERY_BQ20Z75 is not set # CONFIG_BATTERY_DS2780 is not set # CONFIG_BATTERY_BQ27x00 is not set # CONFIG_BATTERY_MAX17040 is not set @@ -4870,7 +4864,6 @@ CONFIG_LIRC_SERIAL=m CONFIG_LIRC_SERIAL_TRANSMITTER=y CONFIG_LIRC_SASEM=m CONFIG_LIRC_SIR=m -CONFIG_LIRC_TTUSBIR=m # CONFIG_SAMPLES is not set @@ -4957,31 +4950,21 @@ CONFIG_STAGING_MEDIA=y # CONFIG_DVB_AS102 is not set # CONFIG_ET131X is not set # CONFIG_SLICOSS is not set -# CONFIG_WLAGS49_H2 is not set -# CONFIG_WLAGS49_H25 is not set # CONFIG_VIDEO_DT3155 is not set # CONFIG_TI_ST is not set # CONFIG_FB_XGI is not set # CONFIG_VIDEO_GO7007 is not set # CONFIG_I2C_BCM2048 is not set # CONFIG_VIDEO_TCM825X is not set -# CONFIG_USB_MSI3101 is not set # CONFIG_DT3155 is not set -# CONFIG_W35UND is not set # CONFIG_PRISM2_USB is not set # CONFIG_ECHO is not set CONFIG_USB_ATMEL=m # CONFIG_COMEDI is not set -# CONFIG_ASUS_OLED is not set # CONFIG_PANEL is not set -# CONFIG_TRANZPORT is not set -# CONFIG_POHMELFS is not set -# CONFIG_IDE_PHISON is not set # CONFIG_LINE6_USB is not set # CONFIG_VME_BUS is not set -# CONFIG_RAR_REGISTER is not set # CONFIG_VT6656 is not set -# CONFIG_USB_SERIAL_QUATECH_USB2 is not set # Larry Finger maintains these (rhbz 913753) CONFIG_RTLLIB=m CONFIG_RTLLIB_CRYPTO_CCMP=m @@ -4990,7 +4973,6 @@ CONFIG_RTLLIB_CRYPTO_WEP=m CONFIG_RTL8192E=m # CONFIG_INPUT_GPIO is not set # CONFIG_VIDEO_CX25821 is not set -# CONFIG_R8187SE is not set # CONFIG_R8188EU is not set # Larry Finger maintains (rhbz 1113422) CONFIG_R8192EE=m @@ -4998,48 +4980,25 @@ CONFIG_R8192EE=m # CONFIG_RTL8192U is not set CONFIG_R8723AU=m # Jes Sorensen maintains this (rhbz 1100162) # CONFIG_8723AU_AP_MODE is not set -# CONFIG_8723AU_P2P is not set # CONFIG_8723AU_BT_COEXIST is not set -# CONFIG_FB_SM7XX is not set -# CONFIG_SPECTRA is not set -# CONFIG_EASYCAP is not set # CONFIG_SOLO6X10 is not set -# CONFIG_ACPI_QUICKSTART is not set # CONFIG_LTE_GDM724X is not set CONFIG_R8712U=m # Larry Finger maintains this (rhbz 699618) -# CONFIG_R8712_AP is not set -# CONFIG_ATH6K_LEGACY is not set -# CONFIG_USB_ENESTORAGE is not set # CONFIG_BCM_WIMAX is not set -# CONFIG_USB_BTMTK is not set # CONFIG_FT1000 is not set # CONFIG_SPEAKUP is not set -# CONFIG_DX_SEP is not set # CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set # CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set -# CONFIG_RTS_PSTOR is not set CONFIG_ALTERA_STAPL=m # CONFIG_DVB_CXD2099 is not set # CONFIG_DVB_RTL2832_SDR is not set # CONFIG_PWM_FSL_FTM is not set # CONFIG_USBIP_CORE is not set # CONFIG_INTEL_MEI is not set -# CONFIG_ZCACHE is not set -# CONFIG_RTS5139 is not set -# CONFIG_NVEC_LEDS is not set # CONFIG_VT6655 is not set -# CONFIG_RAMSTER is not set # CONFIG_USB_WPAN_HCD is not set # CONFIG_WIMAX_GDM72XX is not set # CONFIG_IPACK_BUS is not set -# CONFIG_CSR_WIFI is not set -# CONFIG_ZCACHE2 is not set -# CONFIG_NET_VENDOR_SILICOM is not set -# CONFIG_SBYPASS is not set -# CONFIG_BPCTL is not set -# CONFIG_CED1401 is not set -# CONFIG_DGRP is not set -# CONFIG_SB105X is not set # CONFIG_LUSTRE_FS is not set # CONFIG_XILLYBUS is not set # CONFIG_DGAP is not set @@ -5060,7 +5019,6 @@ CONFIG_NOP_USB_XCEIV=m # CONFIG_IMA is not set CONFIG_IMA_MEASURE_PCR_IDX=10 -CONFIG_IMA_AUDIT=y CONFIG_IMA_LSM_RULES=y # CONFIG_EVM is not set @@ -5072,8 +5030,7 @@ CONFIG_LSM_MMAP_MIN_ADDR=65536 CONFIG_STRIP_ASM_SYMS=y # CONFIG_RCU_FANOUT_EXACT is not set -# FIXME: Revisit FAST_NO_HZ after it's fixed -# CONFIG_RCU_FAST_NO_HZ is not set +CONFIG_RCU_FAST_NO_HZ=y CONFIG_RCU_NOCB_CPU=y CONFIG_RCU_NOCB_CPU_ALL=y CONFIG_RCU_CPU_STALL_TIMEOUT=60 @@ -5090,15 +5047,6 @@ CONFIG_FSNOTIFY=y CONFIG_FANOTIFY=y CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y -CONFIG_IEEE802154=m -CONFIG_IEEE802154_6LOWPAN=m -CONFIG_IEEE802154_DRIVERS=m -CONFIG_IEEE802154_FAKEHARD=m -CONFIG_IEEE802154_FAKELB=m - -CONFIG_MAC802154=m -CONFIG_NET_MPLS_GSO=m - # CONFIG_HSR is not set # CONFIG_EXTCON is not set @@ -5120,6 +5068,7 @@ CONFIG_PTP_1588_CLOCK_PCH=m CONFIG_CLEANCACHE=y CONFIG_FRONTSWAP=y CONFIG_ZSWAP=y +# CONFIG_ZBUD is not set CONFIG_ZSMALLOC=y # CONFIG_PGTABLE_MAPPING is not set @@ -5151,7 +5100,6 @@ CONFIG_GPIO_VIPERBOARD=m # CONFIG_RADIO_MIROPCM20 is not set # CONFIG_USB_GPIO_VBUS is not set # CONFIG_GPIO_SCH is not set -# CONFIG_GPIO_LANGWELL is not set # CONFIG_GPIO_RDC321X is not set # CONFIG_GPIO_VX855 is not set # CONFIG_GPIO_PCH is not set @@ -5164,9 +5112,11 @@ CONFIG_GPIO_VIPERBOARD=m # CONFIG_GPIO_BCM_KONA is not set # CONFIG_GPIO_SCH311X is not set # CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set # FIXME: Why? -CONFIG_EVENT_POWER_TRACING_DEPRECATED=y CONFIG_TEST_KSTRTOX=y CONFIG_XZ_DEC=y @@ -5199,13 +5149,14 @@ CONFIG_PSTORE_RAM=m # CONFIG_TEST_MODULE is not set # CONFIG_TEST_USER_COPY is not set # CONFIG_TEST_BPF is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_TEST_RHASHTABLE is not set # CONFIG_AVERAGE is not set # CONFIG_VMXNET3 is not set # CONFIG_SIGMA is not set -CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 CONFIG_BCMA=m CONFIG_BCMA_BLOCKIO=y @@ -5233,6 +5184,7 @@ CONFIG_FMC_CHARDEV=m # CONFIG_GENWQE is not set # CONFIG_POWERCAP is not set +# CONFIG_THUNDERBOLT is not set # CONFIG_HSI is not set @@ -5244,10 +5196,10 @@ CONFIG_FMC_CHARDEV=m # CONFIG_MODULE_SIG is not set # CONFIG_SYSTEM_TRUSTED_KEYRING is not set # CONFIG_SYSTEM_BLACKLIST_KEYRING is not set -# CONFIG_MODULE_VERIFY_ELF is not set -# CONFIG_CRYPTO_KEY_TYPE is not set -# CONFIG_PGP_LIBRARY is not set -# CONFIG_PGP_PRELOAD is not set # CONFIG_RTC_DRV_EFI is not set # CONFIG_NET_XGENE is not set + +# CONFIG_GLOB_SELFTEST is not set + +# CONFIG_SBSAUART_TTY is not set diff --git a/config-i686-PAE b/config-i686-PAE index fdc8a8bd..eebaa6fb 100644 --- a/config-i686-PAE +++ b/config-i686-PAE @@ -1,6 +1,5 @@ # CONFIG_HIGHMEM4G is not set CONFIG_HIGHMEM64G=y -# CONFIG_OLPC_OPENFIRMWARE is not set CONFIG_XEN_DEV_EVTCHN=m CONFIG_XEN_SYS_HYPERVISOR=y diff --git a/config-nodebug b/config-nodebug index 29901613..ed691337 100644 --- a/config-nodebug +++ b/config-nodebug @@ -31,14 +31,12 @@ CONFIG_CPUMASK_OFFSTACK=y # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_DEBUG_FUNC_TRACE is not set # CONFIG_DEBUG_SG is not set # CONFIG_DEBUG_PI_LIST is not set # CONFIG_DEBUG_PAGEALLOC is not set -# CONFIG_DEBUG_WRITECOUNT is not set # CONFIG_DEBUG_OBJECTS is not set # CONFIG_DEBUG_OBJECTS_SELFTEST is not set # CONFIG_DEBUG_OBJECTS_FREE is not set @@ -53,7 +51,6 @@ CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1 # CONFIG_MODULE_FORCE_UNLOAD is not set -# CONFIG_SYSCTL_SYSCALL_CHECK is not set # CONFIG_DEBUG_NOTIFIERS is not set @@ -97,7 +94,6 @@ CONFIG_PM_ADVANCED_DEBUG=y # CONFIG_CEPH_LIB_PRETTYDEBUG is not set # CONFIG_QUOTA_DEBUG is not set -CONFIG_PCI_DEFAULT_USE_CRS=y CONFIG_KGDB_KDB=y CONFIG_KDB_KEYBOARD=y diff --git a/config-powerpc-generic b/config-powerpc-generic index 9c0ad601..bc0f9433 100644 --- a/config-powerpc-generic +++ b/config-powerpc-generic @@ -14,7 +14,6 @@ CONFIG_TAU_AVERAGE=y # CONFIG_GEN_RTC is not set # CONFIG_GEN_RTC_X is not set CONFIG_RTC_DRV_GENERIC=y -CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set CONFIG_ADB=y @@ -61,21 +60,17 @@ CONFIG_CAPI_EICON=y CONFIG_NVRAM=y -# CONFIG_PCMCIA_M8XX is not set # CONFIG_SCSI_AHA1542 is not set # CONFIG_SCSI_IN2000 is not set # CONFIG_SCSI_IPS is not set -# CONFIG_NI52 is not set # CONFIG_NI65 is not set # CONFIG_LANCE is not set # CONFIG_3C515 is not set -# CONFIG_ELPLUS is not set CONFIG_MEMORY_HOTPLUG=y # Stuff which wants bus_to_virt() or virt_to_bus() # CONFIG_BLK_CPQ_DA is not set -# CONFIG_VIDEO_STRADIS is not set # CONFIG_VIDEO_ZORAN is not set # CONFIG_ATM_HORIZON is not set # CONFIG_ATM_FIRESTREAM is not set @@ -97,7 +92,6 @@ CONFIG_PPC_MEDIA5200=y # CONFIG_PPC_LITE5200 is not set CONFIG_PPC_BESTCOMM=y CONFIG_PMAC_RACKMETER=m -CONFIG_USB_OHCI_HCD_PPC_SOC=y CONFIG_USB_OHCI_HCD_PCI=y CONFIG_USB_OHCI_HCD_PPC_OF=y CONFIG_USB_OHCI_HCD_PPC_OF_BE=y @@ -186,7 +180,6 @@ CONFIG_PATA_OF_PLATFORM=m CONFIG_USB_EHCI_HCD_PPC_OF=y # CONFIG_MPC5121_ADS is not set -# CONFIG_MPC5121_GENERIC is not set CONFIG_MTD_OF_PARTS=y # CONFIG_MTD_NAND_FSL_ELBC is not set CONFIG_THERMAL=y @@ -227,7 +220,6 @@ CONFIG_NET_VENDOR_IBM=y # CONFIG_QUICC_ENGINE is not set # CONFIG_QE_GPIO is not set -# CONFIG_MPC8xxx_GPIO is not set CONFIG_IDE_GD=y CONFIG_IDE_GD_ATA=y @@ -278,7 +270,6 @@ CONFIG_MMC_SDHCI_OF=m # CONFIG_CONSISTENT_SIZE_BOOL is not set -CONFIG_CAN_SJA1000_OF_PLATFORM=m CONFIG_PPC_EMULATED_STATS=y @@ -292,7 +283,6 @@ CONFIG_PPC_DISABLE_WERROR=y # CONFIG_XILINX_EMACLITE is not set CONFIG_GPIO_WM831X=m -# CONFIG_GPIO_LANGWELL is not set # CONFIG_GPIO_UCB1400 is not set # CONFIG_EDAC_MPC85XX is not set @@ -305,7 +295,6 @@ CONFIG_SPARSE_IRQ=y CONFIG_PATA_MACIO=y CONFIG_SERIAL_GRLIB_GAISLER_APBUART=m # CONFIG_PMIC_ADP5520 is not set -# CONFIG_MFD_88PM8607 is not set # CONFIG_MFD_MAX8997 is not set # CONFIG_MFD_TPS65910 is not set # CONFIG_MFD_TPS65912_I2C is not set @@ -314,7 +303,6 @@ CONFIG_SERIAL_GRLIB_GAISLER_APBUART=m # CONFIG_MMC_SDHCI_OF_ESDHC is not set # CONFIG_MMC_SDHCI_OF_HLWD is not set -# CONFIG_MFD_TC35892 is not set # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_GPIO_SCH is not set @@ -368,10 +356,7 @@ CONFIG_PPC_DENORMALISATION=y # CONFIG_RTC_DRV_SNVS is not set # CONFIG_ASYMMETRIC_KEY_TYPE is not set -# CONFIG_OF_DISPLAY_TIMING is not set -# CONFIG_OF_VIDEOMODE is not set -# CONFIG_POWERNV_MSI is not set # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_POWER_RESET_GPIO=y diff --git a/config-powerpc64 b/config-powerpc64 index 7f413359..e24be4fa 100644 --- a/config-powerpc64 +++ b/config-powerpc64 @@ -8,11 +8,9 @@ CONFIG_PPC_PMAC64=y CONFIG_PPC_MAPLE=y # CONFIG_PPC_CELL is not set # CONFIG_PPC_IBM_CELL_BLADE is not set -# CONFIG_PPC_ISERIES is not set CONFIG_PPC_PSERIES=y CONFIG_PPC_PMAC=y CONFIG_PPC_POWERNV=y -CONFIG_POWERNV_MSI=y CONFIG_PPC_POWERNV_RTAS=y CONFIG_SENSORS_IBMPOWERNV=y CONFIG_HW_RANDOM_POWERNV=m @@ -51,15 +49,10 @@ CONFIG_SCSI_IPR=m CONFIG_SCSI_IPR_TRACE=y CONFIG_SCSI_IPR_DUMP=y CONFIG_HVC_RTAS=y -# CONFIG_HVC_ISERIES is not set CONFIG_HVC_OPAL=y # iSeries device drivers # -# CONFIG_ISERIES_VETH is not set -CONFIG_VIODASD=m -CONFIG_VIOCD=m -CONFIG_VIOTAPE=m CONFIG_PASEMI_MAC=m CONFIG_SERIAL_OF_PLATFORM=m @@ -86,10 +79,8 @@ CONFIG_NR_CPUS=1024 # CONFIG_FB_ATY128 is not set # CONFIG_FB_ATY is not set -# CONFIG_POWER4_ONLY is not set CONFIG_RTAS_PROC=y -CONFIG_IOMMU_VMERGE=y CONFIG_NUMA=y CONFIG_NUMA_BALANCING=y CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y @@ -119,17 +110,14 @@ CONFIG_INFINIBAND_EHCA=m CONFIG_XMON_DISASSEMBLY=y -CONFIG_SCSI_IBMVSCSIS=m # CONFIG_TUNE_CELL is not set # CONFIG_BLK_DEV_PLATFORM is not set -# CONFIG_VIRQ_DEBUG is not set CONFIG_EDAC_CPC925=m CONFIG_FRAME_WARN=2048 -CONFIG_PHYP_DUMP=y CONFIG_FORCE_MAX_ZONEORDER=9 CONFIG_VIRTUALIZATION=y @@ -140,12 +128,14 @@ CONFIG_SCSI_IBMVFC=m CONFIG_IBM_BSR=m CONFIG_CRASH_DUMP=y +CONFIG_FA_DUMP=y CONFIG_RELOCATABLE=y CONFIG_RCU_FANOUT=64 CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set +CONFIG_CMA_AREAS=7 CONFIG_KVM_BOOK3S_64=m CONFIG_KVM_BOOK3S_64_HV=m CONFIG_KVM_BOOK3S_64_PR=m @@ -189,3 +179,5 @@ CONFIG_BPF_JIT=y # CONFIG_PPC_TRANSACTIONAL_MEM is not set # CONFIG_SND_HDA_INTEL is not set CONFIG_BLK_DEV_RSXX=m + +# CONFIG_CARL9170 is not set diff --git a/config-powerpc64le b/config-powerpc64le index 8fb97963..ee43fdb3 100644 --- a/config-powerpc64le +++ b/config-powerpc64le @@ -1,5 +1 @@ -# CONFIG_VIRTUALIZATION is not set -# CONFIG_BPF_JIT is not set CONFIG_CPU_LITTLE_ENDIAN=y - -# CONFIG_CARL9170 is not set diff --git a/config-powerpc64p7 b/config-powerpc64p7 index d8ce7e0b..60baede6 100644 --- a/config-powerpc64p7 +++ b/config-powerpc64p7 @@ -3,12 +3,9 @@ CONFIG_POWER7_CPU=y # CONFIG_PPC_MAPLE is not set # CONFIG_PPC_CELL is not set # CONFIG_PPC_IBM_CELL_BLADE is not set -# CONFIG_PPC_ISERIES is not set -# CONFIG_POWER3 is not set CONFIG_PPC_PSERIES=y # CONFIG_PPC_PMAC is not set CONFIG_PPC_POWERNV=y -CONFIG_POWERNV_MSI=y CONFIG_PPC_POWERNV_RTAS=y CONFIG_HW_RANDOM_POWERNV=m CONFIG_SENSORS_IBMPOWERNV=y @@ -43,15 +40,10 @@ CONFIG_SCSI_IPR=m CONFIG_SCSI_IPR_TRACE=y CONFIG_SCSI_IPR_DUMP=y CONFIG_HVC_RTAS=y -# CONFIG_HVC_ISERIES is not set CONFIG_HVC_OPAL=y # iSeries device drivers # -# CONFIG_ISERIES_VETH is not set -CONFIG_VIODASD=m -CONFIG_VIOCD=m -CONFIG_VIOTAPE=m CONFIG_SERIAL_OF_PLATFORM=m @@ -77,10 +69,8 @@ CONFIG_NR_CPUS=1024 # CONFIG_FB_ATY128 is not set # CONFIG_FB_ATY is not set -# CONFIG_POWER4_ONLY is not set CONFIG_RTAS_PROC=y -CONFIG_IOMMU_VMERGE=y CONFIG_NUMA=y CONFIG_NUMA_BALANCING=y CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y @@ -110,17 +100,14 @@ CONFIG_INFINIBAND_EHCA=m CONFIG_XMON_DISASSEMBLY=y -CONFIG_SCSI_IBMVSCSIS=m # CONFIG_TUNE_CELL is not set # CONFIG_BLK_DEV_PLATFORM is not set -# CONFIG_VIRQ_DEBUG is not set CONFIG_EDAC_CPC925=m CONFIG_FRAME_WARN=2048 -CONFIG_PHYP_DUMP=y CONFIG_FORCE_MAX_ZONEORDER=9 CONFIG_VIRTUALIZATION=y @@ -131,12 +118,14 @@ CONFIG_SCSI_IBMVFC=m CONFIG_IBM_BSR=m CONFIG_CRASH_DUMP=y +CONFIG_FA_DUMP=y CONFIG_RELOCATABLE=y CONFIG_RCU_FANOUT=64 CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set +CONFIG_CMA_AREAS=7 CONFIG_KVM_BOOK3S_64=m CONFIG_KVM_BOOK3S_64_HV=m CONFIG_KVM_BOOK3S_64_PR=m diff --git a/config-s390x b/config-s390x index 874f8084..f9472348 100644 --- a/config-s390x +++ b/config-s390x @@ -14,7 +14,6 @@ CONFIG_HZ_100=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_LOG_BUF_SHIFT=16 -CONFIG_NO_IDLE_HZ=y # # I/O subsystem configuration @@ -25,13 +24,9 @@ CONFIG_QDIO=m # Misc # CONFIG_IPL=y -# CONFIG_IPL_TAPE is not set -CONFIG_IPL_VM=y -# CONFIG_PROCESS_DEBUG is not set CONFIG_PFAULT=y CONFIG_SHARED_KERNEL=y CONFIG_CMM=m -CONFIG_CMM_PROC=y # CONFIG_NETIUCV is not set CONFIG_SMSGIUCV=m CONFIG_CRASH_DUMP=y @@ -40,7 +35,6 @@ CONFIG_CRASH_DUMP=y # SCSI low-level drivers # CONFIG_ZFCP=m -CONFIG_ZFCPDUMP=y CONFIG_CCW=y # @@ -83,7 +77,6 @@ CONFIG_TN3270_FS=m # # S/390 tape interface support # -CONFIG_S390_TAPE_BLOCK=y # # S/390 tape hardware support @@ -149,10 +142,7 @@ CONFIG_CRYPTO_AES_S390=m # CONFIG_PACK_STACK=y CONFIG_CHECK_STACK=y -# CONFIG_WARN_STACK is not set -# CONFIG_SMALL_STACK is not set -CONFIG_ZVM_WATCHDOG=m CONFIG_DIAG288_WATCHDOG=m CONFIG_VMLOGRDR=m CONFIG_MONREADER=m @@ -171,15 +161,12 @@ CONFIG_VIRT_CPU_ACCOUNTING=y CONFIG_STACK_GUARD=256 CONFIG_CMM_IUCV=y -# CONFIG_DETECT_SOFTLOCKUP is not set CONFIG_S390_HYPFS_FS=y CONFIG_MONWRITER=m CONFIG_ZCRYPT=m -CONFIG_ZCRYPT_MONOLITHIC=y -CONFIG_S390_EXEC_PROTECT=y CONFIG_AFIUCV=m CONFIG_S390_PRNG=m @@ -218,7 +205,6 @@ CONFIG_SMSGIUCV_EVENT=m CONFIG_VMCP=y -CONFIG_ZFCP_DIF=y CONFIG_SCHED_MC=y CONFIG_SCHED_BOOK=y @@ -235,10 +221,30 @@ CONFIG_SCM_BLOCK=m CONFIG_SCM_BLOCK_CLUSTER_WRITE=y # CONFIG_S390_PTDUMP is not set # CONFIG_ASYMMETRIC_KEY_TYPE is not set -# CONFIG_PCI is not set + +CONFIG_PCI=y +CONFIG_PCI_NR_FUNCTIONS=64 +CONFIG_PCI_NR_MSI=256 +CONFIG_HOTPLUG_PCI=y +CONFIG_HOTPLUG_PCI_CPCI=y +CONFIG_HOTPLUG_PCI_SHPC=y +CONFIG_HOTPLUG_PCI_S390=y # CONFIG_NEW_LEDS is not set # CONFIG_HID is not set +# CONFIG_MTD is not set + +# CONFIG_PARPORT is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_FB is not set +# CONFIG_MFD_CORE is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_CB710_CORE is not set +# CONFIG_FCOE is not set +# CONFIG_FUSION is not set +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set # CONFIG_INPUT is not set # CONFIG_INPUT_JOYDEV is not set @@ -248,6 +254,8 @@ CONFIG_SCM_BLOCK_CLUSTER_WRITE=y # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set # CONFIG_INPUT_MISC is not set +# CONFIG_GAMEPORT_EMU10K1 is not set +# CONFIG_GAMEPORT_FM801 is not set # CONFIG_SERIO is not set # CONFIG_ACCESSIBILITY is not set @@ -269,6 +277,17 @@ CONFIG_SCM_BLOCK_CLUSTER_WRITE=y # CONFIG_I2C_NFORCE2 is not set # CONFIG_PTP_1588_CLOCK is not set # CONFIG_PPS is not set +# CONFIG_W1 is not set +# CONFIG_HWMON is not set +# CONFIG_SSB is not set +# CONFIG_BCMA is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set +# CONFIG_LCD_CLASS_DEVICE is not set +# CONFIG_LCD_PLATFORM is not set +# CONFIG_BACKLIGHT_CLASS_DEVICE is not set +# CONFIG_MFD_RTSX_PCI is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_VX855 is not set # CONFIG_PHYLIB is not set # CONFIG_ATM_DRIVERS is not set @@ -282,4 +301,14 @@ CONFIG_SCM_BLOCK_CLUSTER_WRITE=y # CONFIG_FMC is not set +CONFIG_MLX4_EN=m +CONFIG_MLX4_EN_DCB=y +CONFIG_INFINIBAND=m +CONFIG_INFINIBAND_USER_ACCESS=m +CONFIG_MLX4_INFINIBAND=m +CONFIG_RDS=m +CONFIG_RDS_RDMA=m +CONFIG_RDS_TCP=m +CONFIG_IRQ_DOMAIN_DEBUG=y + CONFIG_CRASH=m diff --git a/config-x86-32-generic b/config-x86-32-generic index dac24a2c..13e1bac7 100644 --- a/config-x86-32-generic +++ b/config-x86-32-generic @@ -2,15 +2,9 @@ # CONFIG_X86_32_NON_STANDARD is not set -# CONFIG_X86_ELAN is not set # CONFIG_X86_GOLDFISH is not set -# CONFIG_X86_NUMAQ is not set -# CONFIG_X86_SUMMIT is not set CONFIG_X86_BIGSMP=y -# CONFIG_X86_VISWS is not set # CONFIG_X86_RDC321X is not set -# CONFIG_X86_ES7000 is not set -# CONFIG_M386 is not set # CONFIG_M486 is not set # CONFIG_M586 is not set # CONFIG_M586TSC is not set @@ -89,7 +83,6 @@ CONFIG_X86_LONGRUN=y # CONFIG_X86_E_POWERSAVER is not set CONFIG_X86_HT=y -CONFIG_X86_TRAMPOLINE=y # CONFIG_4KSTACKS is not set @@ -113,7 +106,6 @@ CONFIG_SCx200_ACB=m CONFIG_PC8736x_GPIO=m # CONFIG_NSC_GPIO is not set -CONFIG_CS5535_GPIO=m CONFIG_GPIO_SCH=m CONFIG_HW_RANDOM_GEODE=m @@ -143,7 +135,6 @@ CONFIG_LBDAF=y CONFIG_OLPC=y -CONFIG_OLPC_OPENFIRMWARE=y CONFIG_BATTERY_OLPC=y CONFIG_MOUSE_PS2_OLPC=y CONFIG_OLPC_XO1_PM=y @@ -160,10 +151,8 @@ CONFIG_RCU_FANOUT=32 # CONFIG_X86_ANCIENT_MCE is not set -# CONFIG_X86_MRST is not set CONFIG_I2C_PXA=m -# CONFIG_GPIO_LANGWELL is not set # CONFIG_INTEL_TXT is not set @@ -184,7 +173,6 @@ CONFIG_POWER_RESET_GPIO=y CONFIG_MTD_OF_PARTS=y CONFIG_MTD_PHYSMAP_OF=m -CONFIG_PROC_DEVICETREE=y CONFIG_SERIAL_OF_PLATFORM=m CONFIG_SERIAL_GRLIB_GAISLER_APBUART=m # CONFIG_MMC_SDHCI_OF is not set @@ -209,7 +197,6 @@ CONFIG_BACKLIGHT_PWM=m # CONFIG_EDAC_SBRIDGE is not set -# CONFIG_X86_WANT_INTEL_MID is not set # CONFIG_OF_SELFTEST is not set # CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set # CONFIG_INPUT_GP2A is not set @@ -223,12 +210,9 @@ CONFIG_BACKLIGHT_PWM=m # CONFIG_BACKLIGHT_OT200 is not set # CONFIG_RTC_DRV_SNVS is not set # CONFIG_RTC_DRV_HYM8563 is not set -# CONFIG_OF_DISPLAY_TIMING is not set -# CONFIG_OF_VIDEOMODE is not set # CONFIG_MLX5_INFINIBAND is not set # CONFIG_PINCTRL_SINGLE is not set -# CONFIG_PINCTRL_CAPRI is not set # CONFIG_PINCTRL_MSM8X74 is not set # CONFIG_PINCTRL_BCM281XX is not set # CONFIG_PINCTRL_APQ8064 is not set diff --git a/config-x86-generic b/config-x86-generic index fb84c0ac..686972fd 100644 --- a/config-x86-generic +++ b/config-x86-generic @@ -52,7 +52,6 @@ CONFIG_EFI_RUNTIME_MAP=y # CONFIG_FB_N411 is not set CONFIG_INTEL_IOMMU=y -CONFIG_DMAR_BROKEN_GFX_WA=y CONFIG_INTEL_IOMMU_FLOPPY_WA=y # CONFIG_INTEL_IOMMU_DEFAULT_ON is not set CONFIG_SCSI_ADVANSYS=m @@ -71,7 +70,6 @@ CONFIG_DEBUG_STACKOVERFLOW=y CONFIG_ACPI=y CONFIG_ACPI_AC=y -# CONFIG_ACPI_ASUS is not set CONFIG_ACPI_BATTERY=y CONFIG_ACPI_BUTTON=y CONFIG_ACPI_CONTAINER=y @@ -88,7 +86,6 @@ CONFIG_ACPI_VIDEO=m CONFIG_ACPI_INITRD_TABLE_OVERRIDE=y # FIXME: Next two are deprecated. Remove them when they disappear upstream # CONFIG_ACPI_PROCFS_POWER is not set -# CONFIG_ACPI_PROC_EVENT is not set CONFIG_PNPACPI=y CONFIG_ACPI_PROCESSOR_AGGREGATOR=m CONFIG_ACPI_HED=m @@ -121,6 +118,7 @@ CONFIG_CRYPTO_DEV_PADLOCK_SHA=m CONFIG_CRYPTO_DEV_CCP=y CONFIG_CRYPTO_DEV_CCP_DD=m CONFIG_CRYPTO_DEV_CCP_CRYPTO=m +CONFIG_CRYPTO_DEV_QAT_DH895xCC=m CONFIG_GENERIC_ISA_DMA=y @@ -144,6 +142,9 @@ CONFIG_IPW2200_QOS=y CONFIG_BLK_DEV_AMD74XX=y +# I2C_ACPI casues I2C to be built in. This should probably be fixed. +CONFIG_I2C=y +CONFIG_ACPI_I2C_OPREGION=y CONFIG_I2C_AMD756=m CONFIG_I2C_AMD756_S4882=m CONFIG_I2C_AMD8111=m @@ -185,6 +186,7 @@ CONFIG_EDAC_X38=m CONFIG_EDAC_MCE_INJ=m CONFIG_EDAC_DECODE_MCE=m CONFIG_EDAC_LEGACY_SYSFS=y +CONFIG_EDAC_IE31200=m CONFIG_SCHED_MC=y @@ -240,7 +242,6 @@ CONFIG_PVPANIC=m # CONFIG_TOUCHSCREEN_INTEL_MID is not set # CONFIG_SMSC37B787_WDT is not set -CONFIG_W83697HF_WDT=m CONFIG_VIA_WDT=m CONFIG_IE6XX_WDT=m @@ -264,7 +265,6 @@ CONFIG_PARAVIRT_TIME_ACCOUNTING=y # PARAVIRT_SPINLOCKS has a 5% perf hit on native hw (see kconfig) # CONFIG_PARAVIRT_SPINLOCKS is not set -CONFIG_KVM_CLOCK=y CONFIG_KVM_GUEST=y CONFIG_KVM_MMU_AUDIT=y # default $x would be nice... # CONFIG_KVM_DEBUG_FS is not set @@ -288,7 +288,6 @@ CONFIG_XEN_COMPAT_XENFS=y CONFIG_XEN_BACKEND=y CONFIG_XEN_BLKDEV_BACKEND=m CONFIG_XEN_DEBUG_FS=y -CONFIG_XEN_PLATFORM_PCI=y CONFIG_XEN_GNTDEV=m CONFIG_INPUT_XEN_KBDDEV_FRONTEND=m CONFIG_XEN_SELFBALLOONING=y @@ -369,6 +368,7 @@ CONFIG_X86_DECODER_SELFTEST=y CONFIG_ACPI_CMPC=m CONFIG_MSI_WMI=m CONFIG_TOSHIBA_BT_RFKILL=m +CONFIG_TOSHIBA_HAPS=m CONFIG_VGA_SWITCHEROO=y CONFIG_LPC_SCH=m @@ -379,12 +379,38 @@ CONFIG_GPIO_ICH=m # CONFIG_GPIO_MCP23S08 is not set # CONFIG_GPIO_F7188X is not set +# These should all go away with IC2_ACPI is fixed +# CONFIG_MFD_AS3711 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_AXP20X is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set + CONFIG_PCI_CNB20LE_QUIRK=y CONFIG_ACPI_EC_DEBUGFS=m # CONFIG_ACPI_APEI_ERST_DEBUG is not set -# CONFIG_ACPI_QUICKSTART is not set CONFIG_INTEL_IDLE=y @@ -469,6 +495,9 @@ CONFIG_VMWARE_VMCI_VSOCKETS=m CONFIG_XZ_DEC_X86=y CONFIG_MPILIB=y +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +CONFIG_SIGNED_PE_FILE_VERIFICATION=y CONFIG_SYSTEM_TRUSTED_KEYRING=y CONFIG_SYSTEM_BLACKLIST_KEYRING=y CONFIG_MODULE_SIG=y @@ -479,6 +508,9 @@ CONFIG_MODULE_SIG_SHA256=y CONFIG_EFI_SECURE_BOOT_SIG_ENFORCE=y CONFIG_EFI_SIGNATURE_LIST_PARSER=y +# CONFIG_KEXEC_FILE is not set +# CONFIG_KEXEC_VERIFY_SIG is not set + CONFIG_MODULE_SIG_UEFI=y CONFIG_VMXNET3=m diff --git a/config-x86_64-generic b/config-x86_64-generic index 2f098161..de467132 100644 --- a/config-x86_64-generic +++ b/config-x86_64-generic @@ -9,7 +9,6 @@ CONFIG_GENERIC_CPU=y CONFIG_X86_UV=y CONFIG_UV_MMTIMER=m CONFIG_NUMA=y -CONFIG_K8_NUMA=y CONFIG_AMD_NUMA=y CONFIG_X86_64_ACPI_NUMA=y # CONFIG_NUMA_EMU is not set @@ -42,6 +41,9 @@ CONFIG_CGROUP_HUGETLB=y CONFIG_MEM_SOFT_DIRTY=y CONFIG_KEXEC_JUMP=y +CONFIG_KEXEC_FILE=y +CONFIG_KEXEC_VERIFY_SIG=y +CONFIG_KEXEC_BZIMAGE_VERIFY_SIG=y CONFIG_ACPI_HOTPLUG_MEMORY=y @@ -49,6 +51,8 @@ CONFIG_ACPI_HOTPLUG_MEMORY=y CONFIG_INTEL_MIC_HOST=m CONFIG_INTEL_MIC_CARD=m +CONFIG_INTEL_MIC_BUS=m +CONFIG_INTEL_MIC_X100_DMA=m # SHPC has half-arsed PCI probing, which makes it load on too many systems CONFIG_HOTPLUG_PCI_SHPC=m @@ -62,7 +66,6 @@ CONFIG_CRYPTO_SHA1_SSSE3=m CONFIG_CRYPTO_SHA256_SSSE3=m CONFIG_CRYPTO_SHA512_SSSE3=m CONFIG_CRYPTO_BLOWFISH_X86_64=m -CONFIG_CRYPTO_BLOWFISH_AVX2_X86_64=m CONFIG_CRYPTO_TWOFISH_X86_64_3WAY=m CONFIG_CRYPTO_CAMELLIA_X86_64=m CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64=m @@ -73,7 +76,7 @@ CONFIG_CRYPTO_CRCT10DIF_PCLMUL=m CONFIG_CRYPTO_SERPENT_AVX_X86_64=m CONFIG_CRYPTO_SERPENT_AVX2_X86_64=m CONFIG_CRYPTO_TWOFISH_AVX_X86_64=m -CONFIG_CRYPTO_TWOFISH_AVX2_X86_64=m +CONFIG_CRYPTO_DES3_EDE_X86_64=m # staging crypto # CONFIG_CRYPTO_SKEIN is not set # CONFIG_CRYPTO_THREEFISH is not set @@ -144,7 +147,6 @@ CONFIG_RCU_FANOUT=64 CONFIG_INTEL_TXT=y -CONFIG_GPIO_LANGWELL=y CONFIG_FUNCTION_GRAPH_TRACER=y @@ -158,6 +160,8 @@ CONFIG_CHECKPOINT_RESTORE=y # Should be 32bit only, but lacks KConfig depends # CONFIG_XO15_EBOOK is not set +CONFIG_THUNDERBOLT=m + CONFIG_NTB=m CONFIG_NTB_NETDEV=m @@ -170,9 +174,12 @@ CONFIG_MLX4_EN_DCB=y CONFIG_SFC=m CONFIG_SFC_MCDI_MON=y CONFIG_SFC_SRIOV=y -CONFIG_SFC_PTP=y CONFIG_SFC_MTD=y # Override MTD stuff because SFC_MTD needs it -CONFIG_MTD_CHAR=m CONFIG_MTD_BLOCK=m +CONFIG_NO_HZ_FULL=y +# CONFIG_NO_HZ_IDLE is not set +# CONFIG_NO_HZ_FULL_ALL is not set +# CONFIG_NO_HZ_FULL_SYSIDLE is not set +# CONFIG_CONTEXT_TRACKING_FORCE is not set diff --git a/crash-driver.patch b/crash-driver.patch index 5765d046..9ec016d5 100644 --- a/crash-driver.patch +++ b/crash-driver.patch @@ -1,69 +1,67 @@ -Bugzilla: N/A -Upstream-status: Fedora mustard - -From 1786bc697d34af944e29437ce44337b0eb8b6799 Mon Sep 17 00:00:00 2001 -From: Kyle McMartin <kyle@dreadnought.bos.jkkm.org> +From: Dave Anderson <anderson@redhat.com> Date: Tue, 26 Nov 2013 12:42:46 -0500 Subject: [PATCH] crash-driver +Bugzilla: N/A +Upstream-status: Fedora mustard --- - arch/arm/include/asm/crash.h | 6 ++ - arch/arm64/include/asm/crash.h | 6 ++ - arch/ia64/include/asm/crash.h | 90 +++++++++++++++++++++++++++ - arch/ia64/kernel/ia64_ksyms.c | 3 + - arch/powerpc/include/asm/crash.h | 6 ++ - arch/s390/include/asm/crash.h | 60 ++++++++++++++++++ - arch/s390/mm/maccess.c | 2 + - arch/x86/include/asm/crash.h | 6 ++ - drivers/char/Kconfig | 3 + - drivers/char/Makefile | 2 + - drivers/char/crash.c | 128 +++++++++++++++++++++++++++++++++++++++ - include/asm-generic/crash.h | 72 ++++++++++++++++++++++ + arch/arm/include/asm/crash-driver.h | 6 ++ + arch/arm64/include/asm/crash-driver.h | 6 ++ + arch/ia64/include/asm/crash-driver.h | 90 ++++++++++++++++++++++ + arch/ia64/kernel/ia64_ksyms.c | 3 + + arch/powerpc/include/asm/crash-driver.h | 6 ++ + arch/s390/include/asm/crash-driver.h | 60 +++++++++++++++ + arch/s390/mm/maccess.c | 2 + + arch/x86/include/asm/crash-driver.h | 6 ++ + drivers/char/Kconfig | 3 + + drivers/char/Makefile | 2 + + drivers/char/crash.c | 128 ++++++++++++++++++++++++++++++++ + include/asm-generic/crash-driver.h | 72 ++++++++++++++++++ 12 files changed, 384 insertions(+) - create mode 100644 arch/arm/include/asm/crash.h - create mode 100644 arch/arm64/include/asm/crash.h - create mode 100644 arch/ia64/include/asm/crash.h - create mode 100644 arch/powerpc/include/asm/crash.h - create mode 100644 arch/s390/include/asm/crash.h - create mode 100644 arch/x86/include/asm/crash.h + create mode 100644 arch/arm/include/asm/crash-driver.h + create mode 100644 arch/arm64/include/asm/crash-driver.h + create mode 100644 arch/ia64/include/asm/crash-driver.h + create mode 100644 arch/powerpc/include/asm/crash-driver.h + create mode 100644 arch/s390/include/asm/crash-driver.h + create mode 100644 arch/x86/include/asm/crash-driver.h create mode 100644 drivers/char/crash.c - create mode 100644 include/asm-generic/crash.h + create mode 100644 include/asm-generic/crash-driver.h -diff --git a/arch/arm/include/asm/crash.h b/arch/arm/include/asm/crash.h +diff --git a/arch/arm/include/asm/crash-driver.h b/arch/arm/include/asm/crash-driver.h new file mode 100644 -index 0000000..1d2e537 +index 000000000000..06e7ae916601 --- /dev/null -+++ b/arch/arm/include/asm/crash.h ++++ b/arch/arm/include/asm/crash-driver.h @@ -0,0 +1,6 @@ +#ifndef _ARM_CRASH_H +#define _ARM_CRASH_H + -+#include <asm-generic/crash.h> ++#include <asm-generic/crash-driver.h> + +#endif /* _ARM_CRASH_H */ -diff --git a/arch/arm64/include/asm/crash.h b/arch/arm64/include/asm/crash.h +diff --git a/arch/arm64/include/asm/crash-driver.h b/arch/arm64/include/asm/crash-driver.h new file mode 100644 -index 0000000..a7fcc28 +index 000000000000..43b26da0c5d6 --- /dev/null -+++ b/arch/arm64/include/asm/crash.h ++++ b/arch/arm64/include/asm/crash-driver.h @@ -0,0 +1,6 @@ +#ifndef _ARM64_CRASH_H +#define _ARM64_CRASH_H + -+#include <asm-generic/crash.h> ++#include <asm-generic/crash-driver.h> + +#endif /* _ARM64_CRASH_H */ -diff --git a/arch/ia64/include/asm/crash.h b/arch/ia64/include/asm/crash.h +diff --git a/arch/ia64/include/asm/crash-driver.h b/arch/ia64/include/asm/crash-driver.h new file mode 100644 -index 0000000..28bd955 +index 000000000000..404bcb93c112 --- /dev/null -+++ b/arch/ia64/include/asm/crash.h ++++ b/arch/ia64/include/asm/crash-driver.h @@ -0,0 +1,90 @@ +#ifndef _ASM_IA64_CRASH_H +#define _ASM_IA64_CRASH_H + +/* -+ * linux/include/asm-ia64/crash.h ++ * linux/include/asm-ia64/crash-driver.h + * + * Copyright (c) 2004 Red Hat, Inc. All rights reserved. + * @@ -150,7 +148,7 @@ index 0000000..28bd955 + +#endif /* _ASM_IA64_CRASH_H */ diff --git a/arch/ia64/kernel/ia64_ksyms.c b/arch/ia64/kernel/ia64_ksyms.c -index 5b7791d..aee4b87 100644 +index 5b7791dd3965..aee4b870c763 100644 --- a/arch/ia64/kernel/ia64_ksyms.c +++ b/arch/ia64/kernel/ia64_ksyms.c @@ -84,6 +84,9 @@ EXPORT_SYMBOL(ia64_save_scratch_fpregs); @@ -163,23 +161,23 @@ index 5b7791d..aee4b87 100644 #if defined(CONFIG_IA64_ESI) || defined(CONFIG_IA64_ESI_MODULE) extern void esi_call_phys (void); EXPORT_SYMBOL_GPL(esi_call_phys); -diff --git a/arch/powerpc/include/asm/crash.h b/arch/powerpc/include/asm/crash.h +diff --git a/arch/powerpc/include/asm/crash-driver.h b/arch/powerpc/include/asm/crash-driver.h new file mode 100644 -index 0000000..daa8c4d +index 000000000000..50092d965dc5 --- /dev/null -+++ b/arch/powerpc/include/asm/crash.h ++++ b/arch/powerpc/include/asm/crash-driver.h @@ -0,0 +1,6 @@ +#ifndef _PPC64_CRASH_H +#define _PPC64_CRASH_H + -+#include <asm-generic/crash.h> ++#include <asm-generic/crash-driver.h> + +#endif /* _PPC64_CRASH_H */ -diff --git a/arch/s390/include/asm/crash.h b/arch/s390/include/asm/crash.h +diff --git a/arch/s390/include/asm/crash-driver.h b/arch/s390/include/asm/crash-driver.h new file mode 100644 -index 0000000..552be5e +index 000000000000..552be5e2c571 --- /dev/null -+++ b/arch/s390/include/asm/crash.h ++++ b/arch/s390/include/asm/crash-driver.h @@ -0,0 +1,60 @@ +#ifndef _S390_CRASH_H +#define _S390_CRASH_H @@ -242,10 +240,10 @@ index 0000000..552be5e + +#endif /* _S390_CRASH_H */ diff --git a/arch/s390/mm/maccess.c b/arch/s390/mm/maccess.c -index d1e0e0c..a2be459 100644 +index 2a2e35416d2f..a529181429bb 100644 --- a/arch/s390/mm/maccess.c +++ b/arch/s390/mm/maccess.c -@@ -219,6 +219,7 @@ void *xlate_dev_mem_ptr(unsigned long addr) +@@ -193,6 +193,7 @@ void *xlate_dev_mem_ptr(unsigned long addr) put_online_cpus(); return bounce; } @@ -253,25 +251,25 @@ index d1e0e0c..a2be459 100644 /* * Free converted buffer for /dev/mem access (if necessary) -@@ -228,3 +229,4 @@ void unxlate_dev_mem_ptr(unsigned long addr, void *buf) +@@ -202,3 +203,4 @@ void unxlate_dev_mem_ptr(unsigned long addr, void *buf) if ((void *) addr != buf) free_page((unsigned long) buf); } +EXPORT_SYMBOL_GPL(unxlate_dev_mem_ptr); -diff --git a/arch/x86/include/asm/crash.h b/arch/x86/include/asm/crash.h +diff --git a/arch/x86/include/asm/crash-driver.h b/arch/x86/include/asm/crash-driver.h new file mode 100644 -index 0000000..27a4156 +index 000000000000..fd4736ec99f5 --- /dev/null -+++ b/arch/x86/include/asm/crash.h ++++ b/arch/x86/include/asm/crash-driver.h @@ -0,0 +1,6 @@ +#ifndef _X86_CRASH_H +#define _X86_CRASH_H + -+#include <asm-generic/crash.h> ++#include <asm-generic/crash-driver.h> + +#endif /* _X86_CRASH_H */ diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig -index fa3243d..83643e5b 100644 +index 6e9f74a5c095..ee6bae16b04c 100644 --- a/drivers/char/Kconfig +++ b/drivers/char/Kconfig @@ -4,6 +4,9 @@ @@ -285,10 +283,10 @@ index fa3243d..83643e5b 100644 config DEVKMEM diff --git a/drivers/char/Makefile b/drivers/char/Makefile -index 7ff1d0d..3ed67af 100644 +index a324f9303e36..33ce2fb1d0a3 100644 --- a/drivers/char/Makefile +++ b/drivers/char/Makefile -@@ -62,3 +62,5 @@ obj-$(CONFIG_JS_RTC) += js-rtc.o +@@ -61,3 +61,5 @@ obj-$(CONFIG_JS_RTC) += js-rtc.o js-rtc-y = rtc.o obj-$(CONFIG_TILE_SROM) += tile-srom.o @@ -296,7 +294,7 @@ index 7ff1d0d..3ed67af 100644 +obj-$(CONFIG_CRASH) += crash.o diff --git a/drivers/char/crash.c b/drivers/char/crash.c new file mode 100644 -index 0000000..a142bb3 +index 000000000000..085378a1d539 --- /dev/null +++ b/drivers/char/crash.c @@ -0,0 +1,128 @@ @@ -332,7 +330,7 @@ index 0000000..a142bb3 +#include <asm/io.h> +#include <asm/uaccess.h> +#include <asm/types.h> -+#include <asm/crash.h> ++#include <asm/crash-driver.h> + +#define CRASH_VERSION "1.0" + @@ -428,17 +426,17 @@ index 0000000..a142bb3 +module_exit(crash_cleanup_module); + +MODULE_LICENSE("GPL"); -diff --git a/include/asm-generic/crash.h b/include/asm-generic/crash.h +diff --git a/include/asm-generic/crash-driver.h b/include/asm-generic/crash-driver.h new file mode 100644 -index 0000000..8a0a69a +index 000000000000..25ab9869d566 --- /dev/null -+++ b/include/asm-generic/crash.h ++++ b/include/asm-generic/crash-driver.h @@ -0,0 +1,72 @@ +#ifndef __CRASH_H__ +#define __CRASH_H__ + +/* -+ * include/linux/crash.h ++ * include/linux/crash-driver.h + * + * Copyright (c) 2013 Red Hat, Inc. All rights reserved. + * @@ -507,5 +505,5 @@ index 0000000..8a0a69a + +#endif /* __CRASH_H__ */ -- -1.8.3.1 +1.9.3 diff --git a/criu-no-expert.patch b/criu-no-expert.patch index 28c8a987..2ac9eb04 100644 --- a/criu-no-expert.patch +++ b/criu-no-expert.patch @@ -1,11 +1,18 @@ +From: "kernel-team@fedoraproject.org" <kernel-team@fedoraproject.org> +Date: Wed, 30 Jan 2013 10:55:31 -0500 +Subject: [PATCH] criu: no expert + Bugzilla: N/A Upstream-status: Fedora mustard +--- + init/Kconfig | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/init/Kconfig b/init/Kconfig -index be8b7f5..7461760 100644 +index 3c866db603a7..bfb3c54d5286 100644 --- a/init/Kconfig +++ b/init/Kconfig -@@ -989,7 +989,7 @@ config DEBUG_BLK_CGROUP +@@ -1149,7 +1149,7 @@ config DEBUG_BLK_CGROUP endif # CGROUPS config CHECKPOINT_RESTORE @@ -14,7 +21,7 @@ index be8b7f5..7461760 100644 default n help Enables additional kernel features in a sake of checkpoint/restore. -@@ -1000,7 +1000,7 @@ config CHECKPOINT_RESTORE +@@ -1160,7 +1160,7 @@ config CHECKPOINT_RESTORE If unsure, say N here. menuconfig NAMESPACES @@ -23,3 +30,6 @@ index be8b7f5..7461760 100644 default !EXPERT help Provides the way to make tasks work with different objects using +-- +1.9.3 + diff --git a/die-floppy-die.patch b/die-floppy-die.patch index 8fd0f3f1..b77c37a9 100644 --- a/die-floppy-die.patch +++ b/die-floppy-die.patch @@ -1,24 +1,23 @@ -Bugzilla: N/A -Upstream-status: Fedora mustard - -From 4ff58b642f80dedb20533978123d89b5ac9b1ed5 Mon Sep 17 00:00:00 2001 From: Kyle McMartin <kyle@phobos.i.jkkm.org> Date: Tue, 30 Mar 2010 00:04:29 -0400 -Subject: die-floppy-die +Subject: [PATCH] die-floppy-die Kill the floppy.ko pnp modalias. We were surviving just fine without autoloading floppy drivers, tyvm. Please feel free to register all complaints in the wastepaper bin. + +Bugzilla: N/A +Upstream-status: Fedora mustard --- - drivers/block/floppy.c | 3 +-- - 1 files changed, 1 insertions(+), 2 deletions(-) + drivers/block/floppy.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c -index 90c4038..f4a0b90 100644 +index 56d46ffb08e1..1c8db250df88 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c -@@ -4619,8 +4619,7 @@ static const struct pnp_device_id floppy_pnpids[] = { +@@ -4634,8 +4634,7 @@ static const struct pnp_device_id floppy_pnpids[] = { {"PNP0700", 0}, {} }; @@ -29,5 +28,5 @@ index 90c4038..f4a0b90 100644 #else -- -1.7.0.1 +1.9.3 diff --git a/disable-i8042-check-on-apple-mac.patch b/disable-i8042-check-on-apple-mac.patch index ec6e4859..73d8037f 100644 --- a/disable-i8042-check-on-apple-mac.patch +++ b/disable-i8042-check-on-apple-mac.patch @@ -1,10 +1,6 @@ -Bugzilla: N/A -Upstream-status: http://lkml.indiana.edu/hypermail/linux/kernel/1005.0/00938.html (and pinged on Dec 17, 2013) - -From 2a79554c864ac58fa2ad982f0fcee2cc2aa33eb5 Mon Sep 17 00:00:00 2001 From: Bastien Nocera <hadess@hadess.net> Date: Thu, 20 May 2010 10:30:31 -0400 -Subject: Disable i8042 checks on Intel Apple Macs +Subject: [PATCH] disable i8042 check on apple mac As those computers never had any i8042 controllers, and the current lookup code could potentially lock up/hang/wait for @@ -12,16 +8,19 @@ timeout for long periods of time. Fixes intermittent hangs on boot on a MacbookAir1,1 +Bugzilla: N/A +Upstream-status: http://lkml.indiana.edu/hypermail/linux/kernel/1005.0/00938.html (and pinged on Dec 17, 2013) + Signed-off-by: Bastien Nocera <hadess@hadess.net> --- - drivers/input/serio/i8042.c | 22 ++++++++++++++++++++++ - 1 files changed, 22 insertions(+), 0 deletions(-) + drivers/input/serio/i8042.c | 22 ++++++++++++++++++++++ + 1 file changed, 22 insertions(+) diff --git a/drivers/input/serio/i8042.c b/drivers/input/serio/i8042.c -index 6440a8f..4d7cf98 100644 +index 9bb95eab6926..4b5015f27f9e 100644 --- a/drivers/input/serio/i8042.c +++ b/drivers/input/serio/i8042.c -@@ -1451,6 +1451,22 @@ static struct platform_driver i8042_driver = { +@@ -1471,6 +1471,22 @@ static struct platform_driver i8042_driver = { .shutdown = i8042_shutdown, }; @@ -44,7 +43,7 @@ index 6440a8f..4d7cf98 100644 static int __init i8042_init(void) { struct platform_device *pdev; -@@ -1458,6 +1474,12 @@ static int __init i8042_init(void) +@@ -1478,6 +1494,12 @@ static int __init i8042_init(void) dbg_init(); @@ -58,5 +57,5 @@ index 6440a8f..4d7cf98 100644 if (err) return err; -- -1.7.0.1 +1.9.3 diff --git a/disable-libdw-unwind-on-non-x86.patch b/disable-libdw-unwind-on-non-x86.patch index 445fc194..a57c7060 100644 --- a/disable-libdw-unwind-on-non-x86.patch +++ b/disable-libdw-unwind-on-non-x86.patch @@ -1,9 +1,19 @@ +From: "kernel-team@fedoraproject.org" <kernel-team@fedoraproject.org> +Date: Fri, 18 Apr 2014 06:58:29 -0400 +Subject: [PATCH] disable libdw unwind on non-x86 + +Bugzilla: 1025603 +Upstream-status: ?? +--- + tools/perf/config/Makefile | 4 ++++ + 1 file changed, 4 insertions(+) + diff --git a/tools/perf/config/Makefile b/tools/perf/config/Makefile -index ee21fa9..19ee413 100644 +index 1f67aa02d240..86c21a24da46 100644 --- a/tools/perf/config/Makefile +++ b/tools/perf/config/Makefile -@@ -34,6 +34,10 @@ ifeq ($(ARCH),arm) - LIBUNWIND_LIBS = -lunwind -lunwind-arm +@@ -52,6 +52,10 @@ ifeq ($(ARCH),powerpc) + CFLAGS += -DHAVE_SKIP_CALLCHAIN_IDX endif +ifneq ($(ARCH),x86) @@ -13,3 +23,6 @@ index ee21fa9..19ee413 100644 ifeq ($(LIBUNWIND_LIBS),) NO_LIBUNWIND := 1 else +-- +1.9.3 + diff --git a/drm-i915-hush-check-crtc-state.patch b/drm-i915-hush-check-crtc-state.patch index 295cad7b..b4bea5f7 100644 --- a/drm-i915-hush-check-crtc-state.patch +++ b/drm-i915-hush-check-crtc-state.patch @@ -1,15 +1,23 @@ -Bugzilla: 1027037 1028785 -Upstream-status: http://lists.freedesktop.org/archives/intel-gfx/2013-November/035948.html +From: Adam Jackson <ajax@redhat.com> +Date: Wed, 13 Nov 2013 10:17:24 -0500 +Subject: [PATCH] drm/i915: hush check crtc state This is _by far_ the most common backtrace for i915 on retrace.fp.o, and it's mostly useless noise. There's not enough context when it's generated to know if something actually went wrong. Downgrade the message to KMS debugging so we can still get it if we want it. -diff -up linux-3.13.0-0.rc0.git2.1.fc21.x86_64/drivers/gpu/drm/i915/intel_display.c.jx linux-3.13.0-0.rc0.git2.1.fc21.x86_64/drivers/gpu/drm/i915/intel_display.c ---- linux-3.13.0-0.rc0.git2.1.fc21.x86_64/drivers/gpu/drm/i915/intel_display.c.jx 2013-11-03 18:41:51.000000000 -0500 -+++ linux-3.13.0-0.rc0.git2.1.fc21.x86_64/drivers/gpu/drm/i915/intel_display.c 2013-11-13 10:12:05.781301624 -0500 -@@ -8803,7 +8803,7 @@ check_crtc_state(struct drm_device *dev) +Bugzilla: 1027037 1028785 +Upstream-status: http://lists.freedesktop.org/archives/intel-gfx/2013-November/035948.html +--- + drivers/gpu/drm/i915/intel_display.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c +index d8324c69fa86..ee0ca36930f8 100644 +--- a/drivers/gpu/drm/i915/intel_display.c ++++ b/drivers/gpu/drm/i915/intel_display.c +@@ -10656,7 +10656,7 @@ check_crtc_state(struct drm_device *dev) if (active && !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { @@ -18,3 +26,6 @@ diff -up linux-3.13.0-0.rc0.git2.1.fc21.x86_64/drivers/gpu/drm/i915/intel_displa intel_dump_pipe_config(crtc, &pipe_config, "[hw state]"); intel_dump_pipe_config(crtc, &crtc->config, +-- +1.9.3 + diff --git a/drm-vmwgfx-Fix-drm.h-include.patch b/drm-vmwgfx-Fix-drm.h-include.patch new file mode 100644 index 00000000..9e6929b9 --- /dev/null +++ b/drm-vmwgfx-Fix-drm.h-include.patch @@ -0,0 +1,34 @@ +From: Josh Boyer <jwboyer@fedoraproject.org> +Date: Fri, 5 Sep 2014 13:19:59 -0400 +Subject: [PATCH] drm/vmwgfx: Fix drm.h include + +The userspace drm.h include doesn't prefix the drm directory. This can lead +to compile failures as /usr/include/drm/ isn't in the standard gcc include +paths. Fix it to be <drm/drm.h>, which matches the rest of the driver drm +header files that get installed into /usr/include/drm. + +Red Hat Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1138759 + +Fixes: 1d7a5cbf8f74e +Reported-by: Jeffrey Bastian <jbastian@redhat.com> +Signed-off-by: Josh Boyer <jwboyer@fedoraproject.org> +--- + include/uapi/drm/vmwgfx_drm.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/include/uapi/drm/vmwgfx_drm.h b/include/uapi/drm/vmwgfx_drm.h +index 4fc66f6b12ce..c472bedbe38e 100644 +--- a/include/uapi/drm/vmwgfx_drm.h ++++ b/include/uapi/drm/vmwgfx_drm.h +@@ -29,7 +29,7 @@ + #define __VMWGFX_DRM_H__ + + #ifndef __KERNEL__ +-#include <drm.h> ++#include <drm/drm.h> + #endif + + #define DRM_VMW_MAX_SURFACE_FACES 6 +-- +1.9.3 + diff --git a/eeepc-wmi-Add-no-backlight-quirk-for-Asus-H87I-PLUS-.patch b/eeepc-wmi-Add-no-backlight-quirk-for-Asus-H87I-PLUS-.patch deleted file mode 100644 index 4cb49332..00000000 --- a/eeepc-wmi-Add-no-backlight-quirk-for-Asus-H87I-PLUS-.patch +++ /dev/null @@ -1,50 +0,0 @@ -Bugzilla: 1097463 -Upstream-status: Sent for 3.16 - -From 7ad066ecd4dfb4c36fb00f9f9eb1a5d6099db834 Mon Sep 17 00:00:00 2001 -From: Hans de Goede <hdegoede@redhat.com> -Date: Mon, 2 Jun 2014 17:41:02 +0200 -Subject: [PATCH 05/14] eeepc-wmi: Add no backlight quirk for Asus H87I-PLUS - Motherboard - -https://bugzilla.redhat.com/show_bug.cgi?id=1097436 - -Signed-off-by: Hans de Goede <hdegoede@redhat.com> ---- - drivers/platform/x86/eeepc-wmi.c | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - -diff --git a/drivers/platform/x86/eeepc-wmi.c b/drivers/platform/x86/eeepc-wmi.c -index 6112933f6278..a7286bbfe28e 100644 ---- a/drivers/platform/x86/eeepc-wmi.c -+++ b/drivers/platform/x86/eeepc-wmi.c -@@ -114,6 +114,10 @@ static struct quirk_entry quirk_asus_x101ch = { - .wmi_backlight_power = true, - }; - -+static struct quirk_entry quirk_asus_no_backlight = { -+ .no_backlight = true, -+}; -+ - static struct quirk_entry *quirks; - - static void et2012_quirks(void) -@@ -182,6 +186,15 @@ static struct dmi_system_id asus_quirks[] = { - }, - .driver_data = &quirk_asus_x101ch, - }, -+ { -+ .callback = dmi_matched, -+ .ident = "ASUSTeK Computer INC. H87I-PLUS", -+ .matches = { -+ DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC."), -+ DMI_MATCH(DMI_BOARD_NAME, "H87I-PLUS"), -+ }, -+ .driver_data = &quirk_asus_no_backlight, -+ }, - {}, - }; - --- -1.9.0 - diff --git a/efi-Add-EFI_SECURE_BOOT-bit.patch b/efi-Add-EFI_SECURE_BOOT-bit.patch new file mode 100644 index 00000000..8f49e006 --- /dev/null +++ b/efi-Add-EFI_SECURE_BOOT-bit.patch @@ -0,0 +1,42 @@ +From: Josh Boyer <jwboyer@fedoraproject.org> +Date: Tue, 27 Aug 2013 13:33:03 -0400 +Subject: [PATCH] efi: Add EFI_SECURE_BOOT bit + +UEFI machines can be booted in Secure Boot mode. Add a EFI_SECURE_BOOT bit +for use with efi_enabled. + +Signed-off-by: Josh Boyer <jwboyer@fedoraproject.org> +--- + arch/x86/kernel/setup.c | 2 ++ + include/linux/efi.h | 1 + + 2 files changed, 3 insertions(+) + +diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c +index 5a5cf7395724..fb282ff6a802 100644 +--- a/arch/x86/kernel/setup.c ++++ b/arch/x86/kernel/setup.c +@@ -1144,7 +1144,9 @@ void __init setup_arch(char **cmdline_p) + + #ifdef CONFIG_EFI_SECURE_BOOT_SIG_ENFORCE + if (boot_params.secure_boot) { ++ set_bit(EFI_SECURE_BOOT, &efi.flags); + enforce_signed_modules(); ++ pr_info("Secure boot enabled\n"); + } + #endif + +diff --git a/include/linux/efi.h b/include/linux/efi.h +index 45cb4ffdea62..ebe6a24cc1e1 100644 +--- a/include/linux/efi.h ++++ b/include/linux/efi.h +@@ -923,6 +923,7 @@ extern int __init efi_setup_pcdp_console(char *); + #define EFI_64BIT 5 /* Is the firmware 64-bit? */ + #define EFI_PARAVIRT 6 /* Access is via a paravirt interface */ + #define EFI_ARCH_1 7 /* First arch-specific bit */ ++#define EFI_SECURE_BOOT 8 /* Are we in Secure Boot mode? */ + + #ifdef CONFIG_EFI + /* +-- +1.9.3 + diff --git a/efi-Disable-secure-boot-if-shim-is-in-insecure-mode.patch b/efi-Disable-secure-boot-if-shim-is-in-insecure-mode.patch new file mode 100644 index 00000000..928e1457 --- /dev/null +++ b/efi-Disable-secure-boot-if-shim-is-in-insecure-mode.patch @@ -0,0 +1,57 @@ +From: Josh Boyer <jwboyer@fedoraproject.org> +Date: Tue, 5 Feb 2013 19:25:05 -0500 +Subject: [PATCH] efi: Disable secure boot if shim is in insecure mode + +A user can manually tell the shim boot loader to disable validation of +images it loads. When a user does this, it creates a UEFI variable called +MokSBState that does not have the runtime attribute set. Given that the +user explicitly disabled validation, we can honor that and not enable +secure boot mode if that variable is set. + +Signed-off-by: Josh Boyer <jwboyer@fedoraproject.org> +--- + arch/x86/boot/compressed/eboot.c | 20 +++++++++++++++++++- + 1 file changed, 19 insertions(+), 1 deletion(-) + +diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c +index 975d11bfaf5b..94bf7819857a 100644 +--- a/arch/x86/boot/compressed/eboot.c ++++ b/arch/x86/boot/compressed/eboot.c +@@ -817,8 +817,9 @@ out: + + static int get_secure_boot(void) + { +- u8 sb, setup; ++ u8 sb, setup, moksbstate; + unsigned long datasize = sizeof(sb); ++ u32 attr; + efi_guid_t var_guid = EFI_GLOBAL_VARIABLE_GUID; + efi_status_t status; + +@@ -842,6 +843,23 @@ static int get_secure_boot(void) + if (setup == 1) + return 0; + ++ /* See if a user has put shim into insecure_mode. If so, and the variable ++ * doesn't have the runtime attribute set, we might as well honor that. ++ */ ++ var_guid = EFI_SHIM_LOCK_GUID; ++ status = efi_early->call((unsigned long)sys_table->runtime->get_variable, ++ L"MokSBState", &var_guid, &attr, &datasize, ++ &moksbstate); ++ ++ /* If it fails, we don't care why. Default to secure */ ++ if (status != EFI_SUCCESS) ++ return 1; ++ ++ if (!(attr & EFI_VARIABLE_RUNTIME_ACCESS)) { ++ if (moksbstate == 1) ++ return 0; ++ } ++ + return 1; + } + +-- +1.9.3 + diff --git a/efi-Make-EFI_SECURE_BOOT_SIG_ENFORCE-depend-on-EFI.patch b/efi-Make-EFI_SECURE_BOOT_SIG_ENFORCE-depend-on-EFI.patch new file mode 100644 index 00000000..18d26948 --- /dev/null +++ b/efi-Make-EFI_SECURE_BOOT_SIG_ENFORCE-depend-on-EFI.patch @@ -0,0 +1,29 @@ +From: Josh Boyer <jwboyer@fedoraproject.org> +Date: Tue, 27 Aug 2013 13:28:43 -0400 +Subject: [PATCH] efi: Make EFI_SECURE_BOOT_SIG_ENFORCE depend on EFI + +The functionality of the config option is dependent upon the platform being +UEFI based. Reflect this in the config deps. + +Signed-off-by: Josh Boyer <jwboyer@fedoraproject.org> +--- + arch/x86/Kconfig | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig +index 61542c282e70..e5ee669e87b6 100644 +--- a/arch/x86/Kconfig ++++ b/arch/x86/Kconfig +@@ -1567,7 +1567,8 @@ config EFI_MIXED + If unsure, say N. + + config EFI_SECURE_BOOT_SIG_ENFORCE +- def_bool n ++ def_bool n ++ depends on EFI + prompt "Force module signing when UEFI Secure Boot is enabled" + ---help--- + UEFI Secure Boot provides a mechanism for ensuring that the +-- +1.9.3 + diff --git a/hibernate-Disable-in-a-signed-modules-environment.patch b/hibernate-Disable-in-a-signed-modules-environment.patch new file mode 100644 index 00000000..53dd6dea --- /dev/null +++ b/hibernate-Disable-in-a-signed-modules-environment.patch @@ -0,0 +1,38 @@ +From: Josh Boyer <jwboyer@fedoraproject.org> +Date: Fri, 20 Jun 2014 08:53:24 -0400 +Subject: [PATCH] hibernate: Disable in a signed modules environment + +There is currently no way to verify the resume image when returning +from hibernate. This might compromise the signed modules trust model, +so until we can work with signed hibernate images we disable it in +a secure modules environment. + +Signed-off-by: Josh Boyer <jwboyer@fedoraproject.org> +--- + kernel/power/hibernate.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/kernel/power/hibernate.c b/kernel/power/hibernate.c +index a9dfa79b6bab..14c7356ff53a 100644 +--- a/kernel/power/hibernate.c ++++ b/kernel/power/hibernate.c +@@ -28,6 +28,7 @@ + #include <linux/syscore_ops.h> + #include <linux/ctype.h> + #include <linux/genhd.h> ++#include <linux/module.h> + #include <trace/events/power.h> + + #include "power.h" +@@ -65,7 +66,7 @@ static const struct platform_hibernation_ops *hibernation_ops; + + bool hibernation_available(void) + { +- return (nohibernate == 0); ++ return ((nohibernate == 0) && !secure_modules()); + } + + /** +-- +1.9.3 + diff --git a/i8042-Also-store-the-aux-firmware-id-in-multi-plexed.patch b/i8042-Also-store-the-aux-firmware-id-in-multi-plexed.patch deleted file mode 100644 index f2a5454b..00000000 --- a/i8042-Also-store-the-aux-firmware-id-in-multi-plexed.patch +++ /dev/null @@ -1,32 +0,0 @@ -From ef15224bce9875f9a5fbc93a2823219df6936a18 Mon Sep 17 00:00:00 2001 -From: Hans de Goede <hdegoede@redhat.com> -Date: Wed, 30 Jul 2014 17:56:05 +0200 -Subject: [PATCH 1/3] i8042: Also store the aux firmware id in multi-plexed aux - ports - -So that firmware-id matching can be used with multiplexed aux ports too. - -Bugzilla: 1110011 -Upstream-status: sent for 3.17/3.18 - -Signed-off-by: Hans de Goede <hdegoede@redhat.com> ---- - drivers/input/serio/i8042.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/input/serio/i8042.c b/drivers/input/serio/i8042.c -index f1aeb0240d6e..4b5015f27f9e 100644 ---- a/drivers/input/serio/i8042.c -+++ b/drivers/input/serio/i8042.c -@@ -1253,6 +1253,8 @@ static int __init i8042_create_aux_port(int idx) - } else { - snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx); - snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1); -+ strlcpy(serio->firmware_id, i8042_aux_firmware_id, -+ sizeof(serio->firmware_id)); - } - - port->serio = serio; --- -1.9.3 - diff --git a/input-kill-stupid-messages.patch b/input-kill-stupid-messages.patch index 754bf8a3..65a3cd68 100644 --- a/input-kill-stupid-messages.patch +++ b/input-kill-stupid-messages.patch @@ -1,11 +1,18 @@ +From: "kernel-team@fedoraproject.org" <kernel-team@fedoraproject.org> +Date: Thu, 29 Jul 2010 16:46:31 -0700 +Subject: [PATCH] input: kill stupid messages + Bugzilla: N/A Upstream-status: Fedora mustard +--- + drivers/input/keyboard/atkbd.c | 4 ++++ + 1 file changed, 4 insertions(+) diff --git a/drivers/input/keyboard/atkbd.c b/drivers/input/keyboard/atkbd.c -index add5ffd..5eb2f03 100644 +index 6f5d79569136..95469f6ecfa5 100644 --- a/drivers/input/keyboard/atkbd.c +++ b/drivers/input/keyboard/atkbd.c -@@ -430,11 +430,15 @@ static irqreturn_t atkbd_interrupt(struct serio *serio, unsigned char data, +@@ -436,11 +436,15 @@ static irqreturn_t atkbd_interrupt(struct serio *serio, unsigned char data, goto out; case ATKBD_RET_ACK: case ATKBD_RET_NAK: @@ -21,3 +28,6 @@ index add5ffd..5eb2f03 100644 goto out; case ATKBD_RET_ERR: atkbd->err_count++; +-- +1.9.3 + diff --git a/input-silence-i8042-noise.patch b/input-silence-i8042-noise.patch new file mode 100644 index 00000000..0872bc3d --- /dev/null +++ b/input-silence-i8042-noise.patch @@ -0,0 +1,65 @@ +From: Peter Jones <pjones@redhat.com> +Date: Thu, 25 Sep 2008 16:23:33 -0400 +Subject: [PATCH] input: silence i8042 noise + +Don't print an error message just because there's no i8042 chip. +Some systems, such as EFI-based Apple systems, won't necessarily have an +i8042 to initialize. We shouldn't be printing an error message in this +case, since not detecting the chip is the correct behavior. + +Bugzilla: N/A +Upstream-status: Fedora mustard +--- + drivers/base/power/main.c | 2 -- + drivers/input/serio/i8042.c | 1 - + net/can/af_can.c | 8 ++------ + 3 files changed, 2 insertions(+), 9 deletions(-) + +diff --git a/drivers/base/power/main.c b/drivers/base/power/main.c +index b67d9aef9fe4..dd58b0fdaafd 100644 +--- a/drivers/base/power/main.c ++++ b/drivers/base/power/main.c +@@ -122,8 +122,6 @@ void device_pm_unlock(void) + */ + void device_pm_add(struct device *dev) + { +- pr_debug("PM: Adding info for %s:%s\n", +- dev->bus ? dev->bus->name : "No Bus", dev_name(dev)); + mutex_lock(&dpm_list_mtx); + if (dev->parent && dev->parent->power.is_prepared) + dev_warn(dev, "parent %s should not be sleeping\n", +diff --git a/drivers/input/serio/i8042.c b/drivers/input/serio/i8042.c +index f5a98af3b325..9bb95eab6926 100644 +--- a/drivers/input/serio/i8042.c ++++ b/drivers/input/serio/i8042.c +@@ -857,7 +857,6 @@ static int __init i8042_check_aux(void) + static int i8042_controller_check(void) + { + if (i8042_flush()) { +- pr_err("No controller found\n"); + return -ENODEV; + } + +diff --git a/net/can/af_can.c b/net/can/af_can.c +index ce82337521f6..a3fee4becc93 100644 +--- a/net/can/af_can.c ++++ b/net/can/af_can.c +@@ -158,13 +158,9 @@ static int can_create(struct net *net, struct socket *sock, int protocol, + err = request_module("can-proto-%d", protocol); + + /* +- * In case of error we only print a message but don't +- * return the error code immediately. Below we will +- * return -EPROTONOSUPPORT ++ * In case of error we but don't return the error code immediately. ++ * Below we will return -EPROTONOSUPPORT + */ +- if (err) +- printk_ratelimited(KERN_ERR "can: request_module " +- "(can-proto-%d) failed.\n", protocol); + + cp = can_get_proto(protocol); + } +-- +1.9.3 + diff --git a/makefile-after_link.patch b/kbuild-AFTER_LINK.patch index ac7c5e15..603e0e05 100644 --- a/makefile-after_link.patch +++ b/kbuild-AFTER_LINK.patch @@ -1,7 +1,3 @@ -Bugzilla: N/A -Upstream-status: ?? - -From fd4e7f06ecc891474dea3a93df083de5f8c50cdc Mon Sep 17 00:00:00 2001 From: Roland McGrath <roland@redhat.com> Date: Mon, 6 Oct 2008 23:03:03 -0700 Subject: [PATCH] kbuild: AFTER_LINK @@ -9,6 +5,9 @@ Subject: [PATCH] kbuild: AFTER_LINK If the make variable AFTER_LINK is set, it is a command line to run after each final link. This includes vmlinux itself and vDSO images. +Bugzilla: N/A +Upstream-status: ?? + Signed-off-by: Roland McGrath <roland@redhat.com> --- arch/arm64/kernel/vdso/Makefile | 3 ++- @@ -21,17 +20,17 @@ Signed-off-by: Roland McGrath <roland@redhat.com> 7 files changed, 17 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kernel/vdso/Makefile b/arch/arm64/kernel/vdso/Makefile -index 6d20b7d162d8..863a01bde0bf 100644 +index ff3bddea482d..d8a439dd6351 100644 --- a/arch/arm64/kernel/vdso/Makefile +++ b/arch/arm64/kernel/vdso/Makefile -@@ -48,7 +48,8 @@ $(obj-vdso): %.o: %.S +@@ -48,7 +48,8 @@ $(obj-vdso): %.o: %.S FORCE # Actual build commands - quiet_cmd_vdsold = VDSOL $@ + quiet_cmd_vdsold = VDSOL $@ - cmd_vdsold = $(CC) $(c_flags) -Wl,-n -Wl,-T $^ -o $@ + cmd_vdsold = $(CC) $(c_flags) -Wl,-n -Wl,-T $^ -o $@ \ -+ $(if $(AFTER_LINK),;$(AFTER_LINK)) - quiet_cmd_vdsoas = VDSOA $@ ++ $(if $(AFTER_LINK),;$(AFTER_LINK)) + quiet_cmd_vdsoas = VDSOA $@ cmd_vdsoas = $(CC) $(a_flags) -c -o $@ $< diff --git a/arch/powerpc/kernel/vdso32/Makefile b/arch/powerpc/kernel/vdso32/Makefile @@ -91,10 +90,10 @@ index 2a8ddfd12a5b..452ca53561fe 100644 cmd_vdso64as = $(CC) $(a_flags) -c -o $@ $< diff --git a/arch/x86/vdso/Makefile b/arch/x86/vdso/Makefile -index 9206ac7961a5..3d7f533f6757 100644 +index 5a4affe025e8..8ff38ce94c8e 100644 --- a/arch/x86/vdso/Makefile +++ b/arch/x86/vdso/Makefile -@@ -181,8 +181,9 @@ $(obj)/vdso32-syms.lds: $(vdso32.so-y:%=$(obj)/vdso32-%-syms.lds) FORCE +@@ -171,8 +171,9 @@ $(vdso32-images:%=$(obj)/%.dbg): $(obj)/vdso32-%.so.dbg: FORCE \ quiet_cmd_vdso = VDSO $@ cmd_vdso = $(CC) -nostdlib -o $@ \ $(VDSO_LDFLAGS) $(VDSO_LDFLAGS_$(filter %.lds,$(^F))) \ @@ -105,9 +104,9 @@ index 9206ac7961a5..3d7f533f6757 100644 + sh $(srctree)/$(src)/checkundef.sh '$(NM)' '$@' VDSO_LDFLAGS = -fPIC -shared $(call cc-ldoption, -Wl$(comma)--hash-style=sysv) \ - $(LTO_CFLAGS) + $(call cc-ldoption, -Wl$(comma)--build-id) -Wl,-Bsymbolic $(LTO_CFLAGS) diff --git a/scripts/link-vmlinux.sh b/scripts/link-vmlinux.sh -index 2dcb37736d84..25e170e92ef1 100644 +index 86a4fe75f453..161637ed5611 100644 --- a/scripts/link-vmlinux.sh +++ b/scripts/link-vmlinux.sh @@ -65,6 +65,10 @@ vmlinux_link() @@ -122,5 +121,5 @@ index 2dcb37736d84..25e170e92ef1 100644 -- -1.8.5.3 +1.9.3 diff --git a/kernel-arm64.patch b/kernel-arm64.patch index 25f0479c..a05aa338 100644 --- a/kernel-arm64.patch +++ b/kernel-arm64.patch @@ -1,767 +1,1145 @@ -commit db044807ca763c21bae298388239be6177c6ccec -Merge: 649c9e3 26bcd8b -Author: Kyle McMartin <kmcmarti@redhat.com> -Date: Wed Jul 30 14:31:24 2014 -0400 +commit 87257d3e584fad0b47e6304da54a1932f42b11bb +Author: Mark Salter <msalter@redhat.com> +Date: Tue Sep 30 17:19:24 2014 -0400 - Merge branch 'master' into devel + arm64: avoid need for console= to enable serial console - Conflicts: - virt/kvm/arm/vgic.c + Tell kernel to prefer one of the serial ports on platforms + pl011, 8250, or sbsa uarts. console= on command line will + override these assumed preferences. + + Signed-off-by: Mark Salter <msalter@redhat.com> -commit 649c9e3a45e81852daf80c126a332297b75cb109 -Author: Ard Biesheuvel <ard.biesheuvel@linaro.org> -Date: Tue Jul 29 12:49:10 2014 +0200 +commit 56db24589d311ea3590527030ede007ec339e2d7 +Author: Tom Lendacky <thomas.lendacky@amd.com> +Date: Tue Sep 9 23:33:17 2014 -0400 - arm64/efi: efistub: don't abort if base of DRAM is occupied + drivers: net: AMD Seattle XGBE PHY support for A0 silicon - If we cannot relocate the kernel Image to its preferred offset of base of DRAM - plus TEXT_OFFSET, instead relocate it to the lowest available 2 MB boundary plus - TEXT_OFFSET. We may lose a bit of memory at the low end, but we can still - proceed normally otherwise. + This patch modifies the upstream AMD XGBE PHY driver to support + A0 Seattle silicon in currently shipping systems. The upstream + Linux driver is targetted for Seattle B0 silicon. - Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> + Signed-off-by: Mark Salter <msalter@redhat.com> -commit 5102fd06b12467a0518537061805483a759bc856 -Author: Ard Biesheuvel <ard.biesheuvel@linaro.org> -Date: Tue Jul 29 12:49:09 2014 +0200 +commit 75554bb2e3c433a47e172d81a0b59df58810dc01 +Author: Tom Lendacky <thomas.lendacky@amd.com> +Date: Tue Sep 9 23:34:07 2014 -0400 - arm64/efi: efistub: cover entire static mem footprint in PE/COFF .text + drivers: net: AMD Seattle XGBE 10GbE support for A0 silicon - The static memory footprint of a kernel Image at boot is larger than the - Image file itself. Things like .bss data and initial page tables are allocated - statically but populated dynamically so their content is not contained in the - Image file. + This patch modifies the upstream AMD 10GbE XGBE Ethernet driver to + support A0 Seattle silicon in currently shipping systems. The + upstream Linux driver is targetted for Seattle B0 silicon. - However, if EFI (or GRUB) has loaded the Image at precisely the desired offset - of base of DRAM + TEXT_OFFSET, the Image will be booted in place, and we have - to make sure that the allocation done by the PE/COFF loader is large enough. + Signed-off-by: Mark Salter <msalter@redhat.com> + +commit 41cb1b3c9e62256b8a4e92c50cd51b2a68d0c9c6 +Author: Graeme Gregory <graeme.gregory@linaro.org> +Date: Fri Jul 26 17:55:02 2013 +0100 + + virtio-mmio: add ACPI probing - Fix this by growing the PE/COFF .text section to cover the entire static - memory footprint. The part of the section that is not covered by the payload - will be zero initialised by the PE/COFF loader. + Added the match table and pointers for ACPI probing to the driver. - Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> + Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org> -commit 3b4dfb00a401b7fecf01d3c89b154907167dff52 -Author: Mark Rutland <mark.rutland@arm.com> -Date: Tue Jul 29 12:49:08 2014 +0200 +commit c06502fb4f00c6996c1f55cd342288508808c678 +Author: Graeme Gregory <graeme.gregory@linaro.org> +Date: Wed Jul 24 11:29:48 2013 +0100 - arm64: spin-table: handle unmapped cpu-release-addrs + net: smc91x: add ACPI probing support. - In certain cases the cpu-release-addr of a CPU may not fall in the - linear mapping (e.g. when the kernel is loaded above this address due to - the presence of other images in memory). This is problematic for the - spin-table code as it assumes that it can trivially convert a - cpu-release-addr to a valid VA in the linear map. + Add device ID LINA0003 for this device and add the match table. - This patch modifies the spin-table code to use a temporary cached - mapping to write to a given cpu-release-addr, enabling us to support - addresses regardless of whether they are covered by the linear mapping. + As its a platform device it needs no other code and will be probed in by + acpi_platform once device ID is added. - Signed-off-by: Mark Rutland <mark.rutland@arm.com> + Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org> -commit a49ad891b2e91338587dc5576c9da73b249a9d13 +commit aad559613ff05a13f940129675659297e7125979 Author: Mark Salter <msalter@redhat.com> -Date: Mon Jul 14 15:52:06 2014 -0400 +Date: Tue Sep 23 12:48:48 2014 -0400 - pci/xgene: use pci_remap_iospace() instead of pci_ioremap_io() + arm64/pci: add coherency inheritance for pci devices Signed-off-by: Mark Salter <msalter@redhat.com> -commit 1a958ec71db226d35ed51756b7164142bb0a60a3 -Author: Tanmay Inamdar <tinamdar@apm.com> -Date: Wed Mar 19 16:12:42 2014 -0700 +commit 8d2a4226d96ccae17fbc0ef7d7d9c5a07ad8b31f +Author: Mark Salter <msalter@redhat.com> +Date: Tue Sep 23 12:35:17 2014 -0400 - MAINTAINERS: entry for APM X-Gene PCIe host driver + arm64/acpi: make acpi disabled by default - Add entry for AppliedMicro X-Gene PCIe host driver. + Signed-off-by: Mark Salter <msalter@redhat.com> + +commit 0553f2b9fc94bfb0f9038003ad6f150cca196aad +Author: Wei Huang <wei@redhat.com> +Date: Thu Sep 18 20:32:03 2014 -0400 + + KVM: fix VTTBR_BADDR_MASK - Signed-off-by: Tanmay Inamdar <tinamdar@apm.com> + The following is patch from AMD to fix VTTBR_BADDR_MASK. According to + AMD, this patch is required to enable KVM on Seattle. + + The current VTTBR_BADDR_MASK only masks 39 bits, which is broken on current + systems. Rather than just add a bit it seems like a good time to also set + things at run-time instead of compile time to accomodate more hardware. + + This patch sets TCR_EL2.PS, VTCR_EL2.T0SZ and vttbr_baddr_mask in runtime, + not compile time. + + In ARMv8, EL2 physical address size (TCR_EL2.PS) and stage2 input address + size (VTCR_EL2.T0SZE) cannot be determined in compile time since they + depend on hardware capability. + + According to Table D4-23 and Table D4-25 in ARM DDI 0487A.b document, + vttbr_x is calculated using different fixed values with consideration + of T0SZ, granule size and the level of translation tables. Therefore, + vttbr_baddr_mask should be determined dynamically. + + Changes since v5: + Fixed declaration of vttbr_baddr_mask to not create multiple instances + Refactored return codes based on feedback + For 32 bit included kvm_arm.h in kvm_mmu.h to explictly pick up + VTTBR_BADDR_MASK + + Changes since v4: + More minor cleanups from review + Moved some functions into headers + Added runtime check in kvm_alloc_stage2_pgd + + Changes since v3: + Another rebase + Addressed minor comments from v2 + + Changes since v2: + Rebased on https://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git next branch + + Changes since v1: + Rebased fix on Jungseok Lee's patch https://lkml.org/lkml/2014/5/12/189 to + provide better long term fix. Updated that patch to log error instead of + silently fail on unaligned vttbr. + + Cc: Marc Zyngier <marc.zyngier@arm.com> + Cc: Christoffer Dall <christoffer.dall@linaro.org> + Cc: Sungjinn Chung <sungjinn.chung@samsung.com> + Signed-off-by: Jungseok Lee <jays.lee@samsung.com> + Signed-off-by: Joel Schopp <joel.schopp@amd.com> + + Signed-off-by: Wei Huang <wei@redhat.com> -commit 03dc92f35b8f8be898ca12e3dc7c15961f414907 -Author: Tanmay Inamdar <tinamdar@apm.com> -Date: Wed Mar 19 16:12:41 2014 -0700 +commit f53d1278fe445b7130f1ff76b2f453b453368284 +Author: Wei Huang <wei@redhat.com> +Date: Thu Sep 18 20:02:57 2014 -0400 - dt-bindings: pci: xgene pcie device tree bindings + KVM/ACPI: Enable ACPI support for KVM virt GIC - This patch adds the bindings for X-Gene PCIe driver. The driver resides - under 'drivers/pci/host/pci-xgene.c' file. + This patches enables ACPI support for KVM virtual GIC. KVM parses + ACPI table for virt GIC related information when DT table is not + present. This is done by retrieving the information defined in + generic_interrupt entry of MADT table. - Signed-off-by: Tanmay Inamdar <tinamdar@apm.com> + Note: Alexander Spyridakis from Virtual Open System posts a + _very_ similar patch to enable acpi-kvm. This patch borrows some + ideas from his patch. + + Signed-off-by: Wei Huang <wei@redhat.com> -commit 1f8d894f2066d9db2b251d512f6f6f772ae7147f -Author: Tanmay Inamdar <tinamdar@apm.com> -Date: Wed Mar 19 16:12:40 2014 -0700 +commit ba63e452ff5b09cc0314f94e163a51c3279b9ca7 +Author: Wei Huang <wei@redhat.com> +Date: Thu Sep 18 20:02:56 2014 -0400 - arm64: dts: APM X-Gene PCIe device tree nodes + KVM/ACPI: Enable ACPI support for virt arch timer - This patch adds the device tree nodes for APM X-Gene PCIe controller and - PCIe clock interface. Since X-Gene SOC supports maximum 5 ports, 5 dts - nodes are added. + This patches enables ACPI support for KVM virtual arch_timer. It + allows KVM to parse ACPI table for virt arch_timer PPI when DT table + is not present. This is done by retrieving the information from + arch_timer_ppi array in arm_arch_timer driver. - Signed-off-by: Tanmay Inamdar <tinamdar@apm.com> + Signed-off-by: Wei Huang <wei@redhat.com> -commit c0855fcf0cc9adcb1ba5e6b1318536c56244796d -Author: Tanmay Inamdar <tinamdar@apm.com> -Date: Wed Mar 19 16:12:39 2014 -0700 +commit dd3f6094c2142786f40a3bc4d69c60b430ecc675 +Author: Wei Huang <wei@redhat.com> +Date: Thu Sep 18 20:02:55 2014 -0400 - pci: APM X-Gene PCIe controller driver + KVM/ACPI: Add kernel parameter kvmacpi to enable KVM ACPI support - This patch adds the AppliedMicro X-Gene SOC PCIe controller driver. - X-Gene PCIe controller supports maximum up to 8 lanes and GEN3 speed. - X-Gene SOC supports maximum 5 PCIe ports. + This patch addes a new kernel parameter, kvmacpi, to turn on ACPI + support for KVM. Users can enable it using "kvmacpi=on" in command + line. When it is on, KVM will will parse ACPI tables to configure related + components. By default this option is off. - Signed-off-by: Tanmay Inamdar <tinamdar@apm.com> + Note that DT will be probed first, no matter kvmacpi is ON or OFF. + This is because many platforms, such qemu/kvm, still supports + DT only. We still want to support Acadia kernel on such platforms. + + Signed-off-by: Wei Huang <wei@redhat.com> -commit 1cc0c322237d3b58b08fe39e79e6c2e2f90a8c98 -Author: Liviu Dudau <Liviu.Dudau@arm.com> -Date: Tue Jul 1 19:44:00 2014 +0100 +commit cdfc19f1fbe88c1610db790ad55318d55ab00ee9 +Author: Mark Salter <msalter@redhat.com> +Date: Thu Sep 18 21:13:05 2014 -0400 - arm64: Add architectural support for PCI + arm64/pci: fix dma coherency inheritance for PCI devices - Use the generic host bridge functions to provide support for - PCI Express on arm64. + The default dma_ops for devices on arm64 systems are noncoherent in + nature and rely upon special operations and bounce buffers to + perform a device DMA operation to/from memory. Some drivers rely + upon coherent operations involving suitably capable hardware. In + this case, a "dma-coherent" property will exist on the corresponding + Device Tree node for the bridge device, or one of its ancestors. + This patch adds support for applying a DMA coherent dma_ops for + PCI devices in the case of such a property. - Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> + Signed-off-by: Mark Salter <msalter@redhat.com> -commit aba1eca911a87959eb4be515110f7a6b8692e9a4 -Author: Liviu Dudau <Liviu.Dudau@arm.com> -Date: Tue Jul 1 19:43:34 2014 +0100 +commit c8a62324eba5718fb43a94a168de7a81787aa94d +Author: Mark Salter <msalter@redhat.com> +Date: Thu Sep 18 15:05:23 2014 -0400 - pci: Remap I/O bus resources into CPU space with pci_remap_iospace() + arm64: add sev to parking protocol - Introduce a default implementation for remapping PCI bus I/O resources - onto the CPU address space. Architectures with special needs may - provide their own version, but most should be able to use this one. + Parking protocol wakes secondary cores with an interrupt. + This patch adds an additional sev() to send an event. This + is a temporary hack for APM Mustang board and not intended + for upstream. - Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> + Signed-off-by: Mark Salter <msalter@redhat.com> -commit e1eacc3da10ca19eff1f88fb342a13586092b613 -Author: Liviu Dudau <liviu@dudau.co.uk> -Date: Tue Jul 1 21:50:50 2014 +0100 +commit e5f4ba1223515c46f1875597e77d5c32a37829ee +Author: Mark Salter <msalter@redhat.com> +Date: Sun Sep 14 09:44:44 2014 -0400 - pci: Add support for creating a generic host_bridge from device tree + Revert "ahci_xgene: Skip the PHY and clock initialization if already configured by the firmware." - Several platforms use a rather generic version of parsing - the device tree to find the host bridge ranges. Move the common code - into the generic PCI code and use it to create a pci_host_bridge - structure that can be used by arch code. + This reverts commit 0bed13bebd6c99d097796d2ca6c4f10fb5b2eabc. - Based on early attempts by Andrew Murray to unify the code. - Used powerpc and microblaze PCI code as starting point. + Temporarily revert for backwards compatibility with rh-0.12-1 firmware + +commit aeff595a5d57264e5f01add5c43f584d88be6a92 +Author: Mark Salter <msalter@redhat.com> +Date: Mon Aug 11 13:46:43 2014 -0400 + + xgene: add support for ACPI-probed serial port + +commit 02429d239f5ae917d870a7611a9d838b7822df1a +Author: Mark Salter <msalter@redhat.com> +Date: Sat Aug 9 12:01:20 2014 -0400 + + sata/xgene: support acpi probing - Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> - Tested-by: Tanmay Inamdar <tinamdar@apm.com> + Signed-off-by: Mark Salter <msalter@redhat.com> -commit aee55d507eb451223b51b52e6617b06b8e518ea6 -Author: Liviu Dudau <Liviu.Dudau@arm.com> -Date: Tue Jul 1 19:43:32 2014 +0100 +commit 774385f250ebb7448ca3eeb344a064ac989c4988 +Author: Hanjun Guo <hanjun.guo@linaro.org> +Date: Thu Aug 28 14:26:16 2014 -0400 - pci: of: Parse and map the IRQ when adding the PCI device. + ARM64 / ACPI: Introduce some PCI functions when PCI is enabled - Enhance the default implementation of pcibios_add_device() to - parse and map the IRQ of the device if a DT binding is available. + Introduce some PCI functions to make ACPI can be compiled when + CONFIG_PCI is enabled, these functions should be revisited when + implemented on ARM64. - Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> + Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> + [fixed up for 3.17-rc] + Signed-off-by: Mark Salter <msalter@redhat.com> -commit 0cf0470962f0498b598ff44e0c671407df54b22e -Author: Liviu Dudau <Liviu.Dudau@arm.com> -Date: Tue Jul 1 19:43:31 2014 +0100 +commit 6f711c98b37f1b0a42c4a523d0380d47ed2f95b9 +Author: Al Stone <ahs3@redhat.com> +Date: Thu Aug 28 13:14:16 2014 -0400 - pci: Introduce a domain number for pci_host_bridge. + Fix arm64 compilation error in PNP code - Make it easier to discover the domain number of a bus by storing - the number in pci_host_bridge for the root bus. Several architectures - have their own way of storing this information, so it makes sense - to try to unify the code. While at this, add a new function that - creates a root bus in a given domain and make pci_create_root_bus() - a wrapper around this function. + Signed-off-by: Mark Salter <msalter@redhat.com> + +commit f874873b7cb10f827bb7f8e08fa282878f740e77 +Author: Bob Moore <robert.moore@intel.com> +Date: Tue Sep 2 08:27:40 2014 +0800 + + ACPICA: Update version to 20140828. - Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> - Tested-by: Tanmay Inamdar <tinamdar@apm.com> + Version 20140828. + + Signed-off-by: Bob Moore <robert.moore@intel.com> + Signed-off-by: Lv Zheng <lv.zheng@intel.com> -commit 1bc8fcf01469c202b4aea5f1d0a3a75c9302f3e2 -Author: Liviu Dudau <Liviu.Dudau@arm.com> -Date: Tue Jul 1 19:43:30 2014 +0100 +commit 26f9b7b90576cf808a50edf1ec86ceece9349c9f +Author: Bob Moore <robert.moore@intel.com> +Date: Tue Sep 2 08:27:27 2014 +0800 - pci: Create pci_host_bridge before its associated bus in pci_create_root_bus. + ACPICA: Disassembler: Fix for gpio_int interrupt polarity flags. - Before commit 7b5436635800 the pci_host_bridge was created before the root bus. - As that commit has added a needless dependency on the bus for pci_alloc_host_bridge() - the creation order has been changed for no good reason. Revert the order of - creation as we are going to depend on the pci_host_bridge structure to retrieve the - domain number of the root bus. + The field is actually 2 bits, not 1. - Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> - Acked-by: Grant Likely <grant.likely@linaro.org> - Tested-by: Tanmay Inamdar <tinamdar@apm.com> + Signed-off-by: Bob Moore <robert.moore@intel.com> + Signed-off-by: Lv Zheng <lv.zheng@intel.com> -commit 55353327169dc08c1047d994e00b8a38630f5a8d -Author: Liviu Dudau <Liviu.Dudau@arm.com> -Date: Tue Jul 1 19:43:29 2014 +0100 +commit 6e1eddc48f6f9b948be4126dd38841f6f70da080 +Author: Hanjun Guo <hanjun.guo@linaro.org> +Date: Tue Sep 2 08:27:19 2014 +0800 - pci: OF: Fix the conversion of IO ranges into IO resources. + ACPICA: Headers: Add GTDT flag definitions for the timer subtable. - The ranges property for a host bridge controller in DT describes - the mapping between the PCI bus address and the CPU physical address. - The resources framework however expects that the IO resources start - at a pseudo "port" address 0 (zero) and have a maximum size of IO_SPACE_LIMIT. - The conversion from pci ranges to resources failed to take that into account. + Mostly by Hanjun Guo <hanjun.guo@linaro.org> - In the process move the function into drivers/of/address.c as it now - depends on pci_address_to_pio() code and make it return an error message. + Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> + Signed-off-by: Bob Moore <robert.moore@intel.com> + Signed-off-by: Lv Zheng <lv.zheng@intel.com> + +commit 1091460efb5542ba87f40ef20daff44215587f26 +Author: Hanjun Guo <hanjun.guo@linaro.org> +Date: Tue Sep 2 08:27:12 2014 +0800 + + ACPICA: ACPI 5.1/Disassembler: Add GICC affinity subtable to SRAT table. - Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> - Tested-by: Tanmay Inamdar <tinamdar@apm.com> + Update template for SRAT. + Add clock_domain to standard CPU affinity subtable. + + Mostly by Hanjun Guo <hanjun.guo@linaro.org> + + Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> + Signed-off-by: Bob Moore <robert.moore@intel.com> + Signed-off-by: Lv Zheng <lv.zheng@intel.com> -commit 34079a20796d5c74e2984c37a99baef4871709a6 -Author: Liviu Dudau <Liviu.Dudau@arm.com> -Date: Tue Jul 1 19:43:28 2014 +0100 +commit 02ba5e067dbb83b0f481db821d05851e9623c401 +Author: Bob Moore <robert.moore@intel.com> +Date: Tue Sep 2 08:27:05 2014 +0800 - pci: Introduce pci_register_io_range() helper function. + ACPICA: Add _PSx names to the METHOD_NAME list. - Some architectures do not have a simple view of the PCI I/O space - and instead use a range of CPU addresses that map to bus addresses. For - some architectures these ranges will be expressed by OF bindings - in a device tree file. + Will be used by iASL. - Introduce a pci_register_io_range() helper function with a generic - implementation that can be used by such architectures to keep track - of the I/O ranges described by the PCI bindings. If the PCI_IOBASE - macro is not defined that signals lack of support for PCI and we - return an error. + Signed-off-by: Bob Moore <robert.moore@intel.com> + Signed-off-by: Lv Zheng <lv.zheng@intel.com> + +commit f2ecef6608a1f74b236df4f93da9b7b5aba4d3fd +Author: Mark Salter <msalter@redhat.com> +Date: Tue Sep 9 22:59:48 2014 -0400 + + arm64: add parking protocol support - Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> + This is a first-cut effort at parking protocol support. It is + very much a work in progress (as is the spec it is based on). + This code deviates from the current spec in a number of ways + to work around current firmware issues and issues with kernels + using 64K page sizes. + + caveat utilitor + + Signed-off-by: Mark Salter <msalter@redhat.com> -commit a81abc095ab4b9b90e446ddbd59247e23df9d4ad -Author: Liviu Dudau <Liviu.Dudau@arm.com> -Date: Tue Jul 1 19:43:27 2014 +0100 +commit 63e220c94f072f10bfae2e1ed375af9dbc017571 +Author: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> +Date: Tue Sep 9 15:37:15 2014 -0500 - pci: Export find_pci_host_bridge() function. + ata: ahci_platform: Add ACPI support for AMD Seattle SATA controller + + This patch adds ACPI support for non-PCI SATA contoller in ahci_platform driver. + It adds ACPI matching table in ahci_platform to support AMD Seattle SATA controller + with following ASL structure in DSDT: + + Device (SATA0) + { + Name(_HID, "AMDI0600") // Seattle AHSATA + Name (_CCA, 1) // Cache-coherent controller + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xE0300000, 0x00010000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,,,) { 387 } + }) + } + + Since ATA driver should not require PCI support for ATA_ACPI, + this patch also removes dependency in the driver/ata/Kconfig. + + Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> + +commit d9d7224bd65fb3c1490f06d635b7aceb035acb1e +Author: Graeme Gregory <graeme.gregory@linaro.org> +Date: Wed Aug 13 13:47:18 2014 +0100 + + tty: SBSA compatible UART - This is a useful function and we should make it visible outside the - generic PCI code. Export it as a GPL symbol. + This is a subset of pl011 UART which does not supprt DMA or baud rate + changing. It does, however, provide earlycon support (i.e., using + "earlycon=ttySBSA" on the kernel command line). - Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> - Tested-by: Tanmay Inamdar <tinamdar@apm.com> + It is specified in the Server Base System Architecture document from + ARM. + + Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org> -commit 78361698444e81bedbf30ec2b7aae1afd110d11f -Author: Liviu Dudau <Liviu.Dudau@arm.com> -Date: Tue Jul 1 19:43:26 2014 +0100 +commit 4c67296fce53fed671a78b698d4552636f499b7f +Author: Mark Salter <msalter@redhat.com> +Date: Thu Aug 14 13:17:37 2014 -0400 - Fix ioport_map() for !CONFIG_GENERIC_IOMAP cases. + arm64: set dma coherency ops for ACPI probed devices - The inline version of ioport_map() that gets used when !CONFIG_GENERIC_IOMAP - is wrong. It returns a mapped (i.e. virtual) address that can start from - zero and completely ignores the PCI_IOBASE and IO_SPACE_LIMIT that most - architectures that use !CONFIG_GENERIC_MAP define. + Search for a _CCA object and set the correct dma ops based + on device coherency attribute and architecture default. - Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> - Acked-by: Arnd Bergmann <arnd@arndb.de> - Tested-by: Tanmay Inamdar <tinamdar@apm.com> + Signed-off-by: Mark Salter <msalter@redhat.com> -commit 5540bbe2eca72e37be2e6a1c18e2fc7e73f0eab6 -Author: Marc Zyngier <marc.zyngier@arm.com> -Date: Mon Jun 30 16:01:50 2014 +0100 +commit 959c571815c440150b2f290bf3d13b2fbadbee70 +Author: Mark Salter <msalter@redhat.com> +Date: Thu Aug 14 12:32:13 2014 -0400 - arm64: KVM: vgic: enable GICv2 emulation on top on GICv3 hardware + acpi: add utility to test for device dma coherency + + ACPI 5.1 adds a _CCA object to indicate memory coherency + of a bus master device. It is an integer with zero meaning + non-coherent and one meaning coherent. This attribute may + be inherited from a parent device. It may also be missing + entirely, in which case, an architecture-specific default + is assumed. - Add the last missing bits that enable GICv2 emulation on top of - GICv3 hardware. + This patch adds a utility function to parse a device handle + (and its parents) for a _CCA object and return the coherency + attribute if found. - Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> + Signed-off-by: Mark Salter <msalter@redhat.com> -commit f057aaf81a7df641bcaa992965a257e3260ad36e -Author: Marc Zyngier <marc.zyngier@arm.com> -Date: Mon Jun 30 16:01:49 2014 +0100 +commit 0dbac48379d3aace2fd7468d83044116f176b4c9 +Author: Mark Salter <msalter@redhat.com> +Date: Mon Sep 8 11:58:46 2014 -0400 - arm64: KVM: vgic: add GICv3 world switch + acpi: fix acpi_os_ioremap for arm64 - Introduce the GICv3 world switch code used to save/restore the - GICv3 context. + The acpi_os_ioremap() function may be used to map normal RAM or IO + regions. The current implementation simply uses ioremap_cache(). This + will work for some architectures, but arm64 ioremap_cache() cannot be + used to map IO regions which don't support caching. So for arm64, use + ioremap() for non-RAM regions. - Acked-by: Catalin Marinas <catalin.marinas@arm.com> - Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> - Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> + Signed-off-by: Mark Salter <msalter@redhat.com> -commit 7f1b8a791bb375933fdc8420cd08f127d07dd259 -Author: Marc Zyngier <marc.zyngier@arm.com> -Date: Mon Jun 30 16:01:48 2014 +0100 +commit c9eab819c2107e0c95cf57233de4de5404851ab6 +Author: Graeme Gregory <graeme.gregory@linaro.org> +Date: Mon Sep 8 10:36:44 2014 -0400 - KVM: ARM: vgic: add the GICv3 backend + acpi: add arm to the platforms that use ioremap - Introduce the support code for emulating a GICv2 on top of GICv3 - hardware. + Now with the base changes to the arm memory mapping it is safe + to convert to using ioremap to map in the tables. - Acked-by: Catalin Marinas <catalin.marinas@arm.com> - Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> + Signed-off-by: Al Stone <al.stone@linaro.org> + Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org> -commit 74428905c3b450eab53a21bee74236501629a443 -Author: Marc Zyngier <marc.zyngier@arm.com> -Date: Mon Jun 30 16:01:47 2014 +0100 +commit 7e772a485f980b826a58ecd9c39fbe82085c55fa +Author: Mark Salter <msalter@redhat.com> +Date: Mon Sep 8 17:04:28 2014 -0400 - arm64: KVM: move HCR_EL2.{IMO, FMO} manipulation into the vgic switch code + acpi/arm64: NOT FOR UPSTREAM - remove EXPERT dependency - GICv3 requires the IMO and FMO bits to be tightly coupled with some - of the interrupt controller's register switch. + For convenience to keep existing configs working, remove + CONFIG_EXPERT dependency from ACPI for ARM64. This shouldn't + go upstream just yet. - In order to have similar code paths, move the manipulation of these - bits to the GICv2 switch code. + Signed-off-by: Mark Salter <msalter@redhat.com> + +commit b42e8f7901e58b86a1cb3ffdf14cb2455fd91ede +Author: Graeme Gregory <graeme.gregory@linaro.org> +Date: Fri Sep 12 22:00:16 2014 +0800 + + Documentation: ACPI for ARM64 - Acked-by: Catalin Marinas <catalin.marinas@arm.com> - Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> - Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> + Add documentation for the guidelines of how to use ACPI + on ARM64. + + Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org> + Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> -commit b691c1f97f1fb5b29c3ae4cc836fdbefe61a11ff -Author: Marc Zyngier <marc.zyngier@arm.com> -Date: Mon Jun 30 16:01:46 2014 +0100 +commit 57dc75b87d5663181e1c19802297e72e51a324ba +Author: Graeme Gregory <graeme.gregory@linaro.org> +Date: Fri Sep 12 22:00:15 2014 +0800 - arm64: KVM: split GICv2 world switch from hyp code + ARM64 / ACPI: Enable ARM64 in Kconfig - Move the GICv2 world switch code into its own file, and add the - necessary indirection to the arm64 switch code. + Add Kconfigs to build ACPI on ARM64, and make ACPI available on ARM64. - Also introduce a new type field to the vgic_params structure. + acpi_idle driver is x86/IA64 dependent now, so make CONFIG_ACPI_PROCESSOR + depend on X86 || IA64, and implement it on ARM64 in the future. - Acked-by: Catalin Marinas <catalin.marinas@arm.com> - Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> - Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> + Reviewed-by: Grant Likely <grant.likely@linaro.org> + Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org> + Signed-off-by: Al Stone <al.stone@linaro.org> + Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> -commit d3f4563f1bebed7f60f714bdab640e477a081c4b -Author: Marc Zyngier <marc.zyngier@arm.com> -Date: Mon Jun 30 16:01:45 2014 +0100 +commit 106c5cb3caff13c91cb6056f88a1c0e710b8e0eb +Author: Al Stone <al.stone@linaro.org> +Date: Fri Sep 12 22:00:14 2014 +0800 - arm64: KVM: remove __kvm_hyp_code_{start, end} from hyp.S + ARM64 / ACPI: Select ACPI_REDUCED_HARDWARE_ONLY if ACPI is enabled on ARM64 - We already have __hyp_text_{start,end} to express the boundaries - of the HYP text section, and __kvm_hyp_code_{start,end} are getting - in the way of a more modular world switch code. + ACPI reduced hardware mode is disabled by default, but ARM64 + can only run properly in ACPI hardware reduced mode, so select + ACPI_REDUCED_HARDWARE_ONLY if ACPI is enabled on ARM64. - Just turn __kvm_hyp_code_{start,end} into #defines mapping the - linker-emited symbols. + Reviewed-by: Grant Likely <grant.likely@linaro.org> + Signed-off-by: Al Stone <al.stone@linaro.org> + Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> + +commit 73f4aca21985ace8989b6fc8af503940c469f1d7 +Author: Hanjun Guo <hanjun.guo@linaro.org> +Date: Fri Sep 12 22:00:13 2014 +0800 + + ARM64 / ACPI: Parse GTDT to initialize arch timer - Acked-by: Catalin Marinas <catalin.marinas@arm.com> - Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> - Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> + Using the information presented by GTDT to initialize the arch + timer (not memory-mapped). + + Originally-by: Amit Daniel Kachhap <amit.daniel@samsung.com> + Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> -commit 8ede261e09ad25ab8229d5efb476d5b4f6dc6434 -Author: Marc Zyngier <marc.zyngier@arm.com> -Date: Mon Jun 30 16:01:44 2014 +0100 +commit 5efba15fb24c25139dd621a417f2b9cbe2e675f5 +Author: Tomasz Nowicki <tomasz.nowicki@linaro.org> +Date: Fri Sep 12 22:00:12 2014 +0800 - KVM: ARM: vgic: revisit implementation of irqchip_in_kernel + ARM64 / ACPI: Add GICv2 specific ACPI boot support - So far, irqchip_in_kernel() was implemented by testing the value of - vctrl_base, which worked fine with GICv2. + ACPI kernel uses MADT table for proper GIC initialization. It needs to + parse GIC related subtables, collect CPU interface and distributor + addresses and call driver initialization function (which is hardware + abstraction agnostic). In a similar way, FDT initialize GICv1/2. - With GICv3, this field is useless, as we're using system registers - instead of a emmory mapped interface. To solve this, add a boolean - flag indicating if the we're using a vgic or not. + NOTE: This commit allow to initialize GICv1/2 basic functionality. + GICv2 vitalization extension, GICv3/4 and ITS are considered as next + steps. - Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> - Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> + Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org> + Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> -commit ff7faf70feb47e5f1cf1e0f0d02e0f2807da11f5 -Author: Marc Zyngier <marc.zyngier@arm.com> -Date: Mon Jun 30 16:01:43 2014 +0100 +commit e060d9d74cecff59ea96d6124ffb1c9c044a4f9d +Author: Hanjun Guo <hanjun.guo@linaro.org> +Date: Fri Sep 12 22:00:11 2014 +0800 - KVM: ARM: vgic: split GICv2 backend from the main vgic code + ARM64 / ACPI: Introduce ACPI_IRQ_MODEL_GIC and register device's gsi - Brutally hack the innocent vgic code, and move the GICv2 specific code - to its own file, using vgic_ops and vgic_params as a way to pass - information between the two blocks. + Introduce ACPI_IRQ_MODEL_GIC which is needed for ARM64 as GIC is + used, and then register device's gsi with the core IRQ subsystem. - Acked-by: Catalin Marinas <catalin.marinas@arm.com> - Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> - Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> + acpi_register_gsi() is similar to DT based irq_of_parse_and_map(), + since gsi is unique in the system, so use hwirq number directly + for the mapping. + + Originally-by: Amit Daniel Kachhap <amit.daniel@samsung.com> + Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> -commit 63480283c0e1dc92f506e5e5306be0ac9b239499 -Author: Marc Zyngier <marc.zyngier@arm.com> -Date: Mon Jun 30 16:01:42 2014 +0100 +commit c25e8f66c630713107967076933b5f349655ea6a +Author: Hanjun Guo <hanjun.guo@linaro.org> +Date: Fri Sep 12 22:00:10 2014 +0800 - KVM: ARM: introduce vgic_params structure + ACPI / processor: Make it possible to get CPU hardware ID via GICC - Move all the data specific to a given GIC implementation into its own - little structure. + Introduce a new function map_gicc_mpidr() to allow MPIDRs to be obtained + from the GICC Structure introduced by ACPI 5.1. - Acked-by: Catalin Marinas <catalin.marinas@arm.com> - Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> - Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> + MPIDR is the CPU hardware ID as local APIC ID on x86 platform, so we use + MPIDR not the GIC CPU interface ID to identify CPUs. + + Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> -commit dcb20f9b66d5615a3e7e492424fa7953c1fe9f01 -Author: Marc Zyngier <marc.zyngier@arm.com> -Date: Mon Jun 30 16:01:41 2014 +0100 +commit 5ce1c3ff91aa9d8012324518789363bb4ded33d4 +Author: Hanjun Guo <hanjun.guo@linaro.org> +Date: Fri Sep 12 22:00:09 2014 +0800 - KVM: ARM: vgic: introduce vgic_enable + ARM64 / ACPI: Parse MADT for SMP initialization - Move the code dealing with enabling the VGIC on to vgic_ops. + MADT contains the information for MPIDR which is essential for + SMP initialization, parse the GIC cpu interface structures to + get the MPIDR value and map it to cpu_logical_map(), and add + enabled cpu with valid MPIDR into cpu_possible_map. - Acked-by: Catalin Marinas <catalin.marinas@arm.com> - Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> - Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> + ACPI 5.1 only has two explicit methods to boot up SMP, PSCI and + Parking protocol, but the Parking protocol is only specified for + ARMv7 now, so make PSCI as the only way for the SMP boot protocol + before some updates for the ACPI spec or the Parking protocol spec. + + Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> + Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org> + +commit 8634cf0fcc8294c355d7cecb55da017ba9ff3ff7 +Author: Hanjun Guo <hanjun.guo@linaro.org> +Date: Fri Sep 12 22:00:08 2014 +0800 + + ACPI / table: Print GIC information when MADT is parsed + + When MADT is parsed, print GIC information to make the boot + log look pretty. + + Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> + Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org> + +commit 05facef9c824235c82d8d9c2ae03fe7a729ceef8 +Author: Hanjun Guo <hanjun.guo@linaro.org> +Date: Fri Sep 12 22:00:07 2014 +0800 + + ARM64 / ACPI: Parse FADT table to get PSCI flags for PSCI init + + There are two flags: PSCI_COMPLIANT and PSCI_USE_HVC. When set, + the former signals to the OS that the firmware is PSCI compliant. + The latter selects the appropriate conduit for PSCI calls by + toggling between Hypervisor Calls (HVC) and Secure Monitor Calls + (SMC). + + FADT table contains such information, parse FADT to get the flags + for PSCI init. Since ACPI 5.1 doesn't support self defined PSCI + function IDs, which means that only PSCI 0.2+ is supported in ACPI. + + At the same time, only ACPI 5.1 or higher verison supports PSCI, + and FADT Major.Minor version was introduced in ACPI 5.1, so we + will check the version and only parse FADT table with version >= 5.1. + + If firmware provides ACPI tables with ACPI version less than 5.1, + OS will be messed up with those information and have no way to init + smp and GIC, so disable ACPI if we get an FADT table with version + less that 5.1. + + Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> + Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org> + Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org> -commit 67e3bcf8dd823eec79c74bc993fa62fb08b1acea -Author: Marc Zyngier <marc.zyngier@arm.com> -Date: Mon Jun 30 16:01:40 2014 +0100 +commit a13a8c748b6170a8a3f4876163ff74e460bd889f +Author: Hanjun Guo <hanjun.guo@linaro.org> +Date: Fri Sep 12 22:00:06 2014 +0800 - KVM: ARM: vgic: abstract VMCR access + ARM64 / ACPI: Make PCI optional for ACPI on ARM64 - Instead of directly messing with with the GICH_VMCR bits for the CPU - interface save/restore code, add accessors that encode/decode the - entire set of registers exposed by VMCR. + As PCI for ARM64 is not ready, so introduce some stub functions + to make PCI optional for ACPI, and make ACPI core run without + CONFIG_PCI on ARM64. - Not the most efficient thing, but given that this code is only used - by the save/restore code, performance is far from being critical. + Since ACPI on X86 and IA64 depends on PCI and this patch only makes + PCI optional for ARM64, it will not break anything on X86 and IA64. - Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> - Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> + Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> -commit 67caf34f138a4f2516a2afcd5657add2eaaf0ab4 -Author: Marc Zyngier <marc.zyngier@arm.com> -Date: Mon Jun 30 16:01:39 2014 +0100 +commit a6bf98355490142fc3f6e9c0839af128e326f16d +Author: Graeme Gregory <graeme.gregory@linaro.org> +Date: Fri Sep 12 22:00:05 2014 +0800 - KVM: ARM: vgic: move underflow handling to vgic_ops + ARM64 / ACPI: If we chose to boot from acpi then disable FDT - Move the code dealing with LR underflow handling to its own functions, - and make them accessible through vgic_ops. + If the early boot methods of acpi are happy that we have valid ACPI + tables and acpi=off has not been passed. Then do not unflat + devicetree effectively disabling further hardware probing from DT. - Acked-by: Catalin Marinas <catalin.marinas@arm.com> - Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> - Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> + Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org> + Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> -commit 30acb0a340d388135ae89bed7e248bad203ec876 -Author: Marc Zyngier <marc.zyngier@arm.com> -Date: Mon Jun 30 16:01:38 2014 +0100 +commit e3b9886532d1e13ddb68e4955ad776a8623f9766 +Author: Al Stone <al.stone@linaro.org> +Date: Fri Sep 12 22:00:04 2014 +0800 - KVM: ARM: vgic: abstract MISR decoding + ARM64 / ACPI: Introduce early_param for "acpi" - Instead of directly dealing with the GICH_MISR bits, move the code to - its own function and use a couple of public flags to represent the - actual state. + Introduce one early parameters "off" for "acpi" to disable ACPI on + ARM64. - Acked-by: Catalin Marinas <catalin.marinas@arm.com> - Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> - Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> + This ensures the kernel uses the DT on a platform that provides both + ACPI tables and DT. + + Signed-off-by: Al Stone <al.stone@linaro.org> + Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org> + Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> -commit 464cbe47011e07b654d161ab4d4bdd05b4d025b3 -Author: Marc Zyngier <marc.zyngier@arm.com> -Date: Mon Jun 30 16:01:37 2014 +0100 +commit cf1cbe39385d417286a98e3abd7ea3456be2e88c +Author: Graeme Gregory <graeme.gregory@linaro.org> +Date: Fri Sep 12 22:00:03 2014 +0800 - KVM: ARM: vgic: abstract EISR bitmap access + ARM64 / ACPI: Introduce sleep-arm.c - Move the GICH_EISR access to its own function. + ACPI 5.1 does not currently support S states for ARM64 hardware but + ACPI code will call acpi_target_system_state() for device power + managment, so introduce sleep-arm.c to allow other drivers to function + until S states are defined. - Acked-by: Catalin Marinas <catalin.marinas@arm.com> - Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> - Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> + Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org> + Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org> + Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> -commit 33930dc5f401e9fc2268c2f128853eb5275e7ab1 -Author: Marc Zyngier <marc.zyngier@arm.com> -Date: Mon Jun 30 16:01:36 2014 +0100 +commit 90e5cfbaf183d0eb92f1977c24da20c4e0a2f6be +Author: Al Stone <al.stone@linaro.org> +Date: Fri Sep 12 22:00:02 2014 +0800 - KVM: ARM: vgic: abstract access to the ELRSR bitmap + ARM64 / ACPI: Get RSDP and ACPI boot-time tables + + As we want to get ACPI tables to parse and then use the information + for system initialization, we should get the RSDP (Root System + Description Pointer) first, it then locates Extended Root Description + Table (XSDT) which contains all the 64-bit physical address that + pointer to other boot-time tables. + + Introduce acpi.c and its related head file in this patch to provide + fundamental needs of extern variables and functions for ACPI core, + and then get boot-time tables as needed. + - asm/acenv.h for arch specific ACPICA environments and + implementation, It is needed unconditionally by ACPI core; + - asm/acpi.h for arch specific variables and functions needed by + ACPI driver core; + - acpi.c for ARM64 related ACPI implementation for ACPI driver + core; + + acpi_boot_table_init() is introduced to get RSDP and boot-time tables, + it will be called in setup_arch() before paging_init(), so we should + use eary_memremap() mechanism here to get the RSDP and all the table + pointers. + + Signed-off-by: Al Stone <al.stone@linaro.org> + Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org> + Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org> + Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> + +commit 2fe5d24887dea3f1bffabf04e364fa9f355ed553 +Author: Tomasz Nowicki <tomasz.nowicki@linaro.org> +Date: Fri Sep 12 22:00:01 2014 +0800 + + ACPI / table: Count matched and successfully parsed entries without specifying max entries - Move the GICH_ELRSR access to its own functions, and add them to - the vgic_ops structure. + It is very useful to traverse all available table entries without max + number of expected entries type. Current acpi_parse_entries() + implementation gives that feature but it does not count those entries, + it returns 0 instead, so fix it to count matched and successfully + entries and return it. - Acked-by: Catalin Marinas <catalin.marinas@arm.com> - Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> - Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> + NOTE: This change has no impact to x86 and ia64 archs since existing code + checks for error occurrence only (acpi_parse_entries(...,0) < 0). + + Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org> + Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> + +commit 8c278c76231f0ba0110e755678eefdd6d077f5da +Author: Ashwin Chaugule <ashwin.chaugule@linaro.org> +Date: Fri Sep 12 22:00:00 2014 +0800 -commit 0dca962ccd5b96fb7174880c1bc25085dcc09927 -Author: Marc Zyngier <marc.zyngier@arm.com> -Date: Mon Jun 30 16:01:35 2014 +0100 + ACPI / table: Add new function to get table entries + + The acpi_table_parse() function has a callback that + passes a pointer to a table_header. Add a new function + which takes this pointer and parses its entries. This + eliminates the need to re-traverse all the tables for + each call. e.g. as in acpi_table_parse_madt() which is + normally called after acpi_table_parse(). + + Signed-off-by: Ashwin Chaugule <ashwin.chaugule@linaro.org> + Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org> + Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> - KVM: ARM: vgic: introduce vgic_ops and LR manipulation primitives +commit 651ab5ff6804fa0f516715b4d47399e587944de0 +Author: Hanjun Guo <hanjun.guo@linaro.org> +Date: Fri Sep 12 21:59:59 2014 +0800 + + ARM64: Move the init of cpu_logical_map(0) before unflatten_device_tree() - In order to split the various register manipulation from the main vgic - code, introduce a vgic_ops structure, and start by abstracting the - LR manipulation code with a couple of accessors. + It always make sense to initialize CPU0's logical map entry from the + hardware values, so move the initialization of cpu_logical_map(0) + before unflatten_device_tree() which is needed by ACPI code later. - Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> - Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> + Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> -commit e66aa6cbdaa25764c58ba8d21da8d1b7d75e7570 -Author: Marc Zyngier <marc.zyngier@arm.com> -Date: Mon Jun 30 16:01:34 2014 +0100 +commit b91246f1a7120de6de8fe630ed01e9a0d0415e88 +Author: Tanmay Inamdar <tinamdar@apm.com> +Date: Fri Sep 26 14:08:27 2014 -0700 - KVM: arm/arm64: vgic: move GICv2 registers to their own structure + MAINTAINERS: entry for APM X-Gene PCIe host driver - In order to make way for the GICv3 registers, move the v2-specific - registers to their own structure. + Add entry for AppliedMicro X-Gene PCIe host driver. - Acked-by: Catalin Marinas <catalin.marinas@arm.com> - Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> - Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> + Signed-off-by: Tanmay Inamdar <tinamdar@apm.com> -commit b04259737c6bb38592c02c93e939fd53909dad04 -Author: Marc Zyngier <marc.zyngier@arm.com> -Date: Mon Jun 30 16:01:33 2014 +0100 +commit d20b104083718058b599a5ca1a925d8c5243e2e1 +Author: Tanmay Inamdar <tinamdar@apm.com> +Date: Fri Sep 26 14:08:26 2014 -0700 - arm64: boot protocol documentation update for GICv3 + dt-bindings: pci: xgene pcie device tree bindings - Linux has some requirements that must be satisfied in order to boot - on a system built with a GICv3. + This patch adds the bindings for X-Gene PCIe driver. The driver resides + under 'drivers/pci/host/pci-xgene.c' file. - Acked-by: Christoffer Dall <christoffer.dall@linaro.org> - Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> + Signed-off-by: Tanmay Inamdar <tinamdar@apm.com> -commit a864693311bd4305214d966b7ca0e0015216c2c4 -Author: Marc Zyngier <marc.zyngier@arm.com> -Date: Mon Jun 30 16:01:32 2014 +0100 +commit 9c429c919b77a3a63ac2843e9e0e2e50e59d28f3 +Author: Tanmay Inamdar <tinamdar@apm.com> +Date: Fri Sep 26 14:08:25 2014 -0700 - arm64: GICv3 device tree binding documentation + arm64: dts: APM X-Gene PCIe device tree nodes - Add the necessary documentation to support GICv3. + This patch adds the device tree nodes for APM X-Gene PCIe host controller and + PCIe clock interface. Since X-Gene SOC supports maximum 5 ports, 5 dts + nodes are added. - Cc: Thomas Gleixner <tglx@linutronix.de> - Cc: Mark Rutland <mark.rutland@arm.com> - Acked-by: Catalin Marinas <catalin.marinas@arm.com> - Acked-by: Rob Herring <robh@kernel.org> - Acked-by: Christoffer Dall <christoffer.dall@linaro.org> - Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> - -commit af3035d3ddddb6e19bac9295f0c785bb2c8e718c -Author: Marc Zyngier <marc.zyngier@arm.com> -Date: Mon Jun 30 16:01:31 2014 +0100 - - irqchip: arm64: Initial support for GICv3 - - The Generic Interrupt Controller (version 3) offers services that are - similar to GICv2, with a number of additional features: - - Affinity routing based on the CPU MPIDR (ARE) - - System register for the CPU interfaces (SRE) - - Support for more that 8 CPUs - - Locality-specific Peripheral Interrupts (LPIs) - - Interrupt Translation Services (ITS) - - This patch adds preliminary support for GICv3 with ARE and SRE, - non-secure mode only. It relies on higher exception levels to grant ARE - and SRE access. - - Support for LPI and ITS will be added at a later time. - - Cc: Thomas Gleixner <tglx@linutronix.de> - Cc: Jason Cooper <jason@lakedaemon.net> - Reviewed-by: Zi Shen Lim <zlim@broadcom.com> - Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> - Reviewed-by: Tirumalesh Chalamarla <tchalamarla@cavium.com> - Reviewed-by: Yun Wu <wuyun.wu@huawei.com> - Reviewed-by: Zhen Lei <thunder.leizhen@huawei.com> - Tested-by: Tirumalesh Chalamarla<tchalamarla@cavium.com> - Tested-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> - Acked-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> - Acked-by: Catalin Marinas <catalin.marinas@arm.com> - Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> + Signed-off-by: Tanmay Inamdar <tinamdar@apm.com> -commit c50b02761c3ad5d37ce8fffe7c0bf6b46d23109e -Author: Marc Zyngier <marc.zyngier@arm.com> -Date: Mon Jun 30 16:01:30 2014 +0100 +commit 3aa4f71932b67e648aff4ae0dc5ace7162d74c1c +Author: Tanmay Inamdar <tinamdar@apm.com> +Date: Fri Sep 26 14:08:24 2014 -0700 - irqchip: ARM: GIC: Move some bits of GICv2 to a library-type file + pci:host: APM X-Gene PCIe host controller driver - A few GICv2 low-level function are actually very useful to GICv3, - and it makes some sense to share them across the two drivers. - They end-up in their own file, with an additional parameter used - to ensure an optional synchronization (unused on GICv2). + This patch adds the AppliedMicro X-Gene SOC PCIe host controller driver. + X-Gene PCIe controller supports maximum up to 8 lanes and GEN3 speed. + X-Gene SOC supports maximum 5 PCIe ports. - Cc: Thomas Gleixner <tglx@linutronix.de> - Cc: Jason Cooper <jason@lakedaemon.net> - Acked-by: Christoffer Dall <christoffer.dall@linaro.org> - Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> + Reviewed-by: Liviu Dudau <Liviu.Dudau@arm.com> + Tested-by: Ming Lei <ming.lei@canonical.com> + Tested-by: Dann Frazier <dann.frazier@canonical.com> + Signed-off-by: Tanmay Inamdar <tinamdar@apm.com> -commit 6a6033cdcbf6022c2848e2181ed6d8b7545af02e -Author: Mark Salter <msalter@redhat.com> -Date: Tue Jun 24 23:16:45 2014 -0400 +commit f3c00bd4ae49b19923049f0f4f9d6a95eaa61b1e +Author: Liviu Dudau <Liviu.Dudau@arm.com> +Date: Tue Sep 23 20:01:14 2014 +0100 - perf: fix arm64 build error + arm64: Add architectural support for PCI - I'm seeing the following build error on arm64: + Use the generic PCI domain and OF functions to provide support for PCI + on arm64. - In file included from util/event.c:3:0: - util/event.h:95:17: error: 'PERF_REGS_MAX' undeclared here (not in a function) - u64 cache_regs[PERF_REGS_MAX]; - ^ + [bhelgaas: Change comments to use generic PCI, not just PCIe. Nothing at + this level is PCIe-specific.] + Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> + Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> + Acked-by: Catalin Marinas <catalin.marinas@arm.com> + +commit 497220defa08534526ad7b20a9c7eb2d0d903ca4 +Author: Liviu Dudau <Liviu.Dudau@arm.com> +Date: Tue Sep 23 20:01:13 2014 +0100 + + PCI: Add pci_remap_iospace() to map bus I/O resources - This patch adds a PEFF_REGS_MAX definition for arm64. + Add pci_remap_iospace() to map bus I/O resources into the CPU virtual + address space. Architectures with special needs may provide their own + version, but most should be able to use this one. - Signed-off-by: Mark Salter <msalter@redhat.com> + This function is useful for PCI host bridge drivers that need to map the + PCI I/O resources into virtual memory space. + + [bhelgaas: phys_addr description, drop temporary "err" variable] + Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> + Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> + Reviewed-by: Rob Herring <robh@kernel.org> + Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> + CC: Arnd Bergmann <arnd@arndb.de> -commit 1de8987fa549d421576c1b61282c4041c8c78a5f -Author: Mark Salter <msalter@redhat.com> -Date: Tue Jun 24 09:50:28 2014 -0400 +commit 7a46ace11cf09b3713dcdc2ef4a17130a738f856 +Author: Liviu Dudau <Liviu.Dudau@arm.com> +Date: Tue Sep 23 20:01:12 2014 +0100 - arm64: use EFI as last resort for reboot and poweroff + PCI: Assign unassigned bus resources in pci_scan_root_bus() - Wire in support for EFI reboot and poweroff functions. We use these - only if no other mechanism has been registered with arm_pm_reboot - and/or pm_power_off respectively. + If the firmware has not assigned all the bus resources and we are not just + probing the PCI buses, it makes sense to assign the unassigned resources + in pci_scan_root_bus(). - Signed-off-by: Mark Salter <msalter@redhat.com> + Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> + Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> + CC: Arnd Bergmann <arnd@arndb.de> + CC: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> + CC: Rob Herring <robh+dt@kernel.org> + +commit fe33bc876010c3ef700c863099f2c3c1a5e2c18b +Author: Liviu Dudau <Liviu.Dudau@arm.com> +Date: Wed Sep 24 11:27:33 2014 -0600 + + of/pci: Add support for parsing PCI host bridge resources from DT + + Provide a function to parse the PCI DT ranges that can be used to create a + pci_host_bridge structure together with its associated bus. + + Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> + [make io_base parameter optional] + Signed-off-by: Robert Richter <rrichter@cavium.com> + Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> + CC: Arnd Bergmann <arnd@arndb.de> + CC: Grant Likely <grant.likely@linaro.org> + CC: Rob Herring <robh+dt@kernel.org> + CC: Catalin Marinas <catalin.marinas@arm.com> -commit 1c973051e86625be7ffb3db90d4a70b9ca4199c6 -Author: Matt Fleming <matt.fleming@intel.com> -Date: Fri Jun 13 12:39:55 2014 +0100 +commit 71094afda69ac873bb3d6486307e3048e21e912c +Author: Liviu Dudau <Liviu.Dudau@arm.com> +Date: Tue Sep 23 20:01:10 2014 +0100 - x86/reboot: Add EFI reboot quirk for ACPI Hardware Reduced flag + of/pci: Add of_pci_get_domain_nr() and of_get_pci_domain_nr() - It appears that the BayTrail-T class of hardware requires EFI in order - to powerdown and reboot and no other reliable method exists. + Add pci_get_new_domain_nr() to allocate a new domain number and + of_get_pci_domain_nr() to retrieve the PCI domain number of a given device + from DT. Host bridge drivers or architecture-specific code can choose to + implement their PCI domain number policy using these two functions. - This quirk is generally applicable to all hardware that has the ACPI - Hardware Reduced bit set, since usually ACPI would be the preferred - method. + Using of_get_pci_domain_nr() guarantees a stable PCI domain number on every + boot provided that all host bridge controllers are assigned a number in the + device tree using "linux,pci-domain" property. Mixing use of + pci_get_new_domain_nr() and of_get_pci_domain_nr() is not recommended as it + can lead to potentially conflicting domain numbers being assigned to root + buses behind different host bridges. - Cc: Len Brown <len.brown@intel.com> - Cc: Mark Salter <msalter@redhat.com> - Cc: "Rafael J. Wysocki" <rafael.j.wysocki@intel.com> - Signed-off-by: Matt Fleming <matt.fleming@intel.com> + Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> + Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> + CC: Arnd Bergmann <arnd@arndb.de> + CC: Grant Likely <grant.likely@linaro.org> + CC: Rob Herring <robh+dt@kernel.org> + CC: Catalin Marinas <catalin.marinas@arm.com> -commit 621b2a0f1df86bd2f147799303b94575f3acee95 -Author: Matt Fleming <matt.fleming@intel.com> -Date: Fri Jun 13 12:35:21 2014 +0100 +commit 6b385455f18d15da6b5d60a3b67fdb846ae1a3b1 +Author: Catalin Marinas <catalin.marinas@arm.com> +Date: Tue Sep 23 20:01:09 2014 +0100 - efi/reboot: Allow powering off machines using EFI + PCI: Add generic domain handling + + The handling of PCI domains (or PCI segments in ACPI speak) is usually a + straightforward affair but its implementation is currently left to the + architectural code, with pci_domain_nr(b) querying the value of the domain + associated with bus b. + + This patch introduces CONFIG_PCI_DOMAINS_GENERIC as an option that can be + selected if an architecture wants a simple implementation where the value + of the domain associated with a bus is stored in struct pci_bus. - Not only can EfiResetSystem() be used to reboot, it can also be used to - power down machines. + The architectures that select CONFIG_PCI_DOMAINS_GENERIC will then have to + implement pci_bus_assign_domain_nr() as a way of setting the domain number + associated with a root bus. All child buses except the root bus will + inherit the domain_nr value from their parent. + + Signed-off-by: Catalin Marinas <Catalin.Marinas@arm.com> + [Renamed pci_set_domain_nr() to pci_bus_assign_domain_nr()] + Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> + Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> + CC: Arnd Bergmann <arnd@arndb.de> + +commit 04b36e0e1da5a96a58dec4f1b393090f00e5b635 +Author: Liviu Dudau <Liviu.Dudau@arm.com> +Date: Tue Sep 23 20:01:08 2014 +0100 + + PCI: Create pci_host_bridge before root bus - By and large, this functionality doesn't work very well across the range - of EFI machines in the wild, so it should definitely only be used as a - last resort. In an ideal world, this wouldn't be needed at all. + Before 7b5436635800 ("PCI: add generic device into pci_host_bridge + struct"), the pci_host_bridge was created before the root bus. Revert the + order of creation as we are going to depend on the pci_host_bridge + structure to retrieve the domain number of the root bus. - Unfortunately, we're starting to see machines where EFI is the *only* - reliable way to power down, and nothing else, not PCI, not ACPI, works. + [bhelgaas: changelog] + Tested-by: Tanmay Inamdar <tinamdar@apm.com> + Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> + Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> + Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> + Acked-by: Grant Likely <grant.likely@linaro.org> + +commit 7569c510218798bd7e5216bf14a42c656f14e891 +Author: Liviu Dudau <Liviu.Dudau@arm.com> +Date: Tue Sep 23 20:01:07 2014 +0100 + + of/pci: Fix the conversion of IO ranges into IO resources - efi_poweroff_required() should be implemented on a per-architecture - basis, since exactly when we should be using EFI runtime services is a - platform-specific decision. There's no analogue for reboot because each - architecture handles reboot very differently - the x86 code in - particular is pretty complex. + The ranges property for a host bridge controller in DT describes the + mapping between the PCI bus address and the CPU physical address. The + resources framework however expects that the IO resources start at a pseudo + "port" address 0 (zero) and have a maximum size of IO_SPACE_LIMIT. The + conversion from PCI ranges to resources failed to take that into account, + returning a CPU physical address instead of a port number. - Patches to enable this for specific classes of hardware will be - submitted separately. + Also fix all the drivers that depend on the old behaviour by fetching the + CPU physical address based on the port number where it is being needed. - Cc: Mark Salter <msalter@redhat.com> - Signed-off-by: Matt Fleming <matt.fleming@intel.com> + Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> + Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> + Acked-by: Linus Walleij <linus.walleij@linaro.org> + CC: Grant Likely <grant.likely@linaro.org> + CC: Rob Herring <robh+dt@kernel.org> + CC: Arnd Bergmann <arnd@arndb.de> + CC: Thierry Reding <thierry.reding@gmail.com> + CC: Simon Horman <horms@verge.net.au> + CC: Catalin Marinas <catalin.marinas@arm.com> -commit 6b2e219b20933cad5d5ba34f7af4efc5317c0fb9 -Author: Matt Fleming <matt.fleming@intel.com> -Date: Fri Jun 13 12:22:22 2014 +0100 +commit 1b381671c9dd2c82cd6f04bc1588d0fc4e1aea59 +Author: Liviu Dudau <Liviu.Dudau@arm.com> +Date: Tue Sep 23 20:01:06 2014 +0100 - efi/reboot: Add generic wrapper around EfiResetSystem() + of/pci: Move of_pci_range_to_resources() to of/address.c - Implement efi_reboot(), which is really just a wrapper around the - EfiResetSystem() EFI runtime service, but it does at least allow us to - funnel all callers through a single location. + We need to enhance of_pci_range_to_resources() enough that it won't make + sense for it to be inline anymore. Move it to drivers/of/address.c, + keeping it under #ifdef CONFIG_PCI. - It also simplifies the callsites since users no longer need to check to - see whether EFI_RUNTIME_SERVICES are enabled. + [bhelgaas: drop extra detail from changelog, move def under CONFIG_PCI] + Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> + Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> + CC: Grant Likely <grant.likely@linaro.org> + CC: Rob Herring <robh+dt@kernel.org> + CC: Arnd Bergmann <arnd@arndb.de> + CC: Catalin Marinas <catalin.marinas@arm.com> + +commit eedd8f88d4895d5c6bc46cf3ddeb114a0fafb7c3 +Author: Bjorn Helgaas <bhelgaas@google.com> +Date: Tue Sep 23 17:27:42 2014 -0600 + + of/pci: Define of_pci_range_to_resource() only when CONFIG_PCI=y + + of_pci_range_to_resource() was previously defined always, but it's only + used by PCI code, so move the definition inside the CONFIG_OF_ADDRESS && + CONFIG_PCI block. - Cc: Tony Luck <tony.luck@intel.com> - Cc: Mark Salter <msalter@redhat.com> - Signed-off-by: Matt Fleming <matt.fleming@intel.com> + Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> -commit d0d41b99122d97f81ad05868dff38ccf0a3ffd33 -Author: Saurabh Tangri <saurabh.tangri@intel.com> -Date: Mon Jun 2 05:18:35 2014 -0700 +commit 4ac73f8ded507537318717bb2b5b6c765db633cd +Author: Liviu Dudau <Liviu.Dudau@arm.com> +Date: Tue Sep 23 20:01:05 2014 +0100 - x86/efi: Move all workarounds to a separate file quirks.c + ARM: Define PCI_IOBASE as the base of virtual PCI IO space - Currently, it's difficult to find all the workarounds that are - applied when running on EFI, because they're littered throughout - various code paths. This change moves all of them into a separate - file with the hope that it will be come the single location for all - our well documented quirks. + This is needed for calls into OF code that parses PCI ranges. It signals + support for memory mapped PCI I/O accesses that are described by device + trees. - Signed-off-by: Saurabh Tangri <saurabh.tangri@intel.com> - Signed-off-by: Matt Fleming <matt.fleming@intel.com> + Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> + Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> + Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> + Acked-by: Arnd Bergmann <arnd@arndb.de> + CC: Russell King <linux@arm.linux.org.uk> + CC: Rob Herring <robh+dt@kernel.org> -commit b5e3a1e8825abb0406ead0e85436df4df20ddcdb -Author: Don Dutile <ddutile@redhat.com> -Date: Tue Mar 25 20:22:26 2014 -0400 +commit ce7af33b6db857c95ac3b65fef37e589e839cc79 +Author: Liviu Dudau <Liviu.Dudau@arm.com> +Date: Tue Sep 23 20:01:04 2014 +0100 - pmu: Adding support for Xgene PMUs + of/pci: Add pci_register_io_range() and pci_pio_to_address() - Message-id: <1395778948-47814-2-git-send-email-ddutile@redhat.com> - Patchwork-id: 78602 - O-Subject: [PATCH 1/3] pmu: Adding support for Xgene PMUs - Bugzilla: 1079110 + Some architectures do not have a simple view of the PCI I/O space and + instead use a range of CPU addresses that map to bus addresses. For some + architectures these ranges will be expressed by OF bindings in a device + tree file. - Backport of these two posted (but not upstream) patches. - Combined into single patch due to gic-patch dependency. + This patch introduces a pci_register_io_range() helper function with a + generic implementation that can be used by such architectures to keep track + of the I/O ranges described by the PCI bindings. If the PCI_IOBASE macro + is not defined, that signals lack of support for PCI and we return an + error. - Signed-off-by: Donald Dutile <ddutile@redhat.com> + In order to retrieve the CPU address associated with an I/O port, a new + helper function pci_pio_to_address() is introduced. This will search in + the list of ranges registered with pci_register_io_range() and return the + CPU address that corresponds to the given port. + + Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> + Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> + Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> + Acked-by: Rob Herring <robh@kernel.org> + CC: Grant Likely <grant.likely@linaro.org> + CC: Arnd Bergmann <arnd@arndb.de> -commit 9f4c27693bb120a3134e3e7e8d452fb02d023e2b -Author: Mark Salter <msalter@redhat.com> -Date: Sun Jun 15 09:06:55 2014 -0400 +commit c5d57f95901af49149ebf6dfc3d7518157e41bfa +Author: Liviu Dudau <Liviu.Dudau@arm.com> +Date: Tue Sep 23 20:01:03 2014 +0100 - arm64: fix up APM Mustang devicetree + asm-generic/io.h: Fix ioport_map() for !CONFIG_GENERIC_IOMAP - These are changes needed when loading device tree blob built with - kernel. i.e. with grub. These are not needed when using devicetree - from Tianocore which will be fixed up at tianocore runtime. + The !CONFIG_GENERIC_IOMAP version of ioport_map() is wrong. It returns a + mapped, i.e., virtual, address that can start from zero and completely + ignores the PCI_IOBASE and IO_SPACE_LIMIT that most architectures that use + !CONFIG_GENERIC_MAP define. - Signed-off-by: Mark Salter <msalter@redhat.com> + Tested-by: Tanmay Inamdar <tinamdar@apm.com> + Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> + Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> + Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> + Acked-by: Arnd Bergmann <arnd@arndb.de> -commit 1f3a5b228be88be3f734d7a43db3b3f81e160443 -Author: Iyappan Subramanian <isubramanian@apm.com> -Date: Mon Jul 14 15:18:05 2014 -0700 +commit a65e51156bec2c8d690b924bbddf1a740309e543 +Author: Mark Salter <msalter@redhat.com> +Date: Tue Jun 24 09:50:28 2014 -0400 - drivers: net: Add APM X-Gene SoC ethernet driver support. + arm64: use EFI as last resort for reboot and poweroff - This patch adds network driver for APM X-Gene SoC ethernet. + Wire in support for EFI reboot and poweroff functions. We use these + only if no other mechanism has been registered with arm_pm_reboot + and/or pm_power_off respectively. - Signed-off-by: Iyappan Subramanian <isubramanian@apm.com> - Signed-off-by: Ravi Patel <rapatel@apm.com> - Signed-off-by: Keyur Chudgar <kchudgar@apm.com> + Signed-off-by: Mark Salter <msalter@redhat.com> -commit 54b3fe04c4a953eeb6907ffe9f57aae282f59457 -Author: Iyappan Subramanian <isubramanian@apm.com> -Date: Mon Jul 14 15:18:04 2014 -0700 +commit c6b81122978c39e52021cc7308edafff88c8b87a +Author: Ard Biesheuvel <ard.biesheuvel@linaro.org> +Date: Wed Jul 30 11:59:04 2014 +0100 - dts: Add bindings for APM X-Gene SoC ethernet driver + arm64/efi: efistub: don't abort if base of DRAM is occupied - This patch adds bindings for APM X-Gene SoC ethernet driver. + If we cannot relocate the kernel Image to its preferred offset of base of DRAM + plus TEXT_OFFSET, instead relocate it to the lowest available 2 MB boundary plus + TEXT_OFFSET. We may lose a bit of memory at the low end, but we can still + proceed normally otherwise. - Signed-off-by: Iyappan Subramanian <isubramanian@apm.com> - Signed-off-by: Ravi Patel <rapatel@apm.com> - Signed-off-by: Keyur Chudgar <kchudgar@apm.com> + Acked-by: Mark Salter <msalter@redhat.com> + Acked-by: Mark Rutland <mark.rutland@arm.com> + Acked-by: Leif Lindholm <leif.lindholm@linaro.org> + Tested-by: Leif Lindholm <leif.lindholm@linaro.org> + Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> + Signed-off-by: Will Deacon <will.deacon@arm.com> -commit 85125c4e1c1b1ef53d6cb77966efa89062540f43 -Author: Iyappan Subramanian <isubramanian@apm.com> -Date: Mon Jul 14 15:18:03 2014 -0700 +commit 81fd1d315f3c5b13f9dcf71cce51dfd3a10331c3 +Author: Ard Biesheuvel <ard.biesheuvel@linaro.org> +Date: Wed Jul 30 11:59:03 2014 +0100 - Documentation: dts: Add bindings for APM X-Gene SoC ethernet driver + arm64/efi: efistub: cover entire static mem footprint in PE/COFF .text + + The static memory footprint of a kernel Image at boot is larger than the + Image file itself. Things like .bss data and initial page tables are allocated + statically but populated dynamically so their content is not contained in the + Image file. - This patch adds documentation for APM X-Gene SoC ethernet DTS binding. + However, if EFI (or GRUB) has loaded the Image at precisely the desired offset + of base of DRAM + TEXT_OFFSET, the Image will be booted in place, and we have + to make sure that the allocation done by the PE/COFF loader is large enough. - Signed-off-by: Iyappan Subramanian <isubramanian@apm.com> - Signed-off-by: Ravi Patel <rapatel@apm.com> - Signed-off-by: Keyur Chudgar <kchudgar@apm.com> + Fix this by growing the PE/COFF .text section to cover the entire static + memory footprint. The part of the section that is not covered by the payload + will be zero initialised by the PE/COFF loader. + + Acked-by: Mark Salter <msalter@redhat.com> + Acked-by: Mark Rutland <mark.rutland@arm.com> + Acked-by: Leif Lindholm <leif.lindholm@linaro.org> + Tested-by: Leif Lindholm <leif.lindholm@linaro.org> + Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> + Signed-off-by: Will Deacon <will.deacon@arm.com> -commit fe8ec437eedc45384c23e1e12a09baa82d24fa16 -Author: Iyappan Subramanian <isubramanian@apm.com> -Date: Mon Jul 14 15:18:02 2014 -0700 +commit 8f5f73c2117c2dc4e8903d162023c34177327ae3 +Author: Mark Rutland <mark.rutland@arm.com> +Date: Wed Jul 30 11:59:02 2014 +0100 - MAINTAINERS: Add entry for APM X-Gene SoC ethernet driver + arm64: spin-table: handle unmapped cpu-release-addrs - This patch adds a MAINTAINERS entry for APM X-Gene SoC - ethernet driver. + In certain cases the cpu-release-addr of a CPU may not fall in the + linear mapping (e.g. when the kernel is loaded above this address due to + the presence of other images in memory). This is problematic for the + spin-table code as it assumes that it can trivially convert a + cpu-release-addr to a valid VA in the linear map. + + This patch modifies the spin-table code to use a temporary cached + mapping to write to a given cpu-release-addr, enabling us to support + addresses regardless of whether they are covered by the linear mapping. - Signed-off-by: Iyappan Subramanian <isubramanian@apm.com> - Signed-off-by: Ravi Patel <rapatel@apm.com> - Signed-off-by: Keyur Chudgar <kchudgar@apm.com> + Acked-by: Leif Lindholm <leif.lindholm@linaro.org> + Tested-by: Leif Lindholm <leif.lindholm@linaro.org> + Tested-by: Mark Salter <msalter@redhat.com> + Signed-off-by: Mark Rutland <mark.rutland@arm.com> + [ardb: added (__force void *) cast] + Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> + Signed-off-by: Will Deacon <will.deacon@arm.com> -commit 237639e43c3d6587985a736f33264e129123d7a5 +commit b00c56bff1ffb6c77655479fb350ee3d5c8bcf63 Author: Mark Salter <msalter@redhat.com> -Date: Fri Jul 25 15:14:32 2014 -0400 +Date: Tue Jun 24 23:16:45 2014 -0400 - arm/kvm: WIP fix for stage2 pgd memory leak + perf: fix arm64 build error + + I'm seeing the following build error on arm64: + + In file included from util/event.c:3:0: + util/event.h:95:17: error: 'PERF_REGS_MAX' undeclared here (not in a function) + u64 cache_regs[PERF_REGS_MAX]; + ^ + + This patch adds a PEFF_REGS_MAX definition for arm64. Signed-off-by: Mark Salter <msalter@redhat.com> -commit 0794e2900e5e4be4b7aa0b389e6b0bf8b55c5cd7 +commit f440dcb067bf1367719e8a41b96a2a83c1232690 Author: Mark Salter <msalter@redhat.com> Date: Thu Jul 17 13:34:50 2014 -0400 @@ -779,24 +1157,7 @@ Date: Thu Jul 17 13:34:50 2014 -0400 Signed-off-by: Mark Salter <msalter@redhat.com> -commit 7adf85b63608b8bea1148f2faa84f475252a9e43 -Author: Mark Salter <msalter@redhat.com> -Date: Fri Jul 25 15:32:05 2014 -0400 - - rtc: ia64: allow other architectures to use EFI RTC - - Currently, the rtc-efi driver is restricted to ia64 only. Newer - architectures with EFI support may want to also use that driver. This - patch moves the platform device setup from ia64 into drivers/rtc and allow - any architecture with CONFIG_EFI=y to use the rtc-efi driver. - - Signed-off-by: Mark Salter <msalter@redhat.com> - Cc: Alessandro Zummo <a.zummo@towertech.it> - Cc: Tony Luck <tony.luck@intel.com> - Cc: Fenghua Yu <fenghua.yu@intel.com> - Cc: Andrew Morton <akpm@linux-foundation.org> - -commit 3b2f96c7a6bfbd46e7dee1d7000081422a7983ce +commit 93b44dc9e1d73d4864a9350888509792f25e4210 Author: Kyle McMartin <kmcmarti@redhat.com> Date: Tue May 13 22:25:26 2014 -0400 @@ -866,287 +1227,339 @@ Date: Tue May 13 22:25:26 2014 -0400 Signed-off-by: Kyle McMartin <kmcmarti@redhat.com> Signed-off-by: Donald Dutile <ddutile@redhat.com> -commit 4b866971e92b925a44da8d876cb57864942a90b8 -Author: Mark Salter <msalter@redhat.com> -Date: Thu Jul 24 15:56:15 2014 +0100 - - arm64: fix soft lockup due to large tlb flush range - - Under certain loads, this soft lockup has been observed: - - BUG: soft lockup - CPU#2 stuck for 22s! [ip6tables:1016] - Modules linked in: ip6t_rpfilter ip6t_REJECT cfg80211 rfkill xt_conntrack ebtable_nat ebtable_broute bridge stp llc ebtable_filter ebtables ip6table_nat nf_conntrack_ipv6 nf_defrag_ipv6 nf_nat_ipv6 ip6table_mangle ip6table_security ip6table_raw ip6table_filter ip6_tables iptable_nat nf_conntrack_ipv4 nf_defrag_ipv4 nf_nat_ipv4 nf_nat nf_conntrack iptable_mangle iptable_security iptable_raw vfat fat efivarfs xfs libcrc32c - - CPU: 2 PID: 1016 Comm: ip6tables Not tainted 3.13.0-0.rc7.30.sa2.aarch64 #1 - task: fffffe03e81d1400 ti: fffffe03f01f8000 task.ti: fffffe03f01f8000 - PC is at __cpu_flush_kern_tlb_range+0xc/0x40 - LR is at __purge_vmap_area_lazy+0x28c/0x3ac - pc : [<fffffe000009c5cc>] lr : [<fffffe0000182710>] pstate: 80000145 - sp : fffffe03f01fbb70 - x29: fffffe03f01fbb70 x28: fffffe03f01f8000 - x27: fffffe0000b19000 x26: 00000000000000d0 - x25: 000000000000001c x24: fffffe03f01fbc50 - x23: fffffe03f01fbc58 x22: fffffe03f01fbc10 - x21: fffffe0000b2a3f8 x20: 0000000000000802 - x19: fffffe0000b2a3c8 x18: 000003fffdf52710 - x17: 000003ff9d8bb910 x16: fffffe000050fbfc - x15: 0000000000005735 x14: 000003ff9d7e1a5c - x13: 0000000000000000 x12: 000003ff9d7e1a5c - x11: 0000000000000007 x10: fffffe0000c09af0 - x9 : fffffe0000ad1000 x8 : 000000000000005c - x7 : fffffe03e8624000 x6 : 0000000000000000 - x5 : 0000000000000000 x4 : 0000000000000000 - x3 : fffffe0000c09cc8 x2 : 0000000000000000 - x1 : 000fffffdfffca80 x0 : 000fffffcd742150 - - The __cpu_flush_kern_tlb_range() function looks like: - - ENTRY(__cpu_flush_kern_tlb_range) - dsb sy - lsr x0, x0, #12 - lsr x1, x1, #12 - 1: tlbi vaae1is, x0 - add x0, x0, #1 - cmp x0, x1 - b.lo 1b - dsb sy - isb - ret - ENDPROC(__cpu_flush_kern_tlb_range) - - The above soft lockup shows the PC at tlbi insn with: - - x0 = 0x000fffffcd742150 - x1 = 0x000fffffdfffca80 - - So __cpu_flush_kern_tlb_range has 0x128ba930 tlbi flushes left - after it has already been looping for 23 seconds!. - - Looking up one frame at __purge_vmap_area_lazy(), there is: - - ... - list_for_each_entry_rcu(va, &vmap_area_list, list) { - if (va->flags & VM_LAZY_FREE) { - if (va->va_start < *start) - *start = va->va_start; - if (va->va_end > *end) - *end = va->va_end; - nr += (va->va_end - va->va_start) >> PAGE_SHIFT; - list_add_tail(&va->purge_list, &valist); - va->flags |= VM_LAZY_FREEING; - va->flags &= ~VM_LAZY_FREE; - } - } - ... - if (nr || force_flush) - flush_tlb_kernel_range(*start, *end); - - So if two areas are being freed, the range passed to - flush_tlb_kernel_range() may be as large as the vmalloc - space. For arm64, this is ~240GB for 4k pagesize and ~2TB - for 64kpage size. - - This patch works around this problem by adding a loop limit. - If the range is larger than the limit, use flush_tlb_all() - rather than flushing based on individual pages. The limit - chosen is arbitrary as the TLB size is implementation - specific and not accessible in an architected way. The aim - of the arbitrary limit is to avoid soft lockup. - - Signed-off-by: Mark Salter <msalter@redhat.com> - [catalin.marinas@arm.com: commit log update] - [catalin.marinas@arm.com: marginal optimisation] - [catalin.marinas@arm.com: changed to MAX_TLB_RANGE and added comment] - Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> - -diff --git a/Documentation/arm64/booting.txt b/Documentation/arm64/booting.txt -index 37fc4f6..da1d4bf 100644 ---- a/Documentation/arm64/booting.txt -+++ b/Documentation/arm64/booting.txt -@@ -141,6 +141,14 @@ Before jumping into the kernel, the following conditions must be met: - the kernel image will be entered must be initialised by software at a - higher exception level to prevent execution in an UNKNOWN state. - -+ For systems with a GICv3 interrupt controller: -+ - If EL3 is present: -+ ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1. -+ ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1. -+ - If the kernel is entered at EL1: -+ ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1 -+ ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1. -+ - The requirements described above for CPU mode, caches, MMUs, architected - timers, coherency and system registers apply to all CPUs. All CPUs must - enter the kernel in the same exception level. -diff --git a/Documentation/devicetree/bindings/arm/gic-v3.txt b/Documentation/devicetree/bindings/arm/gic-v3.txt + Documentation/arm64/arm-acpi.txt | 218 +++++++ + .../devicetree/bindings/pci/xgene-pci.txt | 57 ++ + Documentation/kernel-parameters.txt | 3 +- + MAINTAINERS | 8 + + arch/arm/include/asm/io.h | 1 + + arch/arm/include/asm/kvm_mmu.h | 13 + + arch/arm/kvm/arm.c | 23 +- + arch/arm/mach-integrator/pci_v3.c | 23 +- + arch/arm64/Kconfig | 28 +- + arch/arm64/Makefile | 1 + + arch/arm64/boot/dts/apm-mustang.dts | 8 + + arch/arm64/boot/dts/apm-storm.dtsi | 165 ++++++ + arch/arm64/include/asm/Kbuild | 1 + + arch/arm64/include/asm/acenv.h | 18 + + arch/arm64/include/asm/acpi.h | 99 ++++ + arch/arm64/include/asm/cpu_ops.h | 1 + + arch/arm64/include/asm/elf.h | 3 +- + arch/arm64/include/asm/io.h | 3 +- + arch/arm64/include/asm/kvm_arm.h | 17 +- + arch/arm64/include/asm/kvm_mmu.h | 75 +++ + arch/arm64/include/asm/pci.h | 37 ++ + arch/arm64/include/asm/pgtable.h | 2 + + arch/arm64/include/asm/psci.h | 3 +- + arch/arm64/include/asm/smp.h | 10 +- + arch/arm64/kernel/Makefile | 5 +- + arch/arm64/kernel/acpi.c | 397 +++++++++++++ + arch/arm64/kernel/cpu_ops.c | 8 +- + arch/arm64/kernel/efi-stub.c | 16 +- + arch/arm64/kernel/efi.c | 11 + + arch/arm64/kernel/head.S | 6 +- + arch/arm64/kernel/pci.c | 70 +++ + arch/arm64/kernel/process.c | 6 + + arch/arm64/kernel/psci.c | 78 ++- + arch/arm64/kernel/setup.c | 64 +- + arch/arm64/kernel/smp.c | 2 +- + arch/arm64/kernel/smp_parking_protocol.c | 110 ++++ + arch/arm64/kernel/smp_spin_table.c | 22 +- + arch/arm64/kernel/time.c | 7 + + arch/arm64/kvm/hyp-init.S | 20 +- + arch/arm64/mm/dma-mapping.c | 65 ++ + arch/arm64/pci/Makefile | 1 + + arch/arm64/pci/pci.c | 28 + + drivers/acpi/Kconfig | 6 +- + drivers/acpi/Makefile | 6 +- + drivers/acpi/acpica/utresrc.c | 4 +- + drivers/acpi/bus.c | 3 + + drivers/acpi/internal.h | 5 + + drivers/acpi/osl.c | 6 +- + drivers/acpi/processor_core.c | 37 ++ + drivers/acpi/sleep-arm.c | 28 + + drivers/acpi/tables.c | 115 +++- + drivers/acpi/utils.c | 26 + + drivers/ata/Kconfig | 2 +- + drivers/ata/ahci_platform.c | 13 + + drivers/ata/ahci_xgene.c | 30 +- + drivers/clocksource/arm_arch_timer.c | 120 +++- + drivers/irqchip/irq-gic-v3.c | 10 + + drivers/irqchip/irq-gic.c | 116 ++++ + drivers/irqchip/irqchip.c | 3 + + drivers/net/ethernet/amd/xgbe/xgbe-dev.c | 12 + + drivers/net/ethernet/amd/xgbe/xgbe-drv.c | 3 + + drivers/net/ethernet/amd/xgbe/xgbe-main.c | 1 + + drivers/net/ethernet/amd/xgbe/xgbe.h | 3 + + drivers/net/ethernet/smsc/smc91x.c | 10 + + drivers/net/phy/amd-xgbe-phy.c | 408 +++++++------ + drivers/of/address.c | 154 +++++ + drivers/of/of_pci.c | 142 +++++ + drivers/pci/host/Kconfig | 10 + + drivers/pci/host/Makefile | 1 + + drivers/pci/host/pci-tegra.c | 10 +- + drivers/pci/host/pci-xgene.c | 659 +++++++++++++++++++++ + drivers/pci/host/pcie-rcar.c | 21 +- + drivers/pci/pci.c | 40 ++ + drivers/pci/probe.c | 46 +- + drivers/pnp/resource.c | 2 + + drivers/tty/Kconfig | 6 + + drivers/tty/Makefile | 1 + + drivers/tty/sbsauart.c | 355 +++++++++++ + drivers/tty/serial/8250/8250_dw.c | 9 + + drivers/virtio/virtio_mmio.c | 12 +- + include/acpi/acnames.h | 4 + + include/acpi/acpi_bus.h | 2 + + include/acpi/acpi_io.h | 6 + + include/acpi/acpixf.h | 2 +- + include/acpi/actbl1.h | 19 +- + include/acpi/actbl3.h | 9 +- + include/asm-generic/io.h | 2 +- + include/asm-generic/pgtable.h | 4 + + include/kvm/arm_vgic.h | 20 +- + include/linux/acpi.h | 5 + + include/linux/clocksource.h | 6 + + include/linux/irqchip/arm-gic-acpi.h | 31 + + include/linux/irqchip/arm-gic.h | 2 + + include/linux/of_address.h | 17 +- + include/linux/of_pci.h | 13 + + include/linux/pci.h | 64 +- + tools/perf/arch/arm64/include/perf_regs.h | 2 + + virt/kvm/arm/arch_timer.c | 108 ++-- + virt/kvm/arm/vgic-v2.c | 75 ++- + virt/kvm/arm/vgic-v3.c | 8 +- + virt/kvm/arm/vgic.c | 32 +- + 101 files changed, 4112 insertions(+), 487 deletions(-) + +diff --git a/Documentation/arm64/arm-acpi.txt b/Documentation/arm64/arm-acpi.txt new file mode 100644 -index 0000000..33cd05e +index 0000000..b7dc826 --- /dev/null -+++ b/Documentation/devicetree/bindings/arm/gic-v3.txt -@@ -0,0 +1,79 @@ -+* ARM Generic Interrupt Controller, version 3 -+ -+AArch64 SMP cores are often associated with a GICv3, providing Private -+Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI), -+Software Generated Interrupts (SGI), and Locality-specific Peripheral -+Interrupts (LPI). -+ -+Main node required properties: -+ -+- compatible : should at least contain "arm,gic-v3". -+- interrupt-controller : Identifies the node as an interrupt controller -+- #interrupt-cells : Specifies the number of cells needed to encode an -+ interrupt source. Must be a single cell with a value of at least 3. -+ -+ The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI -+ interrupts. Other values are reserved for future use. -+ -+ The 2nd cell contains the interrupt number for the interrupt type. -+ SPI interrupts are in the range [0-987]. PPI interrupts are in the -+ range [0-15]. -+ -+ The 3rd cell is the flags, encoded as follows: -+ bits[3:0] trigger type and level flags. -+ 1 = edge triggered -+ 4 = level triggered -+ -+ Cells 4 and beyond are reserved for future use. When the 1st cell -+ has a value of 0 or 1, cells 4 and beyond act as padding, and may be -+ ignored. It is recommended that padding cells have a value of 0. -+ -+- reg : Specifies base physical address(s) and size of the GIC -+ registers, in the following order: -+ - GIC Distributor interface (GICD) -+ - GIC Redistributors (GICR), one range per redistributor region -+ - GIC CPU interface (GICC) -+ - GIC Hypervisor interface (GICH) -+ - GIC Virtual CPU interface (GICV) -+ -+ GICC, GICH and GICV are optional. -+ -+- interrupts : Interrupt source of the VGIC maintenance interrupt. -+ -+Optional -+ -+- redistributor-stride : If using padding pages, specifies the stride -+ of consecutive redistributors. Must be a multiple of 64kB. -+ -+- #redistributor-regions: The number of independent contiguous regions -+ occupied by the redistributors. Required if more than one such -+ region is present. -+ -+Examples: -+ -+ gic: interrupt-controller@2cf00000 { -+ compatible = "arm,gic-v3"; -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ reg = <0x0 0x2f000000 0 0x10000>, // GICD -+ <0x0 0x2f100000 0 0x200000>, // GICR -+ <0x0 0x2c000000 0 0x2000>, // GICC -+ <0x0 0x2c010000 0 0x2000>, // GICH -+ <0x0 0x2c020000 0 0x2000>; // GICV -+ interrupts = <1 9 4>; -+ }; ++++ b/Documentation/arm64/arm-acpi.txt +@@ -0,0 +1,218 @@ ++ACPI on ARMv8 Servers ++--------------------- + -+ gic: interrupt-controller@2c010000 { -+ compatible = "arm,gic-v3"; -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ redistributor-stride = <0x0 0x40000>; // 256kB stride -+ #redistributor-regions = <2>; -+ reg = <0x0 0x2c010000 0 0x10000>, // GICD -+ <0x0 0x2d000000 0 0x800000>, // GICR 1: CPUs 0-31 -+ <0x0 0x2e000000 0 0x800000>; // GICR 2: CPUs 32-63 -+ <0x0 0x2c040000 0 0x2000>, // GICC -+ <0x0 0x2c060000 0 0x2000>, // GICH -+ <0x0 0x2c080000 0 0x2000>; // GICV -+ interrupts = <1 9 4>; -+ }; -diff --git a/Documentation/devicetree/bindings/net/apm-xgene-enet.txt b/Documentation/devicetree/bindings/net/apm-xgene-enet.txt -new file mode 100644 -index 0000000..3e2a295 ---- /dev/null -+++ b/Documentation/devicetree/bindings/net/apm-xgene-enet.txt -@@ -0,0 +1,72 @@ -+APM X-Gene SoC Ethernet nodes ++ACPI can be used for ARMv8 general purpose servers designed to follow ++the SBSA specification (currently available to people with an ARM login at ++http://silver.arm.com). + -+Ethernet nodes are defined to describe on-chip ethernet interfaces in -+APM X-Gene SoC. ++The kernel will implement minimum ACPI version is 5.1 + errata as released by ++the UEFI Forum, which is available at <http://www.uefi.org/acpi/specs>. + -+Required properties: -+- compatible: Should be "apm,xgene-enet" -+- reg: Address and length of the register set for the device. It contains the -+ information of registers in the same order as described by reg-names -+- reg-names: Should contain the register set names -+ "enet_csr": Ethernet control and status register address space -+ "ring_csr": Descriptor ring control and status register address space -+ "ring_cmd": Descriptor ring command register address space -+- interrupts: Ethernet main interrupt -+- clocks: Reference to the clock entry. -+- local-mac-address: MAC address assigned to this device -+- phy-connection-type: Interface type between ethernet device and PHY device -+- phy-handle: Reference to a PHY node connected to this device -+ -+- mdio: Device tree subnode with the following required -+ properties: -+ -+ - compatible: Must be "apm,xgene-mdio". -+ - #address-cells: Must be <1>. -+ - #size-cells: Must be <0>. -+ -+ For the phy on the mdio bus, there must be a node with the following -+ fields: -+ -+ - compatible: PHY identifier. Please refer ./phy.txt for the format. -+ - reg: The ID number for the phy. ++If the machine does not meet the requirements of the SBSA, or cannot be ++described in the required ACPI specifications then it is likely that Device Tree ++(DT) is more suitable for the hardware. + -+Optional properties: -+- status : Should be "ok" or "disabled" for enabled/disabled. -+ Default is "ok". ++Relationship with Device Tree ++----------------------------- + ++ACPI support in drivers and subsystems for ARMv8 should never be mutually ++exclusive with DT support at compile time. + -+Example: -+ menetclk: menetclk { -+ compatible = "apm,xgene-device-clock"; -+ clock-output-names = "menetclk"; -+ status = "ok"; -+ }; ++At boot time the kernel will only use one description method depending on ++parameters passed from the bootloader (including kernel bootargs). + -+ menet: ethernet@17020000 { -+ compatible = "apm,xgene-enet"; -+ status = "disabled"; -+ reg = <0x0 0x17020000 0x0 0xd100>, -+ <0x0 0X17030000 0x0 0X400>, -+ <0x0 0X10000000 0x0 0X200>; -+ reg-names = "enet_csr", "ring_csr", "ring_cmd"; -+ interrupts = <0x0 0x3c 0x4>; -+ clocks = <&menetclk 0>; -+ local-mac-address = [00 01 73 00 00 01]; -+ phy-connection-type = "rgmii"; -+ phy-handle = <&menetphy>; -+ mdio { -+ compatible = "apm,xgene-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ menetphy: menetphy@3 { -+ compatible = "ethernet-phy-id001c.c915"; -+ reg = <0x3>; -+ }; ++Regardless of whether DT or ACPI is used, the kernel must always be capable ++of booting with either scheme (in kernels with both schemes enabled at compile ++time). + -+ }; -+ }; ++When booting using ACPI tables the /chosen node in DT will still be parsed ++to extract the kernel command line and initrd path. No other section of ++the DT will be used. ++ ++Booting using ACPI tables ++------------------------- ++ ++Currently, the only defined method to pass ACPI tables to the kernel on ARMv8 ++is via the UEFI system configuration table. ++ ++The UEFI implementation MUST set the ACPI_20_TABLE_GUID to point to the ++RSDP table (the table with the ACPI signature "RSD PTR "). ++ ++The pointer to the RSDP table will be retrieved from EFI by the ACPI core. ++ ++Processing of ACPI tables may be disabled by passing acpi=off on the kernel ++command line. ++ ++DO use an XSDT; RSDTs are deprecated and should not be used on arm64. They ++only allow for 32-bit addresses. ++ ++DO NOT use the 32-bit address fields in the FADT; they are deprecated. The ++64-bit alternatives MUST be used. ++ ++The minimum set of tables MUST include RSDP, XSDT, FACS, FADT, DSDT, MADT ++and GTDT. If PCI is used the MCFG table MUST also be present. ++ ++ACPI Detection ++-------------- ++ ++Drivers should determine their probe() type by checking for ACPI_HANDLE, ++or .of_node, or other information in the device structure. This is ++detailed further in the "Driver Recommendations" section. ++ ++In non-driver code If the presence of ACPI needs to be detected at runtime, ++then check the value of acpi_disabled. If CONFIG_ACPI is not set, ++acpi_disabled will always be 1. ++ ++Device Enumeration ++------------------ ++ ++Device descriptions in ACPI should use standard recognized ACPI interfaces. ++These are far simpler than the information provided via Device Tree. Drivers ++should take into account this simplicity and work with sensible defaults. ++ ++On no account should a Device Tree attempt to be replicated in ASL using such ++constructs as Name(KEY0, "Value1") type constructs. Additional driver specific ++data should be represented with the appropriate _DSD (ACPI Section 6.2.5) ++structure. _DSM (ACPI Section 9.14.1) should only be used if _DSD cannot ++represent the data required. ++ ++This data should be rare and not OS specific. For x86 ACPI has taken to ++identifying itself as Windows because it was found that only one path was ++routinely tested. For ARMv8 it would be preferable to have only one well ++tested path. + -+/* Board-specific peripheral configurations */ -+&menet { -+ status = "ok"; ++_DSD covers more than the generic server case and care should be taken not to ++replicate highly specific embedded behaviour from DT into generic servers. ++ ++Common _DSD bindings should be submitted to ASWG to be included in the ++document :- ++ ++http://www.uefi.org/sites/default/files/resources/_DSD-implementation-guide-toplevel.htm ++ ++If these bindings are mirrored from DT care should be taken to ensure they are ++reviewed as DT bindings before submission to limit divergance in bindings. ++ ++Programmable Power Control Resources ++------------------------------------ ++ ++Programmable power control resources include such resources as voltage/current ++providers (regulators) and clock sources. ++ ++For power control of these resources they should be represented with Power ++Resource Objects (ACPI Section 7.1). The ACPI core will then handle correctly ++enabling/disabling of resources as they are needed. ++ ++The ACPI 5.1 specification does not contain any standard binding for these ++objects to enable programmable levels or rates so this should be avoided if ++possible and the resources set to appropriate levels by the firmware. If this is ++not possible then any manipulation should be abstracted in ASL. ++ ++Each device in ACPI has D-states and these can be controlled through ++the optional methods _PS0..._PS3 where _PS0 is full on and _PS3 is full off. ++ ++If either _PS0 or _PS3 is implemented, then the other method must also be ++implemented. ++ ++If a device requires usage or setup of a power resource when on, the ASL ++should organize that it is allocated/enabled using the _PS0 method. ++ ++Resources allocated/enabled in the _PS0 method should be disabled/de-allocated ++in the _PS3 method. ++ ++Such code in _PS? methods will of course be very platform specific but ++should allow the driver to operate the device without special non-standard ++values being read from ASL. Further, abstracting the use of these resources ++allows hardware revisions without requiring updates to the kernel. ++ ++Clocks ++------ ++ ++Like clocks that are part of the power resources there is no standard way ++to represent a clock tree in ACPI 5.1 in a similar manner to how it is ++described in DT. ++ ++Devices affected by this include things like UARTs, SoC driven LCD displays, ++etc. ++ ++The firmware (for example, UEFI) should initialize these clocks to fixed working ++values before the kernel is executed. ++ ++Driver Recommendations ++---------------------- ++ ++DO NOT remove any FDT handling when adding ACPI support for a driver. Different ++systems may use the same device. ++ ++DO try and keep complex sections of ACPI and DT functionality separate. This ++may mean a patch to break out some complex DT to another function before ++the patch to add ACPI. This may happen in other functions but is most likely ++in probe function. This gives a clearer flow of data for reviewing driver ++source. ++ ++probe() :- ++ ++static int device_probe_dt(struct platform_device *pdev) ++{ ++ /* DT specific functionality */ ++ ... ++} ++ ++static int device_probe_acpi(struct platform_device *pdev) ++{ ++ /* ACPI specific functionality */ ++ ... ++} ++ ++static int device_probe(stuct platform_device *pdev) ++{ ++ ... ++ struct device_node node = pdev->dev.of_node; ++ ... ++ ++ if (node) ++ ret = device_probe_dt(pdev); ++ else if (ACPI_HANDLE(&pdev->dev)) ++ ret = device_probe_acpi(pdev); ++ else ++ /* other initialization */ ++ ... ++ /* Continue with any generic probe operations */ ++ ... ++} ++ ++DO keep the MODULE_DEVICE_TABLE entries together in the driver to make it clear ++the different names the driver is probed for, both from DT and from ACPI. ++ ++module device tables :- ++ ++static struct of_device_id virtio_mmio_match[] = { ++ { .compatible = "virtio,mmio", }, ++ { } +}; ++MODULE_DEVICE_TABLE(of, virtio_mmio_match); ++ ++static const struct acpi_device_id virtio_mmio_acpi_match[] = { ++ { "LNRO0005", }, ++ { } ++}; ++MODULE_DEVICE_TABLE(acpi, virtio_mmio_acpi_match); ++ ++ASWG ++---- ++ ++The following areas are not yet well defined for ARM in the current ACPI ++specification and are expected to be worked through in the UEFI ACPI ++Specification Working Group (ASWG) <http://www.uefi.org/workinggroups>. ++Participation in this group is open to all UEFI members. ++ ++ - ACPI based CPU topology ++ - ACPI based Power management ++ - CPU idle control based on PSCI ++ - CPU performance control (CPPC) ++ - ACPI based SMMU ++ - ITS support for GIC in MADT ++ ++No code shall be accepted into the kernel unless it complies with the released ++standards from UEFI ASWG. If there are features missing from ACPI to make it ++function on a platform, ECRs should be submitted to ASWG and go through the ++approval process. diff --git a/Documentation/devicetree/bindings/pci/xgene-pci.txt b/Documentation/devicetree/bindings/pci/xgene-pci.txt new file mode 100644 -index 0000000..e19fdb8 +index 0000000..1070b06 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xgene-pci.txt -@@ -0,0 +1,52 @@ +@@ -0,0 +1,57 @@ +* AppliedMicro X-Gene PCIe interface + +Required properties: @@ -1170,10 +1583,12 @@ index 0000000..e19fdb8 + +Optional properties: +- status: Either "ok" or "disabled". ++- dma-coherent: Present if dma operations are coherent + +Example: + +SoC specific DT Entry: ++ + pcie0: pcie@1f2b0000 { + status = "disabled"; + device_type = "pci"; @@ -1182,178 +1597,256 @@ index 0000000..e19fdb8 + #size-cells = <2>; + #address-cells = <3>; + reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ -+ 0xe0 0xd0000000 0x0 0x00200000>; /* PCI config space */ ++ 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ + reg-names = "csr", "cfg"; -+ ranges = <0x01000000 0x00 0x00000000 0xe0 0x00000000 0x00 0x00010000 /* io */ -+ 0x02000000 0x00 0x10000000 0xe0 0x10000000 0x00 0x80000000>; /* mem */ -+ dma-ranges = <0x42000000 0x40 0x00000000 0x40 0x00000000 0x40 0x00000000>; ++ ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ ++ 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */ ++ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 ++ 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1 + 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1 + 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1 + 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; ++ dma-coherent; + clocks = <&pcie0clk 0>; + }; + ++ +Board specific DT Entry: + &pcie0 { + status = "ok"; + }; +diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt +index 10d51c2..9464c6d 100644 +--- a/Documentation/kernel-parameters.txt ++++ b/Documentation/kernel-parameters.txt +@@ -165,7 +165,7 @@ multipliers 'Kilo', 'Mega', and 'Giga', equalling 2^10, 2^20, and 2^30 + bytes respectively. Such letter suffixes can also be entirely omitted. + + +- acpi= [HW,ACPI,X86] ++ acpi= [HW,ACPI,X86,ARM] + Advanced Configuration and Power Interface + Format: { force | off | strict | noirq | rsdt } + force -- enable ACPI if default was off +@@ -175,6 +175,7 @@ bytes respectively. Such letter suffixes can also be entirely omitted. + strictly ACPI specification compliant. + rsdt -- prefer RSDT over (default) XSDT + copy_dsdt -- copy DSDT to memory ++ For ARM64, ONLY "acpi=off" is available. + + See also Documentation/power/runtime_pm.txt, pci=noacpi + diff --git a/MAINTAINERS b/MAINTAINERS -index 86efa7e..14a3ef1 100644 +index 3705430..f6b49e4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -699,6 +699,14 @@ S: Maintained - F: drivers/net/appletalk/ - F: net/appletalk/ - -+APPLIED MICRO (APM) X-GENE SOC ETHERNET DRIVER -+M: Iyappan Subramanian <isubramanian@apm.com> -+M: Keyur Chudgar <kchudgar@apm.com> -+M: Ravi Patel <rapatel@apm.com> -+S: Supported -+F: drivers/net/ethernet/apm/xgene/ -+F: Documentation/devicetree/bindings/net/apm-xgene-enet.txt -+ - APTINA CAMERA SENSOR PLL - M: Laurent Pinchart <Laurent.pinchart@ideasonboard.com> - L: linux-media@vger.kernel.org -@@ -6851,6 +6859,13 @@ S: Maintained - F: Documentation/devicetree/bindings/pci/host-generic-pci.txt - F: drivers/pci/host/pci-host-generic.c +@@ -6940,6 +6940,14 @@ L: linux-pci@vger.kernel.org + S: Maintained + F: drivers/pci/host/*spear* +PCI DRIVER FOR APPLIEDMICRO XGENE +M: Tanmay Inamdar <tinamdar@apm.com> +L: linux-pci@vger.kernel.org +L: linux-arm-kernel@lists.infradead.org +S: Maintained ++F: Documentation/devicetree/bindings/pci/xgene-pci.txt +F: drivers/pci/host/pci-xgene.c + PCMCIA SUBSYSTEM P: Linux PCMCIA Team L: linux-pcmcia@lists.infradead.org -diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h -index 193ceaf..d6d5227 100644 ---- a/arch/arm/include/asm/kvm_host.h -+++ b/arch/arm/include/asm/kvm_host.h -@@ -225,6 +225,11 @@ static inline int kvm_arch_dev_ioctl_check_extension(long ext) - return 0; - } +diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h +index 3d23418..22b7529 100644 +--- a/arch/arm/include/asm/io.h ++++ b/arch/arm/include/asm/io.h +@@ -178,6 +178,7 @@ static inline void __iomem *__typesafe_io(unsigned long addr) + + /* PCI fixed i/o mapping */ + #define PCI_IO_VIRT_BASE 0xfee00000 ++#define PCI_IOBASE PCI_IO_VIRT_BASE + + #if defined(CONFIG_PCI) + void pci_ioremap_set_mem_type(int mem_type); +diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h +index 5cc0b0f..03a08bb 100644 +--- a/arch/arm/include/asm/kvm_mmu.h ++++ b/arch/arm/include/asm/kvm_mmu.h +@@ -21,6 +21,7 @@ + + #include <asm/memory.h> + #include <asm/page.h> ++#include <asm/kvm_arm.h> -+static inline void vgic_arch_setup(const struct vgic_params *vgic) + /* + * We directly use the kernel VA for the HYP, as we can directly share +@@ -178,6 +179,18 @@ static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva, + + void stage2_flush_vm(struct kvm *kvm); + ++static inline int kvm_get_phys_addr_shift(void) ++{ ++ return KVM_PHYS_SHIFT; ++} ++ ++ ++static inline u32 get_vttbr_baddr_mask(void) +{ -+ BUG_ON(vgic->type != VGIC_V2); ++ return VTTBR_BADDR_MASK; +} + - int kvm_perf_init(void); - int kvm_perf_teardown(void); - -diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c -index 85598b5..713e807 100644 ---- a/arch/arm/kernel/asm-offsets.c -+++ b/arch/arm/kernel/asm-offsets.c -@@ -182,13 +182,13 @@ int main(void) - DEFINE(VCPU_HYP_PC, offsetof(struct kvm_vcpu, arch.fault.hyp_pc)); - #ifdef CONFIG_KVM_ARM_VGIC - DEFINE(VCPU_VGIC_CPU, offsetof(struct kvm_vcpu, arch.vgic_cpu)); -- DEFINE(VGIC_CPU_HCR, offsetof(struct vgic_cpu, vgic_hcr)); -- DEFINE(VGIC_CPU_VMCR, offsetof(struct vgic_cpu, vgic_vmcr)); -- DEFINE(VGIC_CPU_MISR, offsetof(struct vgic_cpu, vgic_misr)); -- DEFINE(VGIC_CPU_EISR, offsetof(struct vgic_cpu, vgic_eisr)); -- DEFINE(VGIC_CPU_ELRSR, offsetof(struct vgic_cpu, vgic_elrsr)); -- DEFINE(VGIC_CPU_APR, offsetof(struct vgic_cpu, vgic_apr)); -- DEFINE(VGIC_CPU_LR, offsetof(struct vgic_cpu, vgic_lr)); -+ DEFINE(VGIC_V2_CPU_HCR, offsetof(struct vgic_cpu, vgic_v2.vgic_hcr)); -+ DEFINE(VGIC_V2_CPU_VMCR, offsetof(struct vgic_cpu, vgic_v2.vgic_vmcr)); -+ DEFINE(VGIC_V2_CPU_MISR, offsetof(struct vgic_cpu, vgic_v2.vgic_misr)); -+ DEFINE(VGIC_V2_CPU_EISR, offsetof(struct vgic_cpu, vgic_v2.vgic_eisr)); -+ DEFINE(VGIC_V2_CPU_ELRSR, offsetof(struct vgic_cpu, vgic_v2.vgic_elrsr)); -+ DEFINE(VGIC_V2_CPU_APR, offsetof(struct vgic_cpu, vgic_v2.vgic_apr)); -+ DEFINE(VGIC_V2_CPU_LR, offsetof(struct vgic_cpu, vgic_v2.vgic_lr)); - DEFINE(VGIC_CPU_NR_LR, offsetof(struct vgic_cpu, nr_lr)); - #ifdef CONFIG_KVM_ARM_TIMER - DEFINE(VCPU_TIMER_CNTV_CTL, offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_ctl)); -diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile -index 789bca9..f7057ed 100644 ---- a/arch/arm/kvm/Makefile -+++ b/arch/arm/kvm/Makefile -@@ -21,4 +21,5 @@ obj-y += kvm-arm.o init.o interrupts.o - obj-y += arm.o handle_exit.o guest.o mmu.o emulate.o reset.o - obj-y += coproc.o coproc_a15.o coproc_a7.o mmio.o psci.o perf.o - obj-$(CONFIG_KVM_ARM_VGIC) += $(KVM)/arm/vgic.o -+obj-$(CONFIG_KVM_ARM_VGIC) += $(KVM)/arm/vgic-v2.o - obj-$(CONFIG_KVM_ARM_TIMER) += $(KVM)/arm/arch_timer.o -diff --git a/arch/arm/kvm/interrupts_head.S b/arch/arm/kvm/interrupts_head.S -index 76af9302..e4eaf30 100644 ---- a/arch/arm/kvm/interrupts_head.S -+++ b/arch/arm/kvm/interrupts_head.S -@@ -421,14 +421,14 @@ vcpu .req r0 @ vcpu pointer always in r0 - ldr r9, [r2, #GICH_ELRSR1] - ldr r10, [r2, #GICH_APR] - -- str r3, [r11, #VGIC_CPU_HCR] -- str r4, [r11, #VGIC_CPU_VMCR] -- str r5, [r11, #VGIC_CPU_MISR] -- str r6, [r11, #VGIC_CPU_EISR] -- str r7, [r11, #(VGIC_CPU_EISR + 4)] -- str r8, [r11, #VGIC_CPU_ELRSR] -- str r9, [r11, #(VGIC_CPU_ELRSR + 4)] -- str r10, [r11, #VGIC_CPU_APR] -+ str r3, [r11, #VGIC_V2_CPU_HCR] -+ str r4, [r11, #VGIC_V2_CPU_VMCR] -+ str r5, [r11, #VGIC_V2_CPU_MISR] -+ str r6, [r11, #VGIC_V2_CPU_EISR] -+ str r7, [r11, #(VGIC_V2_CPU_EISR + 4)] -+ str r8, [r11, #VGIC_V2_CPU_ELRSR] -+ str r9, [r11, #(VGIC_V2_CPU_ELRSR + 4)] -+ str r10, [r11, #VGIC_V2_CPU_APR] - - /* Clear GICH_HCR */ - mov r5, #0 -@@ -436,7 +436,7 @@ vcpu .req r0 @ vcpu pointer always in r0 - - /* Save list registers */ - add r2, r2, #GICH_LR0 -- add r3, r11, #VGIC_CPU_LR -+ add r3, r11, #VGIC_V2_CPU_LR - ldr r4, [r11, #VGIC_CPU_NR_LR] - 1: ldr r6, [r2], #4 - str r6, [r3], #4 -@@ -463,9 +463,9 @@ vcpu .req r0 @ vcpu pointer always in r0 - add r11, vcpu, #VCPU_VGIC_CPU - - /* We only restore a minimal set of registers */ -- ldr r3, [r11, #VGIC_CPU_HCR] -- ldr r4, [r11, #VGIC_CPU_VMCR] -- ldr r8, [r11, #VGIC_CPU_APR] -+ ldr r3, [r11, #VGIC_V2_CPU_HCR] -+ ldr r4, [r11, #VGIC_V2_CPU_VMCR] -+ ldr r8, [r11, #VGIC_V2_CPU_APR] - - str r3, [r2, #GICH_HCR] - str r4, [r2, #GICH_VMCR] -@@ -473,7 +473,7 @@ vcpu .req r0 @ vcpu pointer always in r0 - - /* Restore list registers */ - add r2, r2, #GICH_LR0 -- add r3, r11, #VGIC_CPU_LR -+ add r3, r11, #VGIC_V2_CPU_LR - ldr r4, [r11, #VGIC_CPU_NR_LR] - 1: ldr r6, [r3], #4 - str r6, [r2], #4 ++ + #endif /* !__ASSEMBLY__ */ + + #endif /* __ARM_KVM_MMU_H__ */ +diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c +index a99e0cd..d0fca8f 100644 +--- a/arch/arm/kvm/arm.c ++++ b/arch/arm/kvm/arm.c +@@ -37,6 +37,7 @@ + #include <asm/mman.h> + #include <asm/tlbflush.h> + #include <asm/cacheflush.h> ++#include <asm/cputype.h> + #include <asm/virt.h> + #include <asm/kvm_arm.h> + #include <asm/kvm_asm.h> +@@ -61,6 +62,12 @@ static atomic64_t kvm_vmid_gen = ATOMIC64_INIT(1); + static u8 kvm_next_vmid; + static DEFINE_SPINLOCK(kvm_vmid_lock); + ++#ifdef CONFIG_ARM64 ++static u64 vttbr_baddr_mask; ++#else ++static u32 vttbr_baddr_mask; ++#endif ++ + static bool vgic_present; + + static void kvm_arm_set_running_vcpu(struct kvm_vcpu *vcpu) +@@ -429,8 +436,14 @@ static void update_vttbr(struct kvm *kvm) + /* update vttbr to be used with the new vmid */ + pgd_phys = virt_to_phys(kvm->arch.pgd); + vmid = ((u64)(kvm->arch.vmid) << VTTBR_VMID_SHIFT) & VTTBR_VMID_MASK; +- kvm->arch.vttbr = pgd_phys & VTTBR_BADDR_MASK; +- kvm->arch.vttbr |= vmid; ++ ++ /* ++ * If the VTTBR isn't aligned there is something wrong with the system ++ * or kernel. ++ */ ++ BUG_ON(pgd_phys & ~vttbr_baddr_mask); ++ ++ kvm->arch.vttbr = pgd_phys | vmid; + + spin_unlock(&kvm_vmid_lock); + } +@@ -1015,6 +1028,12 @@ int kvm_arch_init(void *opaque) + } + } + ++ vttbr_baddr_mask = get_vttbr_baddr_mask(); ++ if (vttbr_baddr_mask == ~0) { ++ kvm_err("Cannot set vttbr_baddr_mask\n"); ++ return -EINVAL; ++ } ++ + cpu_notifier_register_begin(); + + err = init_hyp_mode(); +diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c +index 05e1f73..c186a17 100644 +--- a/arch/arm/mach-integrator/pci_v3.c ++++ b/arch/arm/mach-integrator/pci_v3.c +@@ -660,6 +660,7 @@ static void __init pci_v3_preinit(void) + { + unsigned long flags; + unsigned int temp; ++ phys_addr_t io_address = pci_pio_to_address(io_mem.start); + + pcibios_min_mem = 0x00100000; + +@@ -701,7 +702,7 @@ static void __init pci_v3_preinit(void) + /* + * Setup window 2 - PCI IO + */ +- v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(io_mem.start) | ++ v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(io_address) | + V3_LB_BASE_ENABLE); + v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0)); + +@@ -742,6 +743,7 @@ static void __init pci_v3_preinit(void) + static void __init pci_v3_postinit(void) + { + unsigned int pci_cmd; ++ phys_addr_t io_address = pci_pio_to_address(io_mem.start); + + pci_cmd = PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE; +@@ -758,7 +760,7 @@ static void __init pci_v3_postinit(void) + "interrupt: %d\n", ret); + #endif + +- register_isa_ports(non_mem.start, io_mem.start, 0); ++ register_isa_ports(non_mem.start, io_address, 0); + } + + /* +@@ -867,33 +869,32 @@ static int __init pci_v3_probe(struct platform_device *pdev) + + for_each_of_pci_range(&parser, &range) { + if (!range.flags) { +- of_pci_range_to_resource(&range, np, &conf_mem); ++ ret = of_pci_range_to_resource(&range, np, &conf_mem); + conf_mem.name = "PCIv3 config"; + } + if (range.flags & IORESOURCE_IO) { +- of_pci_range_to_resource(&range, np, &io_mem); ++ ret = of_pci_range_to_resource(&range, np, &io_mem); + io_mem.name = "PCIv3 I/O"; + } + if ((range.flags & IORESOURCE_MEM) && + !(range.flags & IORESOURCE_PREFETCH)) { + non_mem_pci = range.pci_addr; + non_mem_pci_sz = range.size; +- of_pci_range_to_resource(&range, np, &non_mem); ++ ret = of_pci_range_to_resource(&range, np, &non_mem); + non_mem.name = "PCIv3 non-prefetched mem"; + } + if ((range.flags & IORESOURCE_MEM) && + (range.flags & IORESOURCE_PREFETCH)) { + pre_mem_pci = range.pci_addr; + pre_mem_pci_sz = range.size; +- of_pci_range_to_resource(&range, np, &pre_mem); ++ ret = of_pci_range_to_resource(&range, np, &pre_mem); + pre_mem.name = "PCIv3 prefetched mem"; + } +- } + +- if (!conf_mem.start || !io_mem.start || +- !non_mem.start || !pre_mem.start) { +- dev_err(&pdev->dev, "missing ranges in device node\n"); +- return -EINVAL; ++ if (ret < 0) { ++ dev_err(&pdev->dev, "missing ranges in device node\n"); ++ return ret; ++ } + } + + pci_v3.map_irq = of_irq_parse_and_map_pci; diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig -index 839f48c..23871dd 100644 +index fd4e81a..e57b91a 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig -@@ -11,6 +11,7 @@ config ARM64 - select ARM_AMBA - select ARM_ARCH_TIMER - select ARM_GIC -+ select ARM_GIC_V3 - select BUILDTIME_EXTABLE_SORT - select CLONE_BACKWARDS - select COMMON_CLK -@@ -76,7 +77,7 @@ config MMU +@@ -1,5 +1,6 @@ + config ARM64 + def_bool y ++ select ACPI_REDUCED_HARDWARE_ONLY if ACPI + select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE + select ARCH_HAS_SG_CHAIN + select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST +@@ -81,7 +82,7 @@ config MMU def_bool y config NO_IOPORT_MAP @@ -1362,20 +1855,23 @@ index 839f48c..23871dd 100644 config STACKTRACE_SUPPORT def_bool y -@@ -151,6 +152,23 @@ menu "Bus support" +@@ -156,6 +157,26 @@ menu "Bus support" config ARM_AMBA bool +config PCI + bool "PCI support" + help -+ This feature enables support for PCIe bus system. If you say Y ++ This feature enables support for PCI bus system. If you say Y + here, the kernel will include drivers and infrastructure code -+ to support PCIe bus devices. ++ to support PCI bus devices. + +config PCI_DOMAINS + def_bool PCI + ++config PCI_DOMAINS_GENERIC ++ def_bool PCI ++ +config PCI_SYSCALL + def_bool PCI + @@ -1386,19 +1882,45 @@ index 839f48c..23871dd 100644 endmenu menu "Kernel Features" +@@ -235,6 +256,9 @@ config SMP + + If you don't know what to do here, say N. + ++config ARM_PARKING_PROTOCOL ++ def_bool y if SMP ++ + config SCHED_MC + bool "Multi-core scheduler support" + depends on SMP +@@ -421,6 +445,8 @@ source "drivers/Kconfig" + + source "drivers/firmware/Kconfig" + ++source "drivers/acpi/Kconfig" ++ + source "fs/Kconfig" + + source "arch/arm64/kvm/Kconfig" +diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile +index 2df5e5d..bddd4e3 100644 +--- a/arch/arm64/Makefile ++++ b/arch/arm64/Makefile +@@ -50,6 +50,7 @@ core-y += arch/arm64/kernel/ arch/arm64/mm/ + core-$(CONFIG_KVM) += arch/arm64/kvm/ + core-$(CONFIG_XEN) += arch/arm64/xen/ + core-$(CONFIG_CRYPTO) += arch/arm64/crypto/ ++drivers-$(CONFIG_PCI) += arch/arm64/pci/ + libs-y := arch/arm64/lib/ $(libs-y) + libs-y += $(LIBGCC) + libs-$(CONFIG_EFI_STUB) += drivers/firmware/efi/libstub/ diff --git a/arch/arm64/boot/dts/apm-mustang.dts b/arch/arm64/boot/dts/apm-mustang.dts -index 6541962..0cb67fc 100644 +index b2f5622..f649000 100644 --- a/arch/arm64/boot/dts/apm-mustang.dts +++ b/arch/arm64/boot/dts/apm-mustang.dts -@@ -28,3 +28,15 @@ - &serial0 { - status = "ok"; +@@ -25,6 +25,14 @@ + }; }; -+ -+&menet { -+ status = "ok"; -+}; -+ + +&pcie0clk { + status = "ok"; +}; @@ -1406,105 +1928,15 @@ index 6541962..0cb67fc 100644 +&pcie0 { + status = "ok"; +}; ++ + &serial0 { + status = "ok"; + }; diff --git a/arch/arm64/boot/dts/apm-storm.dtsi b/arch/arm64/boot/dts/apm-storm.dtsi -index 40aa96c..fb2ee54 100644 +index c0aceef..403197a 100644 --- a/arch/arm64/boot/dts/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm-storm.dtsi -@@ -24,56 +24,56 @@ - compatible = "apm,potenza", "arm,armv8"; - reg = <0x0 0x000>; - enable-method = "spin-table"; -- cpu-release-addr = <0x1 0x0000fff8>; -+ cpu-release-addr = <0x40 0x0000f000>; - }; - cpu@001 { - device_type = "cpu"; - compatible = "apm,potenza", "arm,armv8"; - reg = <0x0 0x001>; - enable-method = "spin-table"; -- cpu-release-addr = <0x1 0x0000fff8>; -+ cpu-release-addr = <0x40 0x0000f000>; - }; - cpu@100 { - device_type = "cpu"; - compatible = "apm,potenza", "arm,armv8"; - reg = <0x0 0x100>; - enable-method = "spin-table"; -- cpu-release-addr = <0x1 0x0000fff8>; -+ cpu-release-addr = <0x40 0x0000f000>; - }; - cpu@101 { - device_type = "cpu"; - compatible = "apm,potenza", "arm,armv8"; - reg = <0x0 0x101>; - enable-method = "spin-table"; -- cpu-release-addr = <0x1 0x0000fff8>; -+ cpu-release-addr = <0x40 0x0000f000>; - }; - cpu@200 { - device_type = "cpu"; - compatible = "apm,potenza", "arm,armv8"; - reg = <0x0 0x200>; - enable-method = "spin-table"; -- cpu-release-addr = <0x1 0x0000fff8>; -+ cpu-release-addr = <0x40 0x0000f000>; - }; - cpu@201 { - device_type = "cpu"; - compatible = "apm,potenza", "arm,armv8"; - reg = <0x0 0x201>; - enable-method = "spin-table"; -- cpu-release-addr = <0x1 0x0000fff8>; -+ cpu-release-addr = <0x40 0x0000f000>; - }; - cpu@300 { - device_type = "cpu"; - compatible = "apm,potenza", "arm,armv8"; - reg = <0x0 0x300>; - enable-method = "spin-table"; -- cpu-release-addr = <0x1 0x0000fff8>; -+ cpu-release-addr = <0x40 0x0000f000>; - }; - cpu@301 { - device_type = "cpu"; - compatible = "apm,potenza", "arm,armv8"; - reg = <0x0 0x301>; - enable-method = "spin-table"; -- cpu-release-addr = <0x1 0x0000fff8>; -+ cpu-release-addr = <0x40 0x0000f000>; - }; - }; - -@@ -97,6 +97,11 @@ - clock-frequency = <50000000>; - }; - -+ pmu { -+ compatible = "arm,armv8-pmuv3"; -+ interrupts = <1 12 0xff04>; -+ }; -+ - soc { - compatible = "simple-bus"; - #address-cells = <2>; -@@ -167,14 +172,13 @@ - clock-output-names = "ethclk"; - }; - -- eth8clk: eth8clk { -+ menetclk: menetclk { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <ðclk 0>; -- clock-names = "eth8clk"; - reg = <0x0 0x1702C000 0x0 0x1000>; - reg-names = "csr-reg"; -- clock-output-names = "eth8clk"; -+ clock-output-names = "menetclk"; - }; - - sataphy1clk: sataphy1clk@1f21c000 { -@@ -270,6 +274,161 @@ +@@ -269,6 +269,171 @@ enable-mask = <0x2>; clock-output-names = "rtcclk"; }; @@ -1568,16 +2000,18 @@ index 40aa96c..fb2ee54 100644 + #size-cells = <2>; + #address-cells = <3>; + reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ -+ 0xe0 0xd0000000 0x0 0x00200000>; /* PCI config space */ ++ 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ + reg-names = "csr", "cfg"; -+ ranges = <0x01000000 0x00 0x00000000 0xe0 0x00000000 0x00 0x00010000 /* io */ -+ 0x02000000 0x00 0x10000000 0xe0 0x10000000 0x00 0x80000000>; /* mem */ -+ dma-ranges = <0x42000000 0x40 0x00000000 0x40 0x00000000 0x40 0x00000000>; ++ ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ ++ 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */ ++ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 ++ 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1 + 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1 + 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1 + 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; ++ dma-coherent; + clocks = <&pcie0clk 0>; + }; + @@ -1589,16 +2023,18 @@ index 40aa96c..fb2ee54 100644 + #size-cells = <2>; + #address-cells = <3>; + reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */ -+ 0xd0 0xd0000000 0x0 0x00200000>; /* PCI config space */ ++ 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */ + reg-names = "csr", "cfg"; -+ ranges = <0x01000000 0x0 0x00000000 0xd0 0x00000000 0x00 0x00010000 /* io */ -+ 0x02000000 0x0 0x10000000 0xd0 0x10000000 0x00 0x80000000>; /* mem */ -+ dma-ranges = <0x42000000 0x40 0x00000000 0x40 0x00000000 0x40 0x00000000>; ++ ranges = <0x01000000 0x0 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */ ++ 0x02000000 0x0 0x80000000 0xd1 0x80000000 0x00 0x80000000>; /* mem */ ++ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 ++ 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1 + 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1 + 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1 + 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>; ++ dma-coherent; + clocks = <&pcie1clk 0>; + }; + @@ -1610,16 +2046,18 @@ index 40aa96c..fb2ee54 100644 + #size-cells = <2>; + #address-cells = <3>; + reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */ -+ 0x90 0xd0000000 0x0 0x00200000>; /* PCI config space */ ++ 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */ + reg-names = "csr", "cfg"; -+ ranges = <0x01000000 0x0 0x00000000 0x90 0x00000000 0x0 0x00010000 /* io */ -+ 0x02000000 0x0 0x10000000 0x90 0x10000000 0x0 0x80000000>; /* mem */ -+ dma-ranges = <0x42000000 0x40 0x00000000 0x40 0x00000000 0x40 0x00000000>; ++ ranges = <0x01000000 0x0 0x00000000 0x90 0x10000000 0x0 0x00010000 /* io */ ++ 0x02000000 0x0 0x80000000 0x91 0x80000000 0x0 0x80000000>; /* mem */ ++ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 ++ 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1 + 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1 + 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1 + 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>; ++ dma-coherent; + clocks = <&pcie2clk 0>; + }; + @@ -1631,16 +2069,18 @@ index 40aa96c..fb2ee54 100644 + #size-cells = <2>; + #address-cells = <3>; + reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */ -+ 0xa0 0xd0000000 0x0 0x00200000>; /* PCI config space */ ++ 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */ + reg-names = "csr", "cfg"; -+ ranges = <0x01000000 0x0 0x00000000 0xa0 0x00000000 0x0 0x00010000 /* io */ -+ 0x02000000 0x0 0x10000000 0xa0 0x10000000 0x0 0x80000000>; /* mem */ -+ dma-ranges = <0x42000000 0x40 0x00000000 0x40 0x00000000 0x40 0x00000000>; ++ ranges = <0x01000000 0x0 0x00000000 0xa0 0x10000000 0x0 0x00010000 /* io */ ++ 0x02000000 0x0 0x80000000 0xa1 0x80000000 0x0 0x80000000>; /* mem */ ++ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 ++ 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1 + 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1 + 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1 + 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>; ++ dma-coherent; + clocks = <&pcie3clk 0>; + }; + @@ -1654,58 +2094,20 @@ index 40aa96c..fb2ee54 100644 + reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */ + 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */ + reg-names = "csr", "cfg"; -+ ranges = <0x01000000 0x0 0x00000000 0xc0 0x00000000 0x0 0x00010000 /* io */ -+ 0x02000000 0x0 0x10000000 0xc0 0x10000000 0x0 0x80000000>; /* mem */ -+ dma-ranges = <0x42000000 0x40 0x00000000 0x40 0x00000000 0x40 0x00000000>; ++ ranges = <0x01000000 0x0 0x00000000 0xc0 0x10000000 0x0 0x00010000 /* io */ ++ 0x02000000 0x0 0x80000000 0xc1 0x80000000 0x0 0x80000000>; /* mem */ ++ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 ++ 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1 + 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1 + 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1 + 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>; ++ dma-coherent; + clocks = <&pcie4clk 0>; }; serial0: serial@1c020000 { -@@ -278,7 +437,7 @@ - compatible = "ns16550a"; - reg = <0 0x1c020000 0x0 0x1000>; - reg-shift = <2>; -- clock-frequency = <10000000>; /* Updated by bootloader */ -+ clock-frequency = <50000000>; /* Updated by bootloader */ - interrupt-parent = <&gic>; - interrupts = <0x0 0x4c 0x4>; - }; -@@ -397,5 +556,30 @@ - #clock-cells = <1>; - clocks = <&rtcclk 0>; - }; -+ -+ menet: ethernet@17020000 { -+ compatible = "apm,xgene-enet"; -+ status = "disabled"; -+ reg = <0x0 0x17020000 0x0 0xd100>, -+ <0x0 0X17030000 0x0 0X400>, -+ <0x0 0X10000000 0x0 0X200>; -+ reg-names = "enet_csr", "ring_csr", "ring_cmd"; -+ interrupts = <0x0 0x3c 0x4>; -+ dma-coherent; -+ clocks = <&menetclk 0>; -+ local-mac-address = [00 00 00 00 00 00]; -+ phy-connection-type = "rgmii"; -+ phy-handle = <&menetphy>; -+ mdio { -+ compatible = "apm,xgene-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ menetphy: menetphy@3 { -+ compatible = "ethernet-phy-id001c.c915"; -+ reg = <0x3>; -+ }; -+ -+ }; -+ }; - }; - }; diff --git a/arch/arm64/include/asm/Kbuild b/arch/arm64/include/asm/Kbuild index 0b3fcf8..07cb417 100644 --- a/arch/arm64/include/asm/Kbuild @@ -1718,6 +2120,147 @@ index 0b3fcf8..07cb417 100644 generic-y += poll.h generic-y += preempt.h generic-y += resource.h +diff --git a/arch/arm64/include/asm/acenv.h b/arch/arm64/include/asm/acenv.h +new file mode 100644 +index 0000000..b49166f +--- /dev/null ++++ b/arch/arm64/include/asm/acenv.h +@@ -0,0 +1,18 @@ ++/* ++ * ARM64 specific ACPICA environments and implementation ++ * ++ * Copyright (C) 2014, Linaro Ltd. ++ * Author: Hanjun Guo <hanjun.guo@linaro.org> ++ * Author: Graeme Gregory <graeme.gregory@linaro.org> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _ASM_ACENV_H ++#define _ASM_ACENV_H ++ ++/* It is required unconditionally by ACPI core, update it when needed. */ ++ ++#endif /* _ASM_ACENV_H */ +diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h +new file mode 100644 +index 0000000..7f6cd91 +--- /dev/null ++++ b/arch/arm64/include/asm/acpi.h +@@ -0,0 +1,99 @@ ++/* ++ * Copyright (C) 2013-2014, Linaro Ltd. ++ * Author: Al Stone <al.stone@linaro.org> ++ * Author: Graeme Gregory <graeme.gregory@linaro.org> ++ * Author: Hanjun Guo <hanjun.guo@linaro.org> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation; ++ */ ++ ++#ifndef _ASM_ACPI_H ++#define _ASM_ACPI_H ++ ++#include <asm/smp_plat.h> ++ ++/* Basic configuration for ACPI */ ++#ifdef CONFIG_ACPI ++#define acpi_strict 1 /* No out-of-spec workarounds on ARM64 */ ++extern int acpi_disabled; ++extern int acpi_noirq; ++extern int acpi_pci_disabled; ++ ++/* 1 to indicate PSCI 0.2+ is implemented */ ++static inline bool acpi_psci_present(void) ++{ ++ return acpi_gbl_FADT.arm_boot_flags & ACPI_FADT_PSCI_COMPLIANT; ++} ++ ++/* 1 to indicate HVC must be used instead of SMC as the PSCI conduit */ ++static inline bool acpi_psci_use_hvc(void) ++{ ++ return acpi_gbl_FADT.arm_boot_flags & ACPI_FADT_PSCI_USE_HVC; ++} ++ ++static inline void disable_acpi(void) ++{ ++ acpi_disabled = 1; ++ acpi_pci_disabled = 1; ++ acpi_noirq = 1; ++} ++ ++/* MPIDR value provided in GICC structure is 64 bits, but ++ * the acpi processor driver use the 32 bits cpu hardware ++ * ID (apic_id on intel platform) everywhere, it is pretty ++ * hard to modify the acpi processor driver to accept the ++ * 64 bits MPIDR value, at the same time, only 32 bits of ++ * the MPIDR is used in the 64 bits MPIDR, just pack the ++ * Affx fields into a single 32 bit identifier to accommodate ++ * the acpi processor drivers. ++ */ ++static inline u32 pack_mpidr_into_32_bits(u64 mpidr) ++{ ++ /* ++ * Bits [0:7] Aff0; ++ * Bits [8:15] Aff1; ++ * Bits [16:23] Aff2; ++ * Bits [32:39] Aff3; ++ */ ++ return (u32) ((mpidr & 0xff00000000) >> 8) | mpidr; ++} ++ ++/* ++ * The ACPI processor driver for ACPI core code needs this macro ++ * to find out this cpu was already mapped (mapping from CPU hardware ++ * ID to CPU logical ID) or not. ++ * ++ * cpu_logical_map(cpu) is the mapping of MPIDR and the logical cpu, ++ * and MPIDR is the cpu hardware ID we needed to pack. ++ */ ++#define cpu_physical_id(cpu) pack_mpidr_into_32_bits(cpu_logical_map(cpu)) ++ ++/* ++ * It's used from ACPI core in kdump to boot UP system with SMP kernel, ++ * with this check the ACPI core will not override the CPU index ++ * obtained from GICC with 0 and not print some error message as well. ++ * Since MADT must provide at least one GICC structure for GIC ++ * initialization, CPU will be always available in MADT on ARM64. ++ */ ++static inline bool acpi_has_cpu_in_madt(void) ++{ ++ return true; ++} ++ ++static inline void arch_fix_phys_package_id(int num, u32 slot) { } ++void __init acpi_smp_init_cpus(void); ++ ++extern int acpi_get_cpu_parked_address(int cpu, u64 *addr); ++ ++#else ++ ++static inline bool acpi_psci_present(void) { return false; } ++static inline bool acpi_psci_use_hvc(void) { return false; } ++static inline void acpi_smp_init_cpus(void) { } ++static inline int acpi_get_cpu_parked_address(int cpu, u64 *addr) { return -EOPNOTSUPP; } ++ ++#endif /* CONFIG_ACPI */ ++ ++#endif /*_ASM_ACPI_H*/ +diff --git a/arch/arm64/include/asm/cpu_ops.h b/arch/arm64/include/asm/cpu_ops.h +index d7b4b38..d149580 100644 +--- a/arch/arm64/include/asm/cpu_ops.h ++++ b/arch/arm64/include/asm/cpu_ops.h +@@ -61,6 +61,7 @@ struct cpu_operations { + }; + + extern const struct cpu_operations *cpu_ops[NR_CPUS]; ++const struct cpu_operations *cpu_get_ops(const char *name); + extern int __init cpu_read_ops(struct device_node *dn, int cpu); + extern void __init cpu_read_bootcpu_ops(void); + diff --git a/arch/arm64/include/asm/elf.h b/arch/arm64/include/asm/elf.h index 01d3aab..8186df6 100644 --- a/arch/arm64/include/asm/elf.h @@ -1733,7 +2276,7 @@ index 01d3aab..8186df6 100644 #define CORE_DUMP_USE_REGSET #define ELF_EXEC_PAGESIZE PAGE_SIZE diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h -index e0ecdcf..dc34039 100644 +index e0ecdcf..f998d90 100644 --- a/arch/arm64/include/asm/io.h +++ b/arch/arm64/include/asm/io.h @@ -121,7 +121,8 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) @@ -1742,130 +2285,162 @@ index e0ecdcf..dc34039 100644 */ -#define IO_SPACE_LIMIT 0xffff +#define arch_has_dev_port() (1) -+#define IO_SPACE_LIMIT 0x1ffffff ++#define IO_SPACE_LIMIT (SZ_32M - 1) #define PCI_IOBASE ((void __iomem *)(MODULES_VADDR - SZ_32M)) static inline u8 inb(unsigned long addr) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h -index 3d69030..cc83520 100644 +index cc83520..ff4a4fa 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h -@@ -76,9 +76,10 @@ +@@ -95,7 +95,6 @@ + /* TCR_EL2 Registers bits */ + #define TCR_EL2_TBI (1 << 20) + #define TCR_EL2_PS (7 << 16) +-#define TCR_EL2_PS_40B (2 << 16) + #define TCR_EL2_TG0 (1 << 14) + #define TCR_EL2_SH0 (3 << 12) + #define TCR_EL2_ORGN0 (3 << 10) +@@ -104,8 +103,6 @@ + #define TCR_EL2_MASK (TCR_EL2_TG0 | TCR_EL2_SH0 | \ + TCR_EL2_ORGN0 | TCR_EL2_IRGN0 | TCR_EL2_T0SZ) + +-#define TCR_EL2_FLAGS (TCR_EL2_PS_40B) +- + /* VTCR_EL2 Registers bits */ + #define VTCR_EL2_PS_MASK (7 << 16) + #define VTCR_EL2_TG0_MASK (1 << 14) +@@ -120,36 +117,28 @@ + #define VTCR_EL2_SL0_MASK (3 << 6) + #define VTCR_EL2_SL0_LVL1 (1 << 6) + #define VTCR_EL2_T0SZ_MASK 0x3f +-#define VTCR_EL2_T0SZ_40B 24 ++#define VTCR_EL2_T0SZ(bits) (64 - (bits)) + + #ifdef CONFIG_ARM64_64K_PAGES + /* + * Stage2 translation configuration: +- * 40bits output (PS = 2) +- * 40bits input (T0SZ = 24) + * 64kB pages (TG0 = 1) + * 2 level page tables (SL = 1) */ - #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \ - HCR_TVM | HCR_BSU_IS | HCR_FB | HCR_TAC | \ -- HCR_AMO | HCR_IMO | HCR_FMO | \ -- HCR_SWIO | HCR_TIDCP | HCR_RW) -+ HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW) - #define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF) -+#define HCR_INT_OVERRIDE (HCR_FMO | HCR_IMO) -+ - - /* Hyp System Control Register (SCTLR_EL2) bits */ - #define SCTLR_EL2_EE (1 << 25) -diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h -index 9fcd54b..a28c35b 100644 ---- a/arch/arm64/include/asm/kvm_asm.h -+++ b/arch/arm64/include/asm/kvm_asm.h -@@ -18,6 +18,8 @@ - #ifndef __ARM_KVM_ASM_H__ - #define __ARM_KVM_ASM_H__ - -+#include <asm/virt.h> -+ + #define VTCR_EL2_FLAGS (VTCR_EL2_TG0_64K | VTCR_EL2_SH0_INNER | \ + VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \ +- VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B) +-#define VTTBR_X (38 - VTCR_EL2_T0SZ_40B) ++ VTCR_EL2_SL0_LVL1) + #else /* - * 0 is reserved as an invalid value. - * Order *must* be kept in sync with the hyp switch code. -@@ -96,13 +98,21 @@ extern char __kvm_hyp_init_end[]; - - extern char __kvm_hyp_vector[]; + * Stage2 translation configuration: +- * 40bits output (PS = 2) +- * 40bits input (T0SZ = 24) + * 4kB pages (TG0 = 0) + * 3 level page tables (SL = 1) + */ + #define VTCR_EL2_FLAGS (VTCR_EL2_TG0_4K | VTCR_EL2_SH0_INNER | \ + VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \ +- VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B) +-#define VTTBR_X (37 - VTCR_EL2_T0SZ_40B) ++ VTCR_EL2_SL0_LVL1) + #endif --extern char __kvm_hyp_code_start[]; --extern char __kvm_hyp_code_end[]; -+#define __kvm_hyp_code_start __hyp_text_start -+#define __kvm_hyp_code_end __hyp_text_end +-#define VTTBR_BADDR_SHIFT (VTTBR_X - 1) +-#define VTTBR_BADDR_MASK (((1LLU << (40 - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT) + #define VTTBR_VMID_SHIFT (48LLU) + #define VTTBR_VMID_MASK (0xffLLU << VTTBR_VMID_SHIFT) - extern void __kvm_flush_vm_context(void); - extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa); +diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h +index 8e138c7..1c70b2f 100644 +--- a/arch/arm64/include/asm/kvm_mmu.h ++++ b/arch/arm64/include/asm/kvm_mmu.h +@@ -167,5 +167,80 @@ static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva, - extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu); -+ -+extern u64 __vgic_v3_get_ich_vtr_el2(void); -+ -+extern char __save_vgic_v2_state[]; -+extern char __restore_vgic_v2_state[]; -+extern char __save_vgic_v3_state[]; -+extern char __restore_vgic_v3_state[]; -+ - #endif + void stage2_flush_vm(struct kvm *kvm); - #endif /* __ARM_KVM_ASM_H__ */ -diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h -index 92242ce..4ae9213 100644 ---- a/arch/arm64/include/asm/kvm_host.h -+++ b/arch/arm64/include/asm/kvm_host.h -@@ -200,4 +200,32 @@ static inline void __cpu_init_hyp_mode(phys_addr_t boot_pgd_ptr, - hyp_stack_ptr, vector_ptr); - } - -+struct vgic_sr_vectors { -+ void *save_vgic; -+ void *restore_vgic; -+}; ++/* ++ * ARMv8 64K architecture limitations: ++ * 16 <= T0SZ <= 21 is valid under 3 level of translation tables ++ * 18 <= T0SZ <= 34 is valid under 2 level of translation tables ++ * 31 <= T0SZ <= 39 is valid under 1 level of transltaion tables ++ * ++ * ARMv8 4K architecture limitations: ++ * 16 <= T0SZ <= 24 is valid under 4 level of translation tables ++ * 21 <= T0SZ <= 33 is valid under 3 level of translation tables ++ * 30 <= T0SZ <= 39 is valid under 2 level of translation tables ++ * ++ * For 4K pages we only support 3 or 4 level, giving T0SZ a range of 16 to 33. ++ * For 64K pages we only support 2 or 3 level, giving T0SZ a range of 16 to 34. ++ * ++ * See Table D4-23 and Table D4-25 in ARM DDI 0487A.b to figure out ++ * the origin of the hardcoded values, 38 and 37. ++ */ + -+static inline void vgic_arch_setup(const struct vgic_params *vgic) ++#ifdef CONFIG_ARM64_64K_PAGES ++static inline int t0sz_to_vttbr_x(int t0sz) +{ -+ extern struct vgic_sr_vectors __vgic_sr_vectors; -+ -+ switch(vgic->type) -+ { -+ case VGIC_V2: -+ __vgic_sr_vectors.save_vgic = __save_vgic_v2_state; -+ __vgic_sr_vectors.restore_vgic = __restore_vgic_v2_state; -+ break; ++ if (t0sz < 16 || t0sz > 34) { ++ kvm_err("Cannot support %d-bit address space\n", 64 - t0sz); ++ return -EINVAL; ++ } + -+#ifdef CONFIG_ARM_GIC_V3 -+ case VGIC_V3: -+ __vgic_sr_vectors.save_vgic = __save_vgic_v3_state; -+ __vgic_sr_vectors.restore_vgic = __restore_vgic_v3_state; -+ break; ++ return 38 - t0sz; ++} ++#else /* 4K pages */ ++static inline int t0sz_to_vttbr_x(int t0sz) ++{ ++ if (t0sz < 16 || t0sz > 33) { ++ kvm_err("Cannot support %d-bit address space\n", 64 - t0sz); ++ return -EINVAL; ++ } ++ return 37 - t0sz; ++} +#endif ++static inline int kvm_get_phys_addr_shift(void) ++{ ++ int pa_range = read_cpuid(ID_AA64MMFR0_EL1) & 0xf; + ++ switch (pa_range) { ++ case 0: return 32; ++ case 1: return 36; ++ case 2: return 40; ++ case 3: return 42; ++ case 4: return 44; ++ case 5: return 48; + default: + BUG(); ++ return 0; + } +} + - #endif /* __ARM64_KVM_HOST_H__ */ -diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h -index 7d29847..d7f77ff 100644 ---- a/arch/arm64/include/asm/kvm_mmu.h -+++ b/arch/arm64/include/asm/kvm_mmu.h -@@ -122,8 +122,16 @@ static inline void kvm_set_s2pmd_writable(pmd_t *pmd) - } - - #define kvm_pgd_addr_end(addr, end) pgd_addr_end(addr, end) --#define kvm_pud_addr_end(addr, end) pud_addr_end(addr, end) --#define kvm_pmd_addr_end(addr, end) pmd_addr_end(addr, end) ++/** ++ * get_vttbr_baddr_mask - get mask value for vttbr base address ++ * ++ * In ARMv8, vttbr_baddr_mask cannot be determined in compile time since the ++ * stage2 input address size depends on hardware capability. Thus, we first ++ * need to read ID_AA64MMFR0_EL1.PARange and then set vttbr_baddr_mask with ++ * consideration of both the granule size and the level of translation tables. ++ */ ++static inline u64 get_vttbr_baddr_mask(void) ++{ ++ int t0sz, vttbr_x; + -+#define kvm_pud_addr_end(addr, end) \ -+({ unsigned long __boundary = ((addr) + PUD_SIZE) & PUD_MASK; \ -+ (__boundary - 1 < (end) - 1)? __boundary: (end); \ -+}) ++ t0sz = VTCR_EL2_T0SZ(kvm_get_phys_addr_shift()); ++ vttbr_x = t0sz_to_vttbr_x(t0sz); ++ if (vttbr_x < 0) ++ return ~0; ++ return GENMASK_ULL(48, (vttbr_x - 1)); + -+#define kvm_pmd_addr_end(addr, end) \ -+({ unsigned long __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \ -+ (__boundary - 1 < (end) - 1)? __boundary: (end); \ -+}) - - struct kvm; - ++} ++ + #endif /* __ASSEMBLY__ */ + #endif /* __ARM64_KVM_MMU_H__ */ diff --git a/arch/arm64/include/asm/pci.h b/arch/arm64/include/asm/pci.h new file mode 100644 -index 0000000..3f7856e +index 0000000..872ba93 --- /dev/null +++ b/arch/arm64/include/asm/pci.h -@@ -0,0 +1,49 @@ +@@ -0,0 +1,37 @@ +#ifndef __ASM_PCI_H +#define __ASM_PCI_H +#ifdef __KERNEL__ @@ -1881,8 +2456,6 @@ index 0000000..3f7856e +#define PCIBIOS_MIN_IO 0x1000 +#define PCIBIOS_MIN_MEM 0 + -+struct pci_host_bridge *find_pci_host_bridge(struct pci_bus *bus); -+ +/* + * Set to 1 if the kernel should re-assign all PCI bus numbers + */ @@ -1897,16 +2470,6 @@ index 0000000..3f7856e +extern int isa_dma_bridge_buggy; + +#ifdef CONFIG_PCI -+static inline int pci_domain_nr(struct pci_bus *bus) -+{ -+ struct pci_host_bridge *bridge = find_pci_host_bridge(bus); -+ -+ if (bridge) -+ return bridge->domain_nr; -+ -+ return 0; -+} -+ +static inline int pci_proc_domain(struct pci_bus *bus) +{ + return 1; @@ -1915,128 +2478,522 @@ index 0000000..3f7856e + +#endif /* __KERNEL__ */ +#endif /* __ASM_PCI_H */ -diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h -index b9349c4..ecbd081 100644 ---- a/arch/arm64/include/asm/tlbflush.h -+++ b/arch/arm64/include/asm/tlbflush.h -@@ -98,8 +98,8 @@ static inline void flush_tlb_page(struct vm_area_struct *vma, - dsb(ish); - } +diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h +index ffe1ba0..a968523 100644 +--- a/arch/arm64/include/asm/pgtable.h ++++ b/arch/arm64/include/asm/pgtable.h +@@ -296,6 +296,8 @@ static inline int has_transparent_hugepage(void) + __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) + #define pgprot_writecombine(prot) \ + __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) ++#define pgprot_device(prot) \ ++ __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) + #define __HAVE_PHYS_MEM_ACCESS_PROT + struct file; + extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, +diff --git a/arch/arm64/include/asm/psci.h b/arch/arm64/include/asm/psci.h +index e5312ea..2454bc5 100644 +--- a/arch/arm64/include/asm/psci.h ++++ b/arch/arm64/include/asm/psci.h +@@ -14,6 +14,7 @@ + #ifndef __ASM_PSCI_H + #define __ASM_PSCI_H + +-int psci_init(void); ++int psci_dt_init(void); ++int psci_acpi_init(void); + + #endif /* __ASM_PSCI_H */ +diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h +index a498f2c..2ebbd55 100644 +--- a/arch/arm64/include/asm/smp.h ++++ b/arch/arm64/include/asm/smp.h +@@ -39,9 +39,10 @@ extern void show_ipi_list(struct seq_file *p, int prec); + extern void handle_IPI(int ipinr, struct pt_regs *regs); --static inline void flush_tlb_range(struct vm_area_struct *vma, -- unsigned long start, unsigned long end) -+static inline void __flush_tlb_range(struct vm_area_struct *vma, -+ unsigned long start, unsigned long end) - { - unsigned long asid = (unsigned long)ASID(vma->vm_mm) << 48; - unsigned long addr; -@@ -112,7 +112,7 @@ static inline void flush_tlb_range(struct vm_area_struct *vma, - dsb(ish); - } + /* +- * Setup the set of possible CPUs (via set_cpu_possible) ++ * Discover the set of possible CPUs and determine their ++ * SMP operations. + */ +-extern void smp_init_cpus(void); ++extern void of_smp_init_cpus(void); --static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end) -+static inline void __flush_tlb_kernel_range(unsigned long start, unsigned long end) - { - unsigned long addr; - start >>= 12; -@@ -125,6 +125,29 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end - } + /* + * Provide a function to raise an IPI cross call on CPUs in callmap. +@@ -49,6 +50,11 @@ extern void smp_init_cpus(void); + extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int)); /* -+ * This is meant to avoid soft lock-ups on large TLB flushing ranges and not -+ * necessarily a performance improvement. ++ * Provide a function to signal a parked secondary CPU. + */ -+#define MAX_TLB_RANGE (1024UL << PAGE_SHIFT) -+ -+static inline void flush_tlb_range(struct vm_area_struct *vma, -+ unsigned long start, unsigned long end) -+{ -+ if ((end - start) <= MAX_TLB_RANGE) -+ __flush_tlb_range(vma, start, end); -+ else -+ flush_tlb_mm(vma->vm_mm); -+} -+ -+static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end) -+{ -+ if ((end - start) <= MAX_TLB_RANGE) -+ __flush_tlb_kernel_range(start, end); -+ else -+ flush_tlb_all(); -+} ++extern void set_smp_boot_wakeup_call(void (*)(int cpu)); + +/* - * On AArch64, the cache coherency is handled via the set_pte_at() function. + * Called from the secondary holding pen, this is the secondary CPU entry point. */ - static inline void update_mmu_cache(struct vm_area_struct *vma, -diff --git a/arch/arm64/include/asm/virt.h b/arch/arm64/include/asm/virt.h -index 215ad46..7a5df52 100644 ---- a/arch/arm64/include/asm/virt.h -+++ b/arch/arm64/include/asm/virt.h -@@ -50,6 +50,10 @@ static inline bool is_hyp_mode_mismatched(void) - return __boot_cpu_mode[0] != __boot_cpu_mode[1]; - } - -+/* The section containing the hypervisor text */ -+extern char __hyp_text_start[]; -+extern char __hyp_text_end[]; -+ - #endif /* __ASSEMBLY__ */ - - #endif /* ! __ASM__VIRT_H */ + asmlinkage void secondary_start_kernel(void); diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile -index cdaedad..36b117a 100644 +index df7ef87..b0bad2e 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile -@@ -29,6 +29,7 @@ arm64-obj-$(CONFIG_ARM64_CPU_SUSPEND) += sleep.o suspend.o +@@ -21,7 +21,8 @@ arm64-obj-$(CONFIG_COMPAT) += sys32.o kuser32.o signal32.o \ + sys_compat.o + arm64-obj-$(CONFIG_FUNCTION_TRACER) += ftrace.o entry-ftrace.o + arm64-obj-$(CONFIG_MODULES) += arm64ksyms.o module.o +-arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o topology.o ++arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o topology.o \ ++ smp_parking_protocol.o + arm64-obj-$(CONFIG_PERF_EVENTS) += perf_regs.o + arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o + arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o +@@ -29,6 +30,8 @@ arm64-obj-$(CONFIG_ARM64_CPU_SUSPEND) += sleep.o suspend.o arm64-obj-$(CONFIG_JUMP_LABEL) += jump_label.o arm64-obj-$(CONFIG_KGDB) += kgdb.o arm64-obj-$(CONFIG_EFI) += efi.o efi-stub.o efi-entry.o +arm64-obj-$(CONFIG_PCI) += pci.o ++arm64-obj-$(CONFIG_ACPI) += acpi.o obj-y += $(arm64-obj-y) vdso/ obj-m += $(arm64-obj-m) -diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offsets.c -index 646f888..e74654c 100644 ---- a/arch/arm64/kernel/asm-offsets.c -+++ b/arch/arm64/kernel/asm-offsets.c -@@ -129,13 +129,24 @@ int main(void) - DEFINE(KVM_TIMER_ENABLED, offsetof(struct kvm, arch.timer.enabled)); - DEFINE(VCPU_KVM, offsetof(struct kvm_vcpu, kvm)); - DEFINE(VCPU_VGIC_CPU, offsetof(struct kvm_vcpu, arch.vgic_cpu)); -- DEFINE(VGIC_CPU_HCR, offsetof(struct vgic_cpu, vgic_hcr)); -- DEFINE(VGIC_CPU_VMCR, offsetof(struct vgic_cpu, vgic_vmcr)); -- DEFINE(VGIC_CPU_MISR, offsetof(struct vgic_cpu, vgic_misr)); -- DEFINE(VGIC_CPU_EISR, offsetof(struct vgic_cpu, vgic_eisr)); -- DEFINE(VGIC_CPU_ELRSR, offsetof(struct vgic_cpu, vgic_elrsr)); -- DEFINE(VGIC_CPU_APR, offsetof(struct vgic_cpu, vgic_apr)); -- DEFINE(VGIC_CPU_LR, offsetof(struct vgic_cpu, vgic_lr)); -+ DEFINE(VGIC_SAVE_FN, offsetof(struct vgic_sr_vectors, save_vgic)); -+ DEFINE(VGIC_RESTORE_FN, offsetof(struct vgic_sr_vectors, restore_vgic)); -+ DEFINE(VGIC_SR_VECTOR_SZ, sizeof(struct vgic_sr_vectors)); -+ DEFINE(VGIC_V2_CPU_HCR, offsetof(struct vgic_cpu, vgic_v2.vgic_hcr)); -+ DEFINE(VGIC_V2_CPU_VMCR, offsetof(struct vgic_cpu, vgic_v2.vgic_vmcr)); -+ DEFINE(VGIC_V2_CPU_MISR, offsetof(struct vgic_cpu, vgic_v2.vgic_misr)); -+ DEFINE(VGIC_V2_CPU_EISR, offsetof(struct vgic_cpu, vgic_v2.vgic_eisr)); -+ DEFINE(VGIC_V2_CPU_ELRSR, offsetof(struct vgic_cpu, vgic_v2.vgic_elrsr)); -+ DEFINE(VGIC_V2_CPU_APR, offsetof(struct vgic_cpu, vgic_v2.vgic_apr)); -+ DEFINE(VGIC_V2_CPU_LR, offsetof(struct vgic_cpu, vgic_v2.vgic_lr)); -+ DEFINE(VGIC_V3_CPU_HCR, offsetof(struct vgic_cpu, vgic_v3.vgic_hcr)); -+ DEFINE(VGIC_V3_CPU_VMCR, offsetof(struct vgic_cpu, vgic_v3.vgic_vmcr)); -+ DEFINE(VGIC_V3_CPU_MISR, offsetof(struct vgic_cpu, vgic_v3.vgic_misr)); -+ DEFINE(VGIC_V3_CPU_EISR, offsetof(struct vgic_cpu, vgic_v3.vgic_eisr)); -+ DEFINE(VGIC_V3_CPU_ELRSR, offsetof(struct vgic_cpu, vgic_v3.vgic_elrsr)); -+ DEFINE(VGIC_V3_CPU_AP0R, offsetof(struct vgic_cpu, vgic_v3.vgic_ap0r)); -+ DEFINE(VGIC_V3_CPU_AP1R, offsetof(struct vgic_cpu, vgic_v3.vgic_ap1r)); -+ DEFINE(VGIC_V3_CPU_LR, offsetof(struct vgic_cpu, vgic_v3.vgic_lr)); - DEFINE(VGIC_CPU_NR_LR, offsetof(struct vgic_cpu, nr_lr)); - DEFINE(KVM_VTTBR, offsetof(struct kvm, arch.vttbr)); - DEFINE(KVM_VGIC_VCTRL, offsetof(struct kvm, arch.vgic.vctrl_base)); +diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c +new file mode 100644 +index 0000000..5486426 +--- /dev/null ++++ b/arch/arm64/kernel/acpi.c +@@ -0,0 +1,397 @@ ++/* ++ * ARM64 Specific Low-Level ACPI Boot Support ++ * ++ * Copyright (C) 2013-2014, Linaro Ltd. ++ * Author: Al Stone <al.stone@linaro.org> ++ * Author: Graeme Gregory <graeme.gregory@linaro.org> ++ * Author: Hanjun Guo <hanjun.guo@linaro.org> ++ * Author: Tomasz Nowicki <tomasz.nowicki@linaro.org> ++ * Author: Naresh Bhat <naresh.bhat@linaro.org> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#define pr_fmt(fmt) "ACPI: " fmt ++ ++#include <linux/init.h> ++#include <linux/acpi.h> ++#include <linux/cpumask.h> ++#include <linux/memblock.h> ++#include <linux/irq.h> ++#include <linux/irqdomain.h> ++#include <linux/bootmem.h> ++#include <linux/smp.h> ++#include <linux/irqchip/arm-gic-acpi.h> ++ ++#include <asm/cputype.h> ++#include <asm/cpu_ops.h> ++ ++#define ARM64_ACPI_DISABLED_DEFAULT 1 ++ ++int acpi_noirq; /* skip ACPI IRQ initialization */ ++int acpi_disabled = ARM64_ACPI_DISABLED_DEFAULT; ++EXPORT_SYMBOL(acpi_disabled); ++ ++int acpi_pci_disabled; /* skip ACPI PCI scan and IRQ initialization */ ++EXPORT_SYMBOL(acpi_pci_disabled); ++ ++static int enabled_cpus; /* Processors (GICC) with enabled flag in MADT */ ++ ++static char *boot_method; ++static u64 parked_address[NR_CPUS]; ++ ++/* ++ * Since we're on ARM, the default interrupt routing model ++ * clearly has to be GIC. ++ */ ++enum acpi_irq_model_id acpi_irq_model = ACPI_IRQ_MODEL_GIC; ++ ++/* ++ * __acpi_map_table() will be called before page_init(), so early_ioremap() ++ * or early_memremap() should be called here to for ACPI table mapping. ++ */ ++char *__init __acpi_map_table(unsigned long phys, unsigned long size) ++{ ++ if (!phys || !size) ++ return NULL; ++ ++ return early_memremap(phys, size); ++} ++ ++void __init __acpi_unmap_table(char *map, unsigned long size) ++{ ++ if (!map || !size) ++ return; ++ ++ early_memunmap(map, size); ++} ++ ++/** ++ * acpi_map_gic_cpu_interface - generates a logical cpu number ++ * and map to MPIDR represented by GICC structure ++ * @mpidr: CPU's hardware id to register, MPIDR represented in MADT ++ * @enabled: this cpu is enabled or not ++ * ++ * Returns the logical cpu number which maps to MPIDR ++ */ ++static int acpi_map_gic_cpu_interface(u64 mpidr, u64 parked_addr, u8 enabled) ++{ ++ int cpu; ++ ++ if (mpidr == INVALID_HWID) { ++ pr_info("Skip invalid cpu hardware ID\n"); ++ return -EINVAL; ++ } ++ ++ total_cpus++; ++ if (!enabled) ++ return -EINVAL; ++ ++ if (enabled_cpus >= NR_CPUS) { ++ pr_warn("NR_CPUS limit of %d reached, Processor %d/0x%llx ignored.\n", ++ NR_CPUS, total_cpus, mpidr); ++ return -EINVAL; ++ } ++ ++ /* No need to check duplicate MPIDRs for the first CPU */ ++ if (enabled_cpus) { ++ /* ++ * Duplicate MPIDRs are a recipe for disaster. Scan ++ * all initialized entries and check for ++ * duplicates. If any is found just ignore the CPU. ++ */ ++ for_each_possible_cpu(cpu) { ++ if (cpu_logical_map(cpu) == mpidr) { ++ pr_err("Firmware bug, duplicate CPU MPIDR: 0x%llx in MADT\n", ++ mpidr); ++ return -EINVAL; ++ } ++ } ++ ++ /* allocate a logical cpu id for the new comer */ ++ cpu = cpumask_next_zero(-1, cpu_possible_mask); ++ } else { ++ /* First GICC entry must be BSP as ACPI spec said */ ++ if (cpu_logical_map(0) != mpidr) { ++ pr_err("First GICC entry with MPIDR 0x%llx is not BSP\n", ++ mpidr); ++ return -EINVAL; ++ } ++ ++ /* ++ * boot_cpu_init() already hold bit 0 in cpu_present_mask ++ * for BSP, no need to allocate again. ++ */ ++ cpu = 0; ++ } ++ ++ parked_address[cpu] = parked_addr; ++ ++ /* CPU 0 was already initialized */ ++ if (cpu) { ++ cpu_ops[cpu] = cpu_get_ops(boot_method); ++ if (!cpu_ops[cpu]) ++ return -EINVAL; ++ ++ if (cpu_ops[cpu]->cpu_init(NULL, cpu)) ++ return -EOPNOTSUPP; ++ ++ /* map the logical cpu id to cpu MPIDR */ ++ cpu_logical_map(cpu) = mpidr; ++ ++ set_cpu_possible(cpu, true); ++ } else { ++ /* get cpu0's ops, no need to return if ops is null */ ++ cpu_ops[0] = cpu_get_ops(boot_method); ++ } ++ ++ enabled_cpus++; ++ return cpu; ++} ++ ++static int __init ++acpi_parse_gic_cpu_interface(struct acpi_subtable_header *header, ++ const unsigned long end) ++{ ++ struct acpi_madt_generic_interrupt *processor; ++ ++ processor = (struct acpi_madt_generic_interrupt *)header; ++ ++ if (BAD_MADT_ENTRY(processor, end)) ++ return -EINVAL; ++ ++ acpi_table_print_madt_entry(header); ++ ++ acpi_map_gic_cpu_interface(processor->arm_mpidr & MPIDR_HWID_BITMASK, ++ processor->parked_address, processor->flags & ACPI_MADT_ENABLED); ++ ++ return 0; ++} ++ ++/* Parse GIC cpu interface entries in MADT for SMP init */ ++void __init acpi_smp_init_cpus(void) ++{ ++ int count; ++ ++ /* ++ * do a partial walk of MADT to determine how many CPUs ++ * we have including disabled CPUs, and get information ++ * we need for SMP init ++ */ ++ count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, ++ acpi_parse_gic_cpu_interface, 0); ++ ++ if (!count) { ++ pr_err("No GIC CPU interface entries present\n"); ++ return; ++ } else if (count < 0) { ++ pr_err("Error parsing GIC CPU interface entry\n"); ++ return; ++ } ++ ++ /* Make boot-up look pretty */ ++ pr_info("%d CPUs enabled, %d CPUs total\n", enabled_cpus, total_cpus); ++} ++ ++int acpi_gsi_to_irq(u32 gsi, unsigned int *irq) ++{ ++ *irq = irq_find_mapping(NULL, gsi); ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(acpi_gsi_to_irq); ++ ++/* ++ * success: return IRQ number (>0) ++ * failure: return =< 0 ++ */ ++int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity) ++{ ++ unsigned int irq; ++ unsigned int irq_type; ++ ++ /* ++ * ACPI have no bindings to indicate SPI or PPI, so we ++ * use different mappings from DT in ACPI. ++ * ++ * For FDT ++ * PPI interrupt: in the range [0, 15]; ++ * SPI interrupt: in the range [0, 987]; ++ * ++ * For ACPI, GSI should be unique so using ++ * the hwirq directly for the mapping: ++ * PPI interrupt: in the range [16, 31]; ++ * SPI interrupt: in the range [32, 1019]; ++ */ ++ ++ if (trigger == ACPI_EDGE_SENSITIVE && ++ polarity == ACPI_ACTIVE_LOW) ++ irq_type = IRQ_TYPE_EDGE_FALLING; ++ else if (trigger == ACPI_EDGE_SENSITIVE && ++ polarity == ACPI_ACTIVE_HIGH) ++ irq_type = IRQ_TYPE_EDGE_RISING; ++ else if (trigger == ACPI_LEVEL_SENSITIVE && ++ polarity == ACPI_ACTIVE_LOW) ++ irq_type = IRQ_TYPE_LEVEL_LOW; ++ else if (trigger == ACPI_LEVEL_SENSITIVE && ++ polarity == ACPI_ACTIVE_HIGH) ++ irq_type = IRQ_TYPE_LEVEL_HIGH; ++ else ++ irq_type = IRQ_TYPE_NONE; ++ ++ /* ++ * Since only one GIC is supported in ACPI 5.0, we can ++ * create mapping refer to the default domain ++ */ ++ irq = irq_create_mapping(NULL, gsi); ++ if (!irq) ++ return irq; ++ ++ /* Set irq type if specified and different than the current one */ ++ if (irq_type != IRQ_TYPE_NONE && ++ irq_type != irq_get_trigger_type(irq)) ++ irq_set_irq_type(irq, irq_type); ++ return irq; ++} ++EXPORT_SYMBOL_GPL(acpi_register_gsi); ++ ++void acpi_unregister_gsi(u32 gsi) ++{ ++} ++EXPORT_SYMBOL_GPL(acpi_unregister_gsi); ++ ++static int __init acpi_parse_fadt(struct acpi_table_header *table) ++{ ++ struct acpi_table_fadt *fadt = (struct acpi_table_fadt *)table; ++ ++ /* ++ * Revision in table header is the FADT Major revision, ++ * and there is a minor revision of FADT which was introduced ++ * by ACPI 5.1, we only deal with ACPI 5.1 or higher revision ++ * to get arm boot flags, or we will disable ACPI. ++ */ ++ if (table->revision > 5 || ++ (table->revision == 5 && fadt->minor_revision >= 1)) { ++ /* ++ * ACPI 5.1 only has two explicit methods to boot up SMP, ++ * PSCI and Parking protocol, but the Parking protocol is ++ * only specified for ARMv7 now, so make PSCI as the only ++ * way for the SMP boot protocol before some updates for ++ * the ACPI spec or the Parking protocol spec. ++ */ ++ if (acpi_psci_present()) ++ boot_method = "psci"; ++ else if (IS_ENABLED(CONFIG_ARM_PARKING_PROTOCOL)) ++ boot_method = "parking-protocol"; ++ ++ if (!boot_method) ++ pr_warn("has no boot support, will not bring up secondary CPUs\n"); ++ return -EOPNOTSUPP; ++ } ++ ++ pr_warn("Unsupported FADT revision %d.%d, should be 5.1+, will disable ACPI\n", ++ table->revision, fadt->minor_revision); ++ disable_acpi(); ++ ++ return -EINVAL; ++} ++ ++/* ++ * acpi_boot_table_init() called from setup_arch(), always. ++ * 1. find RSDP and get its address, and then find XSDT ++ * 2. extract all tables and checksums them all ++ * 3. check ACPI FADT revisoin ++ * ++ * We can parse ACPI boot-time tables such as MADT after ++ * this function is called. ++ */ ++void __init acpi_boot_table_init(void) ++{ ++ /* If acpi_disabled, bail out */ ++ if (acpi_disabled) ++ return; ++ ++ /* Initialize the ACPI boot-time table parser. */ ++ if (acpi_table_init()) { ++ disable_acpi(); ++ return; ++ } ++ ++ if (acpi_table_parse(ACPI_SIG_FADT, acpi_parse_fadt)) ++ pr_err("Can't find FADT or error happened during parsing FADT\n"); ++} ++ ++void __init acpi_gic_init(void) ++{ ++ struct acpi_table_header *table; ++ acpi_status status; ++ acpi_size tbl_size; ++ int err; ++ ++ status = acpi_get_table_with_size(ACPI_SIG_MADT, 0, &table, &tbl_size); ++ if (ACPI_FAILURE(status)) { ++ const char *msg = acpi_format_exception(status); ++ ++ pr_err("Failed to get MADT table, %s\n", msg); ++ return; ++ } ++ ++ err = gic_v2_acpi_init(table); ++ if (err) ++ pr_err("Failed to initialize GIC IRQ controller"); ++ ++ early_acpi_os_unmap_memory((char *)table, tbl_size); ++} ++ ++/* ++ * Parked Address in ACPI GIC structure will be used as the CPU ++ * release address ++ */ ++int acpi_get_cpu_parked_address(int cpu, u64 *addr) ++{ ++ if (!addr || !parked_address[cpu]) ++ return -EINVAL; ++ ++ *addr = parked_address[cpu]; ++ ++ return 0; ++} ++ ++static int __init parse_acpi(char *arg) ++{ ++ if (!arg) ++ return -EINVAL; ++ ++ /* "acpi=off" disables both ACPI table parsing and interpreter */ ++ if (strcmp(arg, "off") == 0) ++ acpi_disabled = 1; ++ else if (strcmp(arg, "on") == 0) ++ acpi_disabled = 0; ++ else ++ return -EINVAL; /* Core will print when we return error */ ++ ++ return 0; ++} ++early_param("acpi", parse_acpi); ++ ++int acpi_isa_irq_to_gsi(unsigned isa_irq, u32 *gsi) ++{ ++ return -1; ++} ++ ++int acpi_register_ioapic(acpi_handle handle, u64 phys_addr, u32 gsi_base) ++{ ++ /* TBD */ ++ return -EINVAL; ++} ++EXPORT_SYMBOL(acpi_register_ioapic); ++ ++int acpi_unregister_ioapic(acpi_handle handle, u32 gsi_base) ++{ ++ /* TBD */ ++ return -EINVAL; ++} ++EXPORT_SYMBOL(acpi_unregister_ioapic); ++ +diff --git a/arch/arm64/kernel/cpu_ops.c b/arch/arm64/kernel/cpu_ops.c +index cce9524..1d90f31 100644 +--- a/arch/arm64/kernel/cpu_ops.c ++++ b/arch/arm64/kernel/cpu_ops.c +@@ -23,19 +23,23 @@ + #include <linux/string.h> + + extern const struct cpu_operations smp_spin_table_ops; ++extern const struct cpu_operations smp_parking_protocol_ops; + extern const struct cpu_operations cpu_psci_ops; + + const struct cpu_operations *cpu_ops[NR_CPUS]; + +-static const struct cpu_operations *supported_cpu_ops[] __initconst = { ++static const struct cpu_operations *supported_cpu_ops[] = { + #ifdef CONFIG_SMP + &smp_spin_table_ops, ++#ifdef CONFIG_ARM_PARKING_PROTOCOL ++ &smp_parking_protocol_ops, ++#endif + #endif + &cpu_psci_ops, + NULL, + }; + +-static const struct cpu_operations * __init cpu_get_ops(const char *name) ++const struct cpu_operations *cpu_get_ops(const char *name) + { + const struct cpu_operations **ops = supported_cpu_ops; + diff --git a/arch/arm64/kernel/efi-stub.c b/arch/arm64/kernel/efi-stub.c -index e786e6c..320ef48 100644 +index 1317fef..d27dd98 100644 --- a/arch/arm64/kernel/efi-stub.c +++ b/arch/arm64/kernel/efi-stub.c -@@ -58,20 +58,16 @@ static efi_status_t handle_kernel_image(efi_system_table_t *sys_table, +@@ -28,20 +28,16 @@ efi_status_t handle_kernel_image(efi_system_table_t *sys_table, kernel_size = _edata - _text; if (*image_addr != (dram_base + TEXT_OFFSET)) { kernel_memsize = kernel_size + (_end - _edata); @@ -2053,7 +3010,7 @@ index e786e6c..320ef48 100644 - if (*image_addr != (dram_base + TEXT_OFFSET)) { - pr_efi_err(sys_table, "Failed to alloc kernel memory\n"); - efi_free(sys_table, kernel_memsize, *image_addr); -- return EFI_ERROR; +- return EFI_LOAD_ERROR; - } - *image_size = kernel_memsize; + memcpy((void *)*reserve_addr + TEXT_OFFSET, (void *)*image_addr, @@ -2064,11 +3021,11 @@ index e786e6c..320ef48 100644 diff --git a/arch/arm64/kernel/efi.c b/arch/arm64/kernel/efi.c -index 14db1f6..453b7f8 100644 +index 03aaa99..6c4de44 100644 --- a/arch/arm64/kernel/efi.c +++ b/arch/arm64/kernel/efi.c -@@ -467,3 +467,14 @@ static int __init arm64_enter_virtual_mode(void) - return 0; +@@ -479,3 +479,14 @@ err_unmap: + return -1; } early_initcall(arm64_enter_virtual_mode); + @@ -2083,18 +3040,10 @@ index 14db1f6..453b7f8 100644 + return pm_power_off == NULL; +} diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S -index a2c1195..8df59be 100644 +index 8730690..0a6e4f9 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S -@@ -22,6 +22,7 @@ - - #include <linux/linkage.h> - #include <linux/init.h> -+#include <linux/irqchip/arm-gic-v3.h> - - #include <asm/assembler.h> - #include <asm/ptrace.h> -@@ -156,7 +157,7 @@ optional_header: +@@ -151,7 +151,7 @@ optional_header: .short 0x20b // PE32+ format .byte 0x02 // MajorLinkerVersion .byte 0x14 // MinorLinkerVersion @@ -2103,7 +3052,7 @@ index a2c1195..8df59be 100644 .long 0 // SizeOfInitializedData .long 0 // SizeOfUninitializedData .long efi_stub_entry - efi_head // AddressOfEntryPoint -@@ -174,7 +175,7 @@ extra_header_fields: +@@ -169,7 +169,7 @@ extra_header_fields: .short 0 // MinorSubsystemVersion .long 0 // Win32VersionValue @@ -2112,7 +3061,7 @@ index a2c1195..8df59be 100644 // Everything before the kernel image is considered part of the header .long stext - efi_head // SizeOfHeaders -@@ -221,7 +222,7 @@ section_table: +@@ -216,7 +216,7 @@ section_table: .byte 0 .byte 0 .byte 0 // end of 0 padding of section name @@ -2121,48 +3070,12 @@ index a2c1195..8df59be 100644 .long stext - efi_head // VirtualAddress .long _edata - stext // SizeOfRawData .long stext - efi_head // PointerToRawData -@@ -295,6 +296,23 @@ CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1 - msr cnthctl_el2, x0 - msr cntvoff_el2, xzr // Clear virtual offset - -+#ifdef CONFIG_ARM_GIC_V3 -+ /* GICv3 system register access */ -+ mrs x0, id_aa64pfr0_el1 -+ ubfx x0, x0, #24, #4 -+ cmp x0, #1 -+ b.ne 3f -+ -+ mrs x0, ICC_SRE_EL2 -+ orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 -+ orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 -+ msr ICC_SRE_EL2, x0 -+ isb // Make sure SRE is now set -+ msr ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults -+ -+3: -+#endif -+ - /* Populate ID registers. */ - mrs x0, midr_el1 - mrs x1, mpidr_el1 -diff --git a/arch/arm64/kernel/hyp-stub.S b/arch/arm64/kernel/hyp-stub.S -index 0959611..a272f33 100644 ---- a/arch/arm64/kernel/hyp-stub.S -+++ b/arch/arm64/kernel/hyp-stub.S -@@ -19,6 +19,7 @@ - - #include <linux/init.h> - #include <linux/linkage.h> -+#include <linux/irqchip/arm-gic-v3.h> - - #include <asm/assembler.h> - #include <asm/ptrace.h> diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c new file mode 100644 -index 0000000..955d6d1 +index 0000000..ce5836c --- /dev/null +++ b/arch/arm64/kernel/pci.c -@@ -0,0 +1,38 @@ +@@ -0,0 +1,70 @@ +/* + * Code borrowed from powerpc/kernel/pci-common.c + * @@ -2201,8 +3114,40 @@ index 0000000..955d6d1 +{ + return res->start; +} ++ ++/* ++ * Try to assign the IRQ number from DT when adding a new device ++ */ ++int pcibios_add_device(struct pci_dev *dev) ++{ ++ dev->irq = of_irq_parse_and_map_pci(dev, 0, 0); ++ ++ return 0; ++} ++ ++ ++#ifdef CONFIG_PCI_DOMAINS_GENERIC ++static bool dt_domain_found = false; ++ ++void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent) ++{ ++ int domain = of_get_pci_domain_nr(parent->of_node); ++ ++ if (domain >= 0) { ++ dt_domain_found = true; ++ } else if (dt_domain_found == true) { ++ dev_err(parent, "Node %s is missing \"linux,pci-domain\" property in DT\n", ++ parent->of_node->full_name); ++ return; ++ } else { ++ domain = pci_get_new_domain_nr(); ++ } ++ ++ bus->domain_nr = domain; ++} ++#endif diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c -index 43b7c34..ec5cbbe 100644 +index 29d4869..c0427bc 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -43,6 +43,7 @@ @@ -2213,7 +3158,7 @@ index 43b7c34..ec5cbbe 100644 #include <asm/compat.h> #include <asm/cacheflush.h> -@@ -176,6 +177,11 @@ void machine_restart(char *cmd) +@@ -182,6 +183,11 @@ void machine_restart(char *cmd) arm_pm_restart(reboot_mode, cmd); /* @@ -2225,1680 +3170,265 @@ index 43b7c34..ec5cbbe 100644 * Whoops - the architecture was unable to reboot. */ printk("Reboot failed -- System halted\n"); -diff --git a/arch/arm64/kernel/smp_spin_table.c b/arch/arm64/kernel/smp_spin_table.c -index 0347d38..70181c1 100644 ---- a/arch/arm64/kernel/smp_spin_table.c -+++ b/arch/arm64/kernel/smp_spin_table.c -@@ -20,6 +20,7 @@ +diff --git a/arch/arm64/kernel/psci.c b/arch/arm64/kernel/psci.c +index 5539547..15ba470 100644 +--- a/arch/arm64/kernel/psci.c ++++ b/arch/arm64/kernel/psci.c +@@ -15,6 +15,7 @@ + + #define pr_fmt(fmt) "psci: " fmt + ++#include <linux/acpi.h> #include <linux/init.h> #include <linux/of.h> #include <linux/smp.h> -+#include <linux/types.h> +@@ -23,6 +24,7 @@ + #include <linux/delay.h> + #include <uapi/linux/psci.h> - #include <asm/cacheflush.h> ++#include <asm/acpi.h> + #include <asm/compiler.h> #include <asm/cpu_ops.h> -@@ -65,12 +66,21 @@ static int smp_spin_table_cpu_init(struct device_node *dn, unsigned int cpu) - - static int smp_spin_table_cpu_prepare(unsigned int cpu) - { -- void **release_addr; -+ __le64 __iomem *release_addr; - - if (!cpu_release_addr[cpu]) - return -ENODEV; - -- release_addr = __va(cpu_release_addr[cpu]); -+ /* -+ * The cpu-release-addr may or may not be inside the linear mapping. -+ * As ioremap_cache will either give us a new mapping or reuse the -+ * existing linear mapping, we can use it to cover both cases. In -+ * either case the memory will be MT_NORMAL. -+ */ -+ release_addr = ioremap_cache(cpu_release_addr[cpu], -+ sizeof(*release_addr)); -+ if (!release_addr) -+ return -ENOMEM; - - /* - * We write the release address as LE regardless of the native -@@ -79,15 +89,16 @@ static int smp_spin_table_cpu_prepare(unsigned int cpu) - * boot-loader's endianess before jumping. This is mandated by - * the boot protocol. - */ -- release_addr[0] = (void *) cpu_to_le64(__pa(secondary_holding_pen)); -- -- __flush_dcache_area(release_addr, sizeof(release_addr[0])); -+ writeq_relaxed(__pa(secondary_holding_pen), release_addr); -+ __flush_dcache_area(release_addr, sizeof(*release_addr)); - - /* - * Send an event to wake up the secondary CPU. - */ - sev(); - -+ iounmap(release_addr); -+ - return 0; + #include <asm/errno.h> +@@ -231,6 +233,33 @@ static void psci_sys_poweroff(void) + invoke_psci_fn(PSCI_0_2_FN_SYSTEM_OFF, 0, 0, 0); } -diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile -index 72a9fd5..32a0961 100644 ---- a/arch/arm64/kvm/Makefile -+++ b/arch/arm64/kvm/Makefile -@@ -20,4 +20,8 @@ kvm-$(CONFIG_KVM_ARM_HOST) += hyp.o hyp-init.o handle_exit.o - kvm-$(CONFIG_KVM_ARM_HOST) += guest.o reset.o sys_regs.o sys_regs_generic_v8.o - - kvm-$(CONFIG_KVM_ARM_VGIC) += $(KVM)/arm/vgic.o -+kvm-$(CONFIG_KVM_ARM_VGIC) += $(KVM)/arm/vgic-v2.o -+kvm-$(CONFIG_KVM_ARM_VGIC) += vgic-v2-switch.o -+kvm-$(CONFIG_KVM_ARM_VGIC) += $(KVM)/arm/vgic-v3.o -+kvm-$(CONFIG_KVM_ARM_VGIC) += vgic-v3-switch.o - kvm-$(CONFIG_KVM_ARM_TIMER) += $(KVM)/arm/arch_timer.o -diff --git a/arch/arm64/kvm/hyp.S b/arch/arm64/kvm/hyp.S -index b0d1512..5945f3b 100644 ---- a/arch/arm64/kvm/hyp.S -+++ b/arch/arm64/kvm/hyp.S -@@ -16,7 +16,6 @@ - */ - - #include <linux/linkage.h> --#include <linux/irqchip/arm-gic.h> - - #include <asm/assembler.h> - #include <asm/memory.h> -@@ -36,9 +35,6 @@ - .pushsection .hyp.text, "ax" - .align PAGE_SHIFT - --__kvm_hyp_code_start: -- .globl __kvm_hyp_code_start -- - .macro save_common_regs - // x2: base address for cpu context - // x3: tmp register -@@ -339,11 +335,8 @@ __kvm_hyp_code_start: - .endm - - .macro activate_traps -- ldr x2, [x0, #VCPU_IRQ_LINES] -- ldr x1, [x0, #VCPU_HCR_EL2] -- orr x2, x2, x1 -- msr hcr_el2, x2 -- -+ ldr x2, [x0, #VCPU_HCR_EL2] -+ msr hcr_el2, x2 - ldr x2, =(CPTR_EL2_TTA) - msr cptr_el2, x2 - -@@ -379,100 +372,33 @@ __kvm_hyp_code_start: - .endm - - /* -- * Save the VGIC CPU state into memory -- * x0: Register pointing to VCPU struct -- * Do not corrupt x1!!! -+ * Call into the vgic backend for state saving - */ - .macro save_vgic_state -- /* Get VGIC VCTRL base into x2 */ -- ldr x2, [x0, #VCPU_KVM] -- kern_hyp_va x2 -- ldr x2, [x2, #KVM_VGIC_VCTRL] -- kern_hyp_va x2 -- cbz x2, 2f // disabled -- -- /* Compute the address of struct vgic_cpu */ -- add x3, x0, #VCPU_VGIC_CPU -- -- /* Save all interesting registers */ -- ldr w4, [x2, #GICH_HCR] -- ldr w5, [x2, #GICH_VMCR] -- ldr w6, [x2, #GICH_MISR] -- ldr w7, [x2, #GICH_EISR0] -- ldr w8, [x2, #GICH_EISR1] -- ldr w9, [x2, #GICH_ELRSR0] -- ldr w10, [x2, #GICH_ELRSR1] -- ldr w11, [x2, #GICH_APR] --CPU_BE( rev w4, w4 ) --CPU_BE( rev w5, w5 ) --CPU_BE( rev w6, w6 ) --CPU_BE( rev w7, w7 ) --CPU_BE( rev w8, w8 ) --CPU_BE( rev w9, w9 ) --CPU_BE( rev w10, w10 ) --CPU_BE( rev w11, w11 ) -- -- str w4, [x3, #VGIC_CPU_HCR] -- str w5, [x3, #VGIC_CPU_VMCR] -- str w6, [x3, #VGIC_CPU_MISR] -- str w7, [x3, #VGIC_CPU_EISR] -- str w8, [x3, #(VGIC_CPU_EISR + 4)] -- str w9, [x3, #VGIC_CPU_ELRSR] -- str w10, [x3, #(VGIC_CPU_ELRSR + 4)] -- str w11, [x3, #VGIC_CPU_APR] -- -- /* Clear GICH_HCR */ -- str wzr, [x2, #GICH_HCR] -- -- /* Save list registers */ -- add x2, x2, #GICH_LR0 -- ldr w4, [x3, #VGIC_CPU_NR_LR] -- add x3, x3, #VGIC_CPU_LR --1: ldr w5, [x2], #4 --CPU_BE( rev w5, w5 ) -- str w5, [x3], #4 -- sub w4, w4, #1 -- cbnz w4, 1b --2: -+ adr x24, __vgic_sr_vectors -+ ldr x24, [x24, VGIC_SAVE_FN] -+ kern_hyp_va x24 -+ blr x24 -+ mrs x24, hcr_el2 -+ mov x25, #HCR_INT_OVERRIDE -+ neg x25, x25 -+ and x24, x24, x25 -+ msr hcr_el2, x24 - .endm - - /* -- * Restore the VGIC CPU state from memory -- * x0: Register pointing to VCPU struct -+ * Call into the vgic backend for state restoring - */ - .macro restore_vgic_state -- /* Get VGIC VCTRL base into x2 */ -- ldr x2, [x0, #VCPU_KVM] -- kern_hyp_va x2 -- ldr x2, [x2, #KVM_VGIC_VCTRL] -- kern_hyp_va x2 -- cbz x2, 2f // disabled -- -- /* Compute the address of struct vgic_cpu */ -- add x3, x0, #VCPU_VGIC_CPU -- -- /* We only restore a minimal set of registers */ -- ldr w4, [x3, #VGIC_CPU_HCR] -- ldr w5, [x3, #VGIC_CPU_VMCR] -- ldr w6, [x3, #VGIC_CPU_APR] --CPU_BE( rev w4, w4 ) --CPU_BE( rev w5, w5 ) --CPU_BE( rev w6, w6 ) -- -- str w4, [x2, #GICH_HCR] -- str w5, [x2, #GICH_VMCR] -- str w6, [x2, #GICH_APR] -- -- /* Restore list registers */ -- add x2, x2, #GICH_LR0 -- ldr w4, [x3, #VGIC_CPU_NR_LR] -- add x3, x3, #VGIC_CPU_LR --1: ldr w5, [x3], #4 --CPU_BE( rev w5, w5 ) -- str w5, [x2], #4 -- sub w4, w4, #1 -- cbnz w4, 1b --2: -+ mrs x24, hcr_el2 -+ ldr x25, [x0, #VCPU_IRQ_LINES] -+ orr x24, x24, #HCR_INT_OVERRIDE -+ orr x24, x24, x25 -+ msr hcr_el2, x24 -+ adr x24, __vgic_sr_vectors -+ ldr x24, [x24, #VGIC_RESTORE_FN] -+ kern_hyp_va x24 -+ blr x24 - .endm - - .macro save_timer_state -@@ -653,6 +579,12 @@ ENTRY(__kvm_flush_vm_context) - ret - ENDPROC(__kvm_flush_vm_context) - -+ // struct vgic_sr_vectors __vgi_sr_vectors; -+ .align 3 -+ENTRY(__vgic_sr_vectors) -+ .skip VGIC_SR_VECTOR_SZ -+ENDPROC(__vgic_sr_vectors) -+ - __kvm_hyp_panic: - // Guess the context by looking at VTTBR: - // If zero, then we're already a host. -@@ -880,7 +812,4 @@ ENTRY(__kvm_hyp_vector) - ventry el1_error_invalid // Error 32-bit EL1 - ENDPROC(__kvm_hyp_vector) - --__kvm_hyp_code_end: -- .globl __kvm_hyp_code_end -- - .popsection -diff --git a/arch/arm64/kvm/vgic-v2-switch.S b/arch/arm64/kvm/vgic-v2-switch.S -new file mode 100644 -index 0000000..ae21177 ---- /dev/null -+++ b/arch/arm64/kvm/vgic-v2-switch.S -@@ -0,0 +1,133 @@ -+/* -+ * Copyright (C) 2012,2013 - ARM Ltd -+ * Author: Marc Zyngier <marc.zyngier@arm.com> -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+ -+#include <linux/linkage.h> -+#include <linux/irqchip/arm-gic.h> -+ -+#include <asm/assembler.h> -+#include <asm/memory.h> -+#include <asm/asm-offsets.h> -+#include <asm/kvm.h> -+#include <asm/kvm_asm.h> -+#include <asm/kvm_arm.h> -+#include <asm/kvm_mmu.h> -+ -+ .text -+ .pushsection .hyp.text, "ax" -+ -+/* -+ * Save the VGIC CPU state into memory -+ * x0: Register pointing to VCPU struct -+ * Do not corrupt x1!!! -+ */ -+ENTRY(__save_vgic_v2_state) -+__save_vgic_v2_state: -+ /* Get VGIC VCTRL base into x2 */ -+ ldr x2, [x0, #VCPU_KVM] -+ kern_hyp_va x2 -+ ldr x2, [x2, #KVM_VGIC_VCTRL] -+ kern_hyp_va x2 -+ cbz x2, 2f // disabled -+ -+ /* Compute the address of struct vgic_cpu */ -+ add x3, x0, #VCPU_VGIC_CPU -+ -+ /* Save all interesting registers */ -+ ldr w4, [x2, #GICH_HCR] -+ ldr w5, [x2, #GICH_VMCR] -+ ldr w6, [x2, #GICH_MISR] -+ ldr w7, [x2, #GICH_EISR0] -+ ldr w8, [x2, #GICH_EISR1] -+ ldr w9, [x2, #GICH_ELRSR0] -+ ldr w10, [x2, #GICH_ELRSR1] -+ ldr w11, [x2, #GICH_APR] -+CPU_BE( rev w4, w4 ) -+CPU_BE( rev w5, w5 ) -+CPU_BE( rev w6, w6 ) -+CPU_BE( rev w7, w7 ) -+CPU_BE( rev w8, w8 ) -+CPU_BE( rev w9, w9 ) -+CPU_BE( rev w10, w10 ) -+CPU_BE( rev w11, w11 ) -+ -+ str w4, [x3, #VGIC_V2_CPU_HCR] -+ str w5, [x3, #VGIC_V2_CPU_VMCR] -+ str w6, [x3, #VGIC_V2_CPU_MISR] -+ str w7, [x3, #VGIC_V2_CPU_EISR] -+ str w8, [x3, #(VGIC_V2_CPU_EISR + 4)] -+ str w9, [x3, #VGIC_V2_CPU_ELRSR] -+ str w10, [x3, #(VGIC_V2_CPU_ELRSR + 4)] -+ str w11, [x3, #VGIC_V2_CPU_APR] -+ -+ /* Clear GICH_HCR */ -+ str wzr, [x2, #GICH_HCR] -+ -+ /* Save list registers */ -+ add x2, x2, #GICH_LR0 -+ ldr w4, [x3, #VGIC_CPU_NR_LR] -+ add x3, x3, #VGIC_V2_CPU_LR -+1: ldr w5, [x2], #4 -+CPU_BE( rev w5, w5 ) -+ str w5, [x3], #4 -+ sub w4, w4, #1 -+ cbnz w4, 1b -+2: -+ ret -+ENDPROC(__save_vgic_v2_state) -+ -+/* -+ * Restore the VGIC CPU state from memory -+ * x0: Register pointing to VCPU struct -+ */ -+ENTRY(__restore_vgic_v2_state) -+__restore_vgic_v2_state: -+ /* Get VGIC VCTRL base into x2 */ -+ ldr x2, [x0, #VCPU_KVM] -+ kern_hyp_va x2 -+ ldr x2, [x2, #KVM_VGIC_VCTRL] -+ kern_hyp_va x2 -+ cbz x2, 2f // disabled -+ -+ /* Compute the address of struct vgic_cpu */ -+ add x3, x0, #VCPU_VGIC_CPU -+ -+ /* We only restore a minimal set of registers */ -+ ldr w4, [x3, #VGIC_V2_CPU_HCR] -+ ldr w5, [x3, #VGIC_V2_CPU_VMCR] -+ ldr w6, [x3, #VGIC_V2_CPU_APR] -+CPU_BE( rev w4, w4 ) -+CPU_BE( rev w5, w5 ) -+CPU_BE( rev w6, w6 ) -+ -+ str w4, [x2, #GICH_HCR] -+ str w5, [x2, #GICH_VMCR] -+ str w6, [x2, #GICH_APR] -+ -+ /* Restore list registers */ -+ add x2, x2, #GICH_LR0 -+ ldr w4, [x3, #VGIC_CPU_NR_LR] -+ add x3, x3, #VGIC_V2_CPU_LR -+1: ldr w5, [x3], #4 -+CPU_BE( rev w5, w5 ) -+ str w5, [x2], #4 -+ sub w4, w4, #1 -+ cbnz w4, 1b -+2: -+ ret -+ENDPROC(__restore_vgic_v2_state) -+ -+ .popsection -diff --git a/arch/arm64/kvm/vgic-v3-switch.S b/arch/arm64/kvm/vgic-v3-switch.S -new file mode 100644 -index 0000000..21e68f6 ---- /dev/null -+++ b/arch/arm64/kvm/vgic-v3-switch.S -@@ -0,0 +1,267 @@ -+/* -+ * Copyright (C) 2012,2013 - ARM Ltd -+ * Author: Marc Zyngier <marc.zyngier@arm.com> -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see <http://www.gnu.org/licenses/>. -+ */ ++static void psci_0_2_set_functions(void) ++{ ++ pr_info("Using standard PSCI v0.2 function IDs\n"); ++ psci_function_id[PSCI_FN_CPU_SUSPEND] = PSCI_0_2_FN64_CPU_SUSPEND; ++ psci_ops.cpu_suspend = psci_cpu_suspend; + -+#include <linux/linkage.h> -+#include <linux/irqchip/arm-gic-v3.h> ++ psci_function_id[PSCI_FN_CPU_OFF] = PSCI_0_2_FN_CPU_OFF; ++ psci_ops.cpu_off = psci_cpu_off; + -+#include <asm/assembler.h> -+#include <asm/memory.h> -+#include <asm/asm-offsets.h> -+#include <asm/kvm.h> -+#include <asm/kvm_asm.h> -+#include <asm/kvm_arm.h> ++ psci_function_id[PSCI_FN_CPU_ON] = PSCI_0_2_FN64_CPU_ON; ++ psci_ops.cpu_on = psci_cpu_on; + -+ .text -+ .pushsection .hyp.text, "ax" ++ psci_function_id[PSCI_FN_MIGRATE] = PSCI_0_2_FN64_MIGRATE; ++ psci_ops.migrate = psci_migrate; + -+/* -+ * We store LRs in reverse order to let the CPU deal with streaming -+ * access. Use this macro to make it look saner... -+ */ -+#define LR_OFFSET(n) (VGIC_V3_CPU_LR + (15 - n) * 8) ++ psci_function_id[PSCI_FN_AFFINITY_INFO] = PSCI_0_2_FN64_AFFINITY_INFO; ++ psci_ops.affinity_info = psci_affinity_info; + -+/* -+ * Save the VGIC CPU state into memory -+ * x0: Register pointing to VCPU struct -+ * Do not corrupt x1!!! -+ */ -+.macro save_vgic_v3_state -+ // Compute the address of struct vgic_cpu -+ add x3, x0, #VCPU_VGIC_CPU -+ -+ // Make sure stores to the GIC via the memory mapped interface -+ // are now visible to the system register interface -+ dsb st -+ -+ // Save all interesting registers -+ mrs x4, ICH_HCR_EL2 -+ mrs x5, ICH_VMCR_EL2 -+ mrs x6, ICH_MISR_EL2 -+ mrs x7, ICH_EISR_EL2 -+ mrs x8, ICH_ELSR_EL2 -+ -+ str w4, [x3, #VGIC_V3_CPU_HCR] -+ str w5, [x3, #VGIC_V3_CPU_VMCR] -+ str w6, [x3, #VGIC_V3_CPU_MISR] -+ str w7, [x3, #VGIC_V3_CPU_EISR] -+ str w8, [x3, #VGIC_V3_CPU_ELRSR] -+ -+ msr ICH_HCR_EL2, xzr -+ -+ mrs x21, ICH_VTR_EL2 -+ mvn w22, w21 -+ ubfiz w23, w22, 2, 4 // w23 = (15 - ListRegs) * 4 -+ -+ adr x24, 1f -+ add x24, x24, x23 -+ br x24 -+ -+1: -+ mrs x20, ICH_LR15_EL2 -+ mrs x19, ICH_LR14_EL2 -+ mrs x18, ICH_LR13_EL2 -+ mrs x17, ICH_LR12_EL2 -+ mrs x16, ICH_LR11_EL2 -+ mrs x15, ICH_LR10_EL2 -+ mrs x14, ICH_LR9_EL2 -+ mrs x13, ICH_LR8_EL2 -+ mrs x12, ICH_LR7_EL2 -+ mrs x11, ICH_LR6_EL2 -+ mrs x10, ICH_LR5_EL2 -+ mrs x9, ICH_LR4_EL2 -+ mrs x8, ICH_LR3_EL2 -+ mrs x7, ICH_LR2_EL2 -+ mrs x6, ICH_LR1_EL2 -+ mrs x5, ICH_LR0_EL2 -+ -+ adr x24, 1f -+ add x24, x24, x23 -+ br x24 -+ -+1: -+ str x20, [x3, #LR_OFFSET(15)] -+ str x19, [x3, #LR_OFFSET(14)] -+ str x18, [x3, #LR_OFFSET(13)] -+ str x17, [x3, #LR_OFFSET(12)] -+ str x16, [x3, #LR_OFFSET(11)] -+ str x15, [x3, #LR_OFFSET(10)] -+ str x14, [x3, #LR_OFFSET(9)] -+ str x13, [x3, #LR_OFFSET(8)] -+ str x12, [x3, #LR_OFFSET(7)] -+ str x11, [x3, #LR_OFFSET(6)] -+ str x10, [x3, #LR_OFFSET(5)] -+ str x9, [x3, #LR_OFFSET(4)] -+ str x8, [x3, #LR_OFFSET(3)] -+ str x7, [x3, #LR_OFFSET(2)] -+ str x6, [x3, #LR_OFFSET(1)] -+ str x5, [x3, #LR_OFFSET(0)] -+ -+ tbnz w21, #29, 6f // 6 bits -+ tbz w21, #30, 5f // 5 bits -+ // 7 bits -+ mrs x20, ICH_AP0R3_EL2 -+ str w20, [x3, #(VGIC_V3_CPU_AP0R + 3*4)] -+ mrs x19, ICH_AP0R2_EL2 -+ str w19, [x3, #(VGIC_V3_CPU_AP0R + 2*4)] -+6: mrs x18, ICH_AP0R1_EL2 -+ str w18, [x3, #(VGIC_V3_CPU_AP0R + 1*4)] -+5: mrs x17, ICH_AP0R0_EL2 -+ str w17, [x3, #VGIC_V3_CPU_AP0R] -+ -+ tbnz w21, #29, 6f // 6 bits -+ tbz w21, #30, 5f // 5 bits -+ // 7 bits -+ mrs x20, ICH_AP1R3_EL2 -+ str w20, [x3, #(VGIC_V3_CPU_AP1R + 3*4)] -+ mrs x19, ICH_AP1R2_EL2 -+ str w19, [x3, #(VGIC_V3_CPU_AP1R + 2*4)] -+6: mrs x18, ICH_AP1R1_EL2 -+ str w18, [x3, #(VGIC_V3_CPU_AP1R + 1*4)] -+5: mrs x17, ICH_AP1R0_EL2 -+ str w17, [x3, #VGIC_V3_CPU_AP1R] -+ -+ // Restore SRE_EL1 access and re-enable SRE at EL1. -+ mrs x5, ICC_SRE_EL2 -+ orr x5, x5, #ICC_SRE_EL2_ENABLE -+ msr ICC_SRE_EL2, x5 -+ isb -+ mov x5, #1 -+ msr ICC_SRE_EL1, x5 -+.endm ++ psci_function_id[PSCI_FN_MIGRATE_INFO_TYPE] = ++ PSCI_0_2_FN_MIGRATE_INFO_TYPE; ++ psci_ops.migrate_info_type = psci_migrate_info_type; + -+/* -+ * Restore the VGIC CPU state from memory -+ * x0: Register pointing to VCPU struct -+ */ -+.macro restore_vgic_v3_state -+ // Disable SRE_EL1 access. Necessary, otherwise -+ // ICH_VMCR_EL2.VFIQEn becomes one, and FIQ happens... -+ msr ICC_SRE_EL1, xzr -+ isb -+ -+ // Compute the address of struct vgic_cpu -+ add x3, x0, #VCPU_VGIC_CPU -+ -+ // Restore all interesting registers -+ ldr w4, [x3, #VGIC_V3_CPU_HCR] -+ ldr w5, [x3, #VGIC_V3_CPU_VMCR] -+ -+ msr ICH_HCR_EL2, x4 -+ msr ICH_VMCR_EL2, x5 -+ -+ mrs x21, ICH_VTR_EL2 -+ -+ tbnz w21, #29, 6f // 6 bits -+ tbz w21, #30, 5f // 5 bits -+ // 7 bits -+ ldr w20, [x3, #(VGIC_V3_CPU_AP1R + 3*4)] -+ msr ICH_AP1R3_EL2, x20 -+ ldr w19, [x3, #(VGIC_V3_CPU_AP1R + 2*4)] -+ msr ICH_AP1R2_EL2, x19 -+6: ldr w18, [x3, #(VGIC_V3_CPU_AP1R + 1*4)] -+ msr ICH_AP1R1_EL2, x18 -+5: ldr w17, [x3, #VGIC_V3_CPU_AP1R] -+ msr ICH_AP1R0_EL2, x17 -+ -+ tbnz w21, #29, 6f // 6 bits -+ tbz w21, #30, 5f // 5 bits -+ // 7 bits -+ ldr w20, [x3, #(VGIC_V3_CPU_AP0R + 3*4)] -+ msr ICH_AP0R3_EL2, x20 -+ ldr w19, [x3, #(VGIC_V3_CPU_AP0R + 2*4)] -+ msr ICH_AP0R2_EL2, x19 -+6: ldr w18, [x3, #(VGIC_V3_CPU_AP0R + 1*4)] -+ msr ICH_AP0R1_EL2, x18 -+5: ldr w17, [x3, #VGIC_V3_CPU_AP0R] -+ msr ICH_AP0R0_EL2, x17 -+ -+ and w22, w21, #0xf -+ mvn w22, w21 -+ ubfiz w23, w22, 2, 4 // w23 = (15 - ListRegs) * 4 -+ -+ adr x24, 1f -+ add x24, x24, x23 -+ br x24 -+ -+1: -+ ldr x20, [x3, #LR_OFFSET(15)] -+ ldr x19, [x3, #LR_OFFSET(14)] -+ ldr x18, [x3, #LR_OFFSET(13)] -+ ldr x17, [x3, #LR_OFFSET(12)] -+ ldr x16, [x3, #LR_OFFSET(11)] -+ ldr x15, [x3, #LR_OFFSET(10)] -+ ldr x14, [x3, #LR_OFFSET(9)] -+ ldr x13, [x3, #LR_OFFSET(8)] -+ ldr x12, [x3, #LR_OFFSET(7)] -+ ldr x11, [x3, #LR_OFFSET(6)] -+ ldr x10, [x3, #LR_OFFSET(5)] -+ ldr x9, [x3, #LR_OFFSET(4)] -+ ldr x8, [x3, #LR_OFFSET(3)] -+ ldr x7, [x3, #LR_OFFSET(2)] -+ ldr x6, [x3, #LR_OFFSET(1)] -+ ldr x5, [x3, #LR_OFFSET(0)] -+ -+ adr x24, 1f -+ add x24, x24, x23 -+ br x24 -+ -+1: -+ msr ICH_LR15_EL2, x20 -+ msr ICH_LR14_EL2, x19 -+ msr ICH_LR13_EL2, x18 -+ msr ICH_LR12_EL2, x17 -+ msr ICH_LR11_EL2, x16 -+ msr ICH_LR10_EL2, x15 -+ msr ICH_LR9_EL2, x14 -+ msr ICH_LR8_EL2, x13 -+ msr ICH_LR7_EL2, x12 -+ msr ICH_LR6_EL2, x11 -+ msr ICH_LR5_EL2, x10 -+ msr ICH_LR4_EL2, x9 -+ msr ICH_LR3_EL2, x8 -+ msr ICH_LR2_EL2, x7 -+ msr ICH_LR1_EL2, x6 -+ msr ICH_LR0_EL2, x5 -+ -+ // Ensure that the above will have reached the -+ // (re)distributors. This ensure the guest will read -+ // the correct values from the memory-mapped interface. -+ isb -+ dsb sy -+ -+ // Prevent the guest from touching the GIC system registers -+ mrs x5, ICC_SRE_EL2 -+ and x5, x5, #~ICC_SRE_EL2_ENABLE -+ msr ICC_SRE_EL2, x5 -+.endm -+ -+ENTRY(__save_vgic_v3_state) -+ save_vgic_v3_state -+ ret -+ENDPROC(__save_vgic_v3_state) -+ -+ENTRY(__restore_vgic_v3_state) -+ restore_vgic_v3_state -+ ret -+ENDPROC(__restore_vgic_v3_state) -+ -+ENTRY(__vgic_v3_get_ich_vtr_el2) -+ mrs x0, ICH_VTR_EL2 -+ ret -+ENDPROC(__vgic_v3_get_ich_vtr_el2) -+ -+ .popsection -diff --git a/arch/ia64/kernel/process.c b/arch/ia64/kernel/process.c -index 55d4ba4..deed6fa 100644 ---- a/arch/ia64/kernel/process.c -+++ b/arch/ia64/kernel/process.c -@@ -662,7 +662,7 @@ void - machine_restart (char *restart_cmd) - { - (void) notify_die(DIE_MACHINE_RESTART, restart_cmd, NULL, 0, 0, 0); -- (*efi.reset_system)(EFI_RESET_WARM, 0, 0, NULL); -+ efi_reboot(REBOOT_WARM, NULL); - } - - void -diff --git a/arch/ia64/kernel/time.c b/arch/ia64/kernel/time.c -index 71c52bc..a149c67 100644 ---- a/arch/ia64/kernel/time.c -+++ b/arch/ia64/kernel/time.c -@@ -384,21 +384,6 @@ static struct irqaction timer_irqaction = { - .name = "timer" - }; - --static struct platform_device rtc_efi_dev = { -- .name = "rtc-efi", -- .id = -1, --}; -- --static int __init rtc_init(void) --{ -- if (platform_device_register(&rtc_efi_dev) < 0) -- printk(KERN_ERR "unable to register rtc device...\n"); -- -- /* not necessarily an error */ -- return 0; --} --module_init(rtc_init); -- - void read_persistent_clock(struct timespec *ts) - { - efi_gettimeofday(ts); -diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h -index 1eb5f64..5d71d0e 100644 ---- a/arch/x86/include/asm/efi.h -+++ b/arch/x86/include/asm/efi.h -@@ -104,6 +104,8 @@ extern void __init runtime_code_page_mkexec(void); - extern void __init efi_runtime_mkexec(void); - extern void __init efi_dump_pagetable(void); - extern void __init efi_apply_memmap_quirks(void); -+extern int __init efi_reuse_config(u64 tables, int nr_tables); -+extern void efi_delete_dummy_variable(void); - - struct efi_setup_data { - u64 fw_vendor; -@@ -156,6 +158,8 @@ static inline efi_status_t efi_thunk_set_virtual_address_map( - return EFI_SUCCESS; - } - #endif /* CONFIG_EFI_MIXED */ ++ arm_pm_restart = psci_sys_reset; + -+extern bool efi_reboot_required(void); - #else - /* - * IF EFI is not configured, have the EFI calls return -ENOSYS. -@@ -168,6 +172,10 @@ static inline efi_status_t efi_thunk_set_virtual_address_map( - #define efi_call5(_f, _a1, _a2, _a3, _a4, _a5) (-ENOSYS) - #define efi_call6(_f, _a1, _a2, _a3, _a4, _a5, _a6) (-ENOSYS) - static inline void parse_efi_setup(u64 phys_addr, u32 data_len) {} -+static inline bool efi_reboot_required(void) -+{ -+ return false; ++ pm_power_off = psci_sys_poweroff; +} - #endif /* CONFIG_EFI */ - - #endif /* _ASM_X86_EFI_H */ -diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c -index 52b1157..17962e6 100644 ---- a/arch/x86/kernel/reboot.c -+++ b/arch/x86/kernel/reboot.c -@@ -28,6 +28,7 @@ - #include <linux/mc146818rtc.h> - #include <asm/realmode.h> - #include <asm/x86_init.h> -+#include <asm/efi.h> - - /* - * Power off function, if any -@@ -401,12 +402,25 @@ static struct dmi_system_id __initdata reboot_dmi_table[] = { - - static int __init reboot_init(void) - { -+ int rv; + - /* - * Only do the DMI check if reboot_type hasn't been overridden - * on the command line - */ -- if (reboot_default) -- dmi_check_system(reboot_dmi_table); -+ if (!reboot_default) -+ return 0; -+ -+ /* -+ * The DMI quirks table takes precedence. If no quirks entry -+ * matches and the ACPI Hardware Reduced bit is set, force EFI -+ * reboot. -+ */ -+ rv = dmi_check_system(reboot_dmi_table); -+ -+ if (!rv && efi_reboot_required()) -+ reboot_type = BOOT_EFI; -+ - return 0; - } - core_initcall(reboot_init); -@@ -528,11 +542,7 @@ static void native_machine_emergency_restart(void) - break; - - case BOOT_EFI: -- if (efi_enabled(EFI_RUNTIME_SERVICES)) -- efi.reset_system(reboot_mode == REBOOT_WARM ? -- EFI_RESET_WARM : -- EFI_RESET_COLD, -- EFI_SUCCESS, 0, NULL); -+ efi_reboot(reboot_mode, NULL); - reboot_type = BOOT_BIOS; - break; - -diff --git a/arch/x86/platform/efi/Makefile b/arch/x86/platform/efi/Makefile -index d51045a..2846aaa 100644 ---- a/arch/x86/platform/efi/Makefile -+++ b/arch/x86/platform/efi/Makefile -@@ -1,4 +1,4 @@ --obj-$(CONFIG_EFI) += efi.o efi_$(BITS).o efi_stub_$(BITS).o -+obj-$(CONFIG_EFI) += quirks.o efi.o efi_$(BITS).o efi_stub_$(BITS).o - obj-$(CONFIG_ACPI_BGRT) += efi-bgrt.o - obj-$(CONFIG_EARLY_PRINTK_EFI) += early_printk.o - obj-$(CONFIG_EFI_MIXED) += efi_thunk_$(BITS).o -diff --git a/arch/x86/platform/efi/efi.c b/arch/x86/platform/efi/efi.c -index 87fc96b..f852443 100644 ---- a/arch/x86/platform/efi/efi.c -+++ b/arch/x86/platform/efi/efi.c -@@ -56,13 +56,6 @@ - - #define EFI_DEBUG - --#define EFI_MIN_RESERVE 5120 -- --#define EFI_DUMMY_GUID \ -- EFI_GUID(0x4424ac57, 0xbe4b, 0x47dd, 0x9e, 0x97, 0xed, 0x50, 0xf0, 0x9f, 0x92, 0xa9) -- --static efi_char16_t efi_dummy_name[6] = { 'D', 'U', 'M', 'M', 'Y', 0 }; -- - struct efi_memory_map memmap; - - static struct efi efi_phys __initdata; -@@ -95,15 +88,6 @@ static int __init setup_add_efi_memmap(char *arg) - } - early_param("add_efi_memmap", setup_add_efi_memmap); - --static bool efi_no_storage_paranoia; -- --static int __init setup_storage_paranoia(char *arg) --{ -- efi_no_storage_paranoia = true; -- return 0; --} --early_param("efi_no_storage_paranoia", setup_storage_paranoia); -- - static efi_status_t virt_efi_get_time(efi_time_t *tm, efi_time_cap_t *tc) - { - unsigned long flags; -@@ -392,37 +376,6 @@ static void __init print_efi_memmap(void) - #endif /* EFI_DEBUG */ - } - --void __init efi_reserve_boot_services(void) --{ -- void *p; -- -- for (p = memmap.map; p < memmap.map_end; p += memmap.desc_size) { -- efi_memory_desc_t *md = p; -- u64 start = md->phys_addr; -- u64 size = md->num_pages << EFI_PAGE_SHIFT; -- -- if (md->type != EFI_BOOT_SERVICES_CODE && -- md->type != EFI_BOOT_SERVICES_DATA) -- continue; -- /* Only reserve where possible: -- * - Not within any already allocated areas -- * - Not over any memory area (really needed, if above?) -- * - Not within any part of the kernel -- * - Not the bios reserved area -- */ -- if ((start + size > __pa_symbol(_text) -- && start <= __pa_symbol(_end)) || -- !e820_all_mapped(start, start+size, E820_RAM) || -- memblock_is_region_reserved(start, size)) { -- /* Could not reserve, skip it */ -- md->num_pages = 0; -- memblock_dbg("Could not reserve boot range [0x%010llx-0x%010llx]\n", -- start, start+size-1); -- } else -- memblock_reserve(start, size); -- } --} -- - void __init efi_unmap_memmap(void) - { - clear_bit(EFI_MEMMAP, &efi.flags); -@@ -432,29 +385,6 @@ void __init efi_unmap_memmap(void) + /* + * PSCI Function IDs for v0.2+ are well defined so use + * standard values. +@@ -264,29 +293,7 @@ static int __init psci_0_2_init(struct device_node *np) + } } - } --void __init efi_free_boot_services(void) --{ -- void *p; +- pr_info("Using standard PSCI v0.2 function IDs\n"); +- psci_function_id[PSCI_FN_CPU_SUSPEND] = PSCI_0_2_FN64_CPU_SUSPEND; +- psci_ops.cpu_suspend = psci_cpu_suspend; - -- for (p = memmap.map; p < memmap.map_end; p += memmap.desc_size) { -- efi_memory_desc_t *md = p; -- unsigned long long start = md->phys_addr; -- unsigned long long size = md->num_pages << EFI_PAGE_SHIFT; +- psci_function_id[PSCI_FN_CPU_OFF] = PSCI_0_2_FN_CPU_OFF; +- psci_ops.cpu_off = psci_cpu_off; - -- if (md->type != EFI_BOOT_SERVICES_CODE && -- md->type != EFI_BOOT_SERVICES_DATA) -- continue; +- psci_function_id[PSCI_FN_CPU_ON] = PSCI_0_2_FN64_CPU_ON; +- psci_ops.cpu_on = psci_cpu_on; - -- /* Could not reserve boot area */ -- if (!size) -- continue; +- psci_function_id[PSCI_FN_MIGRATE] = PSCI_0_2_FN64_MIGRATE; +- psci_ops.migrate = psci_migrate; - -- free_bootmem_late(start, size); -- } -- -- efi_unmap_memmap(); --} -- - static int __init efi_systab_init(void *phys) - { - if (efi_enabled(EFI_64BIT)) { -@@ -649,62 +579,6 @@ static int __init efi_memmap_init(void) - return 0; - } - --/* -- * A number of config table entries get remapped to virtual addresses -- * after entering EFI virtual mode. However, the kexec kernel requires -- * their physical addresses therefore we pass them via setup_data and -- * correct those entries to their respective physical addresses here. -- * -- * Currently only handles smbios which is necessary for some firmware -- * implementation. -- */ --static int __init efi_reuse_config(u64 tables, int nr_tables) --{ -- int i, sz, ret = 0; -- void *p, *tablep; -- struct efi_setup_data *data; -- -- if (!efi_setup) -- return 0; -- -- if (!efi_enabled(EFI_64BIT)) -- return 0; -- -- data = early_memremap(efi_setup, sizeof(*data)); -- if (!data) { -- ret = -ENOMEM; -- goto out; -- } -- -- if (!data->smbios) -- goto out_memremap; -- -- sz = sizeof(efi_config_table_64_t); -- -- p = tablep = early_memremap(tables, nr_tables * sz); -- if (!p) { -- pr_err("Could not map Configuration table!\n"); -- ret = -ENOMEM; -- goto out_memremap; -- } +- psci_function_id[PSCI_FN_AFFINITY_INFO] = PSCI_0_2_FN64_AFFINITY_INFO; +- psci_ops.affinity_info = psci_affinity_info; - -- for (i = 0; i < efi.systab->nr_tables; i++) { -- efi_guid_t guid; +- psci_function_id[PSCI_FN_MIGRATE_INFO_TYPE] = +- PSCI_0_2_FN_MIGRATE_INFO_TYPE; +- psci_ops.migrate_info_type = psci_migrate_info_type; - -- guid = ((efi_config_table_64_t *)p)->guid; +- arm_pm_restart = psci_sys_reset; - -- if (!efi_guidcmp(guid, SMBIOS_TABLE_GUID)) -- ((efi_config_table_64_t *)p)->table = data->smbios; -- p += sz; -- } -- early_iounmap(tablep, nr_tables * sz); -- --out_memremap: -- early_iounmap(data, sizeof(*data)); --out: -- return ret; --} -- - void __init efi_init(void) - { - efi_char16_t *c16; -@@ -1057,11 +931,7 @@ static void __init kexec_enter_virtual_mode(void) - runtime_code_page_mkexec(); - - /* clean DUMMY object */ -- efi.set_variable(efi_dummy_name, &EFI_DUMMY_GUID, -- EFI_VARIABLE_NON_VOLATILE | -- EFI_VARIABLE_BOOTSERVICE_ACCESS | -- EFI_VARIABLE_RUNTIME_ACCESS, -- 0, NULL); -+ efi_delete_dummy_variable(); - #endif - } - -@@ -1179,11 +1049,7 @@ static void __init __efi_enter_virtual_mode(void) - free_pages((unsigned long)new_memmap, pg_shift); +- pm_power_off = psci_sys_poweroff; ++ psci_0_2_set_functions(); - /* clean DUMMY object */ -- efi.set_variable(efi_dummy_name, &EFI_DUMMY_GUID, -- EFI_VARIABLE_NON_VOLATILE | -- EFI_VARIABLE_BOOTSERVICE_ACCESS | -- EFI_VARIABLE_RUNTIME_ACCESS, -- 0, NULL); -+ efi_delete_dummy_variable(); - } - - void __init efi_enter_virtual_mode(void) -@@ -1230,86 +1096,6 @@ u64 efi_mem_attributes(unsigned long phys_addr) - return 0; - } + out_put_node: + of_node_put(np); +@@ -339,7 +346,7 @@ static const struct of_device_id psci_of_match[] __initconst = { + {}, + }; --/* -- * Some firmware implementations refuse to boot if there's insufficient space -- * in the variable store. Ensure that we never use more than a safe limit. -- * -- * Return EFI_SUCCESS if it is safe to write 'size' bytes to the variable -- * store. -- */ --efi_status_t efi_query_variable_store(u32 attributes, unsigned long size) --{ -- efi_status_t status; -- u64 storage_size, remaining_size, max_size; -- -- if (!(attributes & EFI_VARIABLE_NON_VOLATILE)) -- return 0; -- -- status = efi.query_variable_info(attributes, &storage_size, -- &remaining_size, &max_size); -- if (status != EFI_SUCCESS) -- return status; -- -- /* -- * We account for that by refusing the write if permitting it would -- * reduce the available space to under 5KB. This figure was provided by -- * Samsung, so should be safe. -- */ -- if ((remaining_size - size < EFI_MIN_RESERVE) && -- !efi_no_storage_paranoia) { -- -- /* -- * Triggering garbage collection may require that the firmware -- * generate a real EFI_OUT_OF_RESOURCES error. We can force -- * that by attempting to use more space than is available. -- */ -- unsigned long dummy_size = remaining_size + 1024; -- void *dummy = kzalloc(dummy_size, GFP_ATOMIC); -- -- if (!dummy) -- return EFI_OUT_OF_RESOURCES; -- -- status = efi.set_variable(efi_dummy_name, &EFI_DUMMY_GUID, -- EFI_VARIABLE_NON_VOLATILE | -- EFI_VARIABLE_BOOTSERVICE_ACCESS | -- EFI_VARIABLE_RUNTIME_ACCESS, -- dummy_size, dummy); -- -- if (status == EFI_SUCCESS) { -- /* -- * This should have failed, so if it didn't make sure -- * that we delete it... -- */ -- efi.set_variable(efi_dummy_name, &EFI_DUMMY_GUID, -- EFI_VARIABLE_NON_VOLATILE | -- EFI_VARIABLE_BOOTSERVICE_ACCESS | -- EFI_VARIABLE_RUNTIME_ACCESS, -- 0, dummy); -- } -- -- kfree(dummy); -- -- /* -- * The runtime code may now have triggered a garbage collection -- * run, so check the variable info again -- */ -- status = efi.query_variable_info(attributes, &storage_size, -- &remaining_size, &max_size); -- -- if (status != EFI_SUCCESS) -- return status; -- -- /* -- * There still isn't enough room, so return an error -- */ -- if (remaining_size - size < EFI_MIN_RESERVE) -- return EFI_OUT_OF_RESOURCES; -- } -- -- return EFI_SUCCESS; --} --EXPORT_SYMBOL_GPL(efi_query_variable_store); -- - static int __init parse_efi_cmdline(char *str) +-int __init psci_init(void) ++int __init psci_dt_init(void) { - if (*str == '=') -@@ -1321,22 +1107,3 @@ static int __init parse_efi_cmdline(char *str) - return 0; + struct device_node *np; + const struct of_device_id *matched_np; +@@ -354,6 +361,29 @@ int __init psci_init(void) + return init_fn(np); } - early_param("efi", parse_efi_cmdline); -- --void __init efi_apply_memmap_quirks(void) --{ -- /* -- * Once setup is done earlier, unmap the EFI memory map on mismatched -- * firmware/kernel architectures since there is no support for runtime -- * services. -- */ -- if (!efi_runtime_supported()) { -- pr_info("efi: Setup done, disabling due to 32/64-bit mismatch\n"); -- efi_unmap_memmap(); -- } -- -- /* -- * UV doesn't support the new EFI pagetable mapping yet. -- */ -- if (is_uv_system()) -- set_bit(EFI_OLD_MEMMAP, &efi.flags); --} -diff --git a/arch/x86/platform/efi/quirks.c b/arch/x86/platform/efi/quirks.c -new file mode 100644 -index 0000000..1b9c4c3 ---- /dev/null -+++ b/arch/x86/platform/efi/quirks.c -@@ -0,0 +1,290 @@ -+#include <linux/init.h> -+#include <linux/kernel.h> -+#include <linux/string.h> -+#include <linux/time.h> -+#include <linux/types.h> -+#include <linux/efi.h> -+#include <linux/slab.h> -+#include <linux/memblock.h> -+#include <linux/bootmem.h> -+#include <linux/acpi.h> -+#include <asm/efi.h> -+#include <asm/uv/uv.h> -+ -+#define EFI_MIN_RESERVE 5120 -+ -+#define EFI_DUMMY_GUID \ -+ EFI_GUID(0x4424ac57, 0xbe4b, 0x47dd, 0x9e, 0x97, 0xed, 0x50, 0xf0, 0x9f, 0x92, 0xa9) -+ -+static efi_char16_t efi_dummy_name[6] = { 'D', 'U', 'M', 'M', 'Y', 0 }; -+ -+static bool efi_no_storage_paranoia; -+ -+/* -+ * Some firmware implementations refuse to boot if there's insufficient -+ * space in the variable store. The implementation of garbage collection -+ * in some FW versions causes stale (deleted) variables to take up space -+ * longer than intended and space is only freed once the store becomes -+ * almost completely full. -+ * -+ * Enabling this option disables the space checks in -+ * efi_query_variable_store() and forces garbage collection. -+ * -+ * Only enable this option if deleting EFI variables does not free up -+ * space in your variable store, e.g. if despite deleting variables -+ * you're unable to create new ones. -+ */ -+static int __init setup_storage_paranoia(char *arg) -+{ -+ efi_no_storage_paranoia = true; -+ return 0; -+} -+early_param("efi_no_storage_paranoia", setup_storage_paranoia); -+ -+/* -+ * Deleting the dummy variable which kicks off garbage collection -+*/ -+void efi_delete_dummy_variable(void) -+{ -+ efi.set_variable(efi_dummy_name, &EFI_DUMMY_GUID, -+ EFI_VARIABLE_NON_VOLATILE | -+ EFI_VARIABLE_BOOTSERVICE_ACCESS | -+ EFI_VARIABLE_RUNTIME_ACCESS, -+ 0, NULL); -+} -+ + +/* -+ * Some firmware implementations refuse to boot if there's insufficient space -+ * in the variable store. Ensure that we never use more than a safe limit. -+ * -+ * Return EFI_SUCCESS if it is safe to write 'size' bytes to the variable -+ * store. ++ * We use PSCI 0.2+ when ACPI is deployed on ARM64 and it's ++ * explicitly clarified in SBBR + */ -+efi_status_t efi_query_variable_store(u32 attributes, unsigned long size) ++int __init psci_acpi_init(void) +{ -+ efi_status_t status; -+ u64 storage_size, remaining_size, max_size; -+ -+ if (!(attributes & EFI_VARIABLE_NON_VOLATILE)) -+ return 0; -+ -+ status = efi.query_variable_info(attributes, &storage_size, -+ &remaining_size, &max_size); -+ if (status != EFI_SUCCESS) -+ return status; -+ -+ /* -+ * We account for that by refusing the write if permitting it would -+ * reduce the available space to under 5KB. This figure was provided by -+ * Samsung, so should be safe. -+ */ -+ if ((remaining_size - size < EFI_MIN_RESERVE) && -+ !efi_no_storage_paranoia) { -+ -+ /* -+ * Triggering garbage collection may require that the firmware -+ * generate a real EFI_OUT_OF_RESOURCES error. We can force -+ * that by attempting to use more space than is available. -+ */ -+ unsigned long dummy_size = remaining_size + 1024; -+ void *dummy = kzalloc(dummy_size, GFP_ATOMIC); -+ -+ if (!dummy) -+ return EFI_OUT_OF_RESOURCES; -+ -+ status = efi.set_variable(efi_dummy_name, &EFI_DUMMY_GUID, -+ EFI_VARIABLE_NON_VOLATILE | -+ EFI_VARIABLE_BOOTSERVICE_ACCESS | -+ EFI_VARIABLE_RUNTIME_ACCESS, -+ dummy_size, dummy); -+ -+ if (status == EFI_SUCCESS) { -+ /* -+ * This should have failed, so if it didn't make sure -+ * that we delete it... -+ */ -+ efi_delete_dummy_variable(); -+ } -+ -+ kfree(dummy); -+ -+ /* -+ * The runtime code may now have triggered a garbage collection -+ * run, so check the variable info again -+ */ -+ status = efi.query_variable_info(attributes, &storage_size, -+ &remaining_size, &max_size); -+ -+ if (status != EFI_SUCCESS) -+ return status; -+ -+ /* -+ * There still isn't enough room, so return an error -+ */ -+ if (remaining_size - size < EFI_MIN_RESERVE) -+ return EFI_OUT_OF_RESOURCES; ++ if (!acpi_psci_present()) { ++ pr_info("is not implemented in ACPI.\n"); ++ return -EOPNOTSUPP; + } + -+ return EFI_SUCCESS; -+} -+EXPORT_SYMBOL_GPL(efi_query_variable_store); -+ -+/* -+ * The UEFI specification makes it clear that the operating system is free to do -+ * whatever it wants with boot services code after ExitBootServices() has been -+ * called. Ignoring this recommendation a significant bunch of EFI implementations -+ * continue calling into boot services code (SetVirtualAddressMap). In order to -+ * work around such buggy implementations we reserve boot services region during -+ * EFI init and make sure it stays executable. Then, after SetVirtualAddressMap(), it -+* is discarded. -+*/ -+void __init efi_reserve_boot_services(void) -+{ -+ void *p; -+ -+ for (p = memmap.map; p < memmap.map_end; p += memmap.desc_size) { -+ efi_memory_desc_t *md = p; -+ u64 start = md->phys_addr; -+ u64 size = md->num_pages << EFI_PAGE_SHIFT; -+ -+ if (md->type != EFI_BOOT_SERVICES_CODE && -+ md->type != EFI_BOOT_SERVICES_DATA) -+ continue; -+ /* Only reserve where possible: -+ * - Not within any already allocated areas -+ * - Not over any memory area (really needed, if above?) -+ * - Not within any part of the kernel -+ * - Not the bios reserved area -+ */ -+ if ((start + size > __pa_symbol(_text) -+ && start <= __pa_symbol(_end)) || -+ !e820_all_mapped(start, start+size, E820_RAM) || -+ memblock_is_region_reserved(start, size)) { -+ /* Could not reserve, skip it */ -+ md->num_pages = 0; -+ memblock_dbg("Could not reserve boot range [0x%010llx-0x%010llx]\n", -+ start, start+size-1); -+ } else -+ memblock_reserve(start, size); -+ } -+} -+ -+void __init efi_free_boot_services(void) -+{ -+ void *p; -+ -+ for (p = memmap.map; p < memmap.map_end; p += memmap.desc_size) { -+ efi_memory_desc_t *md = p; -+ unsigned long long start = md->phys_addr; -+ unsigned long long size = md->num_pages << EFI_PAGE_SHIFT; ++ pr_info("probing for conduit method from ACPI.\n"); + -+ if (md->type != EFI_BOOT_SERVICES_CODE && -+ md->type != EFI_BOOT_SERVICES_DATA) -+ continue; ++ if (acpi_psci_use_hvc()) ++ invoke_psci_fn = __invoke_psci_fn_hvc; ++ else ++ invoke_psci_fn = __invoke_psci_fn_smc; + -+ /* Could not reserve boot area */ -+ if (!size) -+ continue; ++ psci_0_2_set_functions(); + -+ free_bootmem_late(start, size); -+ } -+ -+ efi_unmap_memmap(); ++ return 0; +} + -+/* -+ * A number of config table entries get remapped to virtual addresses -+ * after entering EFI virtual mode. However, the kexec kernel requires -+ * their physical addresses therefore we pass them via setup_data and -+ * correct those entries to their respective physical addresses here. -+ * -+ * Currently only handles smbios which is necessary for some firmware -+ * implementation. -+ */ -+int __init efi_reuse_config(u64 tables, int nr_tables) -+{ -+ int i, sz, ret = 0; -+ void *p, *tablep; -+ struct efi_setup_data *data; -+ -+ if (!efi_setup) -+ return 0; -+ -+ if (!efi_enabled(EFI_64BIT)) -+ return 0; -+ -+ data = early_memremap(efi_setup, sizeof(*data)); -+ if (!data) { -+ ret = -ENOMEM; -+ goto out; -+ } -+ -+ if (!data->smbios) -+ goto out_memremap; -+ -+ sz = sizeof(efi_config_table_64_t); -+ -+ p = tablep = early_memremap(tables, nr_tables * sz); -+ if (!p) { -+ pr_err("Could not map Configuration table!\n"); -+ ret = -ENOMEM; -+ goto out_memremap; -+ } -+ -+ for (i = 0; i < efi.systab->nr_tables; i++) { -+ efi_guid_t guid; -+ -+ guid = ((efi_config_table_64_t *)p)->guid; + #ifdef CONFIG_SMP + + static int __init cpu_psci_cpu_init(struct device_node *dn, unsigned int cpu) +diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c +index edb146d..a793a20 100644 +--- a/arch/arm64/kernel/setup.c ++++ b/arch/arm64/kernel/setup.c +@@ -43,6 +43,7 @@ + #include <linux/of_fdt.h> + #include <linux/of_platform.h> + #include <linux/efi.h> ++#include <linux/acpi.h> + + #include <asm/fixmap.h> + #include <asm/cpu.h> +@@ -59,6 +60,10 @@ + #include <asm/memblock.h> + #include <asm/psci.h> + #include <asm/efi.h> ++#include <asm/acpi.h> + -+ if (!efi_guidcmp(guid, SMBIOS_TABLE_GUID)) -+ ((efi_config_table_64_t *)p)->table = data->smbios; -+ p += sz; -+ } -+ early_iounmap(tablep, nr_tables * sz); ++int acadia_kvm_acpi=0; ++EXPORT_SYMBOL(acadia_kvm_acpi); + + unsigned int processor_id; + EXPORT_SYMBOL(processor_id); +@@ -385,22 +390,34 @@ void __init setup_arch(char **cmdline_p) + + parse_early_param(); + ++ if (acpi_disabled) ++ disable_acpi(); + -+out_memremap: -+ early_iounmap(data, sizeof(*data)); -+out: -+ return ret; -+} + efi_init(); + arm64_memblock_init(); + ++ /* Parse the ACPI tables for possible boot-time configuration */ ++ acpi_boot_table_init(); + -+void __init efi_apply_memmap_quirks(void) -+{ -+ /* -+ * Once setup is done earlier, unmap the EFI memory map on mismatched -+ * firmware/kernel architectures since there is no support for runtime -+ * services. -+ */ -+ if (!efi_runtime_supported()) { -+ pr_info("efi: Setup done, disabling due to 32/64-bit mismatch\n"); -+ efi_unmap_memmap(); + paging_init(); + request_standard_resources(); + + efi_idmap_init(); + +- unflatten_device_tree(); +- +- psci_init(); +- + cpu_logical_map(0) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; +- cpu_read_bootcpu_ops(); ++ if (acpi_disabled) { ++ unflatten_device_tree(); ++ psci_dt_init(); ++ cpu_read_bootcpu_ops(); ++#ifdef CONFIG_SMP ++ of_smp_init_cpus(); ++#endif ++ } else { ++ psci_acpi_init(); ++ acpi_smp_init_cpus(); + } + -+ /* -+ * UV doesn't support the new EFI pagetable mapping yet. -+ */ -+ if (is_uv_system()) -+ set_bit(EFI_OLD_MEMMAP, &efi.flags); -+} -+ -+/* -+ * For most modern platforms the preferred method of powering off is via -+ * ACPI. However, there are some that are known to require the use of -+ * EFI runtime services and for which ACPI does not work at all. -+ * -+ * Using EFI is a last resort, to be used only if no other option -+ * exists. -+ */ -+bool efi_reboot_required(void) -+{ -+ if (!acpi_gbl_reduced_hardware) -+ return false; -+ -+ efi_reboot_quirk_mode = EFI_RESET_WARM; -+ return true; -+} -+ -+bool efi_poweroff_required(void) -+{ -+ return !!acpi_gbl_reduced_hardware; -+} -diff --git a/drivers/ata/ahci_xgene.c b/drivers/ata/ahci_xgene.c -index ee3a365..f9431b4 100644 ---- a/drivers/ata/ahci_xgene.c -+++ b/drivers/ata/ahci_xgene.c -@@ -131,7 +131,8 @@ static unsigned int xgene_ahci_qc_issue(struct ata_queued_cmd *qc) - struct xgene_ahci_context *ctx = hpriv->plat_data; - int rc = 0; + #ifdef CONFIG_SMP +- smp_init_cpus(); + smp_build_mpidr_hash(); + #endif -- if (unlikely(ctx->last_cmd[ap->port_no] == ATA_CMD_ID_ATA)) -+ if (unlikely(ctx->last_cmd[ap->port_no] == ATA_CMD_ID_ATA || -+ ctx->last_cmd[ap->port_no] == ATA_CMD_SMART)) - xgene_ahci_restart_engine(ap); +@@ -413,6 +430,19 @@ void __init setup_arch(char **cmdline_p) + #endif + } - rc = ahci_qc_issue(qc); -diff --git a/drivers/firmware/efi/Makefile b/drivers/firmware/efi/Makefile -index 9553496..c135154 100644 ---- a/drivers/firmware/efi/Makefile -+++ b/drivers/firmware/efi/Makefile -@@ -1,7 +1,7 @@ - # - # Makefile for linux kernel - # --obj-$(CONFIG_EFI) += efi.o vars.o -+obj-$(CONFIG_EFI) += efi.o vars.o reboot.o - obj-$(CONFIG_EFI_VARS) += efivars.o - obj-$(CONFIG_EFI_VARS_PSTORE) += efi-pstore.o - obj-$(CONFIG_UEFI_CPER) += cper.o -diff --git a/drivers/firmware/efi/reboot.c b/drivers/firmware/efi/reboot.c -new file mode 100644 -index 0000000..f94fb95 ---- /dev/null -+++ b/drivers/firmware/efi/reboot.c -@@ -0,0 +1,55 @@ -+/* -+ * Copyright (C) 2014 Intel Corporation; author Matt Fleming -+ */ -+#include <linux/efi.h> -+#include <linux/reboot.h> -+ -+int efi_reboot_quirk_mode = -1; -+ -+void efi_reboot(enum reboot_mode reboot_mode, const char *__unused) ++static int __init parse_kvm_acpi(char *arg) +{ -+ int efi_mode; -+ -+ if (!efi_enabled(EFI_RUNTIME_SERVICES)) -+ return; -+ -+ switch (reboot_mode) { -+ case REBOOT_WARM: -+ case REBOOT_SOFT: -+ efi_mode = EFI_RESET_WARM; -+ break; -+ default: -+ efi_mode = EFI_RESET_COLD; -+ break; ++ if (!arg) ++ return -EINVAL; ++ ++ if (strcmp(arg, "on") == 0) { ++ acadia_kvm_acpi = 1; + } + -+ /* -+ * If a quirk forced an EFI reset mode, always use that. -+ */ -+ if (efi_reboot_quirk_mode != -1) -+ efi_mode = efi_reboot_quirk_mode; -+ -+ efi.reset_system(efi_mode, EFI_SUCCESS, 0, NULL); -+} -+ -+bool __weak efi_poweroff_required(void) -+{ -+ return false; -+} -+ -+static void efi_power_off(void) -+{ -+ efi.reset_system(EFI_RESET_SHUTDOWN, EFI_SUCCESS, 0, NULL); -+} -+ -+static int __init efi_shutdown_init(void) -+{ -+ if (!efi_enabled(EFI_RUNTIME_SERVICES)) -+ return -ENODEV; -+ -+ if (efi_poweroff_required()) -+ pm_power_off = efi_power_off; -+ + return 0; +} -+late_initcall(efi_shutdown_init); -diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig -index bbb746e..7f0c2a3 100644 ---- a/drivers/irqchip/Kconfig -+++ b/drivers/irqchip/Kconfig -@@ -10,6 +10,11 @@ config ARM_GIC - config GIC_NON_BANKED - bool - -+config ARM_GIC_V3 -+ bool -+ select IRQ_DOMAIN -+ select MULTI_IRQ_HANDLER ++early_param("kvmacpi", parse_kvm_acpi); ++ + static int __init arm64_device_init(void) + { + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +@@ -505,3 +535,25 @@ const struct seq_operations cpuinfo_op = { + .stop = c_stop, + .show = c_show + }; + - config ARM_NVIC - bool - select IRQ_DOMAIN -diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile -index 62a13e5..c57e642 100644 ---- a/drivers/irqchip/Makefile -+++ b/drivers/irqchip/Makefile -@@ -15,7 +15,8 @@ obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o - obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o - obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi-nmi.o - obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o --obj-$(CONFIG_ARM_GIC) += irq-gic.o -+obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o -+obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-common.o - obj-$(CONFIG_ARM_NVIC) += irq-nvic.o - obj-$(CONFIG_ARM_VIC) += irq-vic.o - obj-$(CONFIG_IMGPDC_IRQ) += irq-imgpdc.o -diff --git a/drivers/irqchip/irq-gic-common.c b/drivers/irqchip/irq-gic-common.c -new file mode 100644 -index 0000000..60ac704 ---- /dev/null -+++ b/drivers/irqchip/irq-gic-common.c -@@ -0,0 +1,115 @@ +/* -+ * Copyright (C) 2002 ARM Limited, All Rights Reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see <http://www.gnu.org/licenses/>. ++ * Temporary hack to avoid need for console= on command line + */ -+ -+#include <linux/interrupt.h> -+#include <linux/io.h> -+#include <linux/irq.h> -+#include <linux/irqchip/arm-gic.h> -+ -+#include "irq-gic-common.h" -+ -+void gic_configure_irq(unsigned int irq, unsigned int type, -+ void __iomem *base, void (*sync_access)(void)) ++static int __init arm64_console_setup(void) +{ -+ u32 enablemask = 1 << (irq % 32); -+ u32 enableoff = (irq / 32) * 4; -+ u32 confmask = 0x2 << ((irq % 16) * 2); -+ u32 confoff = (irq / 16) * 4; -+ bool enabled = false; -+ u32 val; -+ -+ /* -+ * Read current configuration register, and insert the config -+ * for "irq", depending on "type". -+ */ -+ val = readl_relaxed(base + GIC_DIST_CONFIG + confoff); -+ if (type == IRQ_TYPE_LEVEL_HIGH) -+ val &= ~confmask; -+ else if (type == IRQ_TYPE_EDGE_RISING) -+ val |= confmask; -+ -+ /* -+ * As recommended by the spec, disable the interrupt before changing -+ * the configuration -+ */ -+ if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) { -+ writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff); -+ if (sync_access) -+ sync_access(); -+ enabled = true; -+ } -+ -+ /* -+ * Write back the new configuration, and possibly re-enable -+ * the interrupt. -+ */ -+ writel_relaxed(val, base + GIC_DIST_CONFIG + confoff); -+ -+ if (enabled) -+ writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); -+ -+ if (sync_access) -+ sync_access(); -+} -+ -+void __init gic_dist_config(void __iomem *base, int gic_irqs, -+ void (*sync_access)(void)) -+{ -+ unsigned int i; -+ -+ /* -+ * Set all global interrupts to be level triggered, active low. -+ */ -+ for (i = 32; i < gic_irqs; i += 16) -+ writel_relaxed(0, base + GIC_DIST_CONFIG + i / 4); -+ -+ /* -+ * Set priority on all global interrupts. -+ */ -+ for (i = 32; i < gic_irqs; i += 4) -+ writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i); -+ -+ /* -+ * Disable all interrupts. Leave the PPI and SGIs alone -+ * as they are enabled by redistributor registers. -+ */ -+ for (i = 32; i < gic_irqs; i += 32) -+ writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i / 8); ++ /* Allow cmdline to override our assumed preferences */ ++ if (console_set_on_cmdline) ++ return 0; + -+ if (sync_access) -+ sync_access(); -+} ++ if (IS_ENABLED(CONFIG_SBSAUART_TTY)) ++ add_preferred_console("ttySBSA", 0, "115200"); + -+void gic_cpu_config(void __iomem *base, void (*sync_access)(void)) -+{ -+ int i; ++ if (IS_ENABLED(CONFIG_SERIAL_AMBA_PL011)) ++ add_preferred_console("ttyAMA", 0, "115200"); + -+ /* -+ * Deal with the banked PPI and SGI interrupts - disable all -+ * PPI interrupts, ensure all SGI interrupts are enabled. -+ */ -+ writel_relaxed(0xffff0000, base + GIC_DIST_ENABLE_CLEAR); -+ writel_relaxed(0x0000ffff, base + GIC_DIST_ENABLE_SET); ++ if (IS_ENABLED(CONFIG_SERIAL_8250)) ++ add_preferred_console("ttyS", 0, "115200"); + -+ /* -+ * Set priority on PPI and SGI interrupts -+ */ -+ for (i = 0; i < 32; i += 4) -+ writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4); -+ -+ if (sync_access) -+ sync_access(); ++ return 0; +} -diff --git a/drivers/irqchip/irq-gic-common.h b/drivers/irqchip/irq-gic-common.h ++early_initcall(arm64_console_setup); +diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c +index 4743397..4e390ac 100644 +--- a/arch/arm64/kernel/smp.c ++++ b/arch/arm64/kernel/smp.c +@@ -321,7 +321,7 @@ void __init smp_prepare_boot_cpu(void) + * cpu logical map array containing MPIDR values related to logical + * cpus. Assumes that cpu_logical_map(0) has already been initialized. + */ +-void __init smp_init_cpus(void) ++void __init of_smp_init_cpus(void) + { + struct device_node *dn = NULL; + unsigned int i, cpu = 1; +diff --git a/arch/arm64/kernel/smp_parking_protocol.c b/arch/arm64/kernel/smp_parking_protocol.c new file mode 100644 -index 0000000..b41f024 +index 0000000..e1153ce --- /dev/null -+++ b/drivers/irqchip/irq-gic-common.h -@@ -0,0 +1,29 @@ ++++ b/arch/arm64/kernel/smp_parking_protocol.c +@@ -0,0 +1,110 @@ +/* -+ * Copyright (C) 2002 ARM Limited, All Rights Reserved. ++ * Parking Protocol SMP initialisation + * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. ++ * Based largely on spin-table method. + * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+ -+#ifndef _IRQ_GIC_COMMON_H -+#define _IRQ_GIC_COMMON_H -+ -+#include <linux/of.h> -+#include <linux/irqdomain.h> -+ -+void gic_configure_irq(unsigned int irq, unsigned int type, -+ void __iomem *base, void (*sync_access)(void)); -+void gic_dist_config(void __iomem *base, int gic_irqs, -+ void (*sync_access)(void)); -+void gic_cpu_config(void __iomem *base, void (*sync_access)(void)); -+ -+#endif /* _IRQ_GIC_COMMON_H */ -diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c -new file mode 100644 -index 0000000..81519ba ---- /dev/null -+++ b/drivers/irqchip/irq-gic-v3.c -@@ -0,0 +1,692 @@ -+/* -+ * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. -+ * Author: Marc Zyngier <marc.zyngier@arm.com> ++ * Copyright (C) 2013 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as @@ -3912,3278 +3442,2035 @@ index 0000000..81519ba + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ -+ -+#include <linux/cpu.h> +#include <linux/delay.h> -+#include <linux/interrupt.h> ++#include <linux/init.h> +#include <linux/of.h> -+#include <linux/of_address.h> -+#include <linux/of_irq.h> -+#include <linux/percpu.h> -+#include <linux/slab.h> -+ -+#include <linux/irqchip/arm-gic-v3.h> ++#include <linux/smp.h> ++#include <linux/types.h> ++#include <linux/acpi.h> + ++#include <asm/cacheflush.h> ++#include <asm/cpu_ops.h> +#include <asm/cputype.h> -+#include <asm/exception.h> +#include <asm/smp_plat.h> + -+#include "irq-gic-common.h" -+#include "irqchip.h" -+ -+struct gic_chip_data { -+ void __iomem *dist_base; -+ void __iomem **redist_base; -+ void __percpu __iomem **rdist; -+ struct irq_domain *domain; -+ u64 redist_stride; -+ u32 redist_regions; -+ unsigned int irq_nr; -+}; -+ -+static struct gic_chip_data gic_data __read_mostly; -+ -+#define gic_data_rdist() (this_cpu_ptr(gic_data.rdist)) -+#define gic_data_rdist_rd_base() (*gic_data_rdist()) -+#define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) -+ -+/* Our default, arbitrary priority value. Linux only uses one anyway. */ -+#define DEFAULT_PMR_VALUE 0xf0 -+ -+static inline unsigned int gic_irq(struct irq_data *d) -+{ -+ return d->hwirq; -+} -+ -+static inline int gic_irq_in_rdist(struct irq_data *d) -+{ -+ return gic_irq(d) < 32; -+} -+ -+static inline void __iomem *gic_dist_base(struct irq_data *d) -+{ -+ if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ -+ return gic_data_rdist_sgi_base(); ++static phys_addr_t cpu_mailbox_addr[NR_CPUS]; + -+ if (d->hwirq <= 1023) /* SPI -> dist_base */ -+ return gic_data.dist_base; -+ -+ if (d->hwirq >= 8192) -+ BUG(); /* LPI Detected!!! */ -+ -+ return NULL; -+} ++static void (*__smp_boot_wakeup)(int cpu); + -+static void gic_do_wait_for_rwp(void __iomem *base) ++void set_smp_boot_wakeup_call(void (*fn)(int cpu)) +{ -+ u32 count = 1000000; /* 1s! */ -+ -+ while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { -+ count--; -+ if (!count) { -+ pr_err_ratelimited("RWP timeout, gone fishing\n"); -+ return; -+ } -+ cpu_relax(); -+ udelay(1); -+ }; ++ __smp_boot_wakeup = fn; +} + -+/* Wait for completion of a distributor change */ -+static void gic_dist_wait_for_rwp(void) ++static int smp_parking_protocol_cpu_init(struct device_node *dn, ++ unsigned int cpu) +{ -+ gic_do_wait_for_rwp(gic_data.dist_base); -+} -+ -+/* Wait for completion of a redistributor change */ -+static void gic_redist_wait_for_rwp(void) -+{ -+ gic_do_wait_for_rwp(gic_data_rdist_rd_base()); -+} -+ -+/* Low level accessors */ -+static u64 gic_read_iar(void) -+{ -+ u64 irqstat; -+ -+ asm volatile("mrs %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat)); -+ return irqstat; -+} -+ -+static void gic_write_pmr(u64 val) -+{ -+ asm volatile("msr " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val)); -+} -+ -+static void gic_write_ctlr(u64 val) -+{ -+ asm volatile("msr " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val)); -+ isb(); -+} -+ -+static void gic_write_grpen1(u64 val) -+{ -+ asm volatile("msr " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val)); -+ isb(); -+} -+ -+static void gic_write_sgi1r(u64 val) -+{ -+ asm volatile("msr " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val)); -+} -+ -+static void gic_enable_sre(void) -+{ -+ u64 val; -+ -+ asm volatile("mrs %0, " __stringify(ICC_SRE_EL1) : "=r" (val)); -+ val |= ICC_SRE_EL1_SRE; -+ asm volatile("msr " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val)); -+ isb(); -+ + /* -+ * Need to check that the SRE bit has actually been set. If -+ * not, it means that SRE is disabled at EL2. We're going to -+ * die painfully, and there is nothing we can do about it. -+ * -+ * Kindly inform the luser. ++ * Determine the mailbox address. + */ -+ asm volatile("mrs %0, " __stringify(ICC_SRE_EL1) : "=r" (val)); -+ if (!(val & ICC_SRE_EL1_SRE)) -+ pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); -+} -+ -+static void gic_enable_redist(void) -+{ -+ void __iomem *rbase; -+ u32 count = 1000000; /* 1s! */ -+ u32 val; -+ -+ rbase = gic_data_rdist_rd_base(); -+ -+ /* Wake up this CPU redistributor */ -+ val = readl_relaxed(rbase + GICR_WAKER); -+ val &= ~GICR_WAKER_ProcessorSleep; -+ writel_relaxed(val, rbase + GICR_WAKER); -+ -+ while (readl_relaxed(rbase + GICR_WAKER) & GICR_WAKER_ChildrenAsleep) { -+ count--; -+ if (!count) { -+ pr_err_ratelimited("redist didn't wake up...\n"); -+ return; -+ } -+ cpu_relax(); -+ udelay(1); -+ }; -+} -+ -+/* -+ * Routines to disable, enable, EOI and route interrupts -+ */ -+static void gic_poke_irq(struct irq_data *d, u32 offset) -+{ -+ u32 mask = 1 << (gic_irq(d) % 32); -+ void (*rwp_wait)(void); -+ void __iomem *base; -+ -+ if (gic_irq_in_rdist(d)) { -+ base = gic_data_rdist_sgi_base(); -+ rwp_wait = gic_redist_wait_for_rwp; -+ } else { -+ base = gic_data.dist_base; -+ rwp_wait = gic_dist_wait_for_rwp; ++ if (!acpi_get_cpu_parked_address(cpu, &cpu_mailbox_addr[cpu])) { ++ pr_info("%s: ACPI parked addr=%llx\n", ++ __func__, cpu_mailbox_addr[cpu]); ++ return 0; + } + -+ writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); -+ rwp_wait(); -+} -+ -+static int gic_peek_irq(struct irq_data *d, u32 offset) -+{ -+ u32 mask = 1 << (gic_irq(d) % 32); -+ void __iomem *base; -+ -+ if (gic_irq_in_rdist(d)) -+ base = gic_data_rdist_sgi_base(); -+ else -+ base = gic_data.dist_base; -+ -+ return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); -+} -+ -+static void gic_mask_irq(struct irq_data *d) -+{ -+ gic_poke_irq(d, GICD_ICENABLER); -+} ++ pr_err("CPU %d: missing or invalid parking protocol mailbox\n", cpu); + -+static void gic_unmask_irq(struct irq_data *d) -+{ -+ gic_poke_irq(d, GICD_ISENABLER); ++ return -1; +} + -+static void gic_eoi_irq(struct irq_data *d) ++static int smp_parking_protocol_cpu_prepare(unsigned int cpu) +{ -+ gic_write_eoir(gic_irq(d)); -+} -+ -+static int gic_set_type(struct irq_data *d, unsigned int type) -+{ -+ unsigned int irq = gic_irq(d); -+ void (*rwp_wait)(void); -+ void __iomem *base; -+ -+ /* Interrupt configuration for SGIs can't be changed */ -+ if (irq < 16) -+ return -EINVAL; -+ -+ if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) -+ return -EINVAL; -+ -+ if (gic_irq_in_rdist(d)) { -+ base = gic_data_rdist_sgi_base(); -+ rwp_wait = gic_redist_wait_for_rwp; -+ } else { -+ base = gic_data.dist_base; -+ rwp_wait = gic_dist_wait_for_rwp; -+ } -+ -+ gic_configure_irq(irq, type, base, rwp_wait); -+ + return 0; +} + -+static u64 gic_mpidr_to_affinity(u64 mpidr) -+{ -+ u64 aff; -+ -+ aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | -+ MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | -+ MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | -+ MPIDR_AFFINITY_LEVEL(mpidr, 0)); -+ -+ return aff; -+} -+ -+static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) -+{ -+ u64 irqnr; -+ -+ do { -+ irqnr = gic_read_iar(); -+ -+ if (likely(irqnr > 15 && irqnr < 1020)) { -+ u64 irq = irq_find_mapping(gic_data.domain, irqnr); -+ if (likely(irq)) { -+ handle_IRQ(irq, regs); -+ continue; -+ } -+ -+ WARN_ONCE(true, "Unexpected SPI received!\n"); -+ gic_write_eoir(irqnr); -+ } -+ if (irqnr < 16) { -+ gic_write_eoir(irqnr); -+#ifdef CONFIG_SMP -+ handle_IPI(irqnr, regs); -+#else -+ WARN_ONCE(true, "Unexpected SGI received!\n"); -+#endif -+ continue; -+ } -+ } while (irqnr != ICC_IAR1_EL1_SPURIOUS); -+} -+ -+static void __init gic_dist_init(void) -+{ -+ unsigned int i; -+ u64 affinity; -+ void __iomem *base = gic_data.dist_base; -+ -+ /* Disable the distributor */ -+ writel_relaxed(0, base + GICD_CTLR); -+ gic_dist_wait_for_rwp(); -+ -+ gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); -+ -+ /* Enable distributor with ARE, Group1 */ -+ writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, -+ base + GICD_CTLR); -+ -+ /* -+ * Set all global interrupts to the boot CPU only. ARE must be -+ * enabled. -+ */ -+ affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); -+ for (i = 32; i < gic_data.irq_nr; i++) -+ writeq_relaxed(affinity, base + GICD_IROUTER + i * 8); -+} -+ -+static int gic_populate_rdist(void) -+{ -+ u64 mpidr = cpu_logical_map(smp_processor_id()); -+ u64 typer; -+ u32 aff; -+ int i; -+ -+ /* -+ * Convert affinity to a 32bit value that can be matched to -+ * GICR_TYPER bits [63:32]. -+ */ -+ aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | -+ MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | -+ MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | -+ MPIDR_AFFINITY_LEVEL(mpidr, 0)); -+ -+ for (i = 0; i < gic_data.redist_regions; i++) { -+ void __iomem *ptr = gic_data.redist_base[i]; -+ u32 reg; -+ -+ reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; -+ if (reg != GIC_PIDR2_ARCH_GICv3 && -+ reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ -+ pr_warn("No redistributor present @%p\n", ptr); -+ break; -+ } -+ -+ do { -+ typer = readq_relaxed(ptr + GICR_TYPER); -+ if ((typer >> 32) == aff) { -+ gic_data_rdist_rd_base() = ptr; -+ pr_info("CPU%d: found redistributor %llx @%p\n", -+ smp_processor_id(), -+ (unsigned long long)mpidr, ptr); -+ return 0; -+ } -+ -+ if (gic_data.redist_stride) { -+ ptr += gic_data.redist_stride; -+ } else { -+ ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ -+ if (typer & GICR_TYPER_VLPIS) -+ ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ -+ } -+ } while (!(typer & GICR_TYPER_LAST)); -+ } -+ -+ /* We couldn't even deal with ourselves... */ -+ WARN(true, "CPU%d: mpidr %llx has no re-distributor!\n", -+ smp_processor_id(), (unsigned long long)mpidr); -+ return -ENODEV; -+} -+ -+static void gic_cpu_init(void) -+{ -+ void __iomem *rbase; -+ -+ /* Register ourselves with the rest of the world */ -+ if (gic_populate_rdist()) -+ return; -+ -+ gic_enable_redist(); -+ -+ rbase = gic_data_rdist_sgi_base(); -+ -+ gic_cpu_config(rbase, gic_redist_wait_for_rwp); -+ -+ /* Enable system registers */ -+ gic_enable_sre(); -+ -+ /* Set priority mask register */ -+ gic_write_pmr(DEFAULT_PMR_VALUE); -+ -+ /* EOI deactivates interrupt too (mode 0) */ -+ gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); -+ -+ /* ... and let's hit the road... */ -+ gic_write_grpen1(1); -+} -+ -+#ifdef CONFIG_SMP -+static int gic_secondary_init(struct notifier_block *nfb, -+ unsigned long action, void *hcpu) -+{ -+ if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) -+ gic_cpu_init(); -+ return NOTIFY_OK; -+} -+ -+/* -+ * Notifier for enabling the GIC CPU interface. Set an arbitrarily high -+ * priority because the GIC needs to be up before the ARM generic timers. -+ */ -+static struct notifier_block gic_cpu_notifier = { -+ .notifier_call = gic_secondary_init, -+ .priority = 100, ++struct parking_protocol_mailbox { ++ __le32 cpu_id; ++ __le32 reserved; ++ __le64 entry_point; +}; + -+static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, -+ u64 cluster_id) ++static int smp_parking_protocol_cpu_boot(unsigned int cpu) +{ -+ int cpu = *base_cpu; -+ u64 mpidr = cpu_logical_map(cpu); -+ u16 tlist = 0; ++ struct parking_protocol_mailbox __iomem *mailbox; + -+ while (cpu < nr_cpu_ids) { -+ /* -+ * If we ever get a cluster of more than 16 CPUs, just -+ * scream and skip that CPU. -+ */ -+ if (WARN_ON((mpidr & 0xff) >= 16)) -+ goto out; -+ -+ tlist |= 1 << (mpidr & 0xf); -+ -+ cpu = cpumask_next(cpu, mask); -+ if (cpu == nr_cpu_ids) -+ goto out; -+ -+ mpidr = cpu_logical_map(cpu); -+ -+ if (cluster_id != (mpidr & ~0xffUL)) { -+ cpu--; -+ goto out; -+ } -+ } -+out: -+ *base_cpu = cpu; -+ return tlist; -+} -+ -+static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) -+{ -+ u64 val; -+ -+ val = (MPIDR_AFFINITY_LEVEL(cluster_id, 3) << 48 | -+ MPIDR_AFFINITY_LEVEL(cluster_id, 2) << 32 | -+ irq << 24 | -+ MPIDR_AFFINITY_LEVEL(cluster_id, 1) << 16 | -+ tlist); -+ -+ pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); -+ gic_write_sgi1r(val); -+} -+ -+static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) -+{ -+ int cpu; -+ -+ if (WARN_ON(irq >= 16)) -+ return; ++ if (!cpu_mailbox_addr[cpu] || !__smp_boot_wakeup) ++ return -ENODEV; + + /* -+ * Ensure that stores to Normal memory are visible to the -+ * other CPUs before issuing the IPI. ++ * The mailbox may or may not be inside the linear mapping. ++ * As ioremap_cache will either give us a new mapping or reuse the ++ * existing linear mapping, we can use it to cover both cases. In ++ * either case the memory will be MT_NORMAL. + */ -+ smp_wmb(); -+ -+ for_each_cpu_mask(cpu, *mask) { -+ u64 cluster_id = cpu_logical_map(cpu) & ~0xffUL; -+ u16 tlist; -+ -+ tlist = gic_compute_target_list(&cpu, mask, cluster_id); -+ gic_send_sgi(cluster_id, tlist, irq); -+ } -+ -+ /* Force the above writes to ICC_SGI1R_EL1 to be executed */ -+ isb(); -+} -+ -+static void gic_smp_init(void) -+{ -+ set_smp_cross_call(gic_raise_softirq); -+ register_cpu_notifier(&gic_cpu_notifier); -+} -+ -+static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, -+ bool force) -+{ -+ unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); -+ void __iomem *reg; -+ int enabled; -+ u64 val; -+ -+ if (gic_irq_in_rdist(d)) -+ return -EINVAL; -+ -+ /* If interrupt was enabled, disable it first */ -+ enabled = gic_peek_irq(d, GICD_ISENABLER); -+ if (enabled) -+ gic_mask_irq(d); -+ -+ reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); -+ val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); -+ -+ writeq_relaxed(val, reg); ++ mailbox = ioremap_cache(cpu_mailbox_addr[cpu], sizeof(*mailbox)); ++ if (!mailbox) ++ return -ENOMEM; + + /* -+ * If the interrupt was enabled, enabled it again. Otherwise, -+ * just wait for the distributor to have digested our changes. ++ * We write the entry point and cpu id as LE regardless of the ++ * native endianess of the kernel. Therefore, any boot-loaders ++ * that read this address need to convert this address to the ++ * Boot-Loader's endianess before jumping. + */ -+ if (enabled) -+ gic_unmask_irq(d); -+ else -+ gic_dist_wait_for_rwp(); ++ writeq(__pa(secondary_entry), &mailbox->entry_point); ++ writel(cpu, &mailbox->cpu_id); ++ __flush_dcache_area(mailbox, sizeof(*mailbox)); ++ __smp_boot_wakeup(cpu); + -+ return IRQ_SET_MASK_OK; -+} -+#else -+#define gic_set_affinity NULL -+#define gic_smp_init() do { } while(0) -+#endif ++ /* temp hack for broken firmware */ ++ sev(); + -+static struct irq_chip gic_chip = { -+ .name = "GICv3", -+ .irq_mask = gic_mask_irq, -+ .irq_unmask = gic_unmask_irq, -+ .irq_eoi = gic_eoi_irq, -+ .irq_set_type = gic_set_type, -+ .irq_set_affinity = gic_set_affinity, -+}; ++ iounmap(mailbox); + -+static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, -+ irq_hw_number_t hw) -+{ -+ /* SGIs are private to the core kernel */ -+ if (hw < 16) -+ return -EPERM; -+ /* PPIs */ -+ if (hw < 32) { -+ irq_set_percpu_devid(irq); -+ irq_set_chip_and_handler(irq, &gic_chip, -+ handle_percpu_devid_irq); -+ set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); -+ } -+ /* SPIs */ -+ if (hw >= 32 && hw < gic_data.irq_nr) { -+ irq_set_chip_and_handler(irq, &gic_chip, -+ handle_fasteoi_irq); -+ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); -+ } -+ irq_set_chip_data(irq, d->host_data); + return 0; +} + -+static int gic_irq_domain_xlate(struct irq_domain *d, -+ struct device_node *controller, -+ const u32 *intspec, unsigned int intsize, -+ unsigned long *out_hwirq, unsigned int *out_type) -+{ -+ if (d->of_node != controller) -+ return -EINVAL; -+ if (intsize < 3) -+ return -EINVAL; -+ -+ switch(intspec[0]) { -+ case 0: /* SPI */ -+ *out_hwirq = intspec[1] + 32; -+ break; -+ case 1: /* PPI */ -+ *out_hwirq = intspec[1] + 16; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; -+ return 0; -+} -+ -+static const struct irq_domain_ops gic_irq_domain_ops = { -+ .map = gic_irq_domain_map, -+ .xlate = gic_irq_domain_xlate, ++const struct cpu_operations smp_parking_protocol_ops = { ++ .name = "parking-protocol", ++ .cpu_init = smp_parking_protocol_cpu_init, ++ .cpu_prepare = smp_parking_protocol_cpu_prepare, ++ .cpu_boot = smp_parking_protocol_cpu_boot, +}; -+ -+static int __init gic_of_init(struct device_node *node, struct device_node *parent) -+{ -+ void __iomem *dist_base; -+ void __iomem **redist_base; -+ u64 redist_stride; -+ u32 redist_regions; -+ u32 reg; -+ int gic_irqs; -+ int err; -+ int i; -+ -+ dist_base = of_iomap(node, 0); -+ if (!dist_base) { -+ pr_err("%s: unable to map gic dist registers\n", -+ node->full_name); -+ return -ENXIO; -+ } -+ -+ reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; -+ if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) { -+ pr_err("%s: no distributor detected, giving up\n", -+ node->full_name); -+ err = -ENODEV; -+ goto out_unmap_dist; -+ } -+ -+ if (of_property_read_u32(node, "#redistributor-regions", &redist_regions)) -+ redist_regions = 1; -+ -+ redist_base = kzalloc(sizeof(*redist_base) * redist_regions, GFP_KERNEL); -+ if (!redist_base) { -+ err = -ENOMEM; -+ goto out_unmap_dist; -+ } -+ -+ for (i = 0; i < redist_regions; i++) { -+ redist_base[i] = of_iomap(node, 1 + i); -+ if (!redist_base[i]) { -+ pr_err("%s: couldn't map region %d\n", -+ node->full_name, i); -+ err = -ENODEV; -+ goto out_unmap_rdist; -+ } -+ } -+ -+ if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) -+ redist_stride = 0; -+ -+ gic_data.dist_base = dist_base; -+ gic_data.redist_base = redist_base; -+ gic_data.redist_regions = redist_regions; -+ gic_data.redist_stride = redist_stride; -+ -+ /* -+ * Find out how many interrupts are supported. -+ * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) -+ */ -+ gic_irqs = readl_relaxed(gic_data.dist_base + GICD_TYPER) & 0x1f; -+ gic_irqs = (gic_irqs + 1) * 32; -+ if (gic_irqs > 1020) -+ gic_irqs = 1020; -+ gic_data.irq_nr = gic_irqs; -+ -+ gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops, -+ &gic_data); -+ gic_data.rdist = alloc_percpu(typeof(*gic_data.rdist)); -+ -+ if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdist)) { -+ err = -ENOMEM; -+ goto out_free; -+ } -+ -+ set_handle_irq(gic_handle_irq); -+ -+ gic_smp_init(); -+ gic_dist_init(); -+ gic_cpu_init(); -+ -+ return 0; -+ -+out_free: -+ if (gic_data.domain) -+ irq_domain_remove(gic_data.domain); -+ free_percpu(gic_data.rdist); -+out_unmap_rdist: -+ for (i = 0; i < redist_regions; i++) -+ if (redist_base[i]) -+ iounmap(redist_base[i]); -+ kfree(redist_base); -+out_unmap_dist: -+ iounmap(dist_base); -+ return err; -+} -+ -+IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); -diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c -index 7c131cf..1ddfdde 100644 ---- a/drivers/irqchip/irq-gic.c -+++ b/drivers/irqchip/irq-gic.c -@@ -47,6 +47,7 @@ - #include <asm/exception.h> - #include <asm/smp_plat.h> +diff --git a/arch/arm64/kernel/smp_spin_table.c b/arch/arm64/kernel/smp_spin_table.c +index 0347d38..4f93c67 100644 +--- a/arch/arm64/kernel/smp_spin_table.c ++++ b/arch/arm64/kernel/smp_spin_table.c +@@ -20,6 +20,7 @@ + #include <linux/init.h> + #include <linux/of.h> + #include <linux/smp.h> ++#include <linux/types.h> -+#include "irq-gic-common.h" - #include "irqchip.h" + #include <asm/cacheflush.h> + #include <asm/cpu_ops.h> +@@ -65,12 +66,21 @@ static int smp_spin_table_cpu_init(struct device_node *dn, unsigned int cpu) - union gic_base { -@@ -189,12 +190,6 @@ static int gic_set_type(struct irq_data *d, unsigned int type) + static int smp_spin_table_cpu_prepare(unsigned int cpu) { - void __iomem *base = gic_dist_base(d); - unsigned int gicirq = gic_irq(d); -- u32 enablemask = 1 << (gicirq % 32); -- u32 enableoff = (gicirq / 32) * 4; -- u32 confmask = 0x2 << ((gicirq % 16) * 2); -- u32 confoff = (gicirq / 16) * 4; -- bool enabled = false; -- u32 val; - - /* Interrupt configuration for SGIs can't be changed */ - if (gicirq < 16) -@@ -208,25 +203,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type) - if (gic_arch_extn.irq_set_type) - gic_arch_extn.irq_set_type(d, type); - -- val = readl_relaxed(base + GIC_DIST_CONFIG + confoff); -- if (type == IRQ_TYPE_LEVEL_HIGH) -- val &= ~confmask; -- else if (type == IRQ_TYPE_EDGE_RISING) -- val |= confmask; -- -- /* -- * As recommended by the spec, disable the interrupt before changing -- * the configuration -- */ -- if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) { -- writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff); -- enabled = true; -- } -- -- writel_relaxed(val, base + GIC_DIST_CONFIG + confoff); -- -- if (enabled) -- writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); -+ gic_configure_irq(gicirq, type, base, NULL); +- void **release_addr; ++ __le64 __iomem *release_addr; - raw_spin_unlock(&irq_controller_lock); + if (!cpu_release_addr[cpu]) + return -ENODEV; -@@ -388,12 +365,6 @@ static void __init gic_dist_init(struct gic_chip_data *gic) - writel_relaxed(0, base + GIC_DIST_CTRL); +- release_addr = __va(cpu_release_addr[cpu]); ++ /* ++ * The cpu-release-addr may or may not be inside the linear mapping. ++ * As ioremap_cache will either give us a new mapping or reuse the ++ * existing linear mapping, we can use it to cover both cases. In ++ * either case the memory will be MT_NORMAL. ++ */ ++ release_addr = ioremap_cache(cpu_release_addr[cpu], ++ sizeof(*release_addr)); ++ if (!release_addr) ++ return -ENOMEM; /* -- * Set all global interrupts to be level triggered, active low. -- */ -- for (i = 32; i < gic_irqs; i += 16) -- writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16); -- -- /* - * Set all global interrupts to this CPU only. + * We write the release address as LE regardless of the native +@@ -79,15 +89,17 @@ static int smp_spin_table_cpu_prepare(unsigned int cpu) + * boot-loader's endianess before jumping. This is mandated by + * the boot protocol. */ - cpumask = gic_get_cpumask(gic); -@@ -402,18 +373,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic) - for (i = 32; i < gic_irqs; i += 4) - writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); - -- /* -- * Set priority on all global interrupts. -- */ -- for (i = 32; i < gic_irqs; i += 4) -- writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4); +- release_addr[0] = (void *) cpu_to_le64(__pa(secondary_holding_pen)); - -- /* -- * Disable all interrupts. Leave the PPI and SGIs alone -- * as these enables are banked registers. -- */ -- for (i = 32; i < gic_irqs; i += 32) -- writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); -+ gic_dist_config(base, gic_irqs, NULL); - - writel_relaxed(1, base + GIC_DIST_CTRL); - } -@@ -423,6 +383,7 @@ static void gic_cpu_init(struct gic_chip_data *gic) - void __iomem *dist_base = gic_data_dist_base(gic); - void __iomem *base = gic_data_cpu_base(gic); - unsigned int cpu_mask, cpu = smp_processor_id(); -+ unsigned int ctrl_mask; - int i; +- __flush_dcache_area(release_addr, sizeof(release_addr[0])); ++ writeq_relaxed(__pa(secondary_holding_pen), release_addr); ++ __flush_dcache_area((__force void *)release_addr, ++ sizeof(*release_addr)); /* -@@ -440,27 +401,32 @@ static void gic_cpu_init(struct gic_chip_data *gic) - if (i != cpu) - gic_cpu_map[i] &= ~cpu_mask; - -- /* -- * Deal with the banked PPI and SGI interrupts - disable all -- * PPI interrupts, ensure all SGI interrupts are enabled. -- */ -- writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); -- writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); -- -- /* -- * Set priority on PPI and SGI interrupts -- */ -- for (i = 0; i < 32; i += 4) -- writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); -+ gic_cpu_config(dist_base, NULL); + * Send an event to wake up the secondary CPU. + */ + sev(); - writel_relaxed(0xf0, base + GIC_CPU_PRIMASK); -- writel_relaxed(1, base + GIC_CPU_CTRL); -+ -+ ctrl_mask = readl(base + GIC_CPU_CTRL); -+ -+ /* Mask out the gic v2 bypass bits */ -+ ctrl_mask &= 0x1e0; ++ iounmap(release_addr); + -+ /* Enable group 0 */ -+ ctrl_mask |= 0x1; -+ writel_relaxed(ctrl_mask, base + GIC_CPU_CTRL); + return 0; } - void gic_cpu_if_down(void) - { -+ unsigned int ctrl_mask; - void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]); -- writel_relaxed(0, cpu_base + GIC_CPU_CTRL); -+ -+ ctrl_mask = readl(cpu_base + GIC_CPU_CTRL); +diff --git a/arch/arm64/kernel/time.c b/arch/arm64/kernel/time.c +index 1a7125c..42f9195 100644 +--- a/arch/arm64/kernel/time.c ++++ b/arch/arm64/kernel/time.c +@@ -35,6 +35,7 @@ + #include <linux/delay.h> + #include <linux/clocksource.h> + #include <linux/clk-provider.h> ++#include <linux/acpi.h> + + #include <clocksource/arm_arch_timer.h> + +@@ -72,6 +73,12 @@ void __init time_init(void) + + tick_setup_hrtimer_broadcast(); + + /* -+ * Disable grp enable bit, leave the bypass bits alone as changing -+ * them could leave the system unstable ++ * Since ACPI or FDT will only one be available in the system, ++ * we can use acpi_generic_timer_init() here safely + */ -+ ctrl_mask &= 0x1e0; -+ writel_relaxed(ctrl_mask, cpu_base + GIC_CPU_CTRL); - } ++ acpi_generic_timer_init(); ++ + arch_timer_rate = arch_timer_get_rate(); + if (!arch_timer_rate) + panic("Unable to initialise architected timer.\n"); +diff --git a/arch/arm64/kvm/hyp-init.S b/arch/arm64/kvm/hyp-init.S +index c319116..fa7e67e 100644 +--- a/arch/arm64/kvm/hyp-init.S ++++ b/arch/arm64/kvm/hyp-init.S +@@ -63,17 +63,21 @@ __do_hyp_init: + mrs x4, tcr_el1 + ldr x5, =TCR_EL2_MASK + and x4, x4, x5 +- ldr x5, =TCR_EL2_FLAGS +- orr x4, x4, x5 +- msr tcr_el2, x4 +- +- ldr x4, =VTCR_EL2_FLAGS + /* + * Read the PARange bits from ID_AA64MMFR0_EL1 and set the PS bits in +- * VTCR_EL2. ++ * TCR_EL2 and both PS bits and T0SZ bits in VTCR_EL2. + */ + mrs x5, ID_AA64MMFR0_EL1 + bfi x4, x5, #16, #3 ++ msr tcr_el2, x4 ++ ++ ldr x4, =VTCR_EL2_FLAGS ++ bfi x4, x5, #16, #3 ++ and x5, x5, #0xf ++ adr x6, t0sz ++ add x6, x6, x5, lsl #2 ++ ldr w5, [x6] ++ orr x4, x4, x5 + msr vtcr_el2, x4 + + mrs x4, mair_el1 +@@ -113,6 +117,10 @@ target: /* We're now in the trampoline code, switch page tables */ + + /* Hello, World! */ + eret ++ ++t0sz: ++ .word VTCR_EL2_T0SZ(32), VTCR_EL2_T0SZ(36), VTCR_EL2_T0SZ(40) ++ .word VTCR_EL2_T0SZ(42), VTCR_EL2_T0SZ(44), VTCR_EL2_T0SZ(48) + ENDPROC(__kvm_hyp_init) + + .ltorg +diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c +index 4164c5a..b864a24 100644 +--- a/arch/arm64/mm/dma-mapping.c ++++ b/arch/arm64/mm/dma-mapping.c +@@ -23,10 +23,13 @@ + #include <linux/dma-mapping.h> + #include <linux/dma-contiguous.h> + #include <linux/of.h> ++#include <linux/of_address.h> + #include <linux/platform_device.h> + #include <linux/vmalloc.h> + #include <linux/swiotlb.h> + #include <linux/amba/bus.h> ++#include <linux/acpi.h> ++#include <linux/pci.h> - #ifdef CONFIG_CPU_PM -@@ -571,6 +537,7 @@ static void gic_cpu_restore(unsigned int gic_nr) - { - int i; - u32 *ptr; -+ unsigned int ctrl_mask; - void __iomem *dist_base; - void __iomem *cpu_base; + #include <asm/cacheflush.h> -@@ -595,7 +562,15 @@ static void gic_cpu_restore(unsigned int gic_nr) - writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4); +@@ -319,6 +322,63 @@ static int dma_bus_notifier(struct notifier_block *nb, + if (of_property_read_bool(dev->of_node, "dma-coherent")) + set_dma_ops(dev, &coherent_swiotlb_dma_ops); - writel_relaxed(0xf0, cpu_base + GIC_CPU_PRIMASK); -- writel_relaxed(1, cpu_base + GIC_CPU_CTRL); ++#ifdef CONFIG_ACPI ++ else if (ACPI_HANDLE(dev)) { ++ acpi_status status; ++ int coherent; + -+ ctrl_mask = readl(cpu_base + GIC_CPU_CTRL); ++ /* ++ * Kernel defaults to noncoherent ops but ACPI 5.1 spec says arm64 ++ * defaults to coherent. Set coherent ops if _CCA not found or _CCA ++ * found and non-zero. ++ */ ++ status = acpi_check_coherency(ACPI_HANDLE(dev), &coherent); ++ if (ACPI_FAILURE(status) || coherent) ++ set_dma_ops(dev, &coherent_swiotlb_dma_ops); ++ } ++#endif ++ return NOTIFY_OK; ++} ++ ++static int dma_bus_notifier_pci(struct notifier_block *nb, ++ unsigned long event, void *_dev) ++{ ++ struct device *dev = _dev; + -+ /* Mask out the gic v2 bypass bits */ -+ ctrl_mask &= 0x1e0; ++ if (event != BUS_NOTIFY_ADD_DEVICE) ++ return NOTIFY_DONE; + -+ /* Enable group 0 */ -+ ctrl_mask |= 0x1; -+ writel_relaxed(ctrl_mask, cpu_base + GIC_CPU_CTRL); ++ /* ++ * PCI devices won't have an of_node but the bridge will. ++ * Search up the device chain until we find an of_node ++ * to check. ++ */ ++ while (dev) { ++ if (dev->of_node) { ++ if (of_dma_is_coherent(dev->of_node)) ++ set_dma_ops(_dev, &coherent_swiotlb_dma_ops); ++ break; ++ } ++#ifdef CONFIG_ACPI ++ if (ACPI_HANDLE(dev)) { ++ acpi_status status; ++ int coherent; ++ ++ /* ++ * Kernel defaults to noncoherent ops but ACPI 5.1 spec says arm64 ++ * defaults to coherent. Set coherent ops if _CCA not found or _CCA ++ * found and non-zero. ++ */ ++ status = acpi_check_coherency(ACPI_HANDLE(dev), &coherent); ++ if (ACPI_FAILURE(status) || coherent) { ++ set_dma_ops(dev, &coherent_swiotlb_dma_ops); ++ break; ++ } ++ } ++#endif ++ dev = dev->parent; ++ } ++ + return NOTIFY_OK; } - static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) -diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig -index edb7186..dc7406c 100644 ---- a/drivers/net/ethernet/Kconfig -+++ b/drivers/net/ethernet/Kconfig -@@ -24,6 +24,7 @@ source "drivers/net/ethernet/allwinner/Kconfig" - source "drivers/net/ethernet/alteon/Kconfig" - source "drivers/net/ethernet/altera/Kconfig" - source "drivers/net/ethernet/amd/Kconfig" -+source "drivers/net/ethernet/apm/Kconfig" - source "drivers/net/ethernet/apple/Kconfig" - source "drivers/net/ethernet/arc/Kconfig" - source "drivers/net/ethernet/atheros/Kconfig" -diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile -index 58de333..224a018 100644 ---- a/drivers/net/ethernet/Makefile -+++ b/drivers/net/ethernet/Makefile -@@ -10,6 +10,7 @@ obj-$(CONFIG_NET_VENDOR_ALLWINNER) += allwinner/ - obj-$(CONFIG_NET_VENDOR_ALTEON) += alteon/ - obj-$(CONFIG_ALTERA_TSE) += altera/ - obj-$(CONFIG_NET_VENDOR_AMD) += amd/ -+obj-$(CONFIG_NET_XGENE) += apm/ - obj-$(CONFIG_NET_VENDOR_APPLE) += apple/ - obj-$(CONFIG_NET_VENDOR_ARC) += arc/ - obj-$(CONFIG_NET_VENDOR_ATHEROS) += atheros/ -diff --git a/drivers/net/ethernet/apm/Kconfig b/drivers/net/ethernet/apm/Kconfig +@@ -330,6 +390,10 @@ static struct notifier_block amba_bus_nb = { + .notifier_call = dma_bus_notifier, + }; + ++static struct notifier_block pci_bus_nb = { ++ .notifier_call = dma_bus_notifier_pci, ++}; ++ + extern int swiotlb_late_init_with_default_size(size_t default_size); + + static int __init swiotlb_late_init(void) +@@ -341,6 +405,7 @@ static int __init swiotlb_late_init(void) + */ + bus_register_notifier(&platform_bus_type, &platform_bus_nb); + bus_register_notifier(&amba_bustype, &amba_bus_nb); ++ bus_register_notifier(&pci_bus_type, &pci_bus_nb); + + dma_ops = &noncoherent_swiotlb_dma_ops; + +diff --git a/arch/arm64/pci/Makefile b/arch/arm64/pci/Makefile new file mode 100644 -index 0000000..ec63d70 +index 0000000..b8d5dbd --- /dev/null -+++ b/drivers/net/ethernet/apm/Kconfig ++++ b/arch/arm64/pci/Makefile @@ -0,0 +1 @@ -+source "drivers/net/ethernet/apm/xgene/Kconfig" -diff --git a/drivers/net/ethernet/apm/Makefile b/drivers/net/ethernet/apm/Makefile -new file mode 100644 -index 0000000..65ce32a ---- /dev/null -+++ b/drivers/net/ethernet/apm/Makefile -@@ -0,0 +1,5 @@ -+# -+# Makefile for APM X-GENE Ethernet driver. -+# -+ -+obj-$(CONFIG_NET_XGENE) += xgene/ -diff --git a/drivers/net/ethernet/apm/xgene/Kconfig b/drivers/net/ethernet/apm/xgene/Kconfig ++obj-y += pci.o +diff --git a/arch/arm64/pci/pci.c b/arch/arm64/pci/pci.c new file mode 100644 -index 0000000..616dff6 +index 0000000..b03b0eb --- /dev/null -+++ b/drivers/net/ethernet/apm/xgene/Kconfig -@@ -0,0 +1,9 @@ -+config NET_XGENE -+ tristate "APM X-Gene SoC Ethernet Driver" -+ select PHYLIB -+ help -+ This is the Ethernet driver for the on-chip ethernet interface on the -+ APM X-Gene SoC. ++++ b/arch/arm64/pci/pci.c +@@ -0,0 +1,28 @@ ++#include <linux/acpi.h> ++#include <linux/types.h> ++#include <linux/kernel.h> ++#include <linux/pci.h> + -+ To compile this driver as a module, choose M here. This module will -+ be called xgene_enet. -diff --git a/drivers/net/ethernet/apm/xgene/Makefile b/drivers/net/ethernet/apm/xgene/Makefile -new file mode 100644 -index 0000000..c643e8a ---- /dev/null -+++ b/drivers/net/ethernet/apm/xgene/Makefile -@@ -0,0 +1,6 @@ -+# -+# Makefile for APM X-Gene Ethernet Driver. -+# -+ -+xgene-enet-objs := xgene_enet_hw.o xgene_enet_main.o xgene_enet_ethtool.o -+obj-$(CONFIG_NET_XGENE) += xgene-enet.o -diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_ethtool.c b/drivers/net/ethernet/apm/xgene/xgene_enet_ethtool.c -new file mode 100644 -index 0000000..63f2aa5 ---- /dev/null -+++ b/drivers/net/ethernet/apm/xgene/xgene_enet_ethtool.c -@@ -0,0 +1,125 @@ -+/* Applied Micro X-Gene SoC Ethernet Driver -+ * -+ * Copyright (c) 2014, Applied Micro Circuits Corporation -+ * Authors: Iyappan Subramanian <isubramanian@apm.com> -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. ++/** ++ * raw_pci_read - Platform-specific PCI config space access. + * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see <http://www.gnu.org/licenses/>. ++ * Default empty implementation. Replace with an architecture-specific setup ++ * routine, if necessary. + */ -+ -+#include <linux/ethtool.h> -+#include "xgene_enet_main.h" -+ -+struct xgene_gstrings_stats { -+ char name[ETH_GSTRING_LEN]; -+ int offset; -+}; -+ -+#define XGENE_STAT(m) { #m, offsetof(struct xgene_enet_pdata, stats.m) } -+ -+static const struct xgene_gstrings_stats gstrings_stats[] = { -+ XGENE_STAT(rx_packets), -+ XGENE_STAT(tx_packets), -+ XGENE_STAT(rx_bytes), -+ XGENE_STAT(tx_bytes), -+ XGENE_STAT(rx_errors), -+ XGENE_STAT(tx_errors), -+ XGENE_STAT(rx_length_errors), -+ XGENE_STAT(rx_crc_errors), -+ XGENE_STAT(rx_frame_errors), -+ XGENE_STAT(rx_fifo_errors) -+}; -+ -+#define XGENE_STATS_LEN ARRAY_SIZE(gstrings_stats) -+ -+static void xgene_get_drvinfo(struct net_device *ndev, -+ struct ethtool_drvinfo *info) ++int __weak raw_pci_read(unsigned int domain, unsigned int bus, ++ unsigned int devfn, int reg, int len, u32 *val) +{ -+ struct xgene_enet_pdata *pdata = netdev_priv(ndev); -+ struct platform_device *pdev = pdata->pdev; -+ -+ strcpy(info->driver, "xgene_enet"); -+ strcpy(info->version, XGENE_DRV_VERSION); -+ snprintf(info->fw_version, ETHTOOL_FWVERS_LEN, "N/A"); -+ sprintf(info->bus_info, "%s", pdev->name); ++ return -EINVAL; +} + -+static int xgene_get_settings(struct net_device *ndev, struct ethtool_cmd *cmd) ++int __weak raw_pci_write(unsigned int domain, unsigned int bus, ++ unsigned int devfn, int reg, int len, u32 val) +{ -+ struct xgene_enet_pdata *pdata = netdev_priv(ndev); -+ struct phy_device *phydev = pdata->phy_dev; -+ -+ if (phydev == NULL) -+ return -ENODEV; -+ -+ return phy_ethtool_gset(phydev, cmd); ++ return -EINVAL; +} + -+static int xgene_set_settings(struct net_device *ndev, struct ethtool_cmd *cmd) ++/* Root bridge scanning */ ++struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) +{ -+ struct xgene_enet_pdata *pdata = netdev_priv(ndev); -+ struct phy_device *phydev = pdata->phy_dev; -+ -+ if (phydev == NULL) -+ return -ENODEV; -+ -+ return phy_ethtool_sset(phydev, cmd); ++ return NULL; +} -+ -+static void xgene_get_strings(struct net_device *ndev, u32 stringset, u8 *data) +diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig +index d0f3265..3343080 100644 +--- a/drivers/acpi/Kconfig ++++ b/drivers/acpi/Kconfig +@@ -5,8 +5,7 @@ + menuconfig ACPI + bool "ACPI (Advanced Configuration and Power Interface) Support" + depends on !IA64_HP_SIM +- depends on IA64 || X86 +- depends on PCI ++ depends on ((IA64 || X86) && PCI) || ARM64 + select PNP + default y + help +@@ -163,6 +162,7 @@ config ACPI_PROCESSOR + tristate "Processor" + select THERMAL + select CPU_IDLE ++ depends on X86 || IA64 + default y + help + This driver installs ACPI as the idle handler for Linux and uses +@@ -263,7 +263,7 @@ config ACPI_DEBUG + + config ACPI_PCI_SLOT + bool "PCI slot detection driver" +- depends on SYSFS ++ depends on SYSFS && PCI + default n + help + This driver creates entries in /sys/bus/pci/slots/ for all PCI +diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile +index 505d4d7..6f3a74d 100644 +--- a/drivers/acpi/Makefile ++++ b/drivers/acpi/Makefile +@@ -23,7 +23,11 @@ acpi-y += nvs.o + + # Power management related files + acpi-y += wakeup.o ++ifeq ($(ARCH), arm64) ++acpi-y += sleep-arm.o ++else # X86, IA64 + acpi-y += sleep.o ++endif + acpi-y += device_pm.o + acpi-$(CONFIG_ACPI_SLEEP) += proc.o + +@@ -39,7 +43,7 @@ acpi-y += processor_core.o + acpi-$(CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC) += processor_pdc.o + acpi-y += ec.o + acpi-$(CONFIG_ACPI_DOCK) += dock.o +-acpi-y += pci_root.o pci_link.o pci_irq.o ++acpi-$(CONFIG_PCI) += pci_root.o pci_link.o pci_irq.o + acpi-y += acpi_lpss.o + acpi-y += acpi_platform.o + acpi-y += acpi_pnp.o +diff --git a/drivers/acpi/acpica/utresrc.c b/drivers/acpi/acpica/utresrc.c +index 14cb6c0..5cd017c 100644 +--- a/drivers/acpi/acpica/utresrc.c ++++ b/drivers/acpi/acpica/utresrc.c +@@ -87,7 +87,9 @@ const char *acpi_gbl_io_decode[] = { + + const char *acpi_gbl_ll_decode[] = { + "ActiveHigh", +- "ActiveLow" ++ "ActiveLow", ++ "ActiveBoth", ++ "Reserved" + }; + + const char *acpi_gbl_max_decode[] = { +diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c +index 8b67bd0..c412fdb 100644 +--- a/drivers/acpi/bus.c ++++ b/drivers/acpi/bus.c +@@ -448,6 +448,9 @@ static int __init acpi_bus_init_irq(void) + case ACPI_IRQ_MODEL_IOSAPIC: + message = "IOSAPIC"; + break; ++ case ACPI_IRQ_MODEL_GIC: ++ message = "GIC"; ++ break; + case ACPI_IRQ_MODEL_PLATFORM: + message = "platform specific model"; + break; +diff --git a/drivers/acpi/internal.h b/drivers/acpi/internal.h +index 4c5cf77..e1e6487 100644 +--- a/drivers/acpi/internal.h ++++ b/drivers/acpi/internal.h +@@ -26,8 +26,13 @@ + acpi_status acpi_os_initialize1(void); + int init_acpi_device_notify(void); + int acpi_scan_init(void); ++#ifdef CONFIG_PCI + void acpi_pci_root_init(void); + void acpi_pci_link_init(void); ++#else ++static inline void acpi_pci_root_init(void) {} ++static inline void acpi_pci_link_init(void) {} ++#endif + void acpi_processor_init(void); + void acpi_platform_init(void); + void acpi_pnp_init(void); +diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c +index 3abe9b2..c50757b 100644 +--- a/drivers/acpi/osl.c ++++ b/drivers/acpi/osl.c +@@ -326,11 +326,11 @@ acpi_map_lookup_virt(void __iomem *virt, acpi_size size) + return NULL; + } + +-#ifndef CONFIG_IA64 +-#define should_use_kmap(pfn) page_is_ram(pfn) +-#else ++#if defined(CONFIG_IA64) || defined(CONFIG_ARM) || defined(CONFIG_ARM64) + /* ioremap will take care of cache attributes */ + #define should_use_kmap(pfn) 0 ++#else ++#define should_use_kmap(pfn) page_is_ram(pfn) + #endif + + static void __iomem *acpi_map(acpi_physical_address pg_off, unsigned long pg_sz) +diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c +index e32321c..4007313 100644 +--- a/drivers/acpi/processor_core.c ++++ b/drivers/acpi/processor_core.c +@@ -64,6 +64,38 @@ static int map_lsapic_id(struct acpi_subtable_header *entry, + return 0; + } + ++/* ++ * On ARM platform, MPIDR value is the hardware ID as apic ID ++ * on Intel platforms ++ */ ++static int map_gicc_mpidr(struct acpi_subtable_header *entry, ++ int device_declaration, u32 acpi_id, int *mpidr) +{ -+ int i; -+ u8 *p = data; ++ struct acpi_madt_generic_interrupt *gicc = ++ container_of(entry, struct acpi_madt_generic_interrupt, header); + -+ if (stringset != ETH_SS_STATS) -+ return; ++ if (!(gicc->flags & ACPI_MADT_ENABLED)) ++ return -ENODEV; + -+ for (i = 0; i < XGENE_STATS_LEN; i++) { -+ memcpy(p, gstrings_stats[i].name, ETH_GSTRING_LEN); -+ p += ETH_GSTRING_LEN; ++ /* In the GIC interrupt model, logical processors are ++ * required to have a Processor Device object in the DSDT, ++ * so we should check device_declaration here ++ */ ++ if (device_declaration && (gicc->uid == acpi_id)) { ++ /* ++ * Only bits [0:7] Aff0, bits [8:15] Aff1, bits [16:23] Aff2 ++ * and bits [32:39] Aff3 are meaningful, so pack the Affx ++ * fields into a single 32 bit identifier to accommodate the ++ * acpi processor drivers. ++ */ ++ *mpidr = ((gicc->arm_mpidr & 0xff00000000) >> 8) ++ | gicc->arm_mpidr; ++ return 0; + } -+} + -+static int xgene_get_sset_count(struct net_device *ndev, int sset) -+{ -+ if (sset != ETH_SS_STATS) -+ return -EINVAL; -+ -+ return XGENE_STATS_LEN; -+} -+ -+static void xgene_get_ethtool_stats(struct net_device *ndev, -+ struct ethtool_stats *dummy, -+ u64 *data) -+{ -+ void *pdata = netdev_priv(ndev); -+ int i; -+ -+ for (i = 0; i < XGENE_STATS_LEN; i++) -+ *data++ = *(u64 *)(pdata + gstrings_stats[i].offset); ++ return -EINVAL; +} + -+static const struct ethtool_ops xgene_ethtool_ops = { -+ .get_drvinfo = xgene_get_drvinfo, -+ .get_settings = xgene_get_settings, -+ .set_settings = xgene_set_settings, -+ .get_link = ethtool_op_get_link, -+ .get_strings = xgene_get_strings, -+ .get_sset_count = xgene_get_sset_count, -+ .get_ethtool_stats = xgene_get_ethtool_stats -+}; -+ -+void xgene_enet_set_ethtool_ops(struct net_device *ndev) -+{ -+ ndev->ethtool_ops = &xgene_ethtool_ops; -+} -diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.c b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.c + static int map_madt_entry(int type, u32 acpi_id) + { + unsigned long madt_end, entry; +@@ -99,6 +131,9 @@ static int map_madt_entry(int type, u32 acpi_id) + } else if (header->type == ACPI_MADT_TYPE_LOCAL_SAPIC) { + if (!map_lsapic_id(header, type, acpi_id, &apic_id)) + break; ++ } else if (header->type == ACPI_MADT_TYPE_GENERIC_INTERRUPT) { ++ if (!map_gicc_mpidr(header, type, acpi_id, &apic_id)) ++ break; + } + entry += header->length; + } +@@ -131,6 +166,8 @@ static int map_mat_entry(acpi_handle handle, int type, u32 acpi_id) + map_lsapic_id(header, type, acpi_id, &apic_id); + } else if (header->type == ACPI_MADT_TYPE_LOCAL_X2APIC) { + map_x2apic_id(header, type, acpi_id, &apic_id); ++ } else if (header->type == ACPI_MADT_TYPE_GENERIC_INTERRUPT) { ++ map_gicc_mpidr(header, type, acpi_id, &apic_id); + } + + exit: +diff --git a/drivers/acpi/sleep-arm.c b/drivers/acpi/sleep-arm.c new file mode 100644 -index 0000000..e52af60 +index 0000000..54578ef --- /dev/null -+++ b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.c -@@ -0,0 +1,747 @@ -+/* Applied Micro X-Gene SoC Ethernet Driver -+ * -+ * Copyright (c) 2014, Applied Micro Circuits Corporation -+ * Authors: Iyappan Subramanian <isubramanian@apm.com> -+ * Ravi Patel <rapatel@apm.com> -+ * Keyur Chudgar <kchudgar@apm.com> ++++ b/drivers/acpi/sleep-arm.c +@@ -0,0 +1,28 @@ ++/* ++ * ARM64 Specific Sleep Functionality + * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. ++ * Copyright (C) 2013-2014, Linaro Ltd. ++ * Author: Graeme Gregory <graeme.gregory@linaro.org> + * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see <http://www.gnu.org/licenses/>. ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. + */ + -+#include "xgene_enet_main.h" -+#include "xgene_enet_hw.h" -+ -+static void xgene_enet_ring_init(struct xgene_enet_desc_ring *ring) -+{ -+ u32 *ring_cfg = ring->state; -+ u64 addr = ring->dma; -+ enum xgene_enet_ring_cfgsize cfgsize = ring->cfgsize; -+ -+ ring_cfg[4] |= (1 << SELTHRSH_POS) & -+ CREATE_MASK(SELTHRSH_POS, SELTHRSH_LEN); -+ ring_cfg[3] |= ACCEPTLERR; -+ ring_cfg[2] |= QCOHERENT; -+ -+ addr >>= 8; -+ ring_cfg[2] |= (addr << RINGADDRL_POS) & -+ CREATE_MASK_ULL(RINGADDRL_POS, RINGADDRL_LEN); -+ addr >>= RINGADDRL_LEN; -+ ring_cfg[3] |= addr & CREATE_MASK_ULL(RINGADDRH_POS, RINGADDRH_LEN); -+ ring_cfg[3] |= ((u32) cfgsize << RINGSIZE_POS) & -+ CREATE_MASK(RINGSIZE_POS, RINGSIZE_LEN); -+} -+ -+static void xgene_enet_ring_set_type(struct xgene_enet_desc_ring *ring) -+{ -+ u32 *ring_cfg = ring->state; -+ bool is_bufpool; -+ u32 val; -+ -+ is_bufpool = xgene_enet_is_bufpool(ring->id); -+ val = (is_bufpool) ? RING_BUFPOOL : RING_REGULAR; -+ ring_cfg[4] |= (val << RINGTYPE_POS) & -+ CREATE_MASK(RINGTYPE_POS, RINGTYPE_LEN); -+ -+ if (is_bufpool) { -+ ring_cfg[3] |= (BUFPOOL_MODE << RINGMODE_POS) & -+ CREATE_MASK(RINGMODE_POS, RINGMODE_LEN); -+ } -+} -+ -+static void xgene_enet_ring_set_recombbuf(struct xgene_enet_desc_ring *ring) -+{ -+ u32 *ring_cfg = ring->state; -+ -+ ring_cfg[3] |= RECOMBBUF; -+ ring_cfg[3] |= (0xf << RECOMTIMEOUTL_POS) & -+ CREATE_MASK(RECOMTIMEOUTL_POS, RECOMTIMEOUTL_LEN); -+ ring_cfg[4] |= 0x7 & CREATE_MASK(RECOMTIMEOUTH_POS, RECOMTIMEOUTH_LEN); -+} -+ -+static void xgene_enet_ring_wr32(struct xgene_enet_desc_ring *ring, -+ u32 offset, u32 data) -+{ -+ struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev); -+ -+ iowrite32(data, pdata->ring_csr_addr + offset); -+} -+ -+static void xgene_enet_ring_rd32(struct xgene_enet_desc_ring *ring, -+ u32 offset, u32 *data) -+{ -+ struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev); -+ -+ *data = ioread32(pdata->ring_csr_addr + offset); -+} -+ -+static void xgene_enet_write_ring_state(struct xgene_enet_desc_ring *ring) -+{ -+ int i; -+ -+ xgene_enet_ring_wr32(ring, CSR_RING_CONFIG, ring->num); -+ for (i = 0; i < NUM_RING_CONFIG; i++) { -+ xgene_enet_ring_wr32(ring, CSR_RING_WR_BASE + (i * 4), -+ ring->state[i]); -+ } -+} -+ -+static void xgene_enet_clr_ring_state(struct xgene_enet_desc_ring *ring) -+{ -+ memset(ring->state, 0, sizeof(u32) * NUM_RING_CONFIG); -+ xgene_enet_write_ring_state(ring); -+} -+ -+static void xgene_enet_set_ring_state(struct xgene_enet_desc_ring *ring) -+{ -+ xgene_enet_ring_set_type(ring); -+ -+ if (xgene_enet_ring_owner(ring->id) == RING_OWNER_ETH0) -+ xgene_enet_ring_set_recombbuf(ring); -+ -+ xgene_enet_ring_init(ring); -+ xgene_enet_write_ring_state(ring); -+} -+ -+static void xgene_enet_set_ring_id(struct xgene_enet_desc_ring *ring) -+{ -+ u32 ring_id_val, ring_id_buf; -+ bool is_bufpool; -+ -+ is_bufpool = xgene_enet_is_bufpool(ring->id); -+ -+ ring_id_val = ring->id & GENMASK(9, 0); -+ ring_id_val |= OVERWRITE; -+ -+ ring_id_buf = (ring->num << 9) & GENMASK(18, 9); -+ ring_id_buf |= PREFETCH_BUF_EN; -+ if (is_bufpool) -+ ring_id_buf |= IS_BUFFER_POOL; -+ -+ xgene_enet_ring_wr32(ring, CSR_RING_ID, ring_id_val); -+ xgene_enet_ring_wr32(ring, CSR_RING_ID_BUF, ring_id_buf); -+} ++#include <linux/acpi.h> + -+static void xgene_enet_clr_desc_ring_id(struct xgene_enet_desc_ring *ring) ++/* ++ * Currently the ACPI 5.1 standard does not define S states in a ++ * manner which is usable for ARM64. These two stubs are sufficient ++ * that system initialises and device PM works. ++ */ ++u32 acpi_target_system_state(void) +{ -+ u32 ring_id; -+ -+ ring_id = ring->id | OVERWRITE; -+ xgene_enet_ring_wr32(ring, CSR_RING_ID, ring_id); -+ xgene_enet_ring_wr32(ring, CSR_RING_ID_BUF, 0); ++ return ACPI_STATE_S0; +} ++EXPORT_SYMBOL_GPL(acpi_target_system_state); + -+struct xgene_enet_desc_ring *xgene_enet_setup_ring( -+ struct xgene_enet_desc_ring *ring) ++int __init acpi_sleep_init(void) +{ -+ u32 size = ring->size; -+ u32 i, data; -+ u64 *desc; -+ bool is_bufpool; -+ -+ xgene_enet_clr_ring_state(ring); -+ xgene_enet_set_ring_state(ring); -+ xgene_enet_set_ring_id(ring); -+ -+ ring->slots = xgene_enet_get_numslots(ring->id, size); -+ -+ is_bufpool = xgene_enet_is_bufpool(ring->id); -+ if (is_bufpool || xgene_enet_ring_owner(ring->id) != RING_OWNER_CPU) -+ return ring; -+ -+ for (i = 0; i < ring->slots; i++) { -+ desc = (u64 *)&ring->raw_desc[i]; -+ desc[EMPTY_SLOT_INDEX] = EMPTY_SLOT; -+ } -+ -+ xgene_enet_ring_rd32(ring, CSR_RING_NE_INT_MODE, &data); -+ data |= BIT(31 - xgene_enet_ring_bufnum(ring->id)); -+ xgene_enet_ring_wr32(ring, CSR_RING_NE_INT_MODE, data); -+ -+ return ring; ++ return -ENOSYS; +} +diff --git a/drivers/acpi/tables.c b/drivers/acpi/tables.c +index 6d5a6cd..47f36d4 100644 +--- a/drivers/acpi/tables.c ++++ b/drivers/acpi/tables.c +@@ -183,6 +183,49 @@ void acpi_table_print_madt_entry(struct acpi_subtable_header *header) + } + break; + ++ case ACPI_MADT_TYPE_GENERIC_INTERRUPT: ++ { ++ struct acpi_madt_generic_interrupt *p = ++ (struct acpi_madt_generic_interrupt *)header; ++ pr_info("GICC (acpi_id[0x%04x] address[%p] MPDIR[0x%llx] %s)\n", ++ p->uid, (void *)(unsigned long)p->base_address, ++ p->arm_mpidr, ++ (p->flags & ACPI_MADT_ENABLED) ? "enabled" : "disabled"); + -+void xgene_enet_clear_ring(struct xgene_enet_desc_ring *ring) -+{ -+ u32 data; -+ bool is_bufpool; -+ -+ is_bufpool = xgene_enet_is_bufpool(ring->id); -+ if (is_bufpool || xgene_enet_ring_owner(ring->id) != RING_OWNER_CPU) -+ goto out; -+ -+ xgene_enet_ring_rd32(ring, CSR_RING_NE_INT_MODE, &data); -+ data &= ~BIT(31 - xgene_enet_ring_bufnum(ring->id)); -+ xgene_enet_ring_wr32(ring, CSR_RING_NE_INT_MODE, data); -+ -+out: -+ xgene_enet_clr_desc_ring_id(ring); -+ xgene_enet_clr_ring_state(ring); -+} -+ -+void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring, -+ struct xgene_enet_pdata *pdata, -+ enum xgene_enet_err_code status) -+{ -+ struct rtnl_link_stats64 *stats = &pdata->stats; -+ -+ switch (status) { -+ case INGRESS_CRC: -+ stats->rx_crc_errors++; -+ break; -+ case INGRESS_CHECKSUM: -+ case INGRESS_CHECKSUM_COMPUTE: -+ stats->rx_errors++; -+ break; -+ case INGRESS_TRUNC_FRAME: -+ stats->rx_frame_errors++; -+ break; -+ case INGRESS_PKT_LEN: -+ stats->rx_length_errors++; -+ break; -+ case INGRESS_PKT_UNDER: -+ stats->rx_frame_errors++; -+ break; -+ case INGRESS_FIFO_OVERRUN: -+ stats->rx_fifo_errors++; -+ break; -+ default: ++ } + break; -+ } -+} -+ -+static void xgene_enet_wr_csr(struct xgene_enet_pdata *pdata, -+ u32 offset, u32 val) -+{ -+ void __iomem *addr = pdata->eth_csr_addr + offset; -+ -+ iowrite32(val, addr); -+} -+ -+static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *pdata, -+ u32 offset, u32 val) -+{ -+ void __iomem *addr = pdata->eth_ring_if_addr + offset; -+ -+ iowrite32(val, addr); -+} -+ -+static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *pdata, -+ u32 offset, u32 val) -+{ -+ void __iomem *addr = pdata->eth_diag_csr_addr + offset; -+ -+ iowrite32(val, addr); -+} -+ -+static void xgene_enet_wr_mcx_csr(struct xgene_enet_pdata *pdata, -+ u32 offset, u32 val) -+{ -+ void __iomem *addr = pdata->mcx_mac_csr_addr + offset; -+ -+ iowrite32(val, addr); -+} -+ -+static bool xgene_enet_wr_indirect(void __iomem *addr, void __iomem *wr, -+ void __iomem *cmd, void __iomem *cmd_done, -+ u32 wr_addr, u32 wr_data) -+{ -+ u32 done; -+ u8 wait = 10; -+ -+ iowrite32(wr_addr, addr); -+ iowrite32(wr_data, wr); -+ iowrite32(XGENE_ENET_WR_CMD, cmd); -+ -+ /* wait for write command to complete */ -+ while (!(done = ioread32(cmd_done)) && wait--) -+ udelay(1); -+ -+ if (!done) -+ return false; -+ -+ iowrite32(0, cmd); -+ -+ return true; -+} -+ -+static void xgene_enet_wr_mcx_mac(struct xgene_enet_pdata *pdata, -+ u32 wr_addr, u32 wr_data) -+{ -+ void __iomem *addr, *wr, *cmd, *cmd_done; -+ bool ret; -+ -+ addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET; -+ wr = pdata->mcx_mac_addr + MAC_WRITE_REG_OFFSET; -+ cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET; -+ cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET; -+ -+ ret = xgene_enet_wr_indirect(addr, wr, cmd, cmd_done, wr_addr, wr_data); -+ if (!ret) -+ netdev_err(pdata->ndev, "MCX mac write failed, addr: %04x\n", -+ wr_addr); -+} -+ -+static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata, -+ u32 offset, u32 *val) -+{ -+ void __iomem *addr = pdata->eth_csr_addr + offset; -+ -+ *val = ioread32(addr); -+} -+ -+static void xgene_enet_rd_diag_csr(struct xgene_enet_pdata *pdata, -+ u32 offset, u32 *val) -+{ -+ void __iomem *addr = pdata->eth_diag_csr_addr + offset; -+ -+ *val = ioread32(addr); -+} -+ -+static void xgene_enet_rd_mcx_csr(struct xgene_enet_pdata *pdata, -+ u32 offset, u32 *val) -+{ -+ void __iomem *addr = pdata->mcx_mac_csr_addr + offset; -+ -+ *val = ioread32(addr); -+} -+ -+static bool xgene_enet_rd_indirect(void __iomem *addr, void __iomem *rd, -+ void __iomem *cmd, void __iomem *cmd_done, -+ u32 rd_addr, u32 *rd_data) -+{ -+ u32 done; -+ u8 wait = 10; -+ -+ iowrite32(rd_addr, addr); -+ iowrite32(XGENE_ENET_RD_CMD, cmd); -+ -+ /* wait for read command to complete */ -+ while (!(done = ioread32(cmd_done)) && wait--) -+ udelay(1); -+ -+ if (!done) -+ return false; -+ -+ *rd_data = ioread32(rd); -+ iowrite32(0, cmd); -+ -+ return true; -+} -+ -+static void xgene_enet_rd_mcx_mac(struct xgene_enet_pdata *pdata, -+ u32 rd_addr, u32 *rd_data) -+{ -+ void __iomem *addr, *rd, *cmd, *cmd_done; -+ bool ret; -+ -+ addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET; -+ rd = pdata->mcx_mac_addr + MAC_READ_REG_OFFSET; -+ cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET; -+ cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET; -+ -+ ret = xgene_enet_rd_indirect(addr, rd, cmd, cmd_done, rd_addr, rd_data); -+ if (!ret) -+ netdev_err(pdata->ndev, "MCX mac read failed, addr: %04x\n", -+ rd_addr); -+} -+ -+static int xgene_mii_phy_write(struct xgene_enet_pdata *pdata, int phy_id, -+ u32 reg, u16 data) -+{ -+ u32 addr = 0, wr_data = 0; -+ u32 done; -+ u8 wait = 10; -+ -+ PHY_ADDR_SET(&addr, phy_id); -+ REG_ADDR_SET(&addr, reg); -+ xgene_enet_wr_mcx_mac(pdata, MII_MGMT_ADDRESS_ADDR, addr); -+ -+ PHY_CONTROL_SET(&wr_data, data); -+ xgene_enet_wr_mcx_mac(pdata, MII_MGMT_CONTROL_ADDR, wr_data); -+ do { -+ usleep_range(5, 10); -+ xgene_enet_rd_mcx_mac(pdata, MII_MGMT_INDICATORS_ADDR, &done); -+ } while ((done & BUSY_MASK) && wait--); -+ -+ if (done & BUSY_MASK) { -+ netdev_err(pdata->ndev, "MII_MGMT write failed\n"); -+ return -1; -+ } -+ -+ return 0; -+} -+ -+static int xgene_mii_phy_read(struct xgene_enet_pdata *pdata, -+ u8 phy_id, u32 reg) -+{ -+ u32 addr = 0; -+ u32 data, done; -+ u8 wait = 10; -+ -+ PHY_ADDR_SET(&addr, phy_id); -+ REG_ADDR_SET(&addr, reg); -+ xgene_enet_wr_mcx_mac(pdata, MII_MGMT_ADDRESS_ADDR, addr); -+ xgene_enet_wr_mcx_mac(pdata, MII_MGMT_COMMAND_ADDR, READ_CYCLE_MASK); -+ do { -+ usleep_range(5, 10); -+ xgene_enet_rd_mcx_mac(pdata, MII_MGMT_INDICATORS_ADDR, &done); -+ } while ((done & BUSY_MASK) && wait--); -+ -+ if (done & BUSY_MASK) { -+ netdev_err(pdata->ndev, "MII_MGMT read failed\n"); -+ return -1; -+ } + -+ xgene_enet_rd_mcx_mac(pdata, MII_MGMT_STATUS_ADDR, &data); -+ xgene_enet_wr_mcx_mac(pdata, MII_MGMT_COMMAND_ADDR, 0); -+ -+ return data; -+} -+ -+void xgene_gmac_set_mac_addr(struct xgene_enet_pdata *pdata) -+{ -+ u32 addr0, addr1; -+ u8 *dev_addr = pdata->ndev->dev_addr; -+ -+ addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) | -+ (dev_addr[1] << 8) | dev_addr[0]; -+ addr1 = (dev_addr[5] << 24) | (dev_addr[4] << 16); -+ addr1 |= pdata->phy_addr & 0xFFFF; -+ -+ xgene_enet_wr_mcx_mac(pdata, STATION_ADDR0_ADDR, addr0); -+ xgene_enet_wr_mcx_mac(pdata, STATION_ADDR1_ADDR, addr1); -+} -+ -+static int xgene_enet_ecc_init(struct xgene_enet_pdata *pdata) -+{ -+ struct net_device *ndev = pdata->ndev; -+ u32 data; -+ u8 wait = 10; -+ -+ xgene_enet_wr_diag_csr(pdata, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0x0); -+ do { -+ usleep_range(100, 110); -+ xgene_enet_rd_diag_csr(pdata, ENET_BLOCK_MEM_RDY_ADDR, &data); -+ } while ((data != 0xffffffff) && wait--); -+ -+ if (data != 0xffffffff) { -+ netdev_err(ndev, "Failed to release memory from shutdown\n"); -+ return -ENODEV; -+ } -+ -+ return 0; -+} -+ -+void xgene_gmac_reset(struct xgene_enet_pdata *pdata) -+{ -+ xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, SOFT_RESET1); -+ xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, 0); -+} -+ -+void xgene_gmac_init(struct xgene_enet_pdata *pdata, int speed) -+{ -+ u32 value, mc2; -+ u32 intf_ctl, rgmii; -+ u32 icm0, icm2; -+ -+ xgene_gmac_reset(pdata); -+ -+ xgene_enet_rd_mcx_csr(pdata, ICM_CONFIG0_REG_0_ADDR, &icm0); -+ xgene_enet_rd_mcx_csr(pdata, ICM_CONFIG2_REG_0_ADDR, &icm2); -+ xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_2_ADDR, &mc2); -+ xgene_enet_rd_mcx_mac(pdata, INTERFACE_CONTROL_ADDR, &intf_ctl); -+ xgene_enet_rd_csr(pdata, RGMII_REG_0_ADDR, &rgmii); -+ -+ switch (speed) { -+ case SPEED_10: -+ ENET_INTERFACE_MODE2_SET(&mc2, 1); -+ CFG_MACMODE_SET(&icm0, 0); -+ CFG_WAITASYNCRD_SET(&icm2, 500); -+ rgmii &= ~CFG_SPEED_1250; -+ break; -+ case SPEED_100: -+ ENET_INTERFACE_MODE2_SET(&mc2, 1); -+ intf_ctl |= ENET_LHD_MODE; -+ CFG_MACMODE_SET(&icm0, 1); -+ CFG_WAITASYNCRD_SET(&icm2, 80); -+ rgmii &= ~CFG_SPEED_1250; -+ break; -+ default: -+ ENET_INTERFACE_MODE2_SET(&mc2, 2); -+ intf_ctl |= ENET_GHD_MODE; -+ CFG_TXCLK_MUXSEL0_SET(&rgmii, 4); -+ xgene_enet_rd_csr(pdata, DEBUG_REG_ADDR, &value); -+ value |= CFG_BYPASS_UNISEC_TX | CFG_BYPASS_UNISEC_RX; -+ xgene_enet_wr_csr(pdata, DEBUG_REG_ADDR, value); ++ case ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR: ++ { ++ struct acpi_madt_generic_distributor *p = ++ (struct acpi_madt_generic_distributor *)header; ++ pr_info("GIC Distributor (gic_id[0x%04x] address[%p] gsi_base[%d])\n", ++ p->gic_id, ++ (void *)(unsigned long)p->base_address, ++ p->global_irq_base); ++ } + break; -+ } -+ -+ mc2 |= FULL_DUPLEX2; -+ xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_2_ADDR, mc2); -+ xgene_enet_wr_mcx_mac(pdata, INTERFACE_CONTROL_ADDR, intf_ctl); -+ -+ xgene_gmac_set_mac_addr(pdata); -+ -+ /* Adjust MDC clock frequency */ -+ xgene_enet_rd_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, &value); -+ MGMT_CLOCK_SEL_SET(&value, 7); -+ xgene_enet_wr_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, value); -+ -+ /* Enable drop if bufpool not available */ -+ xgene_enet_rd_csr(pdata, RSIF_CONFIG_REG_ADDR, &value); -+ value |= CFG_RSIF_FPBUFF_TIMEOUT_EN; -+ xgene_enet_wr_csr(pdata, RSIF_CONFIG_REG_ADDR, value); -+ -+ /* Rtype should be copied from FP */ -+ xgene_enet_wr_csr(pdata, RSIF_RAM_DBG_REG0_ADDR, 0); -+ xgene_enet_wr_csr(pdata, RGMII_REG_0_ADDR, rgmii); -+ -+ /* Rx-Tx traffic resume */ -+ xgene_enet_wr_csr(pdata, CFG_LINK_AGGR_RESUME_0_ADDR, TX_PORT0); -+ -+ xgene_enet_wr_mcx_csr(pdata, ICM_CONFIG0_REG_0_ADDR, icm0); -+ xgene_enet_wr_mcx_csr(pdata, ICM_CONFIG2_REG_0_ADDR, icm2); -+ -+ xgene_enet_rd_mcx_csr(pdata, RX_DV_GATE_REG_0_ADDR, &value); -+ value &= ~TX_DV_GATE_EN0; -+ value &= ~RX_DV_GATE_EN0; -+ value |= RESUME_RX0; -+ xgene_enet_wr_mcx_csr(pdata, RX_DV_GATE_REG_0_ADDR, value); -+ -+ xgene_enet_wr_csr(pdata, CFG_BYPASS_ADDR, RESUME_TX); -+} -+ -+static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *pdata) -+{ -+ u32 val = 0xffffffff; -+ -+ xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQASSOC_ADDR, val); -+ xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPQASSOC_ADDR, val); -+ xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEWQASSOC_ADDR, val); -+ xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEFPQASSOC_ADDR, val); -+} -+ -+void xgene_enet_cle_bypass(struct xgene_enet_pdata *pdata, -+ u32 dst_ring_num, u16 bufpool_id) -+{ -+ u32 cb; -+ u32 fpsel; -+ -+ fpsel = xgene_enet_ring_bufnum(bufpool_id) - 0x20; -+ -+ xgene_enet_rd_csr(pdata, CLE_BYPASS_REG0_0_ADDR, &cb); -+ cb |= CFG_CLE_BYPASS_EN0; -+ CFG_CLE_IP_PROTOCOL0_SET(&cb, 3); -+ xgene_enet_wr_csr(pdata, CLE_BYPASS_REG0_0_ADDR, cb); -+ -+ xgene_enet_rd_csr(pdata, CLE_BYPASS_REG1_0_ADDR, &cb); -+ CFG_CLE_DSTQID0_SET(&cb, dst_ring_num); -+ CFG_CLE_FPSEL0_SET(&cb, fpsel); -+ xgene_enet_wr_csr(pdata, CLE_BYPASS_REG1_0_ADDR, cb); -+} -+ -+void xgene_gmac_rx_enable(struct xgene_enet_pdata *pdata) -+{ -+ u32 data; -+ -+ xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data); -+ xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data | RX_EN); -+} -+ -+void xgene_gmac_tx_enable(struct xgene_enet_pdata *pdata) -+{ -+ u32 data; -+ -+ xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data); -+ xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data | TX_EN); -+} -+ -+void xgene_gmac_rx_disable(struct xgene_enet_pdata *pdata) -+{ -+ u32 data; -+ -+ xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data); -+ xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data & ~RX_EN); -+} + -+void xgene_gmac_tx_disable(struct xgene_enet_pdata *pdata) -+{ -+ u32 data; -+ -+ xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data); -+ xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data & ~TX_EN); -+} -+ -+void xgene_enet_reset(struct xgene_enet_pdata *pdata) -+{ -+ u32 val; -+ -+ clk_prepare_enable(pdata->clk); -+ clk_disable_unprepare(pdata->clk); -+ clk_prepare_enable(pdata->clk); -+ xgene_enet_ecc_init(pdata); -+ xgene_enet_config_ring_if_assoc(pdata); -+ -+ /* Enable auto-incr for scanning */ -+ xgene_enet_rd_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, &val); -+ val |= SCAN_AUTO_INCR; -+ MGMT_CLOCK_SEL_SET(&val, 1); -+ xgene_enet_wr_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, val); -+} -+ -+void xgene_gport_shutdown(struct xgene_enet_pdata *pdata) -+{ -+ clk_disable_unprepare(pdata->clk); -+} -+ -+static int xgene_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) -+{ -+ struct xgene_enet_pdata *pdata = bus->priv; -+ u32 val; -+ -+ val = xgene_mii_phy_read(pdata, mii_id, regnum); -+ netdev_dbg(pdata->ndev, "mdio_rd: bus=%d reg=%d val=%x\n", -+ mii_id, regnum, val); -+ -+ return val; -+} -+ -+static int xgene_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, -+ u16 val) -+{ -+ struct xgene_enet_pdata *pdata = bus->priv; -+ int ret; -+ -+ netdev_dbg(pdata->ndev, "mdio_wr: bus=%d reg=%d val=%x\n", -+ mii_id, regnum, val); -+ ret = xgene_mii_phy_write(pdata, mii_id, regnum, val); -+ -+ return ret; -+} -+ -+static void xgene_enet_adjust_link(struct net_device *ndev) -+{ -+ struct xgene_enet_pdata *pdata = netdev_priv(ndev); -+ struct phy_device *phydev = pdata->phy_dev; -+ -+ if (phydev->link) { -+ if (pdata->phy_speed != phydev->speed) { -+ xgene_gmac_init(pdata, phydev->speed); -+ xgene_gmac_rx_enable(pdata); -+ xgene_gmac_tx_enable(pdata); -+ pdata->phy_speed = phydev->speed; -+ phy_print_status(phydev); ++ case ACPI_MADT_TYPE_GENERIC_MSI_FRAME: ++ { ++ struct acpi_madt_generic_msi_frame *p = ++ (struct acpi_madt_generic_msi_frame *)header; ++ pr_info("GIC MSI Frame (msi_fame_id[%d] address[%p])\n", ++ p->msi_frame_id, ++ (void *)(unsigned long)p->base_address); + } -+ } else { -+ xgene_gmac_rx_disable(pdata); -+ xgene_gmac_tx_disable(pdata); -+ pdata->phy_speed = SPEED_UNKNOWN; -+ phy_print_status(phydev); -+ } -+} -+ -+static int xgene_enet_phy_connect(struct net_device *ndev) -+{ -+ struct xgene_enet_pdata *pdata = netdev_priv(ndev); -+ struct device_node *phy_np; -+ struct phy_device *phy_dev; -+ struct device *dev = &pdata->pdev->dev; -+ -+ phy_np = of_parse_phandle(dev->of_node, "phy-handle", 0); -+ if (!phy_np) { -+ netdev_dbg(ndev, "No phy-handle found\n"); -+ return -ENODEV; -+ } ++ break; + -+ phy_dev = of_phy_connect(ndev, phy_np, &xgene_enet_adjust_link, -+ 0, pdata->phy_mode); -+ if (!phy_dev) { -+ netdev_err(ndev, "Could not connect to PHY\n"); -+ return -ENODEV; -+ } ++ case ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR: ++ { ++ struct acpi_madt_generic_redistributor *p = ++ (struct acpi_madt_generic_redistributor *)header; ++ pr_info("GIC Redistributor (address[%p] region_size[0x%x])\n", ++ (void *)(unsigned long)p->base_address, ++ p->length); ++ } ++ break; + -+ pdata->phy_speed = SPEED_UNKNOWN; -+ phy_dev->supported &= ~SUPPORTED_10baseT_Half & -+ ~SUPPORTED_100baseT_Half & -+ ~SUPPORTED_1000baseT_Half; -+ phy_dev->advertising = phy_dev->supported; -+ pdata->phy_dev = phy_dev; + default: + pr_warn("Found unsupported MADT entry (type = 0x%x)\n", + header->type); +@@ -192,17 +235,14 @@ void acpi_table_print_madt_entry(struct acpi_subtable_header *header) + + + int __init +-acpi_table_parse_entries(char *id, +- unsigned long table_size, +- int entry_id, +- acpi_tbl_entry_handler handler, +- unsigned int max_entries) ++acpi_parse_entries(unsigned long table_size, ++ acpi_tbl_entry_handler handler, ++ struct acpi_table_header *table_header, ++ int entry_id, unsigned int max_entries) + { +- struct acpi_table_header *table_header = NULL; + struct acpi_subtable_header *entry; +- unsigned int count = 0; ++ int count = 0; + unsigned long table_end; +- acpi_size tbl_size; + + if (acpi_disabled) + return -ENODEV; +@@ -210,13 +250,11 @@ acpi_table_parse_entries(char *id, + if (!handler) + return -EINVAL; + +- if (strncmp(id, ACPI_SIG_MADT, 4) == 0) +- acpi_get_table_with_size(id, acpi_apic_instance, &table_header, &tbl_size); +- else +- acpi_get_table_with_size(id, 0, &table_header, &tbl_size); ++ if (!table_size) ++ return -EINVAL; + + if (!table_header) { +- pr_warn("%4.4s not present\n", id); ++ pr_warn("Table header not present\n"); + return -ENODEV; + } + +@@ -230,32 +268,67 @@ acpi_table_parse_entries(char *id, + while (((unsigned long)entry) + sizeof(struct acpi_subtable_header) < + table_end) { + if (entry->type == entry_id +- && (!max_entries || count++ < max_entries)) ++ && (!max_entries || count < max_entries)) { + if (handler(entry, table_end)) +- goto err; ++ return -EINVAL; ++ ++ count++; ++ } + + /* + * If entry->length is 0, break from this loop to avoid + * infinite loop. + */ + if (entry->length == 0) { +- pr_err("[%4.4s:0x%02x] Invalid zero length\n", id, entry_id); +- goto err; ++ pr_err("[0x%02x] Invalid zero length\n", entry_id); ++ return -EINVAL; + } + + entry = (struct acpi_subtable_header *) + ((unsigned long)entry + entry->length); + } + -+ return 0; + if (max_entries && count > max_entries) { + pr_warn("[%4.4s:0x%02x] ignored %i entries of %i found\n", +- id, entry_id, count - max_entries, count); ++ table_header->signature, entry_id, count - max_entries, ++ count); + } + +- early_acpi_os_unmap_memory((char *)table_header, tbl_size); + return count; +-err: +} + -+int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata) ++int __init ++acpi_table_parse_entries(char *id, ++ unsigned long table_size, ++ int entry_id, ++ acpi_tbl_entry_handler handler, ++ unsigned int max_entries) +{ -+ struct net_device *ndev = pdata->ndev; -+ struct device *dev = &pdata->pdev->dev; -+ struct device_node *child_np; -+ struct device_node *mdio_np = NULL; -+ struct mii_bus *mdio_bus; -+ int ret; -+ -+ for_each_child_of_node(dev->of_node, child_np) { -+ if (of_device_is_compatible(child_np, "apm,xgene-mdio")) { -+ mdio_np = child_np; -+ break; -+ } -+ } -+ -+ if (!mdio_np) { -+ netdev_dbg(ndev, "No mdio node in the dts\n"); -+ return -1; -+ } ++ struct acpi_table_header *table_header = NULL; ++ acpi_size tbl_size; ++ int count; + -+ mdio_bus = mdiobus_alloc(); -+ if (!mdio_bus) -+ return -ENOMEM; ++ if (acpi_disabled) ++ return -ENODEV; + -+ mdio_bus->name = "APM X-Gene MDIO bus"; -+ mdio_bus->read = xgene_enet_mdio_read; -+ mdio_bus->write = xgene_enet_mdio_write; -+ snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%s-%s", "xgene-mii", -+ ndev->name); ++ if (!handler) ++ return -EINVAL; + -+ mdio_bus->priv = pdata; -+ mdio_bus->parent = &ndev->dev; ++ if (strncmp(id, ACPI_SIG_MADT, 4) == 0) ++ acpi_get_table_with_size(id, acpi_apic_instance, &table_header, &tbl_size); ++ else ++ acpi_get_table_with_size(id, 0, &table_header, &tbl_size); + -+ ret = of_mdiobus_register(mdio_bus, mdio_np); -+ if (ret) { -+ netdev_err(ndev, "Failed to register MDIO bus\n"); -+ goto err; ++ if (!table_header) { ++ pr_warn("%4.4s not present\n", id); ++ return -ENODEV; + } -+ pdata->mdio_bus = mdio_bus; -+ -+ ret = xgene_enet_phy_connect(ndev); -+ if (ret) -+ goto err; -+ -+ return ret; -+ -+err: -+ mdiobus_free(mdio_bus); -+ -+ return ret; -+} + -+int xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata) -+{ -+ struct mii_bus *mdio_bus; ++ count = acpi_parse_entries(table_size, handler, table_header, ++ entry_id, max_entries); + -+ mdio_bus = pdata->mdio_bus; -+ mdiobus_unregister(mdio_bus); -+ mdiobus_free(mdio_bus); -+ pdata->mdio_bus = NULL; + early_acpi_os_unmap_memory((char *)table_header, tbl_size); +- return -EINVAL; ++ return count; + } + + int __init +diff --git a/drivers/acpi/utils.c b/drivers/acpi/utils.c +index 07c8c5a..aec9656 100644 +--- a/drivers/acpi/utils.c ++++ b/drivers/acpi/utils.c +@@ -698,3 +698,29 @@ bool acpi_check_dsm(acpi_handle handle, const u8 *uuid, int rev, u64 funcs) + return false; + } + EXPORT_SYMBOL(acpi_check_dsm); + -+ return 0; -+} -diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h -new file mode 100644 -index 0000000..2041313 ---- /dev/null -+++ b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h -@@ -0,0 +1,375 @@ -+/* Applied Micro X-Gene SoC Ethernet Driver -+ * -+ * Copyright (c) 2014, Applied Micro Circuits Corporation -+ * Authors: Iyappan Subramanian <isubramanian@apm.com> -+ * Ravi Patel <rapatel@apm.com> -+ * Keyur Chudgar <kchudgar@apm.com> -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. ++/** ++ * acpi_check_coherency - check for memory coherency of a device ++ * @handle: ACPI device handle ++ * @val: Pointer to returned value + * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see <http://www.gnu.org/licenses/>. ++ * Search a device and its parents for a _CCA method and return ++ * its value. + */ -+ -+#ifndef __XGENE_ENET_HW_H__ -+#define __XGENE_ENET_HW_H__ -+ -+#include "xgene_enet_main.h" -+ -+struct xgene_enet_pdata; -+struct xgene_enet_stats; -+ -+/* clears and then set bits */ -+static inline void xgene_set_bits(u32 *dst, u32 val, u32 start, u32 len) -+{ -+ u32 end = start + len - 1; -+ u32 mask = GENMASK(end, start); -+ -+ *dst &= ~mask; -+ *dst |= (val << start) & mask; -+} -+ -+static inline u32 xgene_get_bits(u32 val, u32 start, u32 end) -+{ -+ return (val & GENMASK(end, start)) >> start; -+} -+ -+#define CSR_RING_ID 0x0008 -+#define OVERWRITE BIT(31) -+#define IS_BUFFER_POOL BIT(20) -+#define PREFETCH_BUF_EN BIT(21) -+#define CSR_RING_ID_BUF 0x000c -+#define CSR_RING_NE_INT_MODE 0x017c -+#define CSR_RING_CONFIG 0x006c -+#define CSR_RING_WR_BASE 0x0070 -+#define NUM_RING_CONFIG 5 -+#define BUFPOOL_MODE 3 -+#define RM3 3 -+#define INC_DEC_CMD_ADDR 0x002c -+#define UDP_HDR_SIZE 2 -+#define BUF_LEN_CODE_2K 0x5000 -+ -+#define CREATE_MASK(pos, len) GENMASK((pos)+(len)-1, (pos)) -+#define CREATE_MASK_ULL(pos, len) GENMASK_ULL((pos)+(len)-1, (pos)) -+ -+/* Empty slot soft signature */ -+#define EMPTY_SLOT_INDEX 1 -+#define EMPTY_SLOT ~0ULL -+ -+#define WORK_DESC_SIZE 32 -+#define BUFPOOL_DESC_SIZE 16 -+ -+#define RING_OWNER_MASK GENMASK(9, 6) -+#define RING_BUFNUM_MASK GENMASK(5, 0) -+ -+#define SELTHRSH_POS 3 -+#define SELTHRSH_LEN 3 -+#define RINGADDRL_POS 5 -+#define RINGADDRL_LEN 27 -+#define RINGADDRH_POS 0 -+#define RINGADDRH_LEN 6 -+#define RINGSIZE_POS 23 -+#define RINGSIZE_LEN 3 -+#define RINGTYPE_POS 19 -+#define RINGTYPE_LEN 2 -+#define RINGMODE_POS 20 -+#define RINGMODE_LEN 3 -+#define RECOMTIMEOUTL_POS 28 -+#define RECOMTIMEOUTL_LEN 3 -+#define RECOMTIMEOUTH_POS 0 -+#define RECOMTIMEOUTH_LEN 2 -+#define NUMMSGSINQ_POS 1 -+#define NUMMSGSINQ_LEN 16 -+#define ACCEPTLERR BIT(19) -+#define QCOHERENT BIT(4) -+#define RECOMBBUF BIT(27) -+ -+#define BLOCK_ETH_CSR_OFFSET 0x2000 -+#define BLOCK_ETH_RING_IF_OFFSET 0x9000 -+#define BLOCK_ETH_CLKRST_CSR_OFFSET 0xC000 -+#define BLOCK_ETH_DIAG_CSR_OFFSET 0xD000 -+ -+#define BLOCK_ETH_MAC_OFFSET 0x0000 -+#define BLOCK_ETH_STATS_OFFSET 0x0014 -+#define BLOCK_ETH_MAC_CSR_OFFSET 0x2800 -+ -+#define MAC_ADDR_REG_OFFSET 0x00 -+#define MAC_COMMAND_REG_OFFSET 0x04 -+#define MAC_WRITE_REG_OFFSET 0x08 -+#define MAC_READ_REG_OFFSET 0x0c -+#define MAC_COMMAND_DONE_REG_OFFSET 0x10 -+ -+#define STAT_ADDR_REG_OFFSET 0x00 -+#define STAT_COMMAND_REG_OFFSET 0x04 -+#define STAT_WRITE_REG_OFFSET 0x08 -+#define STAT_READ_REG_OFFSET 0x0c -+#define STAT_COMMAND_DONE_REG_OFFSET 0x10 -+ -+#define MII_MGMT_CONFIG_ADDR 0x20 -+#define MII_MGMT_COMMAND_ADDR 0x24 -+#define MII_MGMT_ADDRESS_ADDR 0x28 -+#define MII_MGMT_CONTROL_ADDR 0x2c -+#define MII_MGMT_STATUS_ADDR 0x30 -+#define MII_MGMT_INDICATORS_ADDR 0x34 -+ -+#define BUSY_MASK BIT(0) -+#define READ_CYCLE_MASK BIT(0) -+#define PHY_CONTROL_SET(dst, val) xgene_set_bits(dst, val, 0, 16) -+ -+#define ENET_SPARE_CFG_REG_ADDR 0x0750 -+#define RSIF_CONFIG_REG_ADDR 0x0010 -+#define RSIF_RAM_DBG_REG0_ADDR 0x0048 -+#define RGMII_REG_0_ADDR 0x07e0 -+#define CFG_LINK_AGGR_RESUME_0_ADDR 0x07c8 -+#define DEBUG_REG_ADDR 0x0700 -+#define CFG_BYPASS_ADDR 0x0294 -+#define CLE_BYPASS_REG0_0_ADDR 0x0490 -+#define CLE_BYPASS_REG1_0_ADDR 0x0494 -+#define CFG_RSIF_FPBUFF_TIMEOUT_EN BIT(31) -+#define RESUME_TX BIT(0) -+#define CFG_SPEED_1250 BIT(24) -+#define TX_PORT0 BIT(0) -+#define CFG_BYPASS_UNISEC_TX BIT(2) -+#define CFG_BYPASS_UNISEC_RX BIT(1) -+#define CFG_CLE_BYPASS_EN0 BIT(31) -+#define CFG_TXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 29, 3) -+ -+#define CFG_CLE_IP_PROTOCOL0_SET(dst, val) xgene_set_bits(dst, val, 16, 2) -+#define CFG_CLE_DSTQID0_SET(dst, val) xgene_set_bits(dst, val, 0, 12) -+#define CFG_CLE_FPSEL0_SET(dst, val) xgene_set_bits(dst, val, 16, 4) -+#define CFG_MACMODE_SET(dst, val) xgene_set_bits(dst, val, 18, 2) -+#define CFG_WAITASYNCRD_SET(dst, val) xgene_set_bits(dst, val, 0, 16) -+#define ICM_CONFIG0_REG_0_ADDR 0x0400 -+#define ICM_CONFIG2_REG_0_ADDR 0x0410 -+#define RX_DV_GATE_REG_0_ADDR 0x05fc -+#define TX_DV_GATE_EN0 BIT(2) -+#define RX_DV_GATE_EN0 BIT(1) -+#define RESUME_RX0 BIT(0) -+#define ENET_CFGSSQMIWQASSOC_ADDR 0xe0 -+#define ENET_CFGSSQMIFPQASSOC_ADDR 0xdc -+#define ENET_CFGSSQMIQMLITEFPQASSOC_ADDR 0xf0 -+#define ENET_CFGSSQMIQMLITEWQASSOC_ADDR 0xf4 -+#define ENET_CFG_MEM_RAM_SHUTDOWN_ADDR 0x70 -+#define ENET_BLOCK_MEM_RDY_ADDR 0x74 -+#define MAC_CONFIG_1_ADDR 0x00 -+#define MAC_CONFIG_2_ADDR 0x04 -+#define MAX_FRAME_LEN_ADDR 0x10 -+#define INTERFACE_CONTROL_ADDR 0x38 -+#define STATION_ADDR0_ADDR 0x40 -+#define STATION_ADDR1_ADDR 0x44 -+#define PHY_ADDR_SET(dst, val) xgene_set_bits(dst, val, 8, 5) -+#define REG_ADDR_SET(dst, val) xgene_set_bits(dst, val, 0, 5) -+#define ENET_INTERFACE_MODE2_SET(dst, val) xgene_set_bits(dst, val, 8, 2) -+#define MGMT_CLOCK_SEL_SET(dst, val) xgene_set_bits(dst, val, 0, 3) -+#define SOFT_RESET1 BIT(31) -+#define TX_EN BIT(0) -+#define RX_EN BIT(2) -+#define ENET_LHD_MODE BIT(25) -+#define ENET_GHD_MODE BIT(26) -+#define FULL_DUPLEX2 BIT(0) -+#define SCAN_AUTO_INCR BIT(5) -+#define TBYT_ADDR 0x38 -+#define TPKT_ADDR 0x39 -+#define TDRP_ADDR 0x45 -+#define TFCS_ADDR 0x47 -+#define TUND_ADDR 0x4a -+ -+#define TSO_IPPROTO_TCP 1 -+#define FULL_DUPLEX 2 -+ -+#define USERINFO_POS 0 -+#define USERINFO_LEN 32 -+#define FPQNUM_POS 32 -+#define FPQNUM_LEN 12 -+#define LERR_POS 60 -+#define LERR_LEN 3 -+#define STASH_POS 52 -+#define STASH_LEN 2 -+#define BUFDATALEN_POS 48 -+#define BUFDATALEN_LEN 12 -+#define DATAADDR_POS 0 -+#define DATAADDR_LEN 42 -+#define COHERENT_POS 63 -+#define HENQNUM_POS 48 -+#define HENQNUM_LEN 12 -+#define TYPESEL_POS 44 -+#define TYPESEL_LEN 4 -+#define ETHHDR_POS 12 -+#define IC_POS 35 /* Insert CRC */ -+#define TCPHDR_POS 0 -+#define TCPHDR_LEN 6 -+#define IPHDR_POS 6 -+#define IPHDR_LEN 6 -+#define EC_POS 22 /* Enable checksum */ -+#define IS_POS 24 /* IP protocol select */ -+ -+#define DATAADDR_MASK CREATE_MASK_ULL(DATAADDR_POS, DATAADDR_LEN) -+#define BUFDATALEN_MASK CREATE_MASK_ULL(BUFDATALEN_POS, BUFDATALEN_LEN) -+#define USERINFO_MASK CREATE_MASK_ULL(USERINFO_POS, USERINFO_LEN) -+#define FPQNUM_MASK CREATE_MASK_ULL(FPQNUM_POS, FPQNUM_LEN) -+#define LERR_MASK CREATE_MASK_ULL(LERR_POS, LERR_LEN) -+#define STASHING_MASK CREATE_MASK_ULL(STASH_POS, STASH_LEN) -+#define COHERENT_MASK BIT_ULL(COHERENT_POS) -+#define HENQNUM_MASK CREATE_MASK_ULL(HENQNUM_POS, HENQNUM_LEN) -+#define TCPHDR_MASK CREATE_MASK(TCPHDR_POS, TCPHDR_LEN) -+#define IPHDR_MASK CREATE_MASK(IPHDR_POS, IPHDR_LEN) -+#define EC_MASK BIT(EC_POS) -+#define IS_MASK BIT(IS_POS) -+#define INSERT_CRC BIT_ULL(IC_POS) -+#define TYPE_ETH_WORK_MESSAGE BIT_ULL(44) -+ -+struct xgene_enet_raw_desc { -+ u64 m0; -+ u64 m1; -+ u64 m2; -+ u64 m3; -+}; -+ -+struct xgene_enet_raw_desc16 { -+ u64 m0; -+ u64 m1; -+}; -+ -+static inline void xgene_enet_cpu_to_le64(void *desc_ptr, int count) -+{ -+ u64 *desc = desc_ptr; -+ int i; -+ -+ for (i = 0; i < count; i++) -+ desc[i] = cpu_to_le64(desc[i]); -+} -+ -+static inline void xgene_enet_le64_to_cpu(void *desc_ptr, int count) ++acpi_status acpi_check_coherency(acpi_handle handle, int *val) +{ -+ u64 *desc = desc_ptr; -+ int i; -+ -+ for (i = 0; i < count; i++) -+ desc[i] = le64_to_cpu(desc[i]); -+} -+ -+static inline void xgene_enet_desc16_to_le64(void *desc_ptr) -+{ -+ u64 *desc; -+ -+ desc = desc_ptr; -+ desc[1] = cpu_to_le64(desc[1]); -+} -+ -+static inline void xgene_enet_le64_to_desc16(void *desc_ptr) -+{ -+ u64 *desc; -+ -+ desc = desc_ptr; -+ desc[1] = le64_to_cpu(desc[1]); -+} -+ -+enum xgene_enet_ring_cfgsize { -+ RING_CFGSIZE_512B, -+ RING_CFGSIZE_2KB, -+ RING_CFGSIZE_16KB, -+ RING_CFGSIZE_64KB, -+ RING_CFGSIZE_512KB, -+ RING_CFGSIZE_INVALID -+}; -+ -+enum xgene_enet_ring_type { -+ RING_DISABLED, -+ RING_REGULAR, -+ RING_BUFPOOL -+}; ++ unsigned long long data; ++ acpi_status status; + -+enum xgene_ring_owner { -+ RING_OWNER_ETH0, -+ RING_OWNER_CPU = 15, -+ RING_OWNER_INVALID -+}; -+ -+enum xgene_enet_ring_bufnum { -+ RING_BUFNUM_REGULAR = 0x0, -+ RING_BUFNUM_BUFPOOL = 0x20, -+ RING_BUFNUM_INVALID ++ do { ++ status = acpi_evaluate_integer(handle, "_CCA", NULL, &data); ++ if (!ACPI_FAILURE(status)) { ++ *val = data; ++ break; ++ } ++ status = acpi_get_parent(handle, &handle); ++ } while (!ACPI_FAILURE(status)); ++ ++ return status; ++} ++EXPORT_SYMBOL(acpi_check_coherency); +diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig +index e1b9278..f2e6c9e 100644 +--- a/drivers/ata/Kconfig ++++ b/drivers/ata/Kconfig +@@ -48,7 +48,7 @@ config ATA_VERBOSE_ERROR + + config ATA_ACPI + bool "ATA ACPI Support" +- depends on ACPI && PCI ++ depends on ACPI + default y + help + This option adds support for ATA-related ACPI objects. +diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c +index f61ddb9..3499bab 100644 +--- a/drivers/ata/ahci_platform.c ++++ b/drivers/ata/ahci_platform.c +@@ -20,6 +20,9 @@ + #include <linux/platform_device.h> + #include <linux/libata.h> + #include <linux/ahci_platform.h> ++#ifdef CONFIG_ATA_ACPI ++#include <linux/acpi.h> ++#endif + #include "ahci.h" + + static const struct ata_port_info ahci_port_info = { +@@ -87,6 +90,13 @@ static const struct of_device_id ahci_of_match[] = { + }; + MODULE_DEVICE_TABLE(of, ahci_of_match); + ++#ifdef CONFIG_ATA_ACPI ++static const struct acpi_device_id ahci_acpi_match[] = { ++ { "AMDI0600", 0 }, /* AMD Seattle AHCI */ ++ { }, +}; ++#endif + -+enum xgene_enet_cmd { -+ XGENE_ENET_WR_CMD = BIT(31), -+ XGENE_ENET_RD_CMD = BIT(30) -+}; + static struct platform_driver ahci_driver = { + .probe = ahci_probe, + .remove = ata_platform_remove_one, +@@ -94,6 +104,9 @@ static struct platform_driver ahci_driver = { + .name = "ahci", + .owner = THIS_MODULE, + .of_match_table = ahci_of_match, ++#ifdef CONFIG_ATA_ACPI ++ .acpi_match_table = ACPI_PTR(ahci_acpi_match), ++#endif + .pm = &ahci_pm_ops, + }, + }; +diff --git a/drivers/ata/ahci_xgene.c b/drivers/ata/ahci_xgene.c +index f03aab1..b02ba9d 100644 +--- a/drivers/ata/ahci_xgene.c ++++ b/drivers/ata/ahci_xgene.c +@@ -28,6 +28,7 @@ + #include <linux/of_address.h> + #include <linux/of_irq.h> + #include <linux/phy/phy.h> ++#include <linux/acpi.h> + #include "ahci.h" + + /* Max # of disk per a controller */ +@@ -137,7 +138,8 @@ static unsigned int xgene_ahci_qc_issue(struct ata_queued_cmd *qc) + struct xgene_ahci_context *ctx = hpriv->plat_data; + int rc = 0; + +- if (unlikely(ctx->last_cmd[ap->port_no] == ATA_CMD_ID_ATA)) ++ if (unlikely(ctx->last_cmd[ap->port_no] == ATA_CMD_ID_ATA || ++ ctx->last_cmd[ap->port_no] == ATA_CMD_SMART)) + xgene_ahci_restart_engine(ap); + + rc = ahci_qc_issue(qc); +@@ -148,14 +150,6 @@ static unsigned int xgene_ahci_qc_issue(struct ata_queued_cmd *qc) + return rc; + } + +-static bool xgene_ahci_is_memram_inited(struct xgene_ahci_context *ctx) +-{ +- void __iomem *diagcsr = ctx->csr_diag; +- +- return (readl(diagcsr + CFG_MEM_RAM_SHUTDOWN) == 0 && +- readl(diagcsr + BLOCK_MEM_RDY) == 0xFFFFFFFF); +-} +- + /** + * xgene_ahci_read_id - Read ID data from the specified device + * @dev: device +@@ -495,11 +489,6 @@ static int xgene_ahci_probe(struct platform_device *pdev) + return -ENODEV; + } + +- if (xgene_ahci_is_memram_inited(ctx)) { +- dev_info(dev, "skip clock and PHY initialization\n"); +- goto skip_clk_phy; +- } +- + /* Due to errata, HW requires full toggle transition */ + rc = ahci_platform_enable_clks(hpriv); + if (rc) +@@ -512,7 +501,7 @@ static int xgene_ahci_probe(struct platform_device *pdev) + + /* Configure the host controller */ + xgene_ahci_hw_init(hpriv); +-skip_clk_phy: + -+enum xgene_enet_err_code { -+ HBF_READ_DATA = 3, -+ HBF_LL_READ = 4, -+ BAD_WORK_MSG = 6, -+ BUFPOOL_TIMEOUT = 15, -+ INGRESS_CRC = 16, -+ INGRESS_CHECKSUM = 17, -+ INGRESS_TRUNC_FRAME = 18, -+ INGRESS_PKT_LEN = 19, -+ INGRESS_PKT_UNDER = 20, -+ INGRESS_FIFO_OVERRUN = 21, -+ INGRESS_CHECKSUM_COMPUTE = 26, -+ ERR_CODE_INVALID + hpriv->flags = AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_NCQ; + + rc = ahci_platform_init_host(pdev, hpriv, &xgene_ahci_port_info); +@@ -527,6 +516,16 @@ disable_resources: + return rc; + } + ++#ifdef CONFIG_ACPI ++static const struct acpi_device_id xgene_ahci_acpi_match[] = { ++ { "APMC0D00", }, ++ { "APMC0D0D", }, ++ { "APMC0D09", }, ++ { } +}; ++MODULE_DEVICE_TABLE(acpi, xgene_ahci_acpi_match); ++#endif + -+static inline enum xgene_ring_owner xgene_enet_ring_owner(u16 id) -+{ -+ return (id & RING_OWNER_MASK) >> 6; -+} -+ -+static inline u8 xgene_enet_ring_bufnum(u16 id) -+{ -+ return id & RING_BUFNUM_MASK; -+} -+ -+static inline bool xgene_enet_is_bufpool(u16 id) -+{ -+ return ((id & RING_BUFNUM_MASK) >= 0x20) ? true : false; -+} -+ -+static inline u16 xgene_enet_get_numslots(u16 id, u32 size) -+{ -+ bool is_bufpool = xgene_enet_is_bufpool(id); -+ -+ return (is_bufpool) ? size / BUFPOOL_DESC_SIZE : -+ size / WORK_DESC_SIZE; -+} -+ -+struct xgene_enet_desc_ring *xgene_enet_setup_ring( -+ struct xgene_enet_desc_ring *ring); -+void xgene_enet_clear_ring(struct xgene_enet_desc_ring *ring); -+ -+void xgene_set_tx_desc(struct xgene_enet_desc_ring *ring, -+ struct xgene_enet_raw_desc *raw_desc); -+void xgene_get_desc(struct xgene_enet_desc_ring *ring, -+ struct xgene_enet_raw_desc *raw_desc); -+void xgene_get_bufpool_desc(struct xgene_enet_desc_ring *ring, -+ struct xgene_enet_raw_desc16 *raw_desc); -+void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring, -+ struct xgene_enet_pdata *pdata, -+ enum xgene_enet_err_code status); -+ -+void xgene_enet_reset(struct xgene_enet_pdata *priv); -+void xgene_gmac_reset(struct xgene_enet_pdata *priv); -+void xgene_gmac_init(struct xgene_enet_pdata *priv, int speed); -+void xgene_gmac_tx_enable(struct xgene_enet_pdata *priv); -+void xgene_gmac_rx_enable(struct xgene_enet_pdata *priv); -+void xgene_gmac_tx_disable(struct xgene_enet_pdata *priv); -+void xgene_gmac_rx_disable(struct xgene_enet_pdata *priv); -+void xgene_gmac_set_mac_addr(struct xgene_enet_pdata *pdata); -+void xgene_enet_cle_bypass(struct xgene_enet_pdata *pdata, -+ u32 dst_ring_num, u16 bufpool_id); -+void xgene_gport_shutdown(struct xgene_enet_pdata *priv); -+void xgene_gmac_get_tx_stats(struct xgene_enet_pdata *pdata); -+ -+int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata); -+int xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata); -+ -+#endif /* __XGENE_ENET_HW_H__ */ -diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_main.c b/drivers/net/ethernet/apm/xgene/xgene_enet_main.c -new file mode 100644 -index 0000000..756523a ---- /dev/null -+++ b/drivers/net/ethernet/apm/xgene/xgene_enet_main.c -@@ -0,0 +1,962 @@ -+/* Applied Micro X-Gene SoC Ethernet Driver -+ * -+ * Copyright (c) 2014, Applied Micro Circuits Corporation -+ * Authors: Iyappan Subramanian <isubramanian@apm.com> -+ * Ravi Patel <rapatel@apm.com> -+ * Keyur Chudgar <kchudgar@apm.com> -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+ -+#include "xgene_enet_main.h" -+#include "xgene_enet_hw.h" -+ -+static void xgene_enet_init_bufpool(struct xgene_enet_desc_ring *buf_pool) -+{ -+ struct xgene_enet_raw_desc16 *raw_desc; -+ int i; -+ -+ for (i = 0; i < buf_pool->slots; i++) { -+ raw_desc = &buf_pool->raw_desc16[i]; -+ -+ /* Hardware expects descriptor in little endian format */ -+ raw_desc->m0 = cpu_to_le64(i | -+ (((u64)buf_pool->dst_ring_num << FPQNUM_POS) & -+ FPQNUM_MASK) | STASHING_MASK); -+ } -+} -+ -+static struct device *ndev_to_dev(struct net_device *ndev) -+{ -+ return ndev->dev.parent; -+} + static const struct of_device_id xgene_ahci_of_match[] = { + {.compatible = "apm,xgene-ahci"}, + {}, +@@ -540,6 +539,7 @@ static struct platform_driver xgene_ahci_driver = { + .name = "xgene-ahci", + .owner = THIS_MODULE, + .of_match_table = xgene_ahci_of_match, ++ .acpi_match_table = ACPI_PTR(xgene_ahci_acpi_match), + }, + }; + +diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c +index 5163ec1..1bec05b 100644 +--- a/drivers/clocksource/arm_arch_timer.c ++++ b/drivers/clocksource/arm_arch_timer.c +@@ -21,6 +21,7 @@ + #include <linux/io.h> + #include <linux/slab.h> + #include <linux/sched_clock.h> ++#include <linux/acpi.h> + + #include <asm/arch_timer.h> + #include <asm/virt.h> +@@ -61,7 +62,8 @@ enum ppi_nr { + MAX_TIMER_PPI + }; + +-static int arch_timer_ppi[MAX_TIMER_PPI]; ++int arch_timer_ppi[MAX_TIMER_PPI]; ++EXPORT_SYMBOL(arch_timer_ppi); + + static struct clock_event_device __percpu *arch_timer_evt; + +@@ -338,8 +340,12 @@ arch_timer_detect_rate(void __iomem *cntbase, struct device_node *np) + if (arch_timer_rate) + return; + +- /* Try to determine the frequency from the device tree or CNTFRQ */ +- if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) { ++ /* ++ * Try to determine the frequency from the device tree or CNTFRQ, ++ * if ACPI is enabled, get the frequency from CNTFRQ ONLY. ++ */ ++ if (!acpi_disabled || ++ of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) { + if (cntbase) + arch_timer_rate = readl_relaxed(cntbase + CNTFRQ); + else +@@ -635,20 +641,8 @@ static void __init arch_timer_common_init(void) + arch_timer_arch_init(); + } + +-static void __init arch_timer_init(struct device_node *np) ++static void __init arch_timer_init(void) + { +- int i; +- +- if (arch_timers_present & ARCH_CP15_TIMER) { +- pr_warn("arch_timer: multiple nodes in dt, skipping\n"); +- return; +- } +- +- arch_timers_present |= ARCH_CP15_TIMER; +- for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++) +- arch_timer_ppi[i] = irq_of_parse_and_map(np, i); +- arch_timer_detect_rate(NULL, np); +- + /* + * If HYP mode is available, we know that the physical timer + * has been configured to be accessible from PL1. Use it, so +@@ -667,13 +661,31 @@ static void __init arch_timer_init(struct device_node *np) + } + } + +- arch_timer_c3stop = !of_property_read_bool(np, "always-on"); +- + arch_timer_register(); + arch_timer_common_init(); + } +-CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_init); +-CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_init); + -+static int xgene_enet_refill_bufpool(struct xgene_enet_desc_ring *buf_pool, -+ u32 nbuf) ++static void __init arch_timer_of_init(struct device_node *np) +{ -+ struct sk_buff *skb; -+ struct xgene_enet_raw_desc16 *raw_desc; -+ struct net_device *ndev; -+ struct device *dev; -+ dma_addr_t dma_addr; -+ u32 tail = buf_pool->tail; -+ u32 slots = buf_pool->slots - 1; -+ u16 bufdatalen, len; + int i; + -+ ndev = buf_pool->ndev; -+ dev = ndev_to_dev(buf_pool->ndev); -+ bufdatalen = BUF_LEN_CODE_2K | (SKB_BUFFER_SIZE & GENMASK(11, 0)); -+ len = XGENE_ENET_MAX_MTU; -+ -+ for (i = 0; i < nbuf; i++) { -+ raw_desc = &buf_pool->raw_desc16[tail]; -+ -+ skb = netdev_alloc_skb_ip_align(ndev, len); -+ if (unlikely(!skb)) -+ return -ENOMEM; -+ buf_pool->rx_skb[tail] = skb; -+ -+ dma_addr = dma_map_single(dev, skb->data, len, DMA_FROM_DEVICE); -+ if (dma_mapping_error(dev, dma_addr)) { -+ netdev_err(ndev, "DMA mapping error\n"); -+ dev_kfree_skb_any(skb); -+ return -EINVAL; -+ } -+ -+ raw_desc->m1 = cpu_to_le64((dma_addr & DATAADDR_MASK) | -+ (((u64)bufdatalen << BUFDATALEN_POS) & -+ BUFDATALEN_MASK) | COHERENT_MASK); -+ tail = (tail + 1) & slots; ++ if (arch_timers_present & ARCH_CP15_TIMER) { ++ pr_warn("arch_timer: multiple nodes in dt, skipping\n"); ++ return; + } + -+ iowrite32(nbuf, buf_pool->cmd); -+ buf_pool->tail = tail; ++ arch_timers_present |= ARCH_CP15_TIMER; ++ for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++) ++ arch_timer_ppi[i] = irq_of_parse_and_map(np, i); + -+ return 0; -+} -+ -+static u16 xgene_enet_dst_ring_num(struct xgene_enet_desc_ring *ring) -+{ -+ struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev); ++ arch_timer_detect_rate(NULL, np); + -+ return ((u16)pdata->rm << 10) | ring->num; -+} -+ -+static u8 xgene_enet_hdr_len(const void *data) -+{ -+ const struct ethhdr *eth = data; ++ arch_timer_c3stop = !of_property_read_bool(np, "always-on"); + -+ return (eth->h_proto == htons(ETH_P_8021Q)) ? VLAN_ETH_HLEN : ETH_HLEN; -+} -+ -+static u32 xgene_enet_ring_len(struct xgene_enet_desc_ring *ring) -+{ -+ u32 *cmd_base = ring->cmd_base; -+ u32 ring_state, num_msgs; -+ -+ ring_state = ioread32(&cmd_base[1]); -+ num_msgs = ring_state & CREATE_MASK(NUMMSGSINQ_POS, NUMMSGSINQ_LEN); -+ -+ return num_msgs >> NUMMSGSINQ_POS; -+} -+ -+static void xgene_enet_delete_bufpool(struct xgene_enet_desc_ring *buf_pool) -+{ -+ struct xgene_enet_raw_desc16 *raw_desc; -+ u32 slots = buf_pool->slots - 1; -+ u32 tail = buf_pool->tail; -+ u32 userinfo; -+ int i, len; -+ -+ len = xgene_enet_ring_len(buf_pool); -+ for (i = 0; i < len; i++) { -+ tail = (tail - 1) & slots; -+ raw_desc = &buf_pool->raw_desc16[tail]; -+ -+ /* Hardware stores descriptor in little endian format */ -+ userinfo = le64_to_cpu(raw_desc->m0) & USERINFO_MASK; -+ dev_kfree_skb_any(buf_pool->rx_skb[userinfo]); -+ } -+ -+ iowrite32(-len, buf_pool->cmd); -+ buf_pool->tail = tail; ++ arch_timer_init(); +} ++CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init); ++CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init); + + static void __init arch_timer_mem_init(struct device_node *np) + { +@@ -740,3 +752,71 @@ static void __init arch_timer_mem_init(struct device_node *np) + } + CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem", + arch_timer_mem_init); + -+static irqreturn_t xgene_enet_rx_irq(const int irq, void *data) ++#ifdef CONFIG_ACPI ++static int __init ++map_generic_timer_interrupt(u32 interrupt, u32 flags) +{ -+ struct xgene_enet_desc_ring *rx_ring = data; -+ -+ if (napi_schedule_prep(&rx_ring->napi)) { -+ disable_irq_nosync(irq); -+ __napi_schedule(&rx_ring->napi); -+ } ++ int trigger, polarity; + -+ return IRQ_HANDLED; -+} ++ if (!interrupt) ++ return 0; + -+static int xgene_enet_tx_completion(struct xgene_enet_desc_ring *cp_ring, -+ struct xgene_enet_raw_desc *raw_desc) -+{ -+ struct sk_buff *skb; -+ struct device *dev; -+ u16 skb_index; -+ u8 status; -+ int ret = 0; -+ -+ skb_index = raw_desc->m0 & USERINFO_MASK; -+ skb = cp_ring->cp_skb[skb_index]; -+ -+ dev = ndev_to_dev(cp_ring->ndev); -+ dma_unmap_single(dev, raw_desc->m1 & DATAADDR_MASK, -+ (raw_desc->m1 & BUFDATALEN_MASK) >> BUFDATALEN_POS, -+ DMA_TO_DEVICE); -+ -+ /* Checking for error */ -+ status = (raw_desc->m0 & LERR_MASK) >> LERR_POS; -+ if (unlikely(status > 2)) { -+ xgene_enet_parse_error(cp_ring, netdev_priv(cp_ring->ndev), -+ status); -+ ret = -1; -+ } ++ trigger = (flags & ACPI_GTDT_INTERRUPT_MODE) ? ACPI_EDGE_SENSITIVE ++ : ACPI_LEVEL_SENSITIVE; + -+ if (likely(skb)) { -+ dev_kfree_skb_any(skb); -+ } else { -+ netdev_err(cp_ring->ndev, "completion skb is NULL\n"); -+ ret = -1; -+ } ++ polarity = (flags & ACPI_GTDT_INTERRUPT_POLARITY) ? ACPI_ACTIVE_LOW ++ : ACPI_ACTIVE_HIGH; + -+ return ret; ++ return acpi_register_gsi(NULL, interrupt, trigger, polarity); +} + -+static u64 xgene_enet_work_msg(struct sk_buff *skb) ++/* Initialize per-processor generic timer */ ++static int __init arch_timer_acpi_init(struct acpi_table_header *table) +{ -+ struct iphdr *iph; -+ u8 l3hlen, l4hlen = 0; -+ u8 csum_enable = 0; -+ u8 proto = 0; -+ u8 ethhdr; -+ u64 hopinfo; -+ -+ if (unlikely(skb->protocol != htons(ETH_P_IP)) && -+ unlikely(skb->protocol != htons(ETH_P_8021Q))) -+ goto out; -+ -+ if (unlikely(!(skb->dev->features & NETIF_F_IP_CSUM))) -+ goto out; -+ -+ iph = ip_hdr(skb); -+ if (unlikely(ip_is_fragment(iph))) -+ goto out; -+ -+ if (likely(iph->protocol == IPPROTO_TCP)) { -+ l4hlen = tcp_hdrlen(skb) >> 2; -+ csum_enable = 1; -+ proto = TSO_IPPROTO_TCP; -+ } else if (iph->protocol == IPPROTO_UDP) { -+ l4hlen = UDP_HDR_SIZE; -+ csum_enable = 1; -+ } -+out: -+ l3hlen = ip_hdrlen(skb) >> 2; -+ ethhdr = xgene_enet_hdr_len(skb->data); -+ hopinfo = (l4hlen & TCPHDR_MASK) | -+ ((l3hlen << IPHDR_POS) & IPHDR_MASK) | -+ (ethhdr << ETHHDR_POS) | -+ (csum_enable << EC_POS) | -+ (proto << IS_POS) | -+ INSERT_CRC | -+ TYPE_ETH_WORK_MESSAGE; -+ -+ return hopinfo; -+} ++ struct acpi_table_gtdt *gtdt; + -+static int xgene_enet_setup_tx_desc(struct xgene_enet_desc_ring *tx_ring, -+ struct sk_buff *skb) -+{ -+ struct device *dev = ndev_to_dev(tx_ring->ndev); -+ struct xgene_enet_raw_desc *raw_desc; -+ dma_addr_t dma_addr; -+ u16 tail = tx_ring->tail; -+ u64 hopinfo; -+ -+ raw_desc = &tx_ring->raw_desc[tail]; -+ memset(raw_desc, 0, sizeof(struct xgene_enet_raw_desc)); -+ -+ dma_addr = dma_map_single(dev, skb->data, skb->len, DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, dma_addr)) { -+ netdev_err(tx_ring->ndev, "DMA mapping error\n"); ++ if (arch_timers_present & ARCH_CP15_TIMER) { ++ pr_warn("arch_timer: already initialized, skipping\n"); + return -EINVAL; + } + -+ /* Hardware expects descriptor in little endian format */ -+ raw_desc->m0 = cpu_to_le64(tail); -+ raw_desc->m1 = cpu_to_le64((dma_addr & DATAADDR_MASK) | -+ (((u64)skb->len << BUFDATALEN_POS) & BUFDATALEN_MASK) | -+ COHERENT_MASK); -+ hopinfo = xgene_enet_work_msg(skb); -+ raw_desc->m3 = cpu_to_le64( -+ (((u64)tx_ring->dst_ring_num << HENQNUM_POS) & -+ HENQNUM_MASK) | hopinfo); -+ tx_ring->cp_ring->cp_skb[tail] = skb; -+ -+ return 0; -+} -+ -+static netdev_tx_t xgene_enet_start_xmit(struct sk_buff *skb, -+ struct net_device *ndev) -+{ -+ struct xgene_enet_pdata *pdata = netdev_priv(ndev); -+ struct xgene_enet_desc_ring *tx_ring = pdata->tx_ring; -+ struct xgene_enet_desc_ring *cp_ring = tx_ring->cp_ring; -+ u32 tx_level, cq_level; -+ -+ tx_level = xgene_enet_ring_len(tx_ring); -+ cq_level = xgene_enet_ring_len(cp_ring); -+ if (unlikely(tx_level > pdata->tx_qcnt_hi || -+ cq_level > pdata->cp_qcnt_hi)) { -+ netif_stop_queue(ndev); -+ return NETDEV_TX_BUSY; -+ } -+ -+ if (xgene_enet_setup_tx_desc(tx_ring, skb)) { -+ dev_kfree_skb_any(skb); -+ return NETDEV_TX_OK; -+ } -+ -+ iowrite32(1, tx_ring->cmd); -+ skb_tx_timestamp(skb); -+ tx_ring->tail = (tx_ring->tail + 1) & (tx_ring->slots - 1); -+ -+ pdata->stats.tx_packets++; -+ pdata->stats.tx_bytes += skb->len; -+ -+ return NETDEV_TX_OK; -+} -+ -+static void xgene_enet_skip_csum(struct sk_buff *skb) -+{ -+ struct iphdr *iph = ip_hdr(skb); -+ -+ if (!ip_is_fragment(iph) || -+ (iph->protocol != IPPROTO_TCP && iph->protocol != IPPROTO_UDP)) { -+ skb->ip_summed = CHECKSUM_UNNECESSARY; -+ } -+} -+ -+static int xgene_enet_rx_frame(struct xgene_enet_desc_ring *rx_ring, -+ struct xgene_enet_raw_desc *raw_desc) -+{ -+ struct net_device *ndev; -+ struct xgene_enet_pdata *pdata; -+ struct device *dev; -+ struct xgene_enet_desc_ring *buf_pool; -+ u32 datalen, skb_index; -+ struct sk_buff *skb; -+ u8 status; -+ int ret = 0; -+ -+ ndev = rx_ring->ndev; -+ pdata = netdev_priv(ndev); -+ dev = ndev_to_dev(rx_ring->ndev); -+ buf_pool = rx_ring->buf_pool; -+ -+ dma_unmap_single(dev, raw_desc->m1 & DATAADDR_MASK, XGENE_ENET_MAX_MTU, -+ DMA_FROM_DEVICE); -+ skb_index = raw_desc->m0 & USERINFO_MASK; -+ skb = buf_pool->rx_skb[skb_index]; -+ -+ /* checking for error */ -+ status = (raw_desc->m0 & LERR_MASK) >> LERR_POS; -+ if (unlikely(status > 2)) { -+ dev_kfree_skb_any(skb); -+ xgene_enet_parse_error(rx_ring, netdev_priv(rx_ring->ndev), -+ status); -+ pdata->stats.rx_dropped++; -+ ret = -1; -+ goto out; -+ } -+ -+ /* strip off CRC as HW isn't doing this */ -+ datalen = (raw_desc->m1 & BUFDATALEN_MASK) >> BUFDATALEN_POS; -+ datalen -= 4; -+ prefetch(skb->data - NET_IP_ALIGN); -+ skb_put(skb, datalen); -+ -+ skb_checksum_none_assert(skb); -+ skb->protocol = eth_type_trans(skb, ndev); -+ if (likely((ndev->features & NETIF_F_IP_CSUM) && -+ skb->protocol == htons(ETH_P_IP))) { -+ xgene_enet_skip_csum(skb); -+ } ++ gtdt = container_of(table, struct acpi_table_gtdt, header); + -+ pdata->stats.rx_packets++; -+ pdata->stats.rx_bytes += datalen; -+ napi_gro_receive(&rx_ring->napi, skb); -+out: -+ if (--rx_ring->nbufpool == 0) { -+ ret = xgene_enet_refill_bufpool(buf_pool, NUM_BUFPOOL); -+ rx_ring->nbufpool = NUM_BUFPOOL; -+ } ++ arch_timers_present |= ARCH_CP15_TIMER; + -+ return ret; -+} ++ arch_timer_ppi[PHYS_SECURE_PPI] = ++ map_generic_timer_interrupt(gtdt->secure_el1_interrupt, ++ gtdt->secure_el1_flags); + -+static bool is_rx_desc(struct xgene_enet_raw_desc *raw_desc) -+{ -+ /* Hardware stores descriptor in little endian format */ -+ raw_desc->m0 = le64_to_cpu(raw_desc->m0); -+ raw_desc->m1 = le64_to_cpu(raw_desc->m1); -+ return ((raw_desc->m0 & FPQNUM_MASK) >> FPQNUM_POS) ? true : false; -+} ++ arch_timer_ppi[PHYS_NONSECURE_PPI] = ++ map_generic_timer_interrupt(gtdt->non_secure_el1_interrupt, ++ gtdt->non_secure_el1_flags); + -+static int xgene_enet_process_ring(struct xgene_enet_desc_ring *ring, -+ int budget) -+{ -+ struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev); -+ struct xgene_enet_raw_desc *raw_desc; -+ u16 head = ring->head; -+ u16 slots = ring->slots - 1; -+ int ret, count = 0; ++ arch_timer_ppi[VIRT_PPI] = ++ map_generic_timer_interrupt(gtdt->virtual_timer_interrupt, ++ gtdt->virtual_timer_flags); + -+ do { -+ raw_desc = &ring->raw_desc[head]; -+ if (unlikely(((u64 *)raw_desc)[EMPTY_SLOT_INDEX] == EMPTY_SLOT)) -+ break; ++ arch_timer_ppi[HYP_PPI] = ++ map_generic_timer_interrupt(gtdt->non_secure_el2_interrupt, ++ gtdt->non_secure_el2_flags); + -+ if (is_rx_desc(raw_desc)) -+ ret = xgene_enet_rx_frame(ring, raw_desc); -+ else -+ ret = xgene_enet_tx_completion(ring, raw_desc); -+ ((u64 *)raw_desc)[EMPTY_SLOT_INDEX] = EMPTY_SLOT; ++ /* Get the frequency from CNTFRQ */ ++ arch_timer_detect_rate(NULL, NULL); + -+ head = (head + 1) & slots; -+ count++; ++ /* Always-on capability */ ++ arch_timer_c3stop = !(gtdt->non_secure_el1_flags & ACPI_GTDT_ALWAYS_ON); + -+ if (ret) -+ break; -+ } while (--budget); -+ -+ if (likely(count)) { -+ iowrite32(-count, ring->cmd); -+ ring->head = head; -+ -+ if (netif_queue_stopped(ring->ndev)) { -+ if (xgene_enet_ring_len(ring) < pdata->cp_qcnt_low) -+ netif_wake_queue(ring->ndev); -+ } -+ } -+ -+ return budget; ++ arch_timer_init(); ++ return 0; +} + -+static int xgene_enet_napi(struct napi_struct *napi, const int budget) ++/* Initialize all the generic timers presented in GTDT */ ++void __init acpi_generic_timer_init(void) +{ -+ struct xgene_enet_desc_ring *ring; -+ int processed; -+ -+ ring = container_of(napi, struct xgene_enet_desc_ring, napi); -+ processed = xgene_enet_process_ring(ring, budget); -+ -+ if (processed != budget) { -+ napi_complete(napi); -+ enable_irq(ring->irq); -+ } ++ if (acpi_disabled) ++ return; + -+ return processed; ++ acpi_table_parse(ACPI_SIG_GTDT, arch_timer_acpi_init); +} -+ -+static void xgene_enet_timeout(struct net_device *ndev) ++#endif +diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c +index a0698b4..d2da911 100644 +--- a/drivers/irqchip/irq-gic-v3.c ++++ b/drivers/irqchip/irq-gic-v3.c +@@ -490,9 +490,19 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) + isb(); + } + ++#ifdef CONFIG_ARM_PARKING_PROTOCOL ++static void gic_wakeup_parked_cpu(int cpu) +{ -+ struct xgene_enet_pdata *pdata = netdev_priv(ndev); -+ -+ xgene_gmac_reset(pdata); ++ gic_raise_softirq(cpumask_of(cpu), 0); +} ++#endif + -+static int xgene_enet_register_irq(struct net_device *ndev) -+{ -+ struct xgene_enet_pdata *pdata = netdev_priv(ndev); -+ struct device *dev = ndev_to_dev(ndev); -+ int ret; -+ -+ ret = devm_request_irq(dev, pdata->rx_ring->irq, xgene_enet_rx_irq, -+ IRQF_SHARED, ndev->name, pdata->rx_ring); -+ if (ret) { -+ netdev_err(ndev, "rx%d interrupt request failed\n", -+ pdata->rx_ring->irq); -+ } -+ -+ return ret; -+} + static void gic_smp_init(void) + { + set_smp_cross_call(gic_raise_softirq); ++#ifdef CONFIG_ARM_PARKING_PROTOCOL ++ set_smp_boot_wakeup_call(gic_wakeup_parked_cpu); ++#endif + register_cpu_notifier(&gic_cpu_notifier); + } + +diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c +index dda6dbc..5d9bdd3 100644 +--- a/drivers/irqchip/irq-gic.c ++++ b/drivers/irqchip/irq-gic.c +@@ -33,12 +33,14 @@ + #include <linux/of.h> + #include <linux/of_address.h> + #include <linux/of_irq.h> ++#include <linux/acpi.h> + #include <linux/irqdomain.h> + #include <linux/interrupt.h> + #include <linux/percpu.h> + #include <linux/slab.h> + #include <linux/irqchip/chained_irq.h> + #include <linux/irqchip/arm-gic.h> ++#include <linux/irqchip/arm-gic-acpi.h> + + #include <asm/cputype.h> + #include <asm/irq.h> +@@ -622,6 +624,13 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) + + raw_spin_unlock_irqrestore(&irq_controller_lock, flags); + } + -+static void xgene_enet_free_irq(struct net_device *ndev) ++#ifdef CONFIG_ARM_PARKING_PROTOCOL ++static void gic_wakeup_parked_cpu(int cpu) +{ -+ struct xgene_enet_pdata *pdata; -+ struct device *dev; -+ -+ pdata = netdev_priv(ndev); -+ dev = ndev_to_dev(ndev); -+ devm_free_irq(dev, pdata->rx_ring->irq, pdata->rx_ring); ++ gic_raise_softirq(cpumask_of(cpu), GIC_DIST_SOFTINT_NSATT); +} ++#endif + #endif + + #ifdef CONFIG_BL_SWITCHER +@@ -977,6 +986,9 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start, + #ifdef CONFIG_SMP + set_smp_cross_call(gic_raise_softirq); + register_cpu_notifier(&gic_cpu_notifier); ++#ifdef CONFIG_ARM_PARKING_PROTOCOL ++ set_smp_boot_wakeup_call(gic_wakeup_parked_cpu); ++#endif + #endif + set_handle_irq(gic_handle_irq); + } +@@ -1029,3 +1041,107 @@ IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); + IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); + + #endif + -+static int xgene_enet_open(struct net_device *ndev) -+{ -+ struct xgene_enet_pdata *pdata = netdev_priv(ndev); -+ int ret; -+ -+ xgene_gmac_tx_enable(pdata); -+ xgene_gmac_rx_enable(pdata); -+ -+ ret = xgene_enet_register_irq(ndev); -+ if (ret) -+ return ret; -+ napi_enable(&pdata->rx_ring->napi); -+ -+ if (pdata->phy_dev) -+ phy_start(pdata->phy_dev); -+ -+ netif_start_queue(ndev); -+ -+ return ret; -+} ++#ifdef CONFIG_ACPI ++static phys_addr_t dist_phy_base, cpu_phy_base; ++static int cpu_base_assigned; + -+static int xgene_enet_close(struct net_device *ndev) ++static int __init ++gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, ++ const unsigned long end) +{ -+ struct xgene_enet_pdata *pdata = netdev_priv(ndev); -+ -+ netif_stop_queue(ndev); ++ struct acpi_madt_generic_interrupt *processor; ++ phys_addr_t gic_cpu_base; + -+ if (pdata->phy_dev) -+ phy_stop(pdata->phy_dev); ++ processor = (struct acpi_madt_generic_interrupt *)header; + -+ napi_disable(&pdata->rx_ring->napi); -+ xgene_enet_free_irq(ndev); -+ xgene_enet_process_ring(pdata->rx_ring, -1); ++ if (BAD_MADT_ENTRY(processor, end)) ++ return -EINVAL; + -+ xgene_gmac_tx_disable(pdata); -+ xgene_gmac_rx_disable(pdata); ++ /* ++ * There is no support for non-banked GICv1/2 register in ACPI spec. ++ * All CPU interface addresses have to be the same. ++ */ ++ gic_cpu_base = processor->base_address; ++ if (cpu_base_assigned && gic_cpu_base != cpu_phy_base) ++ return -EFAULT; + ++ cpu_phy_base = gic_cpu_base; ++ cpu_base_assigned = 1; + return 0; +} + -+static void xgene_enet_delete_ring(struct xgene_enet_desc_ring *ring) -+{ -+ struct xgene_enet_pdata *pdata; -+ struct device *dev; -+ -+ pdata = netdev_priv(ring->ndev); -+ dev = ndev_to_dev(ring->ndev); -+ -+ xgene_enet_clear_ring(ring); -+ dma_free_coherent(dev, ring->size, ring->desc_addr, ring->dma); -+} -+ -+static void xgene_enet_delete_desc_rings(struct xgene_enet_pdata *pdata) -+{ -+ struct xgene_enet_desc_ring *buf_pool; -+ -+ if (pdata->tx_ring) { -+ xgene_enet_delete_ring(pdata->tx_ring); -+ pdata->tx_ring = NULL; -+ } -+ -+ if (pdata->rx_ring) { -+ buf_pool = pdata->rx_ring->buf_pool; -+ xgene_enet_delete_bufpool(buf_pool); -+ xgene_enet_delete_ring(buf_pool); -+ xgene_enet_delete_ring(pdata->rx_ring); -+ pdata->rx_ring = NULL; -+ } -+} -+ -+static int xgene_enet_get_ring_size(struct device *dev, -+ enum xgene_enet_ring_cfgsize cfgsize) ++static int __init ++gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header, ++ const unsigned long end) +{ -+ int size = -EINVAL; ++ struct acpi_madt_generic_distributor *dist; + -+ switch (cfgsize) { -+ case RING_CFGSIZE_512B: -+ size = 0x200; -+ break; -+ case RING_CFGSIZE_2KB: -+ size = 0x800; -+ break; -+ case RING_CFGSIZE_16KB: -+ size = 0x4000; -+ break; -+ case RING_CFGSIZE_64KB: -+ size = 0x10000; -+ break; -+ case RING_CFGSIZE_512KB: -+ size = 0x80000; -+ break; -+ default: -+ dev_err(dev, "Unsupported cfg ring size %d\n", cfgsize); -+ break; -+ } -+ -+ return size; -+} ++ dist = (struct acpi_madt_generic_distributor *)header; + -+static void xgene_enet_free_desc_ring(struct xgene_enet_desc_ring *ring) -+{ -+ struct device *dev; -+ -+ if (!ring) -+ return; -+ -+ dev = ndev_to_dev(ring->ndev); -+ -+ if (ring->desc_addr) { -+ xgene_enet_clear_ring(ring); -+ dma_free_coherent(dev, ring->size, ring->desc_addr, ring->dma); -+ } -+ devm_kfree(dev, ring); -+} -+ -+static void xgene_enet_free_desc_rings(struct xgene_enet_pdata *pdata) -+{ -+ struct device *dev = &pdata->pdev->dev; -+ struct xgene_enet_desc_ring *ring; -+ -+ ring = pdata->tx_ring; -+ if (ring && ring->cp_ring && ring->cp_ring->cp_skb) -+ devm_kfree(dev, ring->cp_ring->cp_skb); -+ xgene_enet_free_desc_ring(ring); -+ -+ ring = pdata->rx_ring; -+ if (ring && ring->buf_pool && ring->buf_pool->rx_skb) -+ devm_kfree(dev, ring->buf_pool->rx_skb); -+ xgene_enet_free_desc_ring(ring->buf_pool); -+ xgene_enet_free_desc_ring(ring); -+} -+ -+static struct xgene_enet_desc_ring *xgene_enet_create_desc_ring( -+ struct net_device *ndev, u32 ring_num, -+ enum xgene_enet_ring_cfgsize cfgsize, u32 ring_id) -+{ -+ struct xgene_enet_desc_ring *ring; -+ struct xgene_enet_pdata *pdata = netdev_priv(ndev); -+ struct device *dev = ndev_to_dev(ndev); -+ u32 size; -+ -+ ring = devm_kzalloc(dev, sizeof(struct xgene_enet_desc_ring), -+ GFP_KERNEL); -+ if (!ring) -+ return NULL; -+ -+ ring->ndev = ndev; -+ ring->num = ring_num; -+ ring->cfgsize = cfgsize; -+ ring->id = ring_id; -+ -+ size = xgene_enet_get_ring_size(dev, cfgsize); -+ ring->desc_addr = dma_zalloc_coherent(dev, size, &ring->dma, -+ GFP_KERNEL); -+ if (!ring->desc_addr) { -+ devm_kfree(dev, ring); -+ return NULL; -+ } -+ ring->size = size; -+ -+ ring->cmd_base = pdata->ring_cmd_addr + (ring->num << 6); -+ ring->cmd = ring->cmd_base + INC_DEC_CMD_ADDR; -+ pdata->rm = RM3; -+ ring = xgene_enet_setup_ring(ring); -+ netdev_dbg(ndev, "ring info: num=%d size=%d id=%d slots=%d\n", -+ ring->num, ring->size, ring->id, ring->slots); -+ -+ return ring; -+} ++ if (BAD_MADT_ENTRY(dist, end)) ++ return -EINVAL; + -+static u16 xgene_enet_get_ring_id(enum xgene_ring_owner owner, u8 bufnum) -+{ -+ return (owner << 6) | (bufnum & GENMASK(5, 0)); ++ dist_phy_base = dist->base_address; ++ return 0; +} + -+static int xgene_enet_create_desc_rings(struct net_device *ndev) ++int __init ++gic_v2_acpi_init(struct acpi_table_header *table) +{ -+ struct xgene_enet_pdata *pdata = netdev_priv(ndev); -+ struct device *dev = ndev_to_dev(ndev); -+ struct xgene_enet_desc_ring *rx_ring, *tx_ring, *cp_ring; -+ struct xgene_enet_desc_ring *buf_pool = NULL; -+ u8 cpu_bufnum = 0, eth_bufnum = 0; -+ u8 bp_bufnum = 0x20; -+ u16 ring_id, ring_num = 0; -+ int ret; ++ void __iomem *cpu_base, *dist_base; ++ int count; + -+ /* allocate rx descriptor ring */ -+ ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU, cpu_bufnum++); -+ rx_ring = xgene_enet_create_desc_ring(ndev, ring_num++, -+ RING_CFGSIZE_16KB, ring_id); -+ if (!rx_ring) { -+ ret = -ENOMEM; -+ goto err; -+ } -+ -+ /* allocate buffer pool for receiving packets */ -+ ring_id = xgene_enet_get_ring_id(RING_OWNER_ETH0, bp_bufnum++); -+ buf_pool = xgene_enet_create_desc_ring(ndev, ring_num++, -+ RING_CFGSIZE_2KB, ring_id); -+ if (!buf_pool) { -+ ret = -ENOMEM; -+ goto err; ++ /* Collect CPU base addresses */ ++ count = acpi_parse_entries(sizeof(struct acpi_table_madt), ++ gic_acpi_parse_madt_cpu, table, ++ ACPI_MADT_TYPE_GENERIC_INTERRUPT, 0); ++ if (count < 0) { ++ pr_err("Error during GICC entries parsing\n"); ++ return -EFAULT; ++ } else if (!count) { ++ pr_err("No valid GICC entries exist\n"); ++ return -EINVAL; + } + -+ rx_ring->nbufpool = NUM_BUFPOOL; -+ rx_ring->buf_pool = buf_pool; -+ rx_ring->irq = pdata->rx_irq; -+ buf_pool->rx_skb = devm_kcalloc(dev, buf_pool->slots, -+ sizeof(struct sk_buff *), GFP_KERNEL); -+ if (!buf_pool->rx_skb) { -+ ret = -ENOMEM; -+ goto err; ++ /* ++ * Find distributor base address. We expect one distributor entry since ++ * ACPI 5.1 spec neither support multi-GIC instances nor GIC cascade. ++ */ ++ count = acpi_parse_entries(sizeof(struct acpi_table_madt), ++ gic_acpi_parse_madt_distributor, table, ++ ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 0); ++ if (count <= 0) { ++ pr_err("Error during GICD entries parsing\n"); ++ return -EFAULT; ++ } else if (!count) { ++ pr_err("No valid GICD entries exist\n"); ++ return -EINVAL; ++ } else if (count > 1) { ++ pr_err("More than one GICD entry detected\n"); ++ return -EINVAL; + } + -+ buf_pool->dst_ring_num = xgene_enet_dst_ring_num(buf_pool); -+ rx_ring->buf_pool = buf_pool; -+ pdata->rx_ring = rx_ring; -+ -+ /* allocate tx descriptor ring */ -+ ring_id = xgene_enet_get_ring_id(RING_OWNER_ETH0, eth_bufnum++); -+ tx_ring = xgene_enet_create_desc_ring(ndev, ring_num++, -+ RING_CFGSIZE_16KB, ring_id); -+ if (!tx_ring) { -+ ret = -ENOMEM; -+ goto err; ++ cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE); ++ if (!cpu_base) { ++ pr_err("Unable to map GICC registers\n"); ++ return -ENOMEM; + } -+ pdata->tx_ring = tx_ring; + -+ cp_ring = pdata->rx_ring; -+ cp_ring->cp_skb = devm_kcalloc(dev, tx_ring->slots, -+ sizeof(struct sk_buff *), GFP_KERNEL); -+ if (!cp_ring->cp_skb) { -+ ret = -ENOMEM; -+ goto err; ++ dist_base = ioremap(dist_phy_base, ACPI_GICV2_DIST_MEM_SIZE); ++ if (!dist_base) { ++ pr_err("Unable to map GICD registers\n"); ++ iounmap(cpu_base); ++ return -ENOMEM; + } -+ pdata->tx_ring->cp_ring = cp_ring; -+ pdata->tx_ring->dst_ring_num = xgene_enet_dst_ring_num(cp_ring); -+ -+ pdata->tx_qcnt_hi = pdata->tx_ring->slots / 2; -+ pdata->cp_qcnt_hi = pdata->rx_ring->slots / 2; -+ pdata->cp_qcnt_low = pdata->cp_qcnt_hi / 2; + ++ /* ++ * Initialize zero GIC instance (no multi-GIC support). Also, set GIC ++ * as default IRQ domain to allow for GSI registration and GSI to IRQ ++ * number translation (see acpi_register_gsi() and acpi_gsi_to_irq()). ++ */ ++ gic_init_bases(0, -1, dist_base, cpu_base, 0, NULL); ++ irq_set_default_host(gic_data[0].domain); + return 0; -+ -+err: -+ xgene_enet_free_desc_rings(pdata); -+ return ret; -+} -+ -+static struct rtnl_link_stats64 *xgene_enet_get_stats64( -+ struct net_device *ndev, -+ struct rtnl_link_stats64 *storage) -+{ -+ struct xgene_enet_pdata *pdata = netdev_priv(ndev); -+ struct rtnl_link_stats64 *stats = &pdata->stats; -+ -+ spin_lock(&pdata->stats_lock); -+ stats->rx_errors += stats->rx_length_errors + -+ stats->rx_crc_errors + -+ stats->rx_frame_errors + -+ stats->rx_fifo_errors; -+ memcpy(storage, &pdata->stats, sizeof(struct rtnl_link_stats64)); -+ spin_unlock(&pdata->stats_lock); -+ -+ return storage; +} ++#endif +diff --git a/drivers/irqchip/irqchip.c b/drivers/irqchip/irqchip.c +index 0fe2f71..9106c6d 100644 +--- a/drivers/irqchip/irqchip.c ++++ b/drivers/irqchip/irqchip.c +@@ -11,6 +11,7 @@ + #include <linux/init.h> + #include <linux/of_irq.h> + #include <linux/irqchip.h> ++#include <linux/irqchip/arm-gic-acpi.h> + + /* + * This special of_device_id is the sentinel at the end of the +@@ -26,4 +27,6 @@ extern struct of_device_id __irqchip_of_table[]; + void __init irqchip_init(void) + { + of_irq_init(__irqchip_of_table); + -+static int xgene_enet_set_mac_address(struct net_device *ndev, void *addr) -+{ -+ struct xgene_enet_pdata *pdata = netdev_priv(ndev); -+ int ret; -+ -+ ret = eth_mac_addr(ndev, addr); -+ if (ret) -+ return ret; -+ xgene_gmac_set_mac_addr(pdata); -+ -+ return ret; -+} -+ -+static const struct net_device_ops xgene_ndev_ops = { -+ .ndo_open = xgene_enet_open, -+ .ndo_stop = xgene_enet_close, -+ .ndo_start_xmit = xgene_enet_start_xmit, -+ .ndo_tx_timeout = xgene_enet_timeout, -+ .ndo_get_stats64 = xgene_enet_get_stats64, -+ .ndo_change_mtu = eth_change_mtu, -+ .ndo_set_mac_address = xgene_enet_set_mac_address, -+}; -+ -+static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata) -+{ -+ struct platform_device *pdev; -+ struct net_device *ndev; -+ struct device *dev; -+ struct resource *res; -+ void *base_addr; -+ const char *mac; -+ int ret; -+ -+ pdev = pdata->pdev; -+ dev = &pdev->dev; -+ ndev = pdata->ndev; -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "enet_csr"); -+ if (!res) { -+ dev_err(dev, "Resource enet_csr not defined\n"); -+ return -ENODEV; -+ } -+ pdata->base_addr = devm_ioremap_resource(dev, res); -+ if (IS_ERR(pdata->base_addr)) { -+ dev_err(dev, "Unable to retrieve ENET Port CSR region\n"); -+ return PTR_ERR(pdata->base_addr); ++ acpi_gic_init(); + } +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c +index ea27383..d0d3ab5 100644 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c +@@ -696,6 +696,18 @@ static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad, + else + mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); + ++ if (XGBE_SEATTLE_A0) { ++ /* The PCS implementation has reversed the devices in ++ * package registers so we need to change 05 to 06 and ++ * 06 to 05 if being read (these registers are readonly ++ * so no need to do this in the write function) ++ */ ++ if ((mmd_address & 0xffff) == 0x05) ++ mmd_address = (mmd_address & ~0xffff) | 0x06; ++ else if ((mmd_address & 0xffff) == 0x06) ++ mmd_address = (mmd_address & ~0xffff) | 0x05; + } + -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ring_csr"); -+ if (!res) { -+ dev_err(dev, "Resource ring_csr not defined\n"); -+ return -ENODEV; -+ } -+ pdata->ring_csr_addr = devm_ioremap_resource(dev, res); -+ if (IS_ERR(pdata->ring_csr_addr)) { -+ dev_err(dev, "Unable to retrieve ENET Ring CSR region\n"); -+ return PTR_ERR(pdata->ring_csr_addr); -+ } + /* The PCS registers are accessed using mmio. The underlying APB3 + * management interface uses indirect addressing to access the MMD + * register sets. This requires accessing of the PCS register in two +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c +index b26d758..ca7895c 100644 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c +@@ -426,6 +426,9 @@ void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata) + hw_feat->rx_ch_cnt++; + hw_feat->tx_ch_cnt++; + ++ /* A0 does not support NUMTC, hardcode it for now */ ++ hw_feat->tc_cnt = XGBE_TC_CNT; ++ + DBGPR("<--xgbe_get_all_hw_features\n"); + } + +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-main.c b/drivers/net/ethernet/amd/xgbe/xgbe-main.c +index bdf9cfa..ba53e41 100644 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-main.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-main.c +@@ -533,6 +533,7 @@ static int xgbe_resume(struct device *dev) + #endif /* CONFIG_PM */ + + static const struct of_device_id xgbe_of_match[] = { ++ { .compatible = "amd,xgbe-seattle-v0a", }, + { .compatible = "amd,xgbe-seattle-v1a", }, + {}, + }; +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h +index e9fe6e6..389bfec 100644 +--- a/drivers/net/ethernet/amd/xgbe/xgbe.h ++++ b/drivers/net/ethernet/amd/xgbe/xgbe.h +@@ -187,8 +187,11 @@ + #define XGBE_FIFO_SIZE_B(x) (x) + #define XGBE_FIFO_SIZE_KB(x) (x * 1024) + ++#define XGBE_TC_CNT 2 + #define XGBE_TC_MIN_QUANTUM 10 + ++#define XGBE_SEATTLE_A0 ((read_cpuid_id() & 0x00f0000f) == 0) ++ + /* Helper macro for descriptor handling + * Always use XGBE_GET_DESC_DATA to access the descriptor data + * since the index is free-running and needs to be and-ed +diff --git a/drivers/net/ethernet/smsc/smc91x.c b/drivers/net/ethernet/smsc/smc91x.c +index bcaa41a..ebad872 100644 +--- a/drivers/net/ethernet/smsc/smc91x.c ++++ b/drivers/net/ethernet/smsc/smc91x.c +@@ -81,6 +81,7 @@ static const char version[] = + #include <linux/workqueue.h> + #include <linux/of.h> + #include <linux/of_device.h> ++#include <linux/acpi.h> + + #include <linux/netdevice.h> + #include <linux/etherdevice.h> +@@ -2408,6 +2409,14 @@ static struct dev_pm_ops smc_drv_pm_ops = { + .resume = smc_drv_resume, + }; + ++#ifdef CONFIG_ACPI ++static const struct acpi_device_id smc91x_acpi_match[] = { ++ { "LNRO0003", }, ++ { } ++}; ++MODULE_DEVICE_TABLE(acpi, smc91x_acpi_match); ++#endif + -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ring_cmd"); -+ if (!res) { -+ dev_err(dev, "Resource ring_cmd not defined\n"); -+ return -ENODEV; -+ } -+ pdata->ring_cmd_addr = devm_ioremap_resource(dev, res); -+ if (IS_ERR(pdata->ring_cmd_addr)) { -+ dev_err(dev, "Unable to retrieve ENET Ring command region\n"); -+ return PTR_ERR(pdata->ring_cmd_addr); -+ } + static struct platform_driver smc_driver = { + .probe = smc_drv_probe, + .remove = smc_drv_remove, +@@ -2416,6 +2425,7 @@ static struct platform_driver smc_driver = { + .owner = THIS_MODULE, + .pm = &smc_drv_pm_ops, + .of_match_table = of_match_ptr(smc91x_match), ++ .acpi_match_table = ACPI_PTR(smc91x_acpi_match), + }, + }; + +diff --git a/drivers/net/phy/amd-xgbe-phy.c b/drivers/net/phy/amd-xgbe-phy.c +index f3230ee..90145d9 100644 +--- a/drivers/net/phy/amd-xgbe-phy.c ++++ b/drivers/net/phy/amd-xgbe-phy.c +@@ -78,12 +78,14 @@ + + MODULE_AUTHOR("Tom Lendacky <thomas.lendacky@amd.com>"); + MODULE_LICENSE("Dual BSD/GPL"); +-MODULE_VERSION("1.0.0-a"); ++MODULE_VERSION("0.0.0-a"); + MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver"); + +-#define XGBE_PHY_ID 0x000162d0 ++#define XGBE_PHY_ID 0x7996ced0 + #define XGBE_PHY_MASK 0xfffffff0 + ++#define XGBE_PHY_SERDES_RETRY 32 ++#define XGBE_PHY_CHANNEL_PROPERTY "amd,serdes-channel" + #define XGBE_PHY_SPEEDSET_PROPERTY "amd,speed-set" + + #define XGBE_AN_INT_CMPLT 0x01 +@@ -118,77 +120,6 @@ MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver"); + #define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100) + #endif + +-/* SerDes integration register offsets */ +-#define SIR0_KR_RT_1 0x002c +-#define SIR0_STATUS 0x0040 +-#define SIR1_SPEED 0x0000 +- +-/* SerDes integration register entry bit positions and sizes */ +-#define SIR0_KR_RT_1_RESET_INDEX 11 +-#define SIR0_KR_RT_1_RESET_WIDTH 1 +-#define SIR0_STATUS_RX_READY_INDEX 0 +-#define SIR0_STATUS_RX_READY_WIDTH 1 +-#define SIR0_STATUS_TX_READY_INDEX 8 +-#define SIR0_STATUS_TX_READY_WIDTH 1 +-#define SIR1_SPEED_DATARATE_INDEX 4 +-#define SIR1_SPEED_DATARATE_WIDTH 2 +-#define SIR1_SPEED_PI_SPD_SEL_INDEX 12 +-#define SIR1_SPEED_PI_SPD_SEL_WIDTH 4 +-#define SIR1_SPEED_PLLSEL_INDEX 3 +-#define SIR1_SPEED_PLLSEL_WIDTH 1 +-#define SIR1_SPEED_RATECHANGE_INDEX 6 +-#define SIR1_SPEED_RATECHANGE_WIDTH 1 +-#define SIR1_SPEED_TXAMP_INDEX 8 +-#define SIR1_SPEED_TXAMP_WIDTH 4 +-#define SIR1_SPEED_WORDMODE_INDEX 0 +-#define SIR1_SPEED_WORDMODE_WIDTH 3 +- +-#define SPEED_10000_CDR 0x7 +-#define SPEED_10000_PLL 0x1 +-#define SPEED_10000_RATE 0x0 +-#define SPEED_10000_TXAMP 0xa +-#define SPEED_10000_WORD 0x7 +- +-#define SPEED_2500_CDR 0x2 +-#define SPEED_2500_PLL 0x0 +-#define SPEED_2500_RATE 0x1 +-#define SPEED_2500_TXAMP 0xf +-#define SPEED_2500_WORD 0x1 +- +-#define SPEED_1000_CDR 0x2 +-#define SPEED_1000_PLL 0x0 +-#define SPEED_1000_RATE 0x3 +-#define SPEED_1000_TXAMP 0xf +-#define SPEED_1000_WORD 0x1 +- +- +-/* SerDes RxTx register offsets */ +-#define RXTX_REG20 0x0050 +-#define RXTX_REG114 0x01c8 +- +-/* SerDes RxTx register entry bit positions and sizes */ +-#define RXTX_REG20_BLWC_ENA_INDEX 2 +-#define RXTX_REG20_BLWC_ENA_WIDTH 1 +-#define RXTX_REG114_PQ_REG_INDEX 9 +-#define RXTX_REG114_PQ_REG_WIDTH 7 +- +-#define RXTX_10000_BLWC 0 +-#define RXTX_10000_PQ 0x1e +- +-#define RXTX_2500_BLWC 1 +-#define RXTX_2500_PQ 0xa +- +-#define RXTX_1000_BLWC 1 +-#define RXTX_1000_PQ 0xa +- +-/* Bit setting and getting macros +- * The get macro will extract the current bit field value from within +- * the variable +- * +- * The set macro will clear the current bit field value within the +- * variable and then set the bit field of the variable to the +- * specified value +- */ + #define GET_BITS(_var, _index, _width) \ + (((_var) >> (_index)) & ((0x1 << (_width)) - 1)) + +@@ -198,71 +129,12 @@ do { \ + (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \ + } while (0) + +-#define XSIR_GET_BITS(_var, _prefix, _field) \ +- GET_BITS((_var), \ +- _prefix##_##_field##_INDEX, \ +- _prefix##_##_field##_WIDTH) +- +-#define XSIR_SET_BITS(_var, _prefix, _field, _val) \ +- SET_BITS((_var), \ +- _prefix##_##_field##_INDEX, \ +- _prefix##_##_field##_WIDTH, (_val)) ++#define XCMU_IOREAD(_priv, _reg) \ ++ ioread16((_priv)->cmu_regs + _reg) + +-/* Macros for reading or writing SerDes integration registers +- * The ioread macros will get bit fields or full values using the +- * register definitions formed using the input names +- * +- * The iowrite macros will set bit fields or full values using the +- * register definitions formed using the input names +- */ +-#define XSIR0_IOREAD(_priv, _reg) \ +- ioread16((_priv)->sir0_regs + _reg) ++#define XCMU_IOWRITE(_priv, _reg, _val) \ ++ iowrite16((_val), (_priv)->cmu_regs + _reg) + +-#define XSIR0_IOREAD_BITS(_priv, _reg, _field) \ +- GET_BITS(XSIR0_IOREAD((_priv), _reg), \ +- _reg##_##_field##_INDEX, \ +- _reg##_##_field##_WIDTH) +- +-#define XSIR0_IOWRITE(_priv, _reg, _val) \ +- iowrite16((_val), (_priv)->sir0_regs + _reg) +- +-#define XSIR0_IOWRITE_BITS(_priv, _reg, _field, _val) \ +-do { \ +- u16 reg_val = XSIR0_IOREAD((_priv), _reg); \ +- SET_BITS(reg_val, \ +- _reg##_##_field##_INDEX, \ +- _reg##_##_field##_WIDTH, (_val)); \ +- XSIR0_IOWRITE((_priv), _reg, reg_val); \ +-} while (0) +- +-#define XSIR1_IOREAD(_priv, _reg) \ +- ioread16((_priv)->sir1_regs + _reg) +- +-#define XSIR1_IOREAD_BITS(_priv, _reg, _field) \ +- GET_BITS(XSIR1_IOREAD((_priv), _reg), \ +- _reg##_##_field##_INDEX, \ +- _reg##_##_field##_WIDTH) +- +-#define XSIR1_IOWRITE(_priv, _reg, _val) \ +- iowrite16((_val), (_priv)->sir1_regs + _reg) +- +-#define XSIR1_IOWRITE_BITS(_priv, _reg, _field, _val) \ +-do { \ +- u16 reg_val = XSIR1_IOREAD((_priv), _reg); \ +- SET_BITS(reg_val, \ +- _reg##_##_field##_INDEX, \ +- _reg##_##_field##_WIDTH, (_val)); \ +- XSIR1_IOWRITE((_priv), _reg, reg_val); \ +-} while (0) +- +- +-/* Macros for reading or writing SerDes RxTx registers +- * The ioread macros will get bit fields or full values using the +- * register definitions formed using the input names +- * +- * The iowrite macros will set bit fields or full values using the +- * register definitions formed using the input names +- */ + #define XRXTX_IOREAD(_priv, _reg) \ + ioread16((_priv)->rxtx_regs + _reg) + +@@ -283,6 +155,77 @@ do { \ + XRXTX_IOWRITE((_priv), _reg, reg_val); \ + } while (0) + ++/* SerDes CMU register offsets */ ++#define CMU_REG15 0x003c ++#define CMU_REG16 0x0040 ++ ++/* SerDes CMU register entry bit positions and sizes */ ++#define CMU_REG16_TX_RATE_CHANGE_BASE 15 ++#define CMU_REG16_RX_RATE_CHANGE_BASE 14 ++#define CMU_REG16_RATE_CHANGE_DECR 2 ++ ++ ++/* SerDes RxTx register offsets */ ++#define RXTX_REG2 0x0008 ++#define RXTX_REG3 0x000c ++#define RXTX_REG5 0x0014 ++#define RXTX_REG6 0x0018 ++#define RXTX_REG20 0x0050 ++#define RXTX_REG53 0x00d4 ++#define RXTX_REG114 0x01c8 ++#define RXTX_REG115 0x01cc ++#define RXTX_REG142 0x0238 ++ ++/* SerDes RxTx register entry bit positions and sizes */ ++#define RXTX_REG2_RESETB_INDEX 15 ++#define RXTX_REG2_RESETB_WIDTH 1 ++#define RXTX_REG3_TX_DATA_RATE_INDEX 14 ++#define RXTX_REG3_TX_DATA_RATE_WIDTH 2 ++#define RXTX_REG3_TX_WORD_MODE_INDEX 11 ++#define RXTX_REG3_TX_WORD_MODE_WIDTH 3 ++#define RXTX_REG5_TXAMP_CNTL_INDEX 7 ++#define RXTX_REG5_TXAMP_CNTL_WIDTH 4 ++#define RXTX_REG6_RX_DATA_RATE_INDEX 9 ++#define RXTX_REG6_RX_DATA_RATE_WIDTH 2 ++#define RXTX_REG6_RX_WORD_MODE_INDEX 11 ++#define RXTX_REG6_RX_WORD_MODE_WIDTH 3 ++#define RXTX_REG20_BLWC_ENA_INDEX 2 ++#define RXTX_REG20_BLWC_ENA_WIDTH 1 ++#define RXTX_REG53_RX_PLLSELECT_INDEX 15 ++#define RXTX_REG53_RX_PLLSELECT_WIDTH 1 ++#define RXTX_REG53_TX_PLLSELECT_INDEX 14 ++#define RXTX_REG53_TX_PLLSELECT_WIDTH 1 ++#define RXTX_REG53_PI_SPD_SEL_CDR_INDEX 10 ++#define RXTX_REG53_PI_SPD_SEL_CDR_WIDTH 4 ++#define RXTX_REG114_PQ_REG_INDEX 9 ++#define RXTX_REG114_PQ_REG_WIDTH 7 ++#define RXTX_REG115_FORCE_LAT_CAL_START_INDEX 2 ++#define RXTX_REG115_FORCE_LAT_CAL_START_WIDTH 1 ++#define RXTX_REG115_FORCE_SUM_CAL_START_INDEX 1 ++#define RXTX_REG115_FORCE_SUM_CAL_START_WIDTH 1 ++#define RXTX_REG142_SUM_CALIB_DONE_INDEX 15 ++#define RXTX_REG142_SUM_CALIB_DONE_WIDTH 1 ++#define RXTX_REG142_SUM_CALIB_ERR_INDEX 14 ++#define RXTX_REG142_SUM_CALIB_ERR_WIDTH 1 ++#define RXTX_REG142_LAT_CALIB_DONE_INDEX 11 ++#define RXTX_REG142_LAT_CALIB_DONE_WIDTH 1 ++ ++#define RXTX_FULL_RATE 0x0 ++#define RXTX_HALF_RATE 0x1 ++#define RXTX_FIFTH_RATE 0x3 ++#define RXTX_66BIT_WORD 0x7 ++#define RXTX_10BIT_WORD 0x1 ++#define RXTX_10G_TX_AMP 0xa ++#define RXTX_1G_TX_AMP 0xf ++#define RXTX_10G_CDR 0x7 ++#define RXTX_1G_CDR 0x2 ++#define RXTX_10G_PLL 0x1 ++#define RXTX_1G_PLL 0x0 ++#define RXTX_10G_PQ 0x1e ++#define RXTX_1G_PQ 0xa ++ ++ ++DEFINE_SPINLOCK(cmu_lock); + + enum amd_xgbe_phy_an { + AMD_XGBE_AN_READY = 0, +@@ -321,18 +264,18 @@ struct amd_xgbe_phy_priv { + + /* SerDes related mmio resources */ + struct resource *rxtx_res; +- struct resource *sir0_res; +- struct resource *sir1_res; ++ struct resource *cmu_res; + + /* SerDes related mmio registers */ + void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */ +- void __iomem *sir0_regs; /* SerDes integration registers (1/2) */ +- void __iomem *sir1_regs; /* SerDes integration registers (2/2) */ ++ void __iomem *cmu_regs; /* SerDes CMU CSRs */ ++ ++ unsigned int serdes_channel; ++ unsigned int speed_set; + + /* Maintain link status for re-starting auto-negotiation */ + unsigned int link; + enum amd_xgbe_phy_mode mode; +- unsigned int speed_set; + + /* Auto-negotiation state machine support */ + struct mutex an_mutex; +@@ -394,33 +337,51 @@ static int amd_xgbe_phy_pcs_power_cycle(struct phy_device *phydev) + static void amd_xgbe_phy_serdes_start_ratechange(struct phy_device *phydev) + { + struct amd_xgbe_phy_priv *priv = phydev->priv; ++ u16 val, mask; + -+ ret = platform_get_irq(pdev, 0); -+ if (ret <= 0) { -+ dev_err(dev, "Unable to get ENET Rx IRQ\n"); -+ ret = ret ? : -ENXIO; -+ return ret; -+ } -+ pdata->rx_irq = ret; ++ /* Assert Rx and Tx ratechange in CMU_reg16 */ ++ val = XCMU_IOREAD(priv, CMU_REG16); + +- /* Assert Rx and Tx ratechange */ +- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, RATECHANGE, 1); ++ mask = (1 << (CMU_REG16_TX_RATE_CHANGE_BASE - ++ (priv->serdes_channel * CMU_REG16_RATE_CHANGE_DECR))) | ++ (1 << (CMU_REG16_RX_RATE_CHANGE_BASE - ++ (priv->serdes_channel * CMU_REG16_RATE_CHANGE_DECR))); ++ val |= mask; + -+ mac = of_get_mac_address(dev->of_node); -+ if (mac) -+ memcpy(ndev->dev_addr, mac, ndev->addr_len); -+ else -+ eth_hw_addr_random(ndev); -+ memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len); ++ XCMU_IOWRITE(priv, CMU_REG16, val); + } + + static void amd_xgbe_phy_serdes_complete_ratechange(struct phy_device *phydev) + { + struct amd_xgbe_phy_priv *priv = phydev->priv; ++ u16 val, mask; + unsigned int wait; +- u16 status; + +- /* Release Rx and Tx ratechange */ +- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, RATECHANGE, 0); ++ /* Release Rx and Tx ratechange for proper channel in CMU_reg16 */ ++ val = XCMU_IOREAD(priv, CMU_REG16); ++ ++ mask = (1 << (CMU_REG16_TX_RATE_CHANGE_BASE - ++ (priv->serdes_channel * CMU_REG16_RATE_CHANGE_DECR))) | ++ (1 << (CMU_REG16_RX_RATE_CHANGE_BASE - ++ (priv->serdes_channel * CMU_REG16_RATE_CHANGE_DECR))); ++ val &= ~mask; + +- /* Wait for Rx and Tx ready */ ++ XCMU_IOWRITE(priv, CMU_REG16, val); ++ ++ /* Wait for Rx and Tx ready in CMU_reg15 */ ++ mask = (1 << priv->serdes_channel) | ++ (1 << (priv->serdes_channel + 8)); + wait = XGBE_PHY_RATECHANGE_COUNT; + while (wait--) { +- usleep_range(50, 75); ++ udelay(50); + +- status = XSIR0_IOREAD(priv, SIR0_STATUS); +- if (XSIR_GET_BITS(status, SIR0_STATUS, RX_READY) && +- XSIR_GET_BITS(status, SIR0_STATUS, TX_READY)) ++ val = XCMU_IOREAD(priv, CMU_REG15); ++ if ((val & mask) == mask) + return; + } + + netdev_dbg(phydev->attached_dev, "SerDes rx/tx not ready (%#hx)\n", +- status); ++ val); + } + + static int amd_xgbe_phy_xgmii_mode(struct phy_device *phydev) +@@ -428,8 +389,8 @@ static int amd_xgbe_phy_xgmii_mode(struct phy_device *phydev) + struct amd_xgbe_phy_priv *priv = phydev->priv; + int ret; + +- /* Enable KR training */ +- ret = amd_xgbe_an_enable_kr_training(phydev); ++ /* Disable KR training */ ++ ret = amd_xgbe_an_disable_kr_training(phydev); + if (ret < 0) + return ret; + +@@ -455,19 +416,30 @@ static int amd_xgbe_phy_xgmii_mode(struct phy_device *phydev) + return ret; + + /* Set SerDes to 10G speed */ ++ spin_lock(&cmu_lock); + -+ pdata->phy_mode = of_get_phy_mode(pdev->dev.of_node); -+ if (pdata->phy_mode < 0) { -+ dev_err(dev, "Incorrect phy-connection-type in DTS\n"); -+ return -EINVAL; -+ } + amd_xgbe_phy_serdes_start_ratechange(phydev); + +- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_10000_RATE); +- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_10000_WORD); +- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP, SPEED_10000_TXAMP); +- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_10000_PLL); +- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PI_SPD_SEL, SPEED_10000_CDR); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG3, TX_DATA_RATE, RXTX_FULL_RATE); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG3, TX_WORD_MODE, RXTX_66BIT_WORD); + -+ pdata->clk = devm_clk_get(&pdev->dev, NULL); -+ ret = IS_ERR(pdata->clk); -+ if (IS_ERR(pdata->clk)) { -+ dev_err(&pdev->dev, "can't get clock\n"); -+ ret = PTR_ERR(pdata->clk); -+ return ret; -+ } ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG5, TXAMP_CNTL, RXTX_10G_TX_AMP); + -+ base_addr = pdata->base_addr; -+ pdata->eth_csr_addr = base_addr + BLOCK_ETH_CSR_OFFSET; -+ pdata->eth_ring_if_addr = base_addr + BLOCK_ETH_RING_IF_OFFSET; -+ pdata->eth_diag_csr_addr = base_addr + BLOCK_ETH_DIAG_CSR_OFFSET; -+ pdata->mcx_mac_addr = base_addr + BLOCK_ETH_MAC_OFFSET; -+ pdata->mcx_stats_addr = base_addr + BLOCK_ETH_STATS_OFFSET; -+ pdata->mcx_mac_csr_addr = base_addr + BLOCK_ETH_MAC_CSR_OFFSET; -+ pdata->rx_buff_cnt = NUM_PKT_BUF; ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RX_DATA_RATE, RXTX_FULL_RATE); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RX_WORD_MODE, RXTX_66BIT_WORD); + +- XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, RXTX_10000_BLWC); +- XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_10000_PQ); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, 0); + -+ return ret; -+} ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, RX_PLLSELECT, RXTX_10G_PLL); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, TX_PLLSELECT, RXTX_10G_PLL); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, PI_SPD_SEL_CDR, RXTX_10G_CDR); + -+static int xgene_enet_init_hw(struct xgene_enet_pdata *pdata) -+{ -+ struct net_device *ndev = pdata->ndev; -+ struct xgene_enet_desc_ring *buf_pool; -+ u16 dst_ring_num; -+ int ret; ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_10G_PQ); + + amd_xgbe_phy_serdes_complete_ratechange(phydev); + ++ spin_unlock(&cmu_lock); + -+ xgene_gmac_tx_disable(pdata); -+ xgene_gmac_rx_disable(pdata); + priv->mode = AMD_XGBE_MODE_KR; + + return 0; +@@ -505,19 +477,30 @@ static int amd_xgbe_phy_gmii_2500_mode(struct phy_device *phydev) + return ret; + + /* Set SerDes to 2.5G speed */ ++ spin_lock(&cmu_lock); + -+ ret = xgene_enet_create_desc_rings(ndev); -+ if (ret) { -+ netdev_err(ndev, "Error in ring configuration\n"); -+ return ret; -+ } + amd_xgbe_phy_serdes_start_ratechange(phydev); + +- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_2500_RATE); +- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_2500_WORD); +- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP, SPEED_2500_TXAMP); +- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_2500_PLL); +- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PI_SPD_SEL, SPEED_2500_CDR); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG3, TX_DATA_RATE, RXTX_HALF_RATE); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG3, TX_WORD_MODE, RXTX_10BIT_WORD); + -+ /* setup buffer pool */ -+ buf_pool = pdata->rx_ring->buf_pool; -+ xgene_enet_init_bufpool(buf_pool); -+ ret = xgene_enet_refill_bufpool(buf_pool, pdata->rx_buff_cnt); -+ if (ret) -+ return ret; ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG5, TXAMP_CNTL, RXTX_1G_TX_AMP); + +- XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, RXTX_2500_BLWC); +- XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_2500_PQ); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RX_DATA_RATE, RXTX_HALF_RATE); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RX_WORD_MODE, RXTX_10BIT_WORD); + -+ dst_ring_num = xgene_enet_dst_ring_num(pdata->rx_ring); -+ xgene_enet_cle_bypass(pdata, dst_ring_num, buf_pool->id); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, 1); + -+ return ret; -+} ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, RX_PLLSELECT, RXTX_1G_PLL); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, TX_PLLSELECT, RXTX_1G_PLL); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, PI_SPD_SEL_CDR, RXTX_1G_CDR); + -+static int xgene_enet_probe(struct platform_device *pdev) -+{ -+ struct net_device *ndev; -+ struct xgene_enet_pdata *pdata; -+ struct device *dev = &pdev->dev; -+ struct napi_struct *napi; -+ int ret; ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_1G_PQ); + + amd_xgbe_phy_serdes_complete_ratechange(phydev); + ++ spin_unlock(&cmu_lock); + -+ ndev = alloc_etherdev(sizeof(struct xgene_enet_pdata)); -+ if (!ndev) -+ return -ENOMEM; + priv->mode = AMD_XGBE_MODE_KX; + + return 0; +@@ -555,19 +538,30 @@ static int amd_xgbe_phy_gmii_mode(struct phy_device *phydev) + return ret; + + /* Set SerDes to 1G speed */ ++ spin_lock(&cmu_lock); + -+ pdata = netdev_priv(ndev); + amd_xgbe_phy_serdes_start_ratechange(phydev); + +- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_1000_RATE); +- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_1000_WORD); +- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP, SPEED_1000_TXAMP); +- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_1000_PLL); +- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PI_SPD_SEL, SPEED_1000_CDR); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG3, TX_DATA_RATE, RXTX_FIFTH_RATE); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG3, TX_WORD_MODE, RXTX_10BIT_WORD); + -+ pdata->pdev = pdev; -+ pdata->ndev = ndev; -+ SET_NETDEV_DEV(ndev, dev); -+ platform_set_drvdata(pdev, pdata); -+ ndev->netdev_ops = &xgene_ndev_ops; -+ xgene_enet_set_ethtool_ops(ndev); -+ ndev->features |= NETIF_F_IP_CSUM | -+ NETIF_F_GSO | -+ NETIF_F_GRO; ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG5, TXAMP_CNTL, RXTX_1G_TX_AMP); + +- XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, RXTX_1000_BLWC); +- XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_1000_PQ); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RX_DATA_RATE, RXTX_FIFTH_RATE); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RX_WORD_MODE, RXTX_10BIT_WORD); + -+ ret = xgene_enet_get_resources(pdata); -+ if (ret) -+ goto err; ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, 1); + -+ xgene_enet_reset(pdata); -+ xgene_gmac_init(pdata, SPEED_1000); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, RX_PLLSELECT, RXTX_1G_PLL); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, TX_PLLSELECT, RXTX_1G_PLL); ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, PI_SPD_SEL_CDR, RXTX_1G_CDR); + -+ spin_lock_init(&pdata->stats_lock); -+ ret = register_netdev(ndev); -+ if (ret) { -+ netdev_err(ndev, "Failed to register netdev\n"); -+ goto err; -+ } ++ XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_1G_PQ); + + amd_xgbe_phy_serdes_complete_ratechange(phydev); + ++ spin_unlock(&cmu_lock); + -+ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); -+ if (ret) { -+ netdev_err(ndev, "No usable DMA configuration\n"); -+ goto err; + priv->mode = AMD_XGBE_MODE_KX; + + return 0; +@@ -639,13 +633,9 @@ static enum amd_xgbe_phy_an amd_xgbe_an_tx_training(struct phy_device *phydev, + if (ret < 0) + return AMD_XGBE_AN_ERROR; + +- XSIR0_IOWRITE_BITS(priv, SIR0_KR_RT_1, RESET, 1); +- + ret |= 0x01; + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret); + +- XSIR0_IOWRITE_BITS(priv, SIR0_KR_RT_1, RESET, 0); +- + return AMD_XGBE_AN_EVENT; + } + +@@ -1291,21 +1281,33 @@ static int amd_xgbe_phy_probe(struct phy_device *phydev) + goto err_priv; + } + +- priv->sir0_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); +- priv->sir0_regs = devm_ioremap_resource(dev, priv->sir0_res); +- if (IS_ERR(priv->sir0_regs)) { +- dev_err(dev, "sir0 ioremap failed\n"); +- ret = PTR_ERR(priv->sir0_regs); ++ /* All xgbe phy devices share the CMU registers so retrieve ++ * the resource and do the ioremap directly rather than ++ * the devm_ioremap_resource call ++ */ ++ priv->cmu_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ if (!priv->cmu_res) { ++ dev_err(dev, "cmu invalid resource\n"); ++ ret = -EINVAL; ++ goto err_rxtx; + } -+ -+ ret = xgene_enet_init_hw(pdata); -+ if (ret) -+ goto err; -+ -+ napi = &pdata->rx_ring->napi; -+ netif_napi_add(ndev, napi, xgene_enet_napi, NAPI_POLL_WEIGHT); -+ ret = xgene_enet_mdio_config(pdata); -+ -+ return ret; -+err: -+ free_netdev(ndev); -+ return ret; -+} -+ -+static int xgene_enet_remove(struct platform_device *pdev) -+{ -+ struct xgene_enet_pdata *pdata; -+ struct net_device *ndev; -+ -+ pdata = platform_get_drvdata(pdev); -+ ndev = pdata->ndev; -+ -+ xgene_gmac_rx_disable(pdata); -+ xgene_gmac_tx_disable(pdata); -+ -+ netif_napi_del(&pdata->rx_ring->napi); -+ xgene_enet_mdio_remove(pdata); -+ xgene_enet_delete_desc_rings(pdata); -+ unregister_netdev(ndev); -+ xgene_gport_shutdown(pdata); -+ free_netdev(ndev); -+ -+ return 0; -+} -+ -+static struct of_device_id xgene_enet_match[] = { -+ {.compatible = "apm,xgene-enet",}, -+ {}, -+}; -+ -+MODULE_DEVICE_TABLE(of, xgene_enet_match); -+ -+static struct platform_driver xgene_enet_driver = { -+ .driver = { -+ .name = "xgene-enet", -+ .owner = THIS_MODULE, -+ .of_match_table = xgene_enet_match, -+ }, -+ .probe = xgene_enet_probe, -+ .remove = xgene_enet_remove, -+}; -+ -+module_platform_driver(xgene_enet_driver); -+ -+MODULE_DESCRIPTION("APM X-Gene SoC Ethernet driver"); -+MODULE_VERSION(XGENE_DRV_VERSION); -+MODULE_AUTHOR("Keyur Chudgar <kchudgar@apm.com>"); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_main.h b/drivers/net/ethernet/apm/xgene/xgene_enet_main.h -new file mode 100644 -index 0000000..f4f7e4a ---- /dev/null -+++ b/drivers/net/ethernet/apm/xgene/xgene_enet_main.h -@@ -0,0 +1,107 @@ -+/* Applied Micro X-Gene SoC Ethernet Driver -+ * -+ * Copyright (c) 2014, Applied Micro Circuits Corporation -+ * Authors: Iyappan Subramanian <isubramanian@apm.com> -+ * Ravi Patel <rapatel@apm.com> -+ * Keyur Chudgar <kchudgar@apm.com> -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+ -+#ifndef __XGENE_ENET_MAIN_H__ -+#define __XGENE_ENET_MAIN_H__ -+ -+#include <linux/clk.h> -+#include <linux/of_platform.h> -+#include <linux/of_net.h> -+#include <linux/of_mdio.h> -+#include <linux/module.h> -+#include <net/ip.h> -+#include <linux/prefetch.h> -+#include <linux/if_vlan.h> -+#include <linux/phy.h> -+#include "xgene_enet_hw.h" -+ -+#define XGENE_DRV_VERSION "v1.0" -+#define XGENE_ENET_MAX_MTU 1536 -+#define SKB_BUFFER_SIZE (XGENE_ENET_MAX_MTU - NET_IP_ALIGN) -+#define NUM_PKT_BUF 64 -+#define NUM_BUFPOOL 32 -+ -+/* software context of a descriptor ring */ -+struct xgene_enet_desc_ring { -+ struct net_device *ndev; -+ u16 id; -+ u16 num; -+ u16 head; -+ u16 tail; -+ u16 slots; -+ u16 irq; -+ u32 size; -+ u32 state[NUM_RING_CONFIG]; -+ void __iomem *cmd_base; -+ void __iomem *cmd; -+ dma_addr_t dma; -+ u16 dst_ring_num; -+ u8 nbufpool; -+ struct sk_buff *(*rx_skb); -+ struct sk_buff *(*cp_skb); -+ enum xgene_enet_ring_cfgsize cfgsize; -+ struct xgene_enet_desc_ring *cp_ring; -+ struct xgene_enet_desc_ring *buf_pool; -+ struct napi_struct napi; -+ union { -+ void *desc_addr; -+ struct xgene_enet_raw_desc *raw_desc; -+ struct xgene_enet_raw_desc16 *raw_desc16; -+ }; -+}; -+ -+/* ethernet private data */ -+struct xgene_enet_pdata { -+ struct net_device *ndev; -+ struct mii_bus *mdio_bus; -+ struct phy_device *phy_dev; -+ int phy_speed; -+ struct clk *clk; -+ struct platform_device *pdev; -+ struct xgene_enet_desc_ring *tx_ring; -+ struct xgene_enet_desc_ring *rx_ring; -+ char *dev_name; -+ u32 rx_buff_cnt; -+ u32 tx_qcnt_hi; -+ u32 cp_qcnt_hi; -+ u32 cp_qcnt_low; -+ u32 rx_irq; -+ void __iomem *eth_csr_addr; -+ void __iomem *eth_ring_if_addr; -+ void __iomem *eth_diag_csr_addr; -+ void __iomem *mcx_mac_addr; -+ void __iomem *mcx_stats_addr; -+ void __iomem *mcx_mac_csr_addr; -+ void __iomem *base_addr; -+ void __iomem *ring_csr_addr; -+ void __iomem *ring_cmd_addr; -+ u32 phy_addr; -+ int phy_mode; -+ u32 speed; -+ u16 rm; -+ struct rtnl_link_stats64 stats; -+ /* statistics lock */ -+ spinlock_t stats_lock; -+}; -+ -+void xgene_enet_set_ethtool_ops(struct net_device *netdev); -+ -+#endif /* __XGENE_ENET_MAIN_H__ */ ++ priv->cmu_regs = devm_ioremap_nocache(dev, priv->cmu_res->start, ++ resource_size(priv->cmu_res)); ++ if (!priv->cmu_regs) { ++ dev_err(dev, "cmu ioremap failed\n"); ++ ret = -ENOMEM; + goto err_rxtx; + } + +- priv->sir1_res = platform_get_resource(pdev, IORESOURCE_MEM, 2); +- priv->sir1_regs = devm_ioremap_resource(dev, priv->sir1_res); +- if (IS_ERR(priv->sir1_regs)) { +- dev_err(dev, "sir1 ioremap failed\n"); +- ret = PTR_ERR(priv->sir1_regs); +- goto err_sir0; ++ /* Get the device serdes channel property */ ++ property = of_get_property(dev->of_node, XGBE_PHY_CHANNEL_PROPERTY, ++ NULL); ++ if (!property) { ++ dev_err(dev, "unable to obtain serdes_channel property\n"); ++ ret = -EINVAL; ++ goto err_cmu; + } ++ priv->serdes_channel = be32_to_cpu(*property); + + /* Get the device speed set property */ + speed_set = 0; +@@ -1324,14 +1326,14 @@ static int amd_xgbe_phy_probe(struct phy_device *phydev) + default: + dev_err(dev, "invalid amd,speed-set property\n"); + ret = -EINVAL; +- goto err_sir1; ++ goto err_cmu; + } + + priv->link = 1; + + ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2); + if (ret < 0) +- goto err_sir1; ++ goto err_cmu; + if ((ret & MDIO_PCS_CTRL2_TYPE) == MDIO_PCS_CTRL2_10GBR) + priv->mode = AMD_XGBE_MODE_KR; + else +@@ -1342,7 +1344,7 @@ static int amd_xgbe_phy_probe(struct phy_device *phydev) + priv->an_workqueue = create_singlethread_workqueue(wq_name); + if (!priv->an_workqueue) { + ret = -ENOMEM; +- goto err_sir1; ++ goto err_cmu; + } + + phydev->priv = priv; +@@ -1352,15 +1354,8 @@ static int amd_xgbe_phy_probe(struct phy_device *phydev) + + return 0; + +-err_sir1: +- devm_iounmap(dev, priv->sir1_regs); +- devm_release_mem_region(dev, priv->sir1_res->start, +- resource_size(priv->sir1_res)); +- +-err_sir0: +- devm_iounmap(dev, priv->sir0_regs); +- devm_release_mem_region(dev, priv->sir0_res->start, +- resource_size(priv->sir0_res)); ++err_cmu: ++ devm_iounmap(dev, priv->cmu_regs); + + err_rxtx: + devm_iounmap(dev, priv->rxtx_regs); +@@ -1392,14 +1387,7 @@ static void amd_xgbe_phy_remove(struct phy_device *phydev) + flush_workqueue(priv->an_workqueue); + destroy_workqueue(priv->an_workqueue); + +- /* Release resources */ +- devm_iounmap(dev, priv->sir1_regs); +- devm_release_mem_region(dev, priv->sir1_res->start, +- resource_size(priv->sir1_res)); +- +- devm_iounmap(dev, priv->sir0_regs); +- devm_release_mem_region(dev, priv->sir0_res->start, +- resource_size(priv->sir0_res)); ++ devm_iounmap(dev, priv->cmu_regs); + + devm_iounmap(dev, priv->rxtx_regs); + devm_release_mem_region(dev, priv->rxtx_res->start, diff --git a/drivers/of/address.c b/drivers/of/address.c -index 5edfcb0..cbbaed2 100644 +index e371825..afdb782 100644 --- a/drivers/of/address.c +++ b/drivers/of/address.c -@@ -5,6 +5,7 @@ +@@ -5,6 +5,8 @@ #include <linux/module.h> #include <linux/of_address.h> #include <linux/pci_regs.h> ++#include <linux/sizes.h> +#include <linux/slab.h> #include <linux/string.h> /* Max address size we deal with */ -@@ -601,12 +602,72 @@ const __be32 *of_get_address(struct device_node *dev, int index, u64 *size, +@@ -293,6 +295,51 @@ struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser, + } + EXPORT_SYMBOL_GPL(of_pci_range_parser_one); + ++/* ++ * of_pci_range_to_resource - Create a resource from an of_pci_range ++ * @range: the PCI range that describes the resource ++ * @np: device node where the range belongs to ++ * @res: pointer to a valid resource that will be updated to ++ * reflect the values contained in the range. ++ * ++ * Returns EINVAL if the range cannot be converted to resource. ++ * ++ * Note that if the range is an IO range, the resource will be converted ++ * using pci_address_to_pio() which can fail if it is called too early or ++ * if the range cannot be matched to any host bridge IO space (our case here). ++ * To guard against that we try to register the IO range first. ++ * If that fails we know that pci_address_to_pio() will do too. ++ */ ++int of_pci_range_to_resource(struct of_pci_range *range, ++ struct device_node *np, struct resource *res) ++{ ++ int err; ++ res->flags = range->flags; ++ res->parent = res->child = res->sibling = NULL; ++ res->name = np->full_name; ++ ++ if (res->flags & IORESOURCE_IO) { ++ unsigned long port; ++ err = pci_register_io_range(range->cpu_addr, range->size); ++ if (err) ++ goto invalid_range; ++ port = pci_address_to_pio(range->cpu_addr); ++ if (port == (unsigned long)-1) { ++ err = -EINVAL; ++ goto invalid_range; ++ } ++ res->start = port; ++ } else { ++ res->start = range->cpu_addr; ++ } ++ res->end = res->start + range->size - 1; ++ return 0; ++ ++invalid_range: ++ res->start = (resource_size_t)OF_BAD_ADDR; ++ res->end = (resource_size_t)OF_BAD_ADDR; ++ return err; ++} + #endif /* CONFIG_PCI */ + + /* +@@ -601,12 +648,119 @@ const __be32 *of_get_address(struct device_node *dev, int index, u64 *size, } EXPORT_SYMBOL(of_get_address); ++#ifdef PCI_IOBASE +struct io_range { + struct list_head list; + phys_addr_t start; @@ -7191,6 +5478,8 @@ index 5edfcb0..cbbaed2 100644 +}; + +static LIST_HEAD(io_range_list); ++static DEFINE_SPINLOCK(io_range_lock); ++#endif + +/* + * Record the PCI IO range (expressed as CPU physical address + size). @@ -7198,35 +5487,76 @@ index 5edfcb0..cbbaed2 100644 + */ +int __weak pci_register_io_range(phys_addr_t addr, resource_size_t size) +{ ++ int err = 0; ++ +#ifdef PCI_IOBASE -+ struct io_range *res; ++ struct io_range *range; + resource_size_t allocated_size = 0; + + /* check if the range hasn't been previously recorded */ -+ list_for_each_entry(res, &io_range_list, list) { -+ if (addr >= res->start && addr + size <= res->start + size) -+ return 0; -+ allocated_size += res->size; ++ spin_lock(&io_range_lock); ++ list_for_each_entry(range, &io_range_list, list) { ++ if (addr >= range->start && addr + size <= range->start + size) { ++ /* range already registered, bail out */ ++ goto end_register; ++ } ++ allocated_size += range->size; + } + + /* range not registed yet, check for available space */ -+ if (allocated_size + size - 1 > IO_SPACE_LIMIT) -+ return -E2BIG; ++ if (allocated_size + size - 1 > IO_SPACE_LIMIT) { ++ /* if it's too big check if 64K space can be reserved */ ++ if (allocated_size + SZ_64K - 1 > IO_SPACE_LIMIT) { ++ err = -E2BIG; ++ goto end_register; ++ } ++ ++ size = SZ_64K; ++ pr_warn("Requested IO range too big, new size set to 64K\n"); ++ } + + /* add the range to the list */ -+ res = kzalloc(sizeof(*res), GFP_KERNEL); -+ if (!res) -+ return -ENOMEM; ++ range = kzalloc(sizeof(*range), GFP_KERNEL); ++ if (!range) { ++ err = -ENOMEM; ++ goto end_register; ++ } + -+ res->start = addr; -+ res->size = size; ++ range->start = addr; ++ range->size = size; + -+ list_add_tail(&res->list, &io_range_list); ++ list_add_tail(&range->list, &io_range_list); + -+ return 0; -+#else -+ return -EINVAL; ++end_register: ++ spin_unlock(&io_range_lock); +#endif ++ ++ return err; ++} ++ ++phys_addr_t pci_pio_to_address(unsigned long pio) ++{ ++ phys_addr_t address = (phys_addr_t)OF_BAD_ADDR; ++ ++#ifdef PCI_IOBASE ++ struct io_range *range; ++ resource_size_t allocated_size = 0; ++ ++ if (pio > IO_SPACE_LIMIT) ++ return address; ++ ++ spin_lock(&io_range_lock); ++ list_for_each_entry(range, &io_range_list, list) { ++ if (pio >= allocated_size && pio < allocated_size + range->size) { ++ address = range->start + pio - allocated_size; ++ break; ++ } ++ allocated_size += range->size; ++ } ++ spin_unlock(&io_range_lock); ++#endif ++ ++ return address; +} + unsigned long __weak pci_address_to_pio(phys_addr_t address) @@ -7234,16 +5564,19 @@ index 5edfcb0..cbbaed2 100644 +#ifdef PCI_IOBASE + struct io_range *res; + resource_size_t offset = 0; ++ unsigned long addr = -1; + ++ spin_lock(&io_range_lock); + list_for_each_entry(res, &io_range_list, list) { -+ if (address >= res->start && -+ address < res->start + res->size) { -+ return res->start - address + offset; ++ if (address >= res->start && address < res->start + res->size) { ++ addr = res->start - address + offset; ++ break; + } + offset += res->size; + } ++ spin_unlock(&io_range_lock); + -+ return (unsigned long)-1; ++ return addr; +#else if (address > IO_SPACE_LIMIT) return (unsigned long)-1; @@ -7253,111 +5586,119 @@ index 5edfcb0..cbbaed2 100644 } static int __of_address_to_resource(struct device_node *dev, -@@ -811,3 +872,50 @@ bool of_dma_is_coherent(struct device_node *np) - return false; - } - EXPORT_SYMBOL_GPL(of_dma_is_coherent); -+ -+/* -+ * of_pci_range_to_resource - Create a resource from an of_pci_range -+ * @range: the PCI range that describes the resource -+ * @np: device node where the range belongs to -+ * @res: pointer to a valid resource that will be updated to -+ * reflect the values contained in the range. -+ * -+ * Returns EINVAL if the range cannot be converted to resource. -+ * -+ * Note that if the range is an IO range, the resource will be converted -+ * using pci_address_to_pio() which can fail if it is called too early or -+ * if the range cannot be matched to any host bridge IO space (our case here). -+ * To guard against that we try to register the IO range first. -+ * If that fails we know that pci_address_to_pio() will do too. -+ */ -+int of_pci_range_to_resource(struct of_pci_range *range, -+ struct device_node *np, struct resource *res) -+{ -+ int err; -+ res->flags = range->flags; -+ res->parent = res->child = res->sibling = NULL; -+ res->name = np->full_name; -+ -+ if (res->flags & IORESOURCE_IO) { -+ unsigned long port = -1; -+ err = pci_register_io_range(range->cpu_addr, range->size); -+ if (err) -+ goto invalid_range; -+ port = pci_address_to_pio(range->cpu_addr); -+ if (port == (unsigned long)-1) { -+ err = -EINVAL; -+ goto invalid_range; -+ } -+ res->start = port; -+ } else { -+ res->start = range->cpu_addr; -+ } -+ res->end = res->start + range->size - 1; -+ return 0; -+ -+invalid_range: -+ res->start = (resource_size_t)OF_BAD_ADDR; -+ res->end = (resource_size_t)OF_BAD_ADDR; -+ return err; -+} -+ diff --git a/drivers/of/of_pci.c b/drivers/of/of_pci.c -index 8481996..e81402a 100644 +index 8481996..8882b46 100644 --- a/drivers/of/of_pci.c +++ b/drivers/of/of_pci.c -@@ -1,6 +1,7 @@ +@@ -1,7 +1,9 @@ #include <linux/kernel.h> #include <linux/export.h> #include <linux/of.h> +#include <linux/of_address.h> #include <linux/of_pci.h> ++#include <linux/slab.h> static inline int __of_pci_pci_compare(struct device_node *node, -@@ -89,6 +90,141 @@ int of_pci_parse_bus_range(struct device_node *node, struct resource *res) + unsigned int data) +@@ -89,6 +91,146 @@ int of_pci_parse_bus_range(struct device_node *node, struct resource *res) } EXPORT_SYMBOL_GPL(of_pci_parse_bus_range); +/** -+ * pci_host_bridge_of_get_ranges - Parse PCI host bridge resources from DT ++ * This function will try to obtain the host bridge domain number by ++ * finding a property called "linux,pci-domain" of the given device node. ++ * ++ * @node: device tree node with the domain information ++ * ++ * Returns the associated domain number from DT in the range [0-0xffff], or ++ * a negative value if the required property is not found. ++ */ ++int of_get_pci_domain_nr(struct device_node *node) ++{ ++ const __be32 *value; ++ int len; ++ u16 domain; ++ ++ value = of_get_property(node, "linux,pci-domain", &len); ++ if (!value || len < sizeof(*value)) ++ return -EINVAL; ++ ++ domain = (u16)be32_to_cpup(value); ++ ++ return domain; ++} ++EXPORT_SYMBOL_GPL(of_get_pci_domain_nr); ++ ++#if defined(CONFIG_OF_ADDRESS) ++/** ++ * of_pci_get_host_bridge_resources - Parse PCI host bridge resources from DT + * @dev: device node of the host bridge having the range property ++ * @busno: bus number associated with the bridge root bus ++ * @bus_max: maximum number of buses for this bridge + * @resources: list where the range of resources will be added after DT parsing -+ * @io_base: pointer to a variable that will contain the physical address for -+ * the start of the I/O range. ++ * @io_base: pointer to a variable that will contain on return the physical ++ * address for the start of the I/O range. Can be NULL if the caller doesn't ++ * expect IO ranges to be present in the device tree. + * -+ * It is the callers job to free the @resources list if an error is returned. ++ * It is the caller's job to free the @resources list. + * + * This function will parse the "ranges" property of a PCI host bridge device + * node and setup the resource mapping based on its content. It is expected + * that the property conforms with the Power ePAPR document. + * -+ * Each architecture is then offered the chance of applying their own -+ * filtering of pci_host_bridge_windows based on their own restrictions by -+ * calling pcibios_fixup_bridge_ranges(). The filtered list of windows -+ * can then be used when creating a pci_host_bridge structure. ++ * It returns zero if the range parsing has been successful or a standard error ++ * value if it failed. + */ -+static int pci_host_bridge_of_get_ranges(struct device_node *dev, -+ struct list_head *resources, resource_size_t *io_base) ++int of_pci_get_host_bridge_resources(struct device_node *dev, ++ unsigned char busno, unsigned char bus_max, ++ struct list_head *resources, resource_size_t *io_base) +{ + struct resource *res; ++ struct resource *bus_range; + struct of_pci_range range; + struct of_pci_range_parser parser; ++ char range_type[4]; + int err; + ++ if (io_base) ++ *io_base = (resource_size_t)OF_BAD_ADDR; ++ ++ bus_range = kzalloc(sizeof(*bus_range), GFP_KERNEL); ++ if (!bus_range) ++ return -ENOMEM; ++ + pr_info("PCI host bridge %s ranges:\n", dev->full_name); + ++ err = of_pci_parse_bus_range(dev, bus_range); ++ if (err) { ++ bus_range->start = busno; ++ bus_range->end = bus_max; ++ bus_range->flags = IORESOURCE_BUS; ++ pr_info(" No bus range found for %s, using %pR\n", ++ dev->full_name, bus_range); ++ } else { ++ if (bus_range->end > bus_range->start + bus_max) ++ bus_range->end = bus_range->start + bus_max; ++ } ++ pci_add_resource(resources, bus_range); ++ + /* Check for ranges property */ + err = of_pci_range_parser_init(&parser, dev); + if (err) -+ return err; ++ goto parse_failed; + + pr_debug("Parsing ranges property...\n"); + for_each_of_pci_range(&parser, &range) { + /* Read next ranges element */ -+ pr_debug("pci_space: 0x%08x pci_addr:0x%016llx cpu_addr:0x%016llx size:0x%016llx\n", -+ range.pci_space, range.pci_addr, range.cpu_addr, range.size); ++ if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_IO) ++ snprintf(range_type, 4, " IO"); ++ else if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_MEM) ++ snprintf(range_type, 4, "MEM"); ++ else ++ snprintf(range_type, 4, "err"); ++ pr_info(" %s %#010llx..%#010llx -> %#010llx\n", range_type, ++ range.cpu_addr, range.cpu_addr + range.size - 1, ++ range.pci_addr); + + /* + * If we failed translation or got a zero-sized region @@ -7367,142 +5708,52 @@ index 8481996..e81402a 100644 + continue; + + res = kzalloc(sizeof(struct resource), GFP_KERNEL); -+ if (!res) -+ return -ENOMEM; ++ if (!res) { ++ err = -ENOMEM; ++ goto parse_failed; ++ } + + err = of_pci_range_to_resource(&range, dev, res); + if (err) -+ return err; -+ -+ if (resource_type(res) == IORESOURCE_IO) ++ goto conversion_failed; ++ ++ if (resource_type(res) == IORESOURCE_IO) { ++ if (!io_base) { ++ pr_err("I/O range found for %s. Please provide an io_base pointer to save CPU base address\n", ++ dev->full_name); ++ err = -EINVAL; ++ goto conversion_failed; ++ } ++ if (*io_base != (resource_size_t)OF_BAD_ADDR) ++ pr_warn("More than one I/O resource converted for %s. CPU base address for old range lost!\n", ++ dev->full_name); + *io_base = range.cpu_addr; ++ } + -+ pci_add_resource_offset(resources, res, -+ res->start - range.pci_addr); -+ } -+ -+ /* Apply architecture specific fixups for the ranges */ -+ return pcibios_fixup_bridge_ranges(resources); -+} -+ -+static atomic_t domain_nr = ATOMIC_INIT(-1); -+ -+/** -+ * of_create_pci_host_bridge - Create a PCI host bridge structure using -+ * information passed in the DT. -+ * @parent: device owning this host bridge -+ * @ops: pci_ops associated with the host controller -+ * @host_data: opaque data structure used by the host controller. -+ * -+ * returns a pointer to the newly created pci_host_bridge structure, or -+ * NULL if the call failed. -+ * -+ * This function will try to obtain the host bridge domain number by -+ * using of_alias_get_id() call with "pci-domain" as a stem. If that -+ * fails, a local allocator will be used that will put each host bridge -+ * in a new domain. -+ */ -+struct pci_host_bridge * -+of_create_pci_host_bridge(struct device *parent, struct pci_ops *ops, void *host_data) -+{ -+ int err, domain, busno; -+ struct resource *bus_range; -+ struct pci_bus *root_bus; -+ struct pci_host_bridge *bridge; -+ resource_size_t io_base = 0; -+ LIST_HEAD(res); -+ -+ bus_range = kzalloc(sizeof(*bus_range), GFP_KERNEL); -+ if (!bus_range) -+ return ERR_PTR(-ENOMEM); -+ -+ domain = of_alias_get_id(parent->of_node, "pci-domain"); -+ if (domain == -ENODEV) -+ domain = atomic_inc_return(&domain_nr); -+ -+ err = of_pci_parse_bus_range(parent->of_node, bus_range); -+ if (err) { -+ dev_info(parent, "No bus range for %s, using default [0-255]\n", -+ parent->of_node->full_name); -+ bus_range->start = 0; -+ bus_range->end = 255; -+ bus_range->flags = IORESOURCE_BUS; -+ } -+ busno = bus_range->start; -+ pci_add_resource(&res, bus_range); -+ -+ /* now parse the rest of host bridge bus ranges */ -+ err = pci_host_bridge_of_get_ranges(parent->of_node, &res, &io_base); -+ if (err) -+ goto err_create; -+ -+ /* then create the root bus */ -+ root_bus = pci_create_root_bus_in_domain(parent, domain, busno, -+ ops, host_data, &res); -+ if (IS_ERR(root_bus)) { -+ err = PTR_ERR(root_bus); -+ goto err_create; ++ pci_add_resource_offset(resources, res, res->start - range.pci_addr); + } + -+ bridge = to_pci_host_bridge(root_bus->bridge); -+ bridge->io_base = io_base; -+ -+ return bridge; ++ return 0; + -+err_create: -+ pci_free_resource_list(&res); -+ return ERR_PTR(err); ++conversion_failed: ++ kfree(res); ++parse_failed: ++ pci_free_resource_list(resources); ++ return err; +} -+EXPORT_SYMBOL_GPL(of_create_pci_host_bridge); ++EXPORT_SYMBOL_GPL(of_pci_get_host_bridge_resources); ++#endif /* CONFIG_OF_ADDRESS */ + #ifdef CONFIG_PCI_MSI static LIST_HEAD(of_pci_msi_chip_list); -diff --git a/drivers/pci/host-bridge.c b/drivers/pci/host-bridge.c -index 0e5f3c9..54ceafd 100644 ---- a/drivers/pci/host-bridge.c -+++ b/drivers/pci/host-bridge.c -@@ -16,12 +16,13 @@ static struct pci_bus *find_pci_root_bus(struct pci_bus *bus) - return bus; - } - --static struct pci_host_bridge *find_pci_host_bridge(struct pci_bus *bus) -+struct pci_host_bridge *find_pci_host_bridge(struct pci_bus *bus) - { - struct pci_bus *root_bus = find_pci_root_bus(bus); - - return to_pci_host_bridge(root_bus->bridge); - } -+EXPORT_SYMBOL_GPL(find_pci_host_bridge); - - void pci_set_host_bridge_release(struct pci_host_bridge *bridge, - void (*release_fn)(struct pci_host_bridge *), -@@ -82,3 +83,18 @@ void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, - res->end = region->end + offset; - } - EXPORT_SYMBOL(pcibios_bus_to_resource); -+ -+/** -+ * Simple version of the platform specific code for filtering the list -+ * of resources obtained from the ranges declaration in DT. -+ * -+ * Platforms can override this function in order to impose stronger -+ * constraints onto the list of resources that a host bridge can use. -+ * The filtered list will then be used to create a root bus and associate -+ * it with the host bridge. -+ * -+ */ -+int __weak pcibios_fixup_bridge_ranges(struct list_head *resources) -+{ -+ return 0; -+} diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig -index 21df477..3b988a2 100644 +index 90f5cca..382fd3d 100644 --- a/drivers/pci/host/Kconfig +++ b/drivers/pci/host/Kconfig -@@ -46,4 +46,14 @@ config PCI_HOST_GENERIC - Say Y here if you want to support a simple generic PCI host - controller, such as the one emulated by kvmtool. +@@ -63,4 +63,14 @@ config PCIE_SPEAR13XX + help + Say Y here if you want PCIe support on SPEAr13XX SoCs. +config PCI_XGENE + bool "X-Gene PCIe controller" @@ -7516,24 +5767,72 @@ index 21df477..3b988a2 100644 + endmenu diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile -index 611ba4b..0801606 100644 +index d0e88f1..845611f 100644 --- a/drivers/pci/host/Makefile +++ b/drivers/pci/host/Makefile -@@ -6,3 +6,4 @@ obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o - obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o +@@ -8,3 +8,4 @@ obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o obj-$(CONFIG_PCI_RCAR_GEN2_PCIE) += pcie-rcar.o obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o + obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o +obj-$(CONFIG_PCI_XGENE) += pci-xgene.o +diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c +index 0fb0fdb..946935d 100644 +--- a/drivers/pci/host/pci-tegra.c ++++ b/drivers/pci/host/pci-tegra.c +@@ -626,13 +626,14 @@ DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable); + static int tegra_pcie_setup(int nr, struct pci_sys_data *sys) + { + struct tegra_pcie *pcie = sys_to_pcie(sys); ++ phys_addr_t io_start = pci_pio_to_address(pcie->io.start); + + pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset); + pci_add_resource_offset(&sys->resources, &pcie->prefetch, + sys->mem_offset); + pci_add_resource(&sys->resources, &pcie->busn); + +- pci_ioremap_io(nr * SZ_64K, pcie->io.start); ++ pci_ioremap_io(nr * SZ_64K, io_start); + + return 1; + } +@@ -737,6 +738,7 @@ static irqreturn_t tegra_pcie_isr(int irq, void *arg) + static void tegra_pcie_setup_translations(struct tegra_pcie *pcie) + { + u32 fpci_bar, size, axi_address; ++ phys_addr_t io_start = pci_pio_to_address(pcie->io.start); + + /* Bar 0: type 1 extended configuration space */ + fpci_bar = 0xfe100000; +@@ -749,7 +751,7 @@ static void tegra_pcie_setup_translations(struct tegra_pcie *pcie) + /* Bar 1: downstream IO bar */ + fpci_bar = 0xfdfc0000; + size = resource_size(&pcie->io); +- axi_address = pcie->io.start; ++ axi_address = io_start; + afi_writel(pcie, axi_address, AFI_AXI_BAR1_START); + afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ); + afi_writel(pcie, fpci_bar, AFI_FPCI_BAR1); +@@ -1520,7 +1522,9 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie) + } + + for_each_of_pci_range(&parser, &range) { +- of_pci_range_to_resource(&range, np, &res); ++ err = of_pci_range_to_resource(&range, np, &res); ++ if (err < 0) ++ return err; + + switch (res.flags & IORESOURCE_TYPE_BITS) { + case IORESOURCE_IO: diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c new file mode 100644 -index 0000000..7bf4ac7 +index 0000000..41c76b8 --- /dev/null +++ b/drivers/pci/host/pci-xgene.c -@@ -0,0 +1,725 @@ +@@ -0,0 +1,659 @@ +/** + * APM X-Gene PCIe Driver + * -+ * Copyright (c) 2013 Applied Micro Circuits Corporation. ++ * Copyright (c) 2014 Applied Micro Circuits Corporation. + * + * Author: Tanmay Inamdar <tinamdar@apm.com>. + * @@ -7562,9 +5861,7 @@ index 0000000..7bf4ac7 +#include <linux/platform_device.h> +#include <linux/slab.h> + -+#define PCIECORE_LTSSM 0x4c +#define PCIECORE_CTLANDSTATUS 0x50 -+#define INTXSTATUSMASK 0x6c +#define PIM1_1L 0x80 +#define IBAR2 0x98 +#define IR2MSK 0x9c @@ -7580,36 +5877,16 @@ index 0000000..7bf4ac7 +#define CFGCTL 0x15c +#define RTDID 0x160 +#define BRIDGE_CFG_0 0x2000 -+#define BRIDGE_CFG_1 0x2004 +#define BRIDGE_CFG_4 0x2010 -+#define BRIDGE_CFG_32 0x2030 -+#define BRIDGE_CFG_14 0x2038 -+#define BRIDGE_CTRL_1 0x2204 -+#define BRIDGE_CTRL_2 0x2208 -+#define BRIDGE_CTRL_5 0x2214 +#define BRIDGE_STATUS_0 0x2600 -+#define MEM_RAM_SHUTDOWN 0xd070 -+#define BLOCK_MEM_RDY 0xd074 + -+#define DEVICE_PORT_TYPE_MASK 0x03c00000 -+#define PM_FORCE_RP_MODE_MASK 0x00000400 -+#define SWITCH_PORT_MODE_MASK 0x00000800 -+#define CLASS_CODE_MASK 0xffffff00 +#define LINK_UP_MASK 0x00000100 -+#define AER_OPTIONAL_ERROR_EN 0xffc00000 -+#define XGENE_PCIE_DEV_CTRL 0x2f0f +#define AXI_EP_CFG_ACCESS 0x10000 -+#define ENABLE_ASPM 0x08000000 -+#define XGENE_PORT_TYPE_RC 0x05000000 -+#define BLOCK_MEM_RDY_VAL 0xFFFFFFFF +#define EN_COHERENCY 0xF0000000 +#define EN_REG 0x00000001 +#define OB_LO_IO 0x00000002 -+#define XGENE_PCIE_VENDORID 0xE008 ++#define XGENE_PCIE_VENDORID 0x10E8 +#define XGENE_PCIE_DEVICEID 0xE004 -+#define XGENE_PCIE_ECC_TIMEOUT 10 /* ms */ -+#define XGENE_LTSSM_DETECT_WAIT 20 /* ms */ -+#define XGENE_LTSSM_L0_WAIT 4 /* ms */ +#define SZ_1T (SZ_1G*1024ULL) +#define PIPE_PHY_RATE_RD(src) ((0xc000 & (u32)(src)) >> 0xe) + @@ -7619,7 +5896,8 @@ index 0000000..7bf4ac7 + struct clk *clk; + void __iomem *csr_base; + void __iomem *cfg_base; -+ u8 link_up; ++ unsigned long cfg_addr; ++ bool link_up; +}; + +static inline u32 pcie_bar_low_val(u32 addr, u32 flags) @@ -7682,8 +5960,7 @@ index 0000000..7bf4ac7 + *val = readl(addr + offset); +} + -+static inline void -+xgene_pcie_cfg_in16(void __iomem *addr, int offset, u32 *val) ++static inline void xgene_pcie_cfg_in16(void __iomem *addr, int offset, u32 *val) +{ + *val = readl(addr + (offset & ~0x3)); + @@ -7696,8 +5973,7 @@ index 0000000..7bf4ac7 + *val &= 0xFFFF; +} + -+static inline void -+xgene_pcie_cfg_in8(void __iomem *addr, int offset, u32 *val) ++static inline void xgene_pcie_cfg_in8(void __iomem *addr, int offset, u32 *val) +{ + *val = readl(addr + (offset & ~0x3)); + @@ -7715,7 +5991,8 @@ index 0000000..7bf4ac7 + *val &= 0xFF; +} + -+/* When the address bit [17:16] is 2'b01, the Configuration access will be ++/* ++ * When the address bit [17:16] is 2'b01, the Configuration access will be + * treated as Type 1 and it will be forwarded to external PCIe device. + */ +static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus) @@ -7728,7 +6005,8 @@ index 0000000..7bf4ac7 + return port->cfg_base; +} + -+/* For Configuration request, RTDID register is used as Bus Number, ++/* ++ * For Configuration request, RTDID register is used as Bus Number, + * Device Number and Function number of the header fields. + */ +static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn) @@ -7749,6 +6027,23 @@ index 0000000..7bf4ac7 + readl(port->csr_base + RTDID); +} + ++/* ++ * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as ++ * the translation between PCI bus to native BUS. Entire DDR region ++ * is mapped on to PCIe space using these registers, so that it is ++ * accessible for EP devices for DMA. The BAR0/1 of bridge should be ++ * hidden during enumeration to avoid the sizing and resource allocation ++ * by PCIe core. ++ */ ++static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset) ++{ ++ if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) || ++ (offset == PCI_BASE_ADDRESS_1))) ++ return true; ++ ++ return false; ++} ++ +static int xgene_pcie_read_config(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 *val) +{ @@ -7758,6 +6053,11 @@ index 0000000..7bf4ac7 + if ((pci_is_root_bus(bus) && devfn != 0) || !port->link_up) + return PCIBIOS_DEVICE_NOT_FOUND; + ++ if (xgene_pcie_hide_rc_bars(bus, offset)) { ++ *val = 0; ++ return PCIBIOS_SUCCESSFUL; ++ } ++ + xgene_pcie_set_rtdid_reg(bus, devfn); + addr = xgene_pcie_get_cfg_base(bus); + switch (len) { @@ -7771,6 +6071,7 @@ index 0000000..7bf4ac7 + xgene_pcie_cfg_in32(addr, offset, val); + break; + } ++ + return PCIBIOS_SUCCESSFUL; +} + @@ -7783,6 +6084,9 @@ index 0000000..7bf4ac7 + if ((pci_is_root_bus(bus) && devfn != 0) || !port->link_up) + return PCIBIOS_DEVICE_NOT_FOUND; + ++ if (xgene_pcie_hide_rc_bars(bus, offset)) ++ return PCIBIOS_SUCCESSFUL; ++ + xgene_pcie_set_rtdid_reg(bus, devfn); + addr = xgene_pcie_get_cfg_base(bus); + switch (len) { @@ -7796,6 +6100,7 @@ index 0000000..7bf4ac7 + xgene_pcie_cfg_out32(addr, offset, val); + break; + } ++ + return PCIBIOS_SUCCESSFUL; +} + @@ -7804,19 +6109,6 @@ index 0000000..7bf4ac7 + .write = xgene_pcie_write_config +}; + -+static void xgene_pcie_program_core(void __iomem *csr_base) -+{ -+ u32 val; -+ -+ val = readl(csr_base + BRIDGE_CFG_0); -+ val |= AER_OPTIONAL_ERROR_EN; -+ writel(val, csr_base + BRIDGE_CFG_0); -+ writel(0x0, csr_base + INTXSTATUSMASK); -+ val = readl(csr_base + BRIDGE_CTRL_1); -+ val = (val & ~0xffff) | XGENE_PCIE_DEV_CTRL; -+ writel(val, csr_base + BRIDGE_CTRL_1); -+} -+ +static u64 xgene_pcie_set_ib_mask(void __iomem *csr_base, u32 addr, + u32 flags, u64 size) +{ @@ -7843,86 +6135,22 @@ index 0000000..7bf4ac7 + return mask; +} + -+static void xgene_pcie_poll_linkup(struct xgene_pcie_port *port, ++static void xgene_pcie_linkup(struct xgene_pcie_port *port, + u32 *lanes, u32 *speed) +{ + void __iomem *csr_base = port->csr_base; -+ ulong timeout; + u32 val32; + -+ /* -+ * A component enters the LTSSM Detect state within -+ * 20ms of the end of fundamental core reset. -+ */ -+ msleep(XGENE_LTSSM_DETECT_WAIT); -+ port->link_up = 0; -+ timeout = jiffies + msecs_to_jiffies(XGENE_LTSSM_L0_WAIT); -+ while (time_before(jiffies, timeout)) { -+ val32 = readl(csr_base + PCIECORE_CTLANDSTATUS); -+ if (val32 & LINK_UP_MASK) { -+ port->link_up = 1; -+ *speed = PIPE_PHY_RATE_RD(val32); -+ val32 = readl(csr_base + BRIDGE_STATUS_0); -+ *lanes = val32 >> 26; -+ break; -+ } -+ msleep(1); ++ port->link_up = false; ++ val32 = readl(csr_base + PCIECORE_CTLANDSTATUS); ++ if (val32 & LINK_UP_MASK) { ++ port->link_up = true; ++ *speed = PIPE_PHY_RATE_RD(val32); ++ val32 = readl(csr_base + BRIDGE_STATUS_0); ++ *lanes = val32 >> 26; + } +} + -+static void xgene_pcie_setup_root_complex(struct xgene_pcie_port *port) -+{ -+ void __iomem *csr_base = port->csr_base; -+ u32 val; -+ -+ val = (XGENE_PCIE_DEVICEID << 16) | XGENE_PCIE_VENDORID; -+ writel(val, csr_base + BRIDGE_CFG_0); -+ -+ val = readl(csr_base + BRIDGE_CFG_1); -+ val &= ~CLASS_CODE_MASK; -+ val |= PCI_CLASS_BRIDGE_PCI << 16; -+ writel(val, csr_base + BRIDGE_CFG_1); -+ -+ val = readl(csr_base + BRIDGE_CFG_14); -+ val |= SWITCH_PORT_MODE_MASK; -+ val &= ~PM_FORCE_RP_MODE_MASK; -+ writel(val, csr_base + BRIDGE_CFG_14); -+ -+ val = readl(csr_base + BRIDGE_CTRL_5); -+ val &= ~DEVICE_PORT_TYPE_MASK; -+ val |= XGENE_PORT_TYPE_RC; -+ writel(val, csr_base + BRIDGE_CTRL_5); -+ -+ val = readl(csr_base + BRIDGE_CTRL_2); -+ val |= ENABLE_ASPM; -+ writel(val, csr_base + BRIDGE_CTRL_2); -+ -+ val = readl(csr_base + BRIDGE_CFG_32); -+ writel(val | (1 << 19), csr_base + BRIDGE_CFG_32); -+} -+ -+/* Return 0 on success */ -+static int xgene_pcie_init_ecc(struct xgene_pcie_port *port) -+{ -+ void __iomem *csr_base = port->csr_base; -+ ulong timeout; -+ u32 val; -+ -+ val = readl(csr_base + MEM_RAM_SHUTDOWN); -+ if (!val) -+ return 0; -+ writel(0x0, csr_base + MEM_RAM_SHUTDOWN); -+ timeout = jiffies + msecs_to_jiffies(XGENE_PCIE_ECC_TIMEOUT); -+ while (time_before(jiffies, timeout)) { -+ val = readl(csr_base + BLOCK_MEM_RDY); -+ if (val == BLOCK_MEM_RDY_VAL) -+ return 0; -+ msleep(1); -+ } -+ -+ return 1; -+} -+ +static int xgene_pcie_init_port(struct xgene_pcie_port *port) +{ + int rc; @@ -7939,34 +6167,11 @@ index 0000000..7bf4ac7 + return rc; + } + -+ rc = xgene_pcie_init_ecc(port); -+ if (rc) { -+ dev_err(port->dev, "memory init failed\n"); -+ return rc; -+ } -+ + return 0; +} + -+static void xgene_pcie_fixup_bridge(struct pci_dev *dev) -+{ -+ int i; -+ -+ /* Hide the PCI host BARs from the kernel as their content doesn't -+ * fit well in the resource management -+ */ -+ for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { -+ dev->resource[i].start = dev->resource[i].end = 0; -+ dev->resource[i].flags = 0; -+ } -+ dev_info(&dev->dev, "Hiding X-Gene pci host bridge resources %s\n", -+ pci_name(dev)); -+} -+DECLARE_PCI_FIXUP_HEADER(XGENE_PCIE_VENDORID, XGENE_PCIE_DEVICEID, -+ xgene_pcie_fixup_bridge); -+ +static int xgene_pcie_map_reg(struct xgene_pcie_port *port, -+ struct platform_device *pdev, u64 *cfg_addr) ++ struct platform_device *pdev) +{ + struct resource *res; + @@ -7979,37 +6184,35 @@ index 0000000..7bf4ac7 + port->cfg_base = devm_ioremap_resource(port->dev, res); + if (IS_ERR(port->cfg_base)) + return PTR_ERR(port->cfg_base); -+ *cfg_addr = res->start; ++ port->cfg_addr = res->start; + + return 0; +} + +static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port, -+ struct resource *res, u32 offset, u64 addr) ++ struct resource *res, u32 offset, ++ u64 cpu_addr, u64 pci_addr) +{ + void __iomem *base = port->csr_base + offset; + resource_size_t size = resource_size(res); + u64 restype = resource_type(res); -+ u64 cpu_addr, pci_addr; + u64 mask = 0; + u32 min_size; + u32 flag = EN_REG; + + if (restype == IORESOURCE_MEM) { -+ cpu_addr = res->start; -+ pci_addr = addr; + min_size = SZ_128M; + } else { -+ cpu_addr = addr; -+ pci_addr = res->start; + min_size = 128; + flag |= OB_LO_IO; + } ++ + if (size >= min_size) + mask = ~(size - 1) | flag; + else + dev_warn(port->dev, "res size 0x%llx less than minimum 0x%x\n", + (u64)size, min_size); ++ + writel(lower_32_bits(cpu_addr), base); + writel(upper_32_bits(cpu_addr), base + 0x04); + writel(lower_32_bits(mask), base + 0x08); @@ -8026,39 +6229,40 @@ index 0000000..7bf4ac7 +} + +static int xgene_pcie_map_ranges(struct xgene_pcie_port *port, -+ struct pci_host_bridge *bridge, -+ u64 cfg_addr) ++ struct list_head *res, ++ resource_size_t io_base) +{ -+ struct device *dev = port->dev; + struct pci_host_bridge_window *window; ++ struct device *dev = port->dev; + int ret; + -+ list_for_each_entry(window, &bridge->windows, list) { ++ list_for_each_entry(window, res, list) { + struct resource *res = window->res; + u64 restype = resource_type(res); -+ dev_dbg(port->dev, "0x%08lx 0x%016llx...0x%016llx\n", -+ res->flags, res->start, res->end); ++ ++ dev_dbg(port->dev, "%pR\n", res); + + switch (restype) { + case IORESOURCE_IO: -+ xgene_pcie_setup_ob_reg(port, res, OMR2BARL, -+ bridge->io_base); -+ ret = pci_remap_iospace(res, bridge->io_base); ++ xgene_pcie_setup_ob_reg(port, res, OMR3BARL, io_base, ++ res->start - window->offset); ++ ret = pci_remap_iospace(res, io_base); + if (ret < 0) + return ret; + break; + case IORESOURCE_MEM: -+ xgene_pcie_setup_ob_reg(port, res, OMR3BARL, ++ xgene_pcie_setup_ob_reg(port, res, OMR1BARL, res->start, + res->start - window->offset); + break; + case IORESOURCE_BUS: + break; + default: -+ dev_err(dev, "invalid io resource!"); ++ dev_err(dev, "invalid io resource - %pR\n", res); + return -EINVAL; + } + } -+ xgene_pcie_setup_cfg_reg(port->csr_base, cfg_addr); ++ xgene_pcie_setup_cfg_reg(port->csr_base, port->cfg_addr); ++ + return 0; +} + @@ -8090,6 +6294,7 @@ index 0000000..7bf4ac7 + *ib_reg_mask |= (1 << 2); + return 2; + } ++ + return -EINVAL; +} + @@ -8100,7 +6305,6 @@ index 0000000..7bf4ac7 + void __iomem *cfg_base = port->cfg_base; + void *bar_addr; + void *pim_addr; -+ u64 restype = range->flags & IORESOURCE_TYPE_BITS; + u64 cpu_addr = range->cpu_addr; + u64 pci_addr = range->pci_addr; + u64 size = range->size; @@ -8115,7 +6319,7 @@ index 0000000..7bf4ac7 + return; + } + -+ if (restype == PCI_BASE_ADDRESS_MEM_PREFETCH) ++ if (range->flags & IORESOURCE_PREFETCH) + flags |= PCI_BASE_ADDRESS_MEM_PREFETCH; + + bar_low = pcie_bar_low_val((u32)cpu_addr, flags); @@ -8143,7 +6347,7 @@ index 0000000..7bf4ac7 + break; + } + -+ xgene_pcie_setup_pims(pim_addr, pci_addr, size); ++ xgene_pcie_setup_pims(pim_addr, pci_addr, ~(size - 1)); +} + +static int pci_dma_range_parser_init(struct of_pci_range_parser *parser, @@ -8159,8 +6363,8 @@ index 0000000..7bf4ac7 + parser->range = of_get_property(node, "dma-ranges", &rlen); + if (!parser->range) + return -ENOENT; -+ + parser->end = parser->range + rlen / sizeof(__be32); ++ + return 0; +} + @@ -8180,6 +6384,7 @@ index 0000000..7bf4ac7 + /* Get the dma-ranges from DT */ + for_each_of_pci_range(&parser, &range) { + u64 end = range.cpu_addr + range.size - 1; ++ + dev_dbg(port->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n", + range.flags, range.cpu_addr, end, range.pci_addr); + xgene_pcie_setup_ib_reg(port, &range, &ib_reg_mask); @@ -8187,53 +6392,81 @@ index 0000000..7bf4ac7 + return 0; +} + ++/* clear bar configuration which was done by firmware */ ++static void xgene_pcie_clear_config(struct xgene_pcie_port *port) ++{ ++ int i; ++ ++ for (i = PIM1_1L; i <= CFGCTL; i += 4) ++ writel(0x0, port->csr_base + i); ++} ++ ++static int xgene_pcie_setup(struct xgene_pcie_port *port, ++ struct list_head *res, ++ resource_size_t io_base) ++{ ++ u32 val, lanes = 0, speed = 0; ++ int ret; ++ ++ xgene_pcie_clear_config(port); ++ ++ /* setup the vendor and device IDs correctly */ ++ val = (XGENE_PCIE_DEVICEID << 16) | XGENE_PCIE_VENDORID; ++ writel(val, port->csr_base + BRIDGE_CFG_0); ++ ++ ret = xgene_pcie_map_ranges(port, res, io_base); ++ if (ret) ++ return ret; ++ ++ ret = xgene_pcie_parse_map_dma_ranges(port); ++ if (ret) ++ return ret; ++ ++ xgene_pcie_linkup(port, &lanes, &speed); ++ if (!port->link_up) ++ dev_info(port->dev, "(rc) link down\n"); ++ else ++ dev_info(port->dev, "(rc) x%d gen-%d link up\n", ++ lanes, speed + 1); ++ return 0; ++} ++ +static int xgene_pcie_probe_bridge(struct platform_device *pdev) +{ -+ struct device_node *np = of_node_get(pdev->dev.of_node); ++ struct device_node *dn = pdev->dev.of_node; + struct xgene_pcie_port *port; -+ struct pci_host_bridge *bridge; -+ resource_size_t lastbus; -+ u32 lanes = 0, speed = 0; -+ u64 cfg_addr = 0; ++ resource_size_t iobase = 0; ++ struct pci_bus *bus; + int ret; ++ LIST_HEAD(res); + + port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); + if (!port) + return -ENOMEM; -+ port->node = np; ++ port->node = of_node_get(pdev->dev.of_node); + port->dev = &pdev->dev; + -+ ret = xgene_pcie_map_reg(port, pdev, &cfg_addr); ++ ret = xgene_pcie_map_reg(port, pdev); + if (ret) + return ret; + + ret = xgene_pcie_init_port(port); + if (ret) + return ret; -+ xgene_pcie_program_core(port->csr_base); -+ xgene_pcie_setup_root_complex(port); + -+ bridge = of_create_pci_host_bridge(&pdev->dev, &xgene_pcie_ops, port); -+ if (IS_ERR_OR_NULL(bridge)) -+ return PTR_ERR(bridge); -+ -+ ret = xgene_pcie_map_ranges(port, bridge, cfg_addr); ++ ret = of_pci_get_host_bridge_resources(dn, 0, 0xff, &res, &iobase); + if (ret) + return ret; + -+ ret = xgene_pcie_parse_map_dma_ranges(port); ++ ret = xgene_pcie_setup(port, &res, iobase); + if (ret) + return ret; + -+ xgene_pcie_poll_linkup(port, &lanes, &speed); -+ if (!port->link_up) -+ dev_info(port->dev, "(rc) link down\n"); -+ else -+ dev_info(port->dev, "(rc) x%d gen-%d link up\n", -+ lanes, speed + 1); ++ bus = pci_scan_root_bus(&pdev->dev, 0, &xgene_pcie_ops, port, &res); ++ if (!bus) ++ return -ENOMEM; ++ + platform_set_drvdata(pdev, port); -+ lastbus = pci_rescan_bus(bridge->bus); -+ pci_bus_update_busn_res_end(bridge->bus, lastbus); + return 0; +} + @@ -8255,73 +6488,143 @@ index 0000000..7bf4ac7 +MODULE_AUTHOR("Tanmay Inamdar <tinamdar@apm.com>"); +MODULE_DESCRIPTION("APM X-Gene PCIe driver"); +MODULE_LICENSE("GPL v2"); +diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c +index 4884ee5..61158e0 100644 +--- a/drivers/pci/host/pcie-rcar.c ++++ b/drivers/pci/host/pcie-rcar.c +@@ -323,6 +323,7 @@ static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie) + + /* Setup PCIe address space mappings for each resource */ + resource_size_t size; ++ resource_size_t res_start; + u32 mask; + + rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win)); +@@ -335,8 +336,13 @@ static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie) + mask = (roundup_pow_of_two(size) / SZ_128) - 1; + rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win)); + +- rcar_pci_write_reg(pcie, upper_32_bits(res->start), PCIEPARH(win)); +- rcar_pci_write_reg(pcie, lower_32_bits(res->start), PCIEPARL(win)); ++ if (res->flags & IORESOURCE_IO) ++ res_start = pci_pio_to_address(res->start); ++ else ++ res_start = res->start; ++ ++ rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPARH(win)); ++ rcar_pci_write_reg(pcie, lower_32_bits(res_start), PCIEPARL(win)); + + /* First resource is for IO */ + mask = PAR_ENABLE; +@@ -363,9 +369,10 @@ static int rcar_pcie_setup(int nr, struct pci_sys_data *sys) + + rcar_pcie_setup_window(i, pcie); + +- if (res->flags & IORESOURCE_IO) +- pci_ioremap_io(nr * SZ_64K, res->start); +- else ++ if (res->flags & IORESOURCE_IO) { ++ phys_addr_t io_start = pci_pio_to_address(res->start); ++ pci_ioremap_io(nr * SZ_64K, io_start); ++ } else + pci_add_resource(&sys->resources, res); + } + pci_add_resource(&sys->resources, &pcie->busn); +@@ -935,8 +942,10 @@ static int rcar_pcie_probe(struct platform_device *pdev) + } + + for_each_of_pci_range(&parser, &range) { +- of_pci_range_to_resource(&range, pdev->dev.of_node, ++ err = of_pci_range_to_resource(&range, pdev->dev.of_node, + &pcie->res[win++]); ++ if (err < 0) ++ return err; + + if (win > RCAR_PCI_MAX_RESOURCES) + break; diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c -index 1c8592b..b81dc68 100644 +index 2c9ac70..6e994fc 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c -@@ -17,6 +17,7 @@ - #include <linux/spinlock.h> - #include <linux/string.h> - #include <linux/log2.h> -+#include <linux/of_pci.h> - #include <linux/pci-aspm.h> - #include <linux/pm_wakeup.h> - #include <linux/interrupt.h> -@@ -1453,6 +1454,9 @@ EXPORT_SYMBOL(pcim_pin_device); - */ - int __weak pcibios_add_device(struct pci_dev *dev) - { -+#ifdef CONFIG_OF -+ dev->irq = of_irq_parse_and_map_pci(dev, 0, 0); -+#endif - return 0; - } - -@@ -2704,6 +2708,39 @@ int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) +@@ -2704,6 +2704,37 @@ int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) } EXPORT_SYMBOL(pci_request_regions_exclusive); +/** + * pci_remap_iospace - Remap the memory mapped I/O space + * @res: Resource describing the I/O space -+ * @phys_addr: physical address where the range will be mapped. ++ * @phys_addr: physical address of range to be mapped + * + * Remap the memory mapped I/O space described by the @res -+ * into the CPU physical address space. Only architectures -+ * that have memory mapped IO defined (and hence PCI_IOBASE) -+ * should call this function. ++ * and the CPU physical address @phys_addr into virtual address space. ++ * Only architectures that have memory mapped IO functions defined ++ * (and the PCI_IOBASE value defined) should call this function. + */ +int __weak pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr) +{ -+ int err = -ENODEV; ++#if defined(PCI_IOBASE) && defined(CONFIG_MMU) ++ unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; + -+#ifdef PCI_IOBASE + if (!(res->flags & IORESOURCE_IO)) + return -EINVAL; + + if (res->end > IO_SPACE_LIMIT) + return -EINVAL; + -+ err = ioremap_page_range(res->start + (unsigned long)PCI_IOBASE, -+ res->end + 1 + (unsigned long)PCI_IOBASE, -+ phys_addr, __pgprot(PROT_DEVICE_nGnRE)); ++ return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr, ++ pgprot_device(PAGE_KERNEL)); +#else + /* this architecture does not have memory mapped I/O space, + so this function should never be called */ -+ WARN_ON(1); ++ WARN_ONCE(1, "This architecture does not support memory mapped I/O\n"); ++ return -ENODEV; +#endif -+ -+ return err; +} + static void __pci_set_master(struct pci_dev *dev, bool enable) { u16 old_cmd, cmd; +@@ -4406,6 +4437,15 @@ static void pci_no_domains(void) + #endif + } + ++#ifdef CONFIG_PCI_DOMAINS ++static atomic_t __domain_nr = ATOMIC_INIT(-1); ++ ++int pci_get_new_domain_nr(void) ++{ ++ return atomic_inc_return(&__domain_nr); ++} ++#endif ++ + /** + * pci_ext_cfg_avail - can we access extended PCI config space? + * diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c -index e3cf8a2..abf5e82 100644 +index 4170113..c3cec34 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c -@@ -515,7 +515,7 @@ static void pci_release_host_bridge_dev(struct device *dev) +@@ -485,7 +485,7 @@ void pci_read_bridge_bases(struct pci_bus *child) + } + } + +-static struct pci_bus *pci_alloc_bus(void) ++static struct pci_bus *pci_alloc_bus(struct pci_bus *parent) + { + struct pci_bus *b; + +@@ -500,6 +500,10 @@ static struct pci_bus *pci_alloc_bus(void) + INIT_LIST_HEAD(&b->resources); + b->max_bus_speed = PCI_SPEED_UNKNOWN; + b->cur_bus_speed = PCI_SPEED_UNKNOWN; ++#ifdef CONFIG_PCI_DOMAINS_GENERIC ++ if (parent) ++ b->domain_nr = parent->domain_nr; ++#endif + return b; + } + +@@ -515,7 +519,7 @@ static void pci_release_host_bridge_dev(struct device *dev) kfree(bridge); } @@ -8330,56 +6633,50 @@ index e3cf8a2..abf5e82 100644 { struct pci_host_bridge *bridge; -@@ -524,7 +524,6 @@ static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b) +@@ -524,7 +528,8 @@ static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b) return NULL; INIT_LIST_HEAD(&bridge->windows); - bridge->bus = b; ++ bridge->dev.release = pci_release_host_bridge_dev; ++ return bridge; } -@@ -1749,8 +1748,9 @@ void __weak pcibios_remove_bus(struct pci_bus *bus) - { - } +@@ -671,7 +676,7 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, + /* + * Allocate a new bus, and inherit stuff from the parent.. + */ +- child = pci_alloc_bus(); ++ child = pci_alloc_bus(parent); + if (!child) + return NULL; --struct pci_bus *pci_create_root_bus(struct device *parent, int bus, -- struct pci_ops *ops, void *sysdata, struct list_head *resources) -+struct pci_bus *pci_create_root_bus_in_domain(struct device *parent, -+ int domain, int bus, struct pci_ops *ops, void *sysdata, -+ struct list_head *resources) - { - int error; - struct pci_host_bridge *bridge; -@@ -1761,37 +1761,41 @@ struct pci_bus *pci_create_root_bus(struct device *parent, int bus, +@@ -1751,37 +1756,37 @@ struct pci_bus *pci_create_root_bus(struct device *parent, int bus, char bus_addr[64]; char *fmt; +- b = pci_alloc_bus(); +- if (!b) + bridge = pci_alloc_host_bridge(); + if (!bridge) -+ return ERR_PTR(-ENOMEM); -+ + return NULL; + + bridge->dev.parent = parent; -+ bridge->dev.release = pci_release_host_bridge_dev; -+ bridge->domain_nr = domain; + - b = pci_alloc_bus(); -- if (!b) -- return NULL; -+ if (!b) { -+ error = -ENOMEM; ++ b = pci_alloc_bus(NULL); ++ if (!b) + goto err_out; -+ } - ++ b->sysdata = sysdata; b->ops = ops; b->number = b->busn_res.start = bus; -- b2 = pci_find_bus(pci_domain_nr(b), bus); -+ b2 = pci_find_bus(bridge->domain_nr, bus); ++ pci_bus_assign_domain_nr(b, parent); + b2 = pci_find_bus(pci_domain_nr(b), bus); if (b2) { /* If we already got to this bus through a different bridge, ignore it */ dev_dbg(&b2->dev, "bus already known\n"); - goto err_out; -+ error = -EEXIST; + goto err_bus_out; } @@ -8389,9 +6686,8 @@ index e3cf8a2..abf5e82 100644 - - bridge->dev.parent = parent; - bridge->dev.release = pci_release_host_bridge_dev; -- dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus); + bridge->bus = b; -+ dev_set_name(&bridge->dev, "pci%04x:%02x", bridge->domain_nr, bus); + dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus); error = pcibios_root_bridge_prepare(bridge); - if (error) { - kfree(bridge); @@ -8407,548 +6703,786 @@ index e3cf8a2..abf5e82 100644 } b->bridge = get_device(&bridge->dev); device_enable_async_suspend(b->bridge); -@@ -1802,7 +1806,7 @@ struct pci_bus *pci_create_root_bus(struct device *parent, int bus, - - b->dev.class = &pcibus_class; - b->dev.parent = b->bridge; -- dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus); -+ dev_set_name(&b->dev, "%04x:%02x", bridge->domain_nr, bus); - error = device_register(&b->dev); - if (error) - goto class_dev_reg_err; -@@ -1848,9 +1852,31 @@ struct pci_bus *pci_create_root_bus(struct device *parent, int bus, +@@ -1838,8 +1843,10 @@ struct pci_bus *pci_create_root_bus(struct device *parent, int bus, class_dev_reg_err: put_device(&bridge->dev); device_unregister(&bridge->dev); +-err_out: +err_bus_out: -+ kfree(b); - err_out: -+ kfree(bridge); -+ return ERR_PTR(error); -+} -+ -+struct pci_bus *pci_create_root_bus(struct device *parent, int bus, -+ struct pci_ops *ops, void *sysdata, struct list_head *resources) -+{ -+ int domain_nr; -+ struct pci_bus *b = pci_alloc_bus(); -+ if (!b) -+ return NULL; -+ -+ b->sysdata = sysdata; -+ domain_nr = pci_domain_nr(b); kfree(b); -- return NULL; -+ -+ b = pci_create_root_bus_in_domain(parent, domain_nr, bus, -+ ops, sysdata, resources); -+ if (IS_ERR(b)) -+ return NULL; ++err_out: ++ kfree(bridge); + return NULL; + } + +@@ -1936,6 +1943,9 @@ struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, + if (!found) + pci_bus_update_busn_res_end(b, max); + ++ if (!pci_has_flag(PCI_PROBE_ONLY)) ++ pci_assign_unassigned_bus_resources(b); + -+ return b; + pci_bus_add_devices(b); + return b; } +diff --git a/drivers/pnp/resource.c b/drivers/pnp/resource.c +index 782e822..d952462 100644 +--- a/drivers/pnp/resource.c ++++ b/drivers/pnp/resource.c +@@ -313,6 +313,7 @@ static int pci_dev_uses_irq(struct pnp_dev *pnp, struct pci_dev *pci, + progif = class & 0xff; + class >>= 8; + ++#ifdef HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ + if (class == PCI_CLASS_STORAGE_IDE) { + /* + * Unless both channels are native-PCI mode only, +@@ -326,6 +327,7 @@ static int pci_dev_uses_irq(struct pnp_dev *pnp, struct pci_dev *pci, + return 1; + } + } ++#endif /* HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ */ - int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max) -diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig -index 0754f5c..4478a59 100644 ---- a/drivers/rtc/Kconfig -+++ b/drivers/rtc/Kconfig -@@ -789,7 +789,7 @@ config RTC_DRV_DA9063 - - config RTC_DRV_EFI - tristate "EFI RTC" -- depends on IA64 -+ depends on EFI + return 0; + } +diff --git a/drivers/tty/Kconfig b/drivers/tty/Kconfig +index b24aa01..50fe279 100644 +--- a/drivers/tty/Kconfig ++++ b/drivers/tty/Kconfig +@@ -419,4 +419,10 @@ config DA_CONSOLE help - If you say yes here you will get support for the EFI - Real Time Clock. -diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile -index 70347d0..f1dfc36 100644 ---- a/drivers/rtc/Makefile -+++ b/drivers/rtc/Makefile -@@ -10,6 +10,10 @@ obj-$(CONFIG_RTC_SYSTOHC) += systohc.o - obj-$(CONFIG_RTC_CLASS) += rtc-core.o - rtc-core-y := class.o interface.o - -+ifdef CONFIG_RTC_DRV_EFI -+rtc-core-y += rtc-efi-platform.o -+endif -+ - rtc-core-$(CONFIG_RTC_INTF_DEV) += rtc-dev.o - rtc-core-$(CONFIG_RTC_INTF_PROC) += rtc-proc.o - rtc-core-$(CONFIG_RTC_INTF_SYSFS) += rtc-sysfs.o -diff --git a/drivers/rtc/rtc-efi-platform.c b/drivers/rtc/rtc-efi-platform.c + This enables a console on a Dash channel. + ++config SBSAUART_TTY ++ tristate "SBSA UART TTY Driver" ++ help ++ Console and system TTY driver for the SBSA UART which is defined ++ in the Server Base System Architecure document for ARM64 servers. ++ + endif # TTY +diff --git a/drivers/tty/Makefile b/drivers/tty/Makefile +index 58ad1c0..c3211c0 100644 +--- a/drivers/tty/Makefile ++++ b/drivers/tty/Makefile +@@ -29,5 +29,6 @@ obj-$(CONFIG_SYNCLINK) += synclink.o + obj-$(CONFIG_PPC_EPAPR_HV_BYTECHAN) += ehv_bytechan.o + obj-$(CONFIG_GOLDFISH_TTY) += goldfish.o + obj-$(CONFIG_DA_TTY) += metag_da.o ++obj-$(CONFIG_SBSAUART_TTY) += sbsauart.o + + obj-y += ipwireless/ +diff --git a/drivers/tty/sbsauart.c b/drivers/tty/sbsauart.c new file mode 100644 -index 0000000..b40fbe3 +index 0000000..402f168 --- /dev/null -+++ b/drivers/rtc/rtc-efi-platform.c -@@ -0,0 +1,31 @@ ++++ b/drivers/tty/sbsauart.c +@@ -0,0 +1,355 @@ +/* -+ * Moved from arch/ia64/kernel/time.c ++ * SBSA (Server Base System Architecture) Compatible UART driver ++ * ++ * Copyright (C) 2014 Linaro Ltd ++ * ++ * Author: Graeme Gregory <graeme.gregory@linaro.org> ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. + * -+ * Copyright (C) 1998-2003 Hewlett-Packard Co -+ * Stephane Eranian <eranian@hpl.hp.com> -+ * David Mosberger <davidm@hpl.hp.com> -+ * Copyright (C) 1999 Don Dugger <don.dugger@intel.com> -+ * Copyright (C) 1999-2000 VA Linux Systems -+ * Copyright (C) 1999-2000 Walt Drummond <drummond@valinux.com> + */ -+#include <linux/init.h> -+#include <linux/kernel.h> ++ ++#include <linux/acpi.h> ++#include <linux/amba/serial.h> ++#include <linux/console.h> ++#include <linux/delay.h> ++#include <linux/interrupt.h> ++#include <linux/io.h> +#include <linux/module.h> -+#include <linux/efi.h> +#include <linux/platform_device.h> ++#include <linux/slab.h> ++#include <linux/serial_core.h> ++#include <linux/tty.h> ++#include <linux/tty_flip.h> + -+static struct platform_device rtc_efi_dev = { -+ .name = "rtc-efi", -+ .id = -1, ++struct sbsa_tty { ++ struct tty_port port; ++ spinlock_t lock; ++ void __iomem *base; ++ u32 irq; ++ int opencount; ++ struct console console; +}; + -+static int __init rtc_init(void) ++static struct tty_driver *sbsa_tty_driver; ++static struct sbsa_tty *sbsa_tty; ++ ++#define SBSAUART_CHAR_MASK 0xFF ++ ++static void sbsa_raw_putc(struct uart_port *port, int c) ++{ ++ while (readw(port->membase + UART01x_FR) & UART01x_FR_TXFF) ++ ; ++ writew(c & 0xFF, port->membase + UART01x_DR); ++} ++ ++static void sbsa_uart_early_write(struct console *con, const char *buf, ++ unsigned count) +{ -+ if (efi_enabled(EFI_RUNTIME_SERVICES)) -+ if (platform_device_register(&rtc_efi_dev) < 0) -+ pr_err("unable to register rtc device...\n"); ++ struct earlycon_device *dev = con->data; + -+ /* not necessarily an error */ ++ uart_console_write(&dev->port, buf, count, sbsa_raw_putc); ++} ++ ++static int __init sbsa_uart_early_console_setup(struct earlycon_device *device, ++ const char *opt) ++{ ++ if (!device->port.membase) ++ return -ENODEV; ++ ++ device->con->write = sbsa_uart_early_write; + return 0; +} -+module_init(rtc_init); -diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h -index 975e1cc..2e2161b 100644 ---- a/include/asm-generic/io.h -+++ b/include/asm-generic/io.h -@@ -331,7 +331,7 @@ static inline void iounmap(void __iomem *addr) - #ifndef CONFIG_GENERIC_IOMAP - static inline void __iomem *ioport_map(unsigned long port, unsigned int nr) - { -- return (void __iomem *) port; -+ return (void __iomem *)(PCI_IOBASE + (port & IO_SPACE_LIMIT)); - } - - static inline void ioport_unmap(void __iomem *p) -diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h -index f27000f..35b0c12 100644 ---- a/include/kvm/arm_vgic.h -+++ b/include/kvm/arm_vgic.h -@@ -24,7 +24,6 @@ - #include <linux/irqreturn.h> - #include <linux/spinlock.h> - #include <linux/types.h> --#include <linux/irqchip/arm-gic.h> - - #define VGIC_NR_IRQS 256 - #define VGIC_NR_SGIS 16 -@@ -32,7 +31,9 @@ - #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS) - #define VGIC_NR_SHARED_IRQS (VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS) - #define VGIC_MAX_CPUS KVM_MAX_VCPUS --#define VGIC_MAX_LRS (1 << 6) -+ -+#define VGIC_V2_MAX_LRS (1 << 6) -+#define VGIC_V3_MAX_LRS 16 - - /* Sanity checks... */ - #if (VGIC_MAX_CPUS > 8) -@@ -68,9 +69,62 @@ struct vgic_bytemap { - u32 shared[VGIC_NR_SHARED_IRQS / 4]; - }; - -+struct kvm_vcpu; ++EARLYCON_DECLARE(sbsauart, sbsa_uart_early_console_setup); + -+enum vgic_type { -+ VGIC_V2, /* Good ol' GICv2 */ -+ VGIC_V3, /* New fancy GICv3 */ -+}; ++static void sbsa_tty_do_write(const char *buf, unsigned count) ++{ ++ unsigned long irq_flags; ++ struct sbsa_tty *qtty = sbsa_tty; ++ void __iomem *base = qtty->base; ++ unsigned n; ++ ++ spin_lock_irqsave(&qtty->lock, irq_flags); ++ for (n = 0; n < count; n++) { ++ while (readw(base + UART01x_FR) & UART01x_FR_TXFF) ++ ; ++ writew(buf[n], base + UART01x_DR); ++ } ++ spin_unlock_irqrestore(&qtty->lock, irq_flags); ++} ++ ++static void sbsauart_fifo_to_tty(struct sbsa_tty *qtty) ++{ ++ void __iomem *base = qtty->base; ++ unsigned int flag, max_count = 32; ++ u16 status, ch; ++ ++ while (max_count--) { ++ status = readw(base + UART01x_FR); ++ if (status & UART01x_FR_RXFE) ++ break; ++ ++ /* Take chars from the FIFO and update status */ ++ ch = readw(base + UART01x_DR); ++ flag = TTY_NORMAL; ++ ++ if (ch & UART011_DR_BE) ++ flag = TTY_BREAK; ++ else if (ch & UART011_DR_PE) ++ flag = TTY_PARITY; ++ else if (ch & UART011_DR_FE) ++ flag = TTY_FRAME; ++ else if (ch & UART011_DR_OE) ++ flag = TTY_OVERRUN; + -+#define LR_STATE_PENDING (1 << 0) -+#define LR_STATE_ACTIVE (1 << 1) -+#define LR_STATE_MASK (3 << 0) -+#define LR_EOI_INT (1 << 2) ++ ch &= SBSAUART_CHAR_MASK; ++ ++ tty_insert_flip_char(&qtty->port, ch, flag); ++ } ++ ++ tty_schedule_flip(&qtty->port); ++ ++ /* Clear the RX IRQ */ ++ writew(UART011_RXIC | UART011_RXIC, base + UART011_ICR); ++} ++ ++static irqreturn_t sbsa_tty_interrupt(int irq, void *dev_id) ++{ ++ struct sbsa_tty *qtty = sbsa_tty; ++ unsigned long irq_flags; + -+struct vgic_lr { -+ u16 irq; -+ u8 source; -+ u8 state; ++ spin_lock_irqsave(&qtty->lock, irq_flags); ++ sbsauart_fifo_to_tty(qtty); ++ spin_unlock_irqrestore(&qtty->lock, irq_flags); ++ ++ return IRQ_HANDLED; ++} ++ ++static int sbsa_tty_open(struct tty_struct *tty, struct file *filp) ++{ ++ struct sbsa_tty *qtty = sbsa_tty; ++ ++ return tty_port_open(&qtty->port, tty, filp); ++} ++ ++static void sbsa_tty_close(struct tty_struct *tty, struct file *filp) ++{ ++ tty_port_close(tty->port, tty, filp); ++} ++ ++static void sbsa_tty_hangup(struct tty_struct *tty) ++{ ++ tty_port_hangup(tty->port); ++} ++ ++static int sbsa_tty_write(struct tty_struct *tty, const unsigned char *buf, ++ int count) ++{ ++ sbsa_tty_do_write(buf, count); ++ return count; ++} ++ ++static int sbsa_tty_write_room(struct tty_struct *tty) ++{ ++ return 32; ++} ++ ++static void sbsa_tty_console_write(struct console *co, const char *b, ++ unsigned count) ++{ ++ sbsa_tty_do_write(b, count); ++ ++ if (b[count - 1] == '\n') ++ sbsa_tty_do_write("\r", 1); ++} ++ ++static struct tty_driver *sbsa_tty_console_device(struct console *c, ++ int *index) ++{ ++ *index = c->index; ++ return sbsa_tty_driver; ++} ++ ++static int sbsa_tty_console_setup(struct console *co, char *options) ++{ ++ if ((unsigned)co->index > 0) ++ return -ENODEV; ++ if (sbsa_tty->base == NULL) ++ return -ENODEV; ++ return 0; ++} ++ ++static struct tty_port_operations sbsa_port_ops = { +}; + -+struct vgic_vmcr { -+ u32 ctlr; -+ u32 abpr; -+ u32 bpr; -+ u32 pmr; ++static const struct tty_operations sbsa_tty_ops = { ++ .open = sbsa_tty_open, ++ .close = sbsa_tty_close, ++ .hangup = sbsa_tty_hangup, ++ .write = sbsa_tty_write, ++ .write_room = sbsa_tty_write_room, +}; + -+struct vgic_ops { -+ struct vgic_lr (*get_lr)(const struct kvm_vcpu *, int); -+ void (*set_lr)(struct kvm_vcpu *, int, struct vgic_lr); -+ void (*sync_lr_elrsr)(struct kvm_vcpu *, int, struct vgic_lr); -+ u64 (*get_elrsr)(const struct kvm_vcpu *vcpu); -+ u64 (*get_eisr)(const struct kvm_vcpu *vcpu); -+ u32 (*get_interrupt_status)(const struct kvm_vcpu *vcpu); -+ void (*enable_underflow)(struct kvm_vcpu *vcpu); -+ void (*disable_underflow)(struct kvm_vcpu *vcpu); -+ void (*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); -+ void (*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); -+ void (*enable)(struct kvm_vcpu *vcpu); ++static int sbsa_tty_create_driver(void) ++{ ++ int ret; ++ struct tty_driver *tty; ++ ++ sbsa_tty = kzalloc(sizeof(*sbsa_tty), GFP_KERNEL); ++ if (sbsa_tty == NULL) { ++ ret = -ENOMEM; ++ goto err_alloc_sbsa_tty_failed; ++ } ++ tty = alloc_tty_driver(1); ++ if (tty == NULL) { ++ ret = -ENOMEM; ++ goto err_alloc_tty_driver_failed; ++ } ++ tty->driver_name = "sbsauart"; ++ tty->name = "ttySBSA"; ++ tty->type = TTY_DRIVER_TYPE_SERIAL; ++ tty->subtype = SERIAL_TYPE_NORMAL; ++ tty->init_termios = tty_std_termios; ++ tty->flags = TTY_DRIVER_RESET_TERMIOS | TTY_DRIVER_REAL_RAW | ++ TTY_DRIVER_DYNAMIC_DEV; ++ tty_set_operations(tty, &sbsa_tty_ops); ++ ret = tty_register_driver(tty); ++ if (ret) ++ goto err_tty_register_driver_failed; ++ ++ sbsa_tty_driver = tty; ++ return 0; ++ ++err_tty_register_driver_failed: ++ put_tty_driver(tty); ++err_alloc_tty_driver_failed: ++ kfree(sbsa_tty); ++ sbsa_tty = NULL; ++err_alloc_sbsa_tty_failed: ++ return ret; ++} ++ ++static void sbsa_tty_delete_driver(void) ++{ ++ tty_unregister_driver(sbsa_tty_driver); ++ put_tty_driver(sbsa_tty_driver); ++ sbsa_tty_driver = NULL; ++ kfree(sbsa_tty); ++ sbsa_tty = NULL; ++} ++ ++static int sbsa_tty_probe(struct platform_device *pdev) ++{ ++ struct sbsa_tty *qtty; ++ int ret = -EINVAL; ++ int i; ++ struct resource *r; ++ struct device *ttydev; ++ void __iomem *base; ++ u32 irq; ++ ++ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (r == NULL) ++ return -EINVAL; ++ ++ base = ioremap(r->start, r->end - r->start); ++ if (base == NULL) ++ pr_err("sbsa_tty: unable to remap base\n"); ++ ++ r = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ if (r == NULL) ++ goto err_unmap; ++ ++ irq = r->start; ++ ++ if (pdev->id > 0) ++ goto err_unmap; ++ ++ ret = sbsa_tty_create_driver(); ++ if (ret) ++ goto err_unmap; ++ ++ qtty = sbsa_tty; ++ spin_lock_init(&qtty->lock); ++ tty_port_init(&qtty->port); ++ qtty->port.ops = &sbsa_port_ops; ++ qtty->base = base; ++ qtty->irq = irq; ++ ++ /* Clear and Mask all IRQs */ ++ writew(0, base + UART011_IMSC); ++ writew(0xFFFF, base + UART011_ICR); ++ ++ ret = request_irq(irq, sbsa_tty_interrupt, IRQF_SHARED, ++ "sbsa_tty", pdev); ++ if (ret) ++ goto err_request_irq_failed; ++ ++ /* Unmask the RX IRQ */ ++ writew(UART011_RXIM | UART011_RTIM, base + UART011_IMSC); ++ ++ ttydev = tty_port_register_device(&qtty->port, sbsa_tty_driver, ++ 0, &pdev->dev); ++ if (IS_ERR(ttydev)) { ++ ret = PTR_ERR(ttydev); ++ goto err_tty_register_device_failed; ++ } ++ ++ strcpy(qtty->console.name, "ttySBSA"); ++ qtty->console.write = sbsa_tty_console_write; ++ qtty->console.device = sbsa_tty_console_device; ++ qtty->console.setup = sbsa_tty_console_setup; ++ qtty->console.flags = CON_PRINTBUFFER; ++ qtty->console.index = pdev->id; ++ register_console(&qtty->console); ++ ++ return 0; ++ ++ tty_unregister_device(sbsa_tty_driver, i); ++err_tty_register_device_failed: ++ free_irq(irq, pdev); ++err_request_irq_failed: ++ sbsa_tty_delete_driver(); ++err_unmap: ++ iounmap(base); ++ return ret; ++} ++ ++static int sbsa_tty_remove(struct platform_device *pdev) ++{ ++ struct sbsa_tty *qtty; ++ ++ qtty = sbsa_tty; ++ unregister_console(&qtty->console); ++ tty_unregister_device(sbsa_tty_driver, pdev->id); ++ iounmap(qtty->base); ++ qtty->base = 0; ++ free_irq(qtty->irq, pdev); ++ sbsa_tty_delete_driver(); ++ return 0; ++} ++ ++static const struct acpi_device_id sbsa_acpi_match[] = { ++ { "ARMH0011", 0 }, ++ { } +}; + -+struct vgic_params { -+ /* vgic type */ -+ enum vgic_type type; -+ /* Physical address of vgic virtual cpu interface */ -+ phys_addr_t vcpu_base; -+ /* Number of list registers */ -+ u32 nr_lr; -+ /* Interrupt number */ -+ unsigned int maint_irq; -+ /* Virtual control interface base address */ -+ void __iomem *vctrl_base; ++static struct platform_driver sbsa_tty_platform_driver = { ++ .probe = sbsa_tty_probe, ++ .remove = sbsa_tty_remove, ++ .driver = { ++ .name = "sbsa_tty", ++ .acpi_match_table = ACPI_PTR(sbsa_acpi_match), ++ } +}; + - struct vgic_dist { - #ifdef CONFIG_KVM_ARM_VGIC - spinlock_t lock; -+ bool in_kernel; - bool ready; ++module_platform_driver(sbsa_tty_platform_driver); ++ ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c +index 57d9df8..e075437 100644 +--- a/drivers/tty/serial/8250/8250_dw.c ++++ b/drivers/tty/serial/8250/8250_dw.c +@@ -313,10 +313,18 @@ static int dw8250_probe_of(struct uart_port *p, + static int dw8250_probe_acpi(struct uart_8250_port *up, + struct dw8250_data *data) + { ++ const struct acpi_device_id *id; + struct uart_port *p = &up->port; - /* Virtual control interface mapping */ -@@ -110,6 +164,29 @@ struct vgic_dist { - #endif + dw8250_setup_port(up); + ++ id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev); ++ if (!id) ++ return -ENODEV; ++ ++ if (!p->uartclk) ++ p->uartclk = (unsigned int)id->driver_data; ++ + p->iotype = UPIO_MEM32; + p->serial_in = dw8250_serial_in32; + p->serial_out = dw8250_serial_out32; +@@ -541,6 +549,7 @@ static const struct acpi_device_id dw8250_acpi_match[] = { + { "INT3435", 0 }, + { "80860F0A", 0 }, + { "8086228A", 0 }, ++ { "APMC0D08", 50000000}, + { }, }; + MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match); +diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c +index c600ccf..10c4775 100644 +--- a/drivers/virtio/virtio_mmio.c ++++ b/drivers/virtio/virtio_mmio.c +@@ -100,8 +100,7 @@ + #include <linux/virtio_config.h> + #include <linux/virtio_mmio.h> + #include <linux/virtio_ring.h> +- +- ++#include <linux/acpi.h> + + /* The alignment to use between consumer and producer parts of vring. + * Currently hardcoded to the page size. */ +@@ -637,6 +636,14 @@ static struct of_device_id virtio_mmio_match[] = { + }; + MODULE_DEVICE_TABLE(of, virtio_mmio_match); -+struct vgic_v2_cpu_if { -+ u32 vgic_hcr; -+ u32 vgic_vmcr; -+ u32 vgic_misr; /* Saved only */ -+ u32 vgic_eisr[2]; /* Saved only */ -+ u32 vgic_elrsr[2]; /* Saved only */ -+ u32 vgic_apr; -+ u32 vgic_lr[VGIC_V2_MAX_LRS]; ++#ifdef CONFIG_ACPI ++static const struct acpi_device_id virtio_mmio_acpi_match[] = { ++ { "LNRO0005", }, ++ { } +}; ++MODULE_DEVICE_TABLE(acpi, virtio_mmio_acpi_match); ++#endif + -+struct vgic_v3_cpu_if { -+#ifdef CONFIG_ARM_GIC_V3 -+ u32 vgic_hcr; -+ u32 vgic_vmcr; -+ u32 vgic_misr; /* Saved only */ -+ u32 vgic_eisr; /* Saved only */ -+ u32 vgic_elrsr; /* Saved only */ -+ u32 vgic_ap0r[4]; -+ u32 vgic_ap1r[4]; -+ u64 vgic_lr[VGIC_V3_MAX_LRS]; + static struct platform_driver virtio_mmio_driver = { + .probe = virtio_mmio_probe, + .remove = virtio_mmio_remove, +@@ -644,6 +651,7 @@ static struct platform_driver virtio_mmio_driver = { + .name = "virtio-mmio", + .owner = THIS_MODULE, + .of_match_table = virtio_mmio_match, ++ .acpi_match_table = ACPI_PTR(virtio_mmio_acpi_match), + }, + }; + +diff --git a/include/acpi/acnames.h b/include/acpi/acnames.h +index c728113..f97804b 100644 +--- a/include/acpi/acnames.h ++++ b/include/acpi/acnames.h +@@ -59,6 +59,10 @@ + #define METHOD_NAME__PRS "_PRS" + #define METHOD_NAME__PRT "_PRT" + #define METHOD_NAME__PRW "_PRW" ++#define METHOD_NAME__PS0 "_PS0" ++#define METHOD_NAME__PS1 "_PS1" ++#define METHOD_NAME__PS2 "_PS2" ++#define METHOD_NAME__PS3 "_PS3" + #define METHOD_NAME__REG "_REG" + #define METHOD_NAME__SB_ "_SB_" + #define METHOD_NAME__SEG "_SEG" +diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h +index 57ee052..a483e61 100644 +--- a/include/acpi/acpi_bus.h ++++ b/include/acpi/acpi_bus.h +@@ -68,6 +68,8 @@ bool acpi_check_dsm(acpi_handle handle, const u8 *uuid, int rev, u64 funcs); + union acpi_object *acpi_evaluate_dsm(acpi_handle handle, const u8 *uuid, + int rev, int func, union acpi_object *argv4); + ++acpi_status acpi_check_coherency(acpi_handle handle, int *val); ++ + static inline union acpi_object * + acpi_evaluate_dsm_typed(acpi_handle handle, const u8 *uuid, int rev, int func, + union acpi_object *argv4, acpi_object_type type) +diff --git a/include/acpi/acpi_io.h b/include/acpi/acpi_io.h +index 444671e..9d573db 100644 +--- a/include/acpi/acpi_io.h ++++ b/include/acpi/acpi_io.h +@@ -1,11 +1,17 @@ + #ifndef _ACPI_IO_H_ + #define _ACPI_IO_H_ + ++#include <linux/mm.h> + #include <linux/io.h> + + static inline void __iomem *acpi_os_ioremap(acpi_physical_address phys, + acpi_size size) + { ++#ifdef CONFIG_ARM64 ++ if (!page_is_ram(phys >> PAGE_SHIFT)) ++ return ioremap(phys, size); +#endif -+}; + - struct vgic_cpu { - #ifdef CONFIG_KVM_ARM_VGIC - /* per IRQ to LR mapping */ -@@ -120,24 +197,24 @@ struct vgic_cpu { - DECLARE_BITMAP( pending_shared, VGIC_NR_SHARED_IRQS); - - /* Bitmap of used/free list registers */ -- DECLARE_BITMAP( lr_used, VGIC_MAX_LRS); -+ DECLARE_BITMAP( lr_used, VGIC_V2_MAX_LRS); - - /* Number of list registers on this CPU */ - int nr_lr; - - /* CPU vif control registers for world switch */ -- u32 vgic_hcr; -- u32 vgic_vmcr; -- u32 vgic_misr; /* Saved only */ -- u32 vgic_eisr[2]; /* Saved only */ -- u32 vgic_elrsr[2]; /* Saved only */ -- u32 vgic_apr; -- u32 vgic_lr[VGIC_MAX_LRS]; -+ union { -+ struct vgic_v2_cpu_if vgic_v2; -+ struct vgic_v3_cpu_if vgic_v3; -+ }; - #endif + return ioremap_cache(phys, size); + } + +diff --git a/include/acpi/acpixf.h b/include/acpi/acpixf.h +index b7c89d4..dc9d037 100644 +--- a/include/acpi/acpixf.h ++++ b/include/acpi/acpixf.h +@@ -46,7 +46,7 @@ + + /* Current ACPICA subsystem version in YYYYMMDD format */ + +-#define ACPI_CA_VERSION 0x20140724 ++#define ACPI_CA_VERSION 0x20140828 + + #include <acpi/acconfig.h> + #include <acpi/actypes.h> +diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h +index 7626bfe..29e7937 100644 +--- a/include/acpi/actbl1.h ++++ b/include/acpi/actbl1.h +@@ -952,7 +952,8 @@ enum acpi_srat_type { + ACPI_SRAT_TYPE_CPU_AFFINITY = 0, + ACPI_SRAT_TYPE_MEMORY_AFFINITY = 1, + ACPI_SRAT_TYPE_X2APIC_CPU_AFFINITY = 2, +- ACPI_SRAT_TYPE_RESERVED = 3 /* 3 and greater are reserved */ ++ ACPI_SRAT_TYPE_GICC_AFFINITY = 3, ++ ACPI_SRAT_TYPE_RESERVED = 4 /* 4 and greater are reserved */ }; - #define LR_EMPTY 0xff + /* +@@ -968,7 +969,7 @@ struct acpi_srat_cpu_affinity { + u32 flags; + u8 local_sapic_eid; + u8 proximity_domain_hi[3]; +- u32 reserved; /* Reserved, must be zero */ ++ u32 clock_domain; + }; -+#define INT_STATUS_EOI (1 << 0) -+#define INT_STATUS_UNDERFLOW (1 << 1) + /* Flags */ +@@ -1010,6 +1011,20 @@ struct acpi_srat_x2apic_cpu_affinity { + + #define ACPI_SRAT_CPU_ENABLED (1) /* 00: Use affinity structure */ + ++/* 3: GICC Affinity (ACPI 5.1) */ ++ ++struct acpi_srat_gicc_affinity { ++ struct acpi_subtable_header header; ++ u32 proximity_domain; ++ u32 acpi_processor_uid; ++ u32 flags; ++ u32 clock_domain; ++}; ++ ++/* Flags for struct acpi_srat_gicc_affinity */ + - struct kvm; - struct kvm_vcpu; - struct kvm_run; -@@ -157,9 +234,25 @@ int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu); - bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run, - struct kvm_exit_mmio *mmio); ++#define ACPI_SRAT_GICC_ENABLED (1) /* 00: Use affinity structure */ ++ + /* Reset to default packing */ --#define irqchip_in_kernel(k) (!!((k)->arch.vgic.vctrl_base)) -+#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel)) - #define vgic_initialized(k) ((k)->arch.vgic.ready) + #pragma pack() +diff --git a/include/acpi/actbl3.h b/include/acpi/actbl3.h +index 787bcc8..5480cb2 100644 +--- a/include/acpi/actbl3.h ++++ b/include/acpi/actbl3.h +@@ -310,10 +310,15 @@ struct acpi_gtdt_timer_entry { + u32 common_flags; + }; -+int vgic_v2_probe(struct device_node *vgic_node, -+ const struct vgic_ops **ops, -+ const struct vgic_params **params); -+#ifdef CONFIG_ARM_GIC_V3 -+int vgic_v3_probe(struct device_node *vgic_node, -+ const struct vgic_ops **ops, -+ const struct vgic_params **params); -+#else -+static inline int vgic_v3_probe(struct device_node *vgic_node, -+ const struct vgic_ops **ops, -+ const struct vgic_params **params) -+{ -+ return -ENODEV; -+} -+#endif ++/* Flag Definitions: timer_flags and virtual_timer_flags above */ + - #else - static inline int kvm_vgic_hyp_init(void) - { -diff --git a/include/linux/efi.h b/include/linux/efi.h -index 41bbf8b..b3fac7c 100644 ---- a/include/linux/efi.h -+++ b/include/linux/efi.h -@@ -20,6 +20,7 @@ - #include <linux/ioport.h> - #include <linux/pfn.h> - #include <linux/pstore.h> -+#include <linux/reboot.h> ++#define ACPI_GTDT_GT_IRQ_MODE (1) ++#define ACPI_GTDT_GT_IRQ_POLARITY (1<<1) ++ + /* Flag Definitions: common_flags above */ - #include <asm/page.h> +-#define ACPI_GTDT_GT_IS_SECURE_TIMER (1) +-#define ACPI_GTDT_GT_ALWAYS_ON (1<<1) ++#define ACPI_GTDT_GT_IS_SECURE_TIMER (1) ++#define ACPI_GTDT_GT_ALWAYS_ON (1<<1) -@@ -875,6 +876,9 @@ extern void efi_reserve_boot_services(void); - extern int efi_get_fdt_params(struct efi_fdt_params *params, int verbose); - extern struct efi_memory_map memmap; + /* 1: SBSA Generic Watchdog Structure */ -+extern int efi_reboot_quirk_mode; -+extern bool efi_poweroff_required(void); -+ - /* Iterate through an efi_memory_map */ - #define for_each_efi_memory_desc(m, md) \ - for ((md) = (m)->map; \ -@@ -926,11 +930,14 @@ static inline bool efi_enabled(int feature) +diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h +index 975e1cc..2e2161b 100644 +--- a/include/asm-generic/io.h ++++ b/include/asm-generic/io.h +@@ -331,7 +331,7 @@ static inline void iounmap(void __iomem *addr) + #ifndef CONFIG_GENERIC_IOMAP + static inline void __iomem *ioport_map(unsigned long port, unsigned int nr) { - return test_bit(feature, &efi.flags) != 0; +- return (void __iomem *) port; ++ return (void __iomem *)(PCI_IOBASE + (port & IO_SPACE_LIMIT)); } -+extern void efi_reboot(enum reboot_mode reboot_mode, const char *__unused); + + static inline void ioport_unmap(void __iomem *p) +diff --git a/include/asm-generic/pgtable.h b/include/asm-generic/pgtable.h +index 53b2acc..977e545 100644 +--- a/include/asm-generic/pgtable.h ++++ b/include/asm-generic/pgtable.h +@@ -249,6 +249,10 @@ static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) + #define pgprot_writecombine pgprot_noncached + #endif + ++#ifndef pgprot_device ++#define pgprot_device pgprot_noncached ++#endif ++ + /* + * When walking page tables, get the address of the next boundary, + * or the end address of the range if that comes earlier. Although no +diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h +index 35b0c12..d98e96b 100644 +--- a/include/kvm/arm_vgic.h ++++ b/include/kvm/arm_vgic.h +@@ -237,17 +237,19 @@ bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run, + #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel)) + #define vgic_initialized(k) ((k)->arch.vgic.ready) + +-int vgic_v2_probe(struct device_node *vgic_node, +- const struct vgic_ops **ops, +- const struct vgic_params **params); ++int vgic_v2_dt_probe(struct device_node *vgic_node, ++ const struct vgic_ops **ops, ++ const struct vgic_params **params); ++int vgic_v2_acpi_probe(const struct vgic_ops **ops, ++ const struct vgic_params **params); + #ifdef CONFIG_ARM_GIC_V3 +-int vgic_v3_probe(struct device_node *vgic_node, +- const struct vgic_ops **ops, +- const struct vgic_params **params); ++int vgic_v3_dt_probe(struct device_node *vgic_node, ++ const struct vgic_ops **ops, ++ const struct vgic_params **params); #else - static inline bool efi_enabled(int feature) +-static inline int vgic_v3_probe(struct device_node *vgic_node, +- const struct vgic_ops **ops, +- const struct vgic_params **params) ++static inline int vgic_v3_dt_probe(struct device_node *vgic_node, ++ const struct vgic_ops **ops, ++ const struct vgic_params **params) { - return false; + return -ENODEV; } -+static inline void -+efi_reboot(enum reboot_mode reboot_mode, const char *__unused) {} +diff --git a/include/linux/acpi.h b/include/linux/acpi.h +index 807cbc4..4615eb1 100644 +--- a/include/linux/acpi.h ++++ b/include/linux/acpi.h +@@ -71,6 +71,7 @@ enum acpi_irq_model_id { + ACPI_IRQ_MODEL_IOAPIC, + ACPI_IRQ_MODEL_IOSAPIC, + ACPI_IRQ_MODEL_PLATFORM, ++ ACPI_IRQ_MODEL_GIC, + ACPI_IRQ_MODEL_COUNT + }; + +@@ -123,6 +124,10 @@ int acpi_numa_init (void); + + int acpi_table_init (void); + int acpi_table_parse(char *id, acpi_tbl_table_handler handler); ++int __init acpi_parse_entries(unsigned long table_size, ++ acpi_tbl_entry_handler handler, ++ struct acpi_table_header *table_header, ++ int entry_id, unsigned int max_entries); + int __init acpi_table_parse_entries(char *id, unsigned long table_size, + int entry_id, + acpi_tbl_entry_handler handler, +diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h +index 653f0e2..5839f98 100644 +--- a/include/linux/clocksource.h ++++ b/include/linux/clocksource.h +@@ -346,4 +346,10 @@ extern void clocksource_of_init(void); + static inline void clocksource_of_init(void) {} #endif - /* -diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h ++#ifdef CONFIG_ACPI ++void acpi_generic_timer_init(void); ++#else ++static inline void acpi_generic_timer_init(void) {} ++#endif ++ + #endif /* _LINUX_CLOCKSOURCE_H */ +diff --git a/include/linux/irqchip/arm-gic-acpi.h b/include/linux/irqchip/arm-gic-acpi.h new file mode 100644 -index 0000000..30cb755 +index 0000000..ad5b577 --- /dev/null -+++ b/include/linux/irqchip/arm-gic-v3.h -@@ -0,0 +1,198 @@ ++++ b/include/linux/irqchip/arm-gic-acpi.h +@@ -0,0 +1,31 @@ +/* -+ * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. -+ * Author: Marc Zyngier <marc.zyngier@arm.com> -+ * ++ * Copyright (C) 2014, Linaro Ltd. ++ * Author: Tomasz Nowicki <tomasz.nowicki@linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+#ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H -+#define __LINUX_IRQCHIP_ARM_GIC_V3_H -+ -+/* -+ * Distributor registers. We assume we're running non-secure, with ARE -+ * being set. Secure-only and non-ARE registers are not described. -+ */ -+#define GICD_CTLR 0x0000 -+#define GICD_TYPER 0x0004 -+#define GICD_IIDR 0x0008 -+#define GICD_STATUSR 0x0010 -+#define GICD_SETSPI_NSR 0x0040 -+#define GICD_CLRSPI_NSR 0x0048 -+#define GICD_SETSPI_SR 0x0050 -+#define GICD_CLRSPI_SR 0x0058 -+#define GICD_SEIR 0x0068 -+#define GICD_ISENABLER 0x0100 -+#define GICD_ICENABLER 0x0180 -+#define GICD_ISPENDR 0x0200 -+#define GICD_ICPENDR 0x0280 -+#define GICD_ISACTIVER 0x0300 -+#define GICD_ICACTIVER 0x0380 -+#define GICD_IPRIORITYR 0x0400 -+#define GICD_ICFGR 0x0C00 -+#define GICD_IROUTER 0x6000 -+#define GICD_PIDR2 0xFFE8 -+ -+#define GICD_CTLR_RWP (1U << 31) -+#define GICD_CTLR_ARE_NS (1U << 4) -+#define GICD_CTLR_ENABLE_G1A (1U << 1) -+#define GICD_CTLR_ENABLE_G1 (1U << 0) -+ -+#define GICD_IROUTER_SPI_MODE_ONE (0U << 31) -+#define GICD_IROUTER_SPI_MODE_ANY (1U << 31) -+ -+#define GIC_PIDR2_ARCH_MASK 0xf0 -+#define GIC_PIDR2_ARCH_GICv3 0x30 -+#define GIC_PIDR2_ARCH_GICv4 0x40 -+ -+/* -+ * Re-Distributor registers, offsets from RD_base + */ -+#define GICR_CTLR GICD_CTLR -+#define GICR_IIDR 0x0004 -+#define GICR_TYPER 0x0008 -+#define GICR_STATUSR GICD_STATUSR -+#define GICR_WAKER 0x0014 -+#define GICR_SETLPIR 0x0040 -+#define GICR_CLRLPIR 0x0048 -+#define GICR_SEIR GICD_SEIR -+#define GICR_PROPBASER 0x0070 -+#define GICR_PENDBASER 0x0078 -+#define GICR_INVLPIR 0x00A0 -+#define GICR_INVALLR 0x00B0 -+#define GICR_SYNCR 0x00C0 -+#define GICR_MOVLPIR 0x0100 -+#define GICR_MOVALLR 0x0110 -+#define GICR_PIDR2 GICD_PIDR2 -+ -+#define GICR_WAKER_ProcessorSleep (1U << 1) -+#define GICR_WAKER_ChildrenAsleep (1U << 2) + -+/* -+ * Re-Distributor registers, offsets from SGI_base -+ */ -+#define GICR_ISENABLER0 GICD_ISENABLER -+#define GICR_ICENABLER0 GICD_ICENABLER -+#define GICR_ISPENDR0 GICD_ISPENDR -+#define GICR_ICPENDR0 GICD_ICPENDR -+#define GICR_ISACTIVER0 GICD_ISACTIVER -+#define GICR_ICACTIVER0 GICD_ICACTIVER -+#define GICR_IPRIORITYR0 GICD_IPRIORITYR -+#define GICR_ICFGR0 GICD_ICFGR -+ -+#define GICR_TYPER_VLPIS (1U << 1) -+#define GICR_TYPER_LAST (1U << 4) ++#ifndef ARM_GIC_ACPI_H_ ++#define ARM_GIC_ACPI_H_ + -+/* -+ * CPU interface registers -+ */ -+#define ICC_CTLR_EL1_EOImode_drop_dir (0U << 1) -+#define ICC_CTLR_EL1_EOImode_drop (1U << 1) -+#define ICC_SRE_EL1_SRE (1U << 0) ++#ifdef CONFIG_ACPI + +/* -+ * Hypervisor interface registers (SRE only) ++ * Hard code here, we can not get memory size from MADT (but FDT does), ++ * Actually no need to do that, because this size can be inferred ++ * from GIC spec. + */ -+#define ICH_LR_VIRTUAL_ID_MASK ((1UL << 32) - 1) -+ -+#define ICH_LR_EOI (1UL << 41) -+#define ICH_LR_GROUP (1UL << 60) -+#define ICH_LR_STATE (3UL << 62) -+#define ICH_LR_PENDING_BIT (1UL << 62) -+#define ICH_LR_ACTIVE_BIT (1UL << 63) -+ -+#define ICH_MISR_EOI (1 << 0) -+#define ICH_MISR_U (1 << 1) ++#define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K) ++#define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K) + -+#define ICH_HCR_EN (1 << 0) -+#define ICH_HCR_UIE (1 << 1) -+ -+#define ICH_VMCR_CTLR_SHIFT 0 -+#define ICH_VMCR_CTLR_MASK (0x21f << ICH_VMCR_CTLR_SHIFT) -+#define ICH_VMCR_BPR1_SHIFT 18 -+#define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT) -+#define ICH_VMCR_BPR0_SHIFT 21 -+#define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT) -+#define ICH_VMCR_PMR_SHIFT 24 -+#define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT) -+ -+#define ICC_EOIR1_EL1 S3_0_C12_C12_1 -+#define ICC_IAR1_EL1 S3_0_C12_C12_0 -+#define ICC_SGI1R_EL1 S3_0_C12_C11_5 -+#define ICC_PMR_EL1 S3_0_C4_C6_0 -+#define ICC_CTLR_EL1 S3_0_C12_C12_4 -+#define ICC_SRE_EL1 S3_0_C12_C12_5 -+#define ICC_GRPEN1_EL1 S3_0_C12_C12_7 -+ -+#define ICC_IAR1_EL1_SPURIOUS 0x3ff -+ -+#define ICC_SRE_EL2 S3_4_C12_C9_5 -+ -+#define ICC_SRE_EL2_SRE (1 << 0) -+#define ICC_SRE_EL2_ENABLE (1 << 3) -+ -+/* -+ * System register definitions -+ */ -+#define ICH_VSEIR_EL2 S3_4_C12_C9_4 -+#define ICH_HCR_EL2 S3_4_C12_C11_0 -+#define ICH_VTR_EL2 S3_4_C12_C11_1 -+#define ICH_MISR_EL2 S3_4_C12_C11_2 -+#define ICH_EISR_EL2 S3_4_C12_C11_3 -+#define ICH_ELSR_EL2 S3_4_C12_C11_5 -+#define ICH_VMCR_EL2 S3_4_C12_C11_7 -+ -+#define __LR0_EL2(x) S3_4_C12_C12_ ## x -+#define __LR8_EL2(x) S3_4_C12_C13_ ## x -+ -+#define ICH_LR0_EL2 __LR0_EL2(0) -+#define ICH_LR1_EL2 __LR0_EL2(1) -+#define ICH_LR2_EL2 __LR0_EL2(2) -+#define ICH_LR3_EL2 __LR0_EL2(3) -+#define ICH_LR4_EL2 __LR0_EL2(4) -+#define ICH_LR5_EL2 __LR0_EL2(5) -+#define ICH_LR6_EL2 __LR0_EL2(6) -+#define ICH_LR7_EL2 __LR0_EL2(7) -+#define ICH_LR8_EL2 __LR8_EL2(0) -+#define ICH_LR9_EL2 __LR8_EL2(1) -+#define ICH_LR10_EL2 __LR8_EL2(2) -+#define ICH_LR11_EL2 __LR8_EL2(3) -+#define ICH_LR12_EL2 __LR8_EL2(4) -+#define ICH_LR13_EL2 __LR8_EL2(5) -+#define ICH_LR14_EL2 __LR8_EL2(6) -+#define ICH_LR15_EL2 __LR8_EL2(7) -+ -+#define __AP0Rx_EL2(x) S3_4_C12_C8_ ## x -+#define ICH_AP0R0_EL2 __AP0Rx_EL2(0) -+#define ICH_AP0R1_EL2 __AP0Rx_EL2(1) -+#define ICH_AP0R2_EL2 __AP0Rx_EL2(2) -+#define ICH_AP0R3_EL2 __AP0Rx_EL2(3) -+ -+#define __AP1Rx_EL2(x) S3_4_C12_C9_ ## x -+#define ICH_AP1R0_EL2 __AP1Rx_EL2(0) -+#define ICH_AP1R1_EL2 __AP1Rx_EL2(1) -+#define ICH_AP1R2_EL2 __AP1Rx_EL2(2) -+#define ICH_AP1R3_EL2 __AP1Rx_EL2(3) -+ -+#ifndef __ASSEMBLY__ -+ -+#include <linux/stringify.h> -+ -+static inline void gic_write_eoir(u64 irq) -+{ -+ asm volatile("msr " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" (irq)); -+ isb(); -+} ++struct acpi_table_header; + ++void acpi_gic_init(void); ++int gic_v2_acpi_init(struct acpi_table_header *table); ++#else ++static inline void acpi_gic_init(void) { } +#endif + -+#endif ++#endif /* ARM_GIC_ACPI_H_ */ +diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h +index 45e2d8c..2b0f246 100644 +--- a/include/linux/irqchip/arm-gic.h ++++ b/include/linux/irqchip/arm-gic.h +@@ -39,6 +39,8 @@ + #define GIC_DIST_SGI_PENDING_CLEAR 0xf10 + #define GIC_DIST_SGI_PENDING_SET 0xf20 + ++#define GIC_DIST_SOFTINT_NSATT 0x8000 ++ + #define GICH_HCR 0x0 + #define GICH_VTR 0x4 + #define GICH_VMCR 0x8 diff --git a/include/linux/of_address.h b/include/linux/of_address.h -index c13b878..33c0420 100644 +index fb7b722..7ebb877 100644 --- a/include/linux/of_address.h +++ b/include/linux/of_address.h -@@ -23,17 +23,8 @@ struct of_pci_range { +@@ -23,17 +23,6 @@ struct of_pci_range { #define for_each_of_pci_range(parser, range) \ for (; of_pci_range_parser_one(parser, range);) @@ -8963,71 +7497,96 @@ index c13b878..33c0420 100644 - res->name = np->full_name; -} - -+extern int of_pci_range_to_resource(struct of_pci_range *range, -+ struct device_node *np, struct resource *res); /* Translate a DMA address from device space to CPU space */ extern u64 of_translate_dma_address(struct device_node *dev, const __be32 *in_addr); -@@ -55,6 +46,7 @@ extern void __iomem *of_iomap(struct device_node *device, int index); +@@ -55,7 +44,9 @@ extern void __iomem *of_iomap(struct device_node *device, int index); extern const __be32 *of_get_address(struct device_node *dev, int index, u64 *size, unsigned int *flags); +extern int pci_register_io_range(phys_addr_t addr, resource_size_t size); extern unsigned long pci_address_to_pio(phys_addr_t addr); ++extern phys_addr_t pci_pio_to_address(unsigned long pio); extern int of_pci_range_parser_init(struct of_pci_range_parser *parser, + struct device_node *node); +@@ -138,6 +129,9 @@ extern const __be32 *of_get_pci_address(struct device_node *dev, int bar_no, + u64 *size, unsigned int *flags); + extern int of_pci_address_to_resource(struct device_node *dev, int bar, + struct resource *r); ++extern int of_pci_range_to_resource(struct of_pci_range *range, ++ struct device_node *np, ++ struct resource *res); + #else /* CONFIG_OF_ADDRESS && CONFIG_PCI */ + static inline int of_pci_address_to_resource(struct device_node *dev, int bar, + struct resource *r) +@@ -153,4 +147,3 @@ static inline const __be32 *of_get_pci_address(struct device_node *dev, + #endif /* CONFIG_OF_ADDRESS && CONFIG_PCI */ + + #endif /* __OF_ADDRESS_H */ +- diff --git a/include/linux/of_pci.h b/include/linux/of_pci.h -index dde3a4a..71e36d0 100644 +index dde3a4a..1fd207e 100644 --- a/include/linux/of_pci.h +++ b/include/linux/of_pci.h -@@ -15,6 +15,9 @@ struct device_node *of_pci_find_child_device(struct device_node *parent, +@@ -15,6 +15,7 @@ struct device_node *of_pci_find_child_device(struct device_node *parent, int of_pci_get_devfn(struct device_node *np); int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin); int of_pci_parse_bus_range(struct device_node *node, struct resource *res); -+struct pci_host_bridge *of_create_pci_host_bridge(struct device *parent, -+ struct pci_ops *ops, void *host_data); -+ ++int of_get_pci_domain_nr(struct device_node *node); #else static inline int of_irq_parse_pci(const struct pci_dev *pdev, struct of_phandle_args *out_irq) { -@@ -43,6 +46,13 @@ of_pci_parse_bus_range(struct device_node *node, struct resource *res) +@@ -43,6 +44,18 @@ of_pci_parse_bus_range(struct device_node *node, struct resource *res) { return -EINVAL; } + -+static inline struct pci_host_bridge * -+of_create_pci_host_bridge(struct device *parent, struct pci_ops *ops, -+ void *host_data) ++static inline int ++of_get_pci_domain_nr(struct device_node *node) +{ -+ return NULL; ++ return -1; +} ++#endif ++ ++#if defined(CONFIG_OF_ADDRESS) ++int of_pci_get_host_bridge_resources(struct device_node *dev, ++ unsigned char busno, unsigned char bus_max, ++ struct list_head *resources, resource_size_t *io_base); #endif #if defined(CONFIG_OF) && defined(CONFIG_PCI_MSI) diff --git a/include/linux/pci.h b/include/linux/pci.h -index 466bcd1..65fb1fc 100644 +index 96453f9..6d540b9 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h -@@ -401,6 +401,8 @@ struct pci_host_bridge_window { - struct pci_host_bridge { - struct device dev; - struct pci_bus *bus; /* root bus */ -+ int domain_nr; -+ resource_size_t io_base; /* physical address for the start of I/O area */ - struct list_head windows; /* pci_host_bridge_windows */ - void (*release_fn)(struct pci_host_bridge *); - void *release_data; -@@ -769,6 +771,9 @@ struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); - struct pci_bus *pci_create_root_bus(struct device *parent, int bus, - struct pci_ops *ops, void *sysdata, - struct list_head *resources); -+struct pci_bus *pci_create_root_bus_in_domain(struct device *parent, -+ int domain, int bus, struct pci_ops *ops, -+ void *sysdata, struct list_head *resources); - int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); - int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); - void pci_bus_release_busn_res(struct pci_bus *b); -@@ -1095,6 +1100,9 @@ int __must_check pci_bus_alloc_resource(struct pci_bus *bus, +@@ -457,6 +457,9 @@ struct pci_bus { + unsigned char primary; /* number of primary bridge */ + unsigned char max_bus_speed; /* enum pci_bus_speed */ + unsigned char cur_bus_speed; /* enum pci_bus_speed */ ++#ifdef CONFIG_PCI_DOMAINS_GENERIC ++ int domain_nr; ++#endif + + char name[48]; + +@@ -559,15 +562,6 @@ struct pci_ops { + int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); + }; + +-/* +- * ACPI needs to be able to access PCI config space before we've done a +- * PCI bus scan and created pci_bus structures. +- */ +-int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, +- int reg, int len, u32 *val); +-int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, +- int reg, int len, u32 val); +- + struct pci_bus_region { + dma_addr_t start; + dma_addr_t end; +@@ -1103,6 +1097,9 @@ int __must_check pci_bus_alloc_resource(struct pci_bus *bus, resource_size_t), void *alignf_data); @@ -9037,22 +7596,89 @@ index 466bcd1..65fb1fc 100644 static inline dma_addr_t pci_bus_address(struct pci_dev *pdev, int bar) { struct pci_bus_region region; -@@ -1805,8 +1813,15 @@ static inline void pci_set_of_node(struct pci_dev *dev) { } - static inline void pci_release_of_node(struct pci_dev *dev) { } - static inline void pci_set_bus_of_node(struct pci_bus *bus) { } - static inline void pci_release_bus_of_node(struct pci_bus *bus) { } +@@ -1288,17 +1285,47 @@ void pci_cfg_access_unlock(struct pci_dev *dev); + */ + #ifdef CONFIG_PCI_DOMAINS + extern int pci_domains_supported; ++int pci_get_new_domain_nr(void); + #else + enum { pci_domains_supported = 0 }; + static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } + static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } ++static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } + #endif /* CONFIG_PCI_DOMAINS */ + ++/* ++ * Generic implementation for PCI domain support. If your ++ * architecture does not need custom management of PCI ++ * domains then this implementation will be used ++ */ ++#ifdef CONFIG_PCI_DOMAINS_GENERIC ++static inline int pci_domain_nr(struct pci_bus *bus) ++{ ++ return bus->domain_nr; ++} ++void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent); ++#else ++static inline void pci_bus_assign_domain_nr(struct pci_bus *bus, ++ struct device *parent) ++{ ++} ++#endif + - #endif /* CONFIG_OF */ + /* some architectures require additional setup to direct VGA traffic */ + typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, + unsigned int command_bits, u32 flags); + void pci_register_set_vga_state(arch_set_vga_state_t func); -+/* Used by architecture code to apply any quirks to the list of -+ * pci_host_bridge resource ranges before they are being used -+ * by of_create_pci_host_bridge() ++/* ++ * ACPI needs to be able to access PCI config space before we've done a ++ * PCI bus scan and created pci_bus structures. + */ -+extern int pcibios_fixup_bridge_ranges(struct list_head *resources); ++int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, ++ int reg, int len, u32 *val); ++int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, ++ int reg, int len, u32 val); ++void pcibios_penalize_isa_irq(int irq, int active); + - #ifdef CONFIG_EEH - static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) - { + #else /* CONFIG_PCI is not enabled */ + + /* +@@ -1400,8 +1427,26 @@ static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, + unsigned int devfn) + { return NULL; } + ++static inline struct pci_bus *pci_find_bus(int domain, int busnr) ++{ return NULL; } ++ ++static inline int pci_bus_write_config_byte(struct pci_bus *bus, ++ unsigned int devfn, int where, u8 val) ++{ return -ENOSYS; } ++ ++static inline int raw_pci_read(unsigned int domain, unsigned int bus, ++ unsigned int devfn, int reg, int len, u32 *val) ++{ return -ENOSYS; } ++ ++static inline int raw_pci_write(unsigned int domain, unsigned int bus, ++ unsigned int devfn, int reg, int len, u32 val) ++{ return -ENOSYS; } ++ ++static inline void pcibios_penalize_isa_irq(int irq, int active) { } ++ + static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } + static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } ++static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } + + #define dev_is_pci(d) (false) + #define dev_is_pf(d) (false) +@@ -1613,7 +1658,6 @@ int pcibios_set_pcie_reset_state(struct pci_dev *dev, + enum pcie_reset_state state); + int pcibios_add_device(struct pci_dev *dev); + void pcibios_release_device(struct pci_dev *dev); +-void pcibios_penalize_isa_irq(int irq, int active); + + #ifdef CONFIG_HIBERNATE_CALLBACKS + extern struct dev_pm_ops pcibios_pm_ops; diff --git a/tools/perf/arch/arm64/include/perf_regs.h b/tools/perf/arch/arm64/include/perf_regs.h index e9441b9..1d3f39c 100644 --- a/tools/perf/arch/arm64/include/perf_regs.h @@ -9066,1114 +7692,353 @@ index e9441b9..1d3f39c 100644 #define PERF_REG_IP PERF_REG_ARM64_PC #define PERF_REG_SP PERF_REG_ARM64_SP -diff --git a/virt/kvm/arm/vgic-v2.c b/virt/kvm/arm/vgic-v2.c -new file mode 100644 -index 0000000..ff597d8 ---- /dev/null -+++ b/virt/kvm/arm/vgic-v2.c -@@ -0,0 +1,259 @@ -+/* -+ * Copyright (C) 2012,2013 ARM Limited, All Rights Reserved. -+ * Author: Marc Zyngier <marc.zyngier@arm.com> -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+ -+#include <linux/cpu.h> -+#include <linux/kvm.h> -+#include <linux/kvm_host.h> -+#include <linux/interrupt.h> -+#include <linux/io.h> -+#include <linux/of.h> -+#include <linux/of_address.h> -+#include <linux/of_irq.h> -+ -+#include <linux/irqchip/arm-gic.h> -+ -+#include <asm/kvm_emulate.h> -+#include <asm/kvm_arm.h> -+#include <asm/kvm_mmu.h> -+ -+static struct vgic_lr vgic_v2_get_lr(const struct kvm_vcpu *vcpu, int lr) -+{ -+ struct vgic_lr lr_desc; -+ u32 val = vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr]; -+ -+ lr_desc.irq = val & GICH_LR_VIRTUALID; -+ if (lr_desc.irq <= 15) -+ lr_desc.source = (val >> GICH_LR_PHYSID_CPUID_SHIFT) & 0x7; -+ else -+ lr_desc.source = 0; -+ lr_desc.state = 0; -+ -+ if (val & GICH_LR_PENDING_BIT) -+ lr_desc.state |= LR_STATE_PENDING; -+ if (val & GICH_LR_ACTIVE_BIT) -+ lr_desc.state |= LR_STATE_ACTIVE; -+ if (val & GICH_LR_EOI) -+ lr_desc.state |= LR_EOI_INT; -+ -+ return lr_desc; -+} -+ -+static void vgic_v2_set_lr(struct kvm_vcpu *vcpu, int lr, -+ struct vgic_lr lr_desc) -+{ -+ u32 lr_val = (lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT) | lr_desc.irq; -+ -+ if (lr_desc.state & LR_STATE_PENDING) -+ lr_val |= GICH_LR_PENDING_BIT; -+ if (lr_desc.state & LR_STATE_ACTIVE) -+ lr_val |= GICH_LR_ACTIVE_BIT; -+ if (lr_desc.state & LR_EOI_INT) -+ lr_val |= GICH_LR_EOI; -+ -+ vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = lr_val; -+} -+ -+static void vgic_v2_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr, -+ struct vgic_lr lr_desc) -+{ -+ if (!(lr_desc.state & LR_STATE_MASK)) -+ set_bit(lr, (unsigned long *)vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr); -+} -+ -+static u64 vgic_v2_get_elrsr(const struct kvm_vcpu *vcpu) -+{ -+ u64 val; -+ -+ val = vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr[1]; -+ val <<= 32; -+ val |= vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr[0]; -+ -+ return val; -+} -+ -+static u64 vgic_v2_get_eisr(const struct kvm_vcpu *vcpu) -+{ -+ u64 val; -+ -+ val = vcpu->arch.vgic_cpu.vgic_v2.vgic_eisr[1]; -+ val <<= 32; -+ val |= vcpu->arch.vgic_cpu.vgic_v2.vgic_eisr[0]; -+ -+ return val; -+} -+ -+static u32 vgic_v2_get_interrupt_status(const struct kvm_vcpu *vcpu) -+{ -+ u32 misr = vcpu->arch.vgic_cpu.vgic_v2.vgic_misr; -+ u32 ret = 0; -+ -+ if (misr & GICH_MISR_EOI) -+ ret |= INT_STATUS_EOI; -+ if (misr & GICH_MISR_U) -+ ret |= INT_STATUS_UNDERFLOW; -+ -+ return ret; -+} -+ -+static void vgic_v2_enable_underflow(struct kvm_vcpu *vcpu) -+{ -+ vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr |= GICH_HCR_UIE; +diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c +index 22fa819..9cd5dbd 100644 +--- a/virt/kvm/arm/arch_timer.c ++++ b/virt/kvm/arm/arch_timer.c +@@ -21,9 +21,11 @@ + #include <linux/kvm.h> + #include <linux/kvm_host.h> + #include <linux/interrupt.h> ++#include <linux/acpi.h> + + #include <clocksource/arm_arch_timer.h> + #include <asm/arch_timer.h> ++#include <asm/acpi.h> + + #include <kvm/arm_vgic.h> + #include <kvm/arm_arch_timer.h> +@@ -244,60 +246,92 @@ static const struct of_device_id arch_timer_of_match[] = { + {}, + }; + +-int kvm_timer_hyp_init(void) ++static int kvm_timer_ppi_parse_dt(unsigned int *ppi) + { + struct device_node *np; +- unsigned int ppi; +- int err; +- +- timecounter = arch_timer_get_timecounter(); +- if (!timecounter) +- return -ENODEV; + + np = of_find_matching_node(NULL, arch_timer_of_match); + if (!np) { +- kvm_err("kvm_arch_timer: can't find DT node\n"); + return -ENODEV; + } + +- ppi = irq_of_parse_and_map(np, 2); +- if (!ppi) { +- kvm_err("kvm_arch_timer: no virtual timer interrupt\n"); +- err = -EINVAL; +- goto out; ++ *ppi = irq_of_parse_and_map(np, 2); ++ if (*ppi == 0) { ++ of_node_put(np); ++ return -EINVAL; + } + +- err = request_percpu_irq(ppi, kvm_arch_timer_handler, +- "kvm guest timer", kvm_get_running_vcpus()); +- if (err) { +- kvm_err("kvm_arch_timer: can't request interrupt %d (%d)\n", +- ppi, err); +- goto out; +- } ++ return 0; +} -+ -+static void vgic_v2_disable_underflow(struct kvm_vcpu *vcpu) + +- host_vtimer_irq = ppi; ++extern int acadia_kvm_acpi; ++extern int arch_timer_ppi[]; + +- err = __register_cpu_notifier(&kvm_timer_cpu_nb); +- if (err) { +- kvm_err("Cannot register timer CPU notifier\n"); +- goto out_free; +- } ++static int kvm_timer_ppi_parse_acpi(unsigned int *ppi) + +- wqueue = create_singlethread_workqueue("kvm_arch_timer"); +- if (!wqueue) { +- err = -ENOMEM; +- goto out_free; +- } +{ -+ vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr &= ~GICH_HCR_UIE; ++ /* retrieve VIRT_PPI info */ ++ *ppi = arch_timer_ppi[2]; + +- kvm_info("%s IRQ%d\n", np->name, ppi); +- on_each_cpu(kvm_timer_init_interrupt, NULL, 1); ++ if (*ppi == 0) ++ return -EINVAL; ++ else ++ return 0; +} + -+static void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp) ++int kvm_timer_hyp_init(void) +{ -+ u32 vmcr = vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr; ++ unsigned int ppi; ++ int err; + -+ vmcrp->ctlr = (vmcr & GICH_VMCR_CTRL_MASK) >> GICH_VMCR_CTRL_SHIFT; -+ vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >> GICH_VMCR_ALIAS_BINPOINT_SHIFT; -+ vmcrp->bpr = (vmcr & GICH_VMCR_BINPOINT_MASK) >> GICH_VMCR_BINPOINT_SHIFT; -+ vmcrp->pmr = (vmcr & GICH_VMCR_PRIMASK_MASK) >> GICH_VMCR_PRIMASK_SHIFT; -+} ++ timecounter = arch_timer_get_timecounter(); ++ if (!timecounter) ++ return -ENODEV; + -+static void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp) -+{ -+ u32 vmcr; ++ /* PPI DT parsing */ ++ err = kvm_timer_ppi_parse_dt(&ppi); + +- goto out; ++ /* if DT parsing fails, try ACPI next */ ++ if (err && !acpi_disabled && acadia_kvm_acpi ) ++ err = kvm_timer_ppi_parse_acpi(&ppi); + -+ vmcr = (vmcrp->ctlr << GICH_VMCR_CTRL_SHIFT) & GICH_VMCR_CTRL_MASK; -+ vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) & GICH_VMCR_ALIAS_BINPOINT_MASK; -+ vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) & GICH_VMCR_BINPOINT_MASK; -+ vmcr |= (vmcrp->pmr << GICH_VMCR_PRIMASK_SHIFT) & GICH_VMCR_PRIMASK_MASK; ++ if (err) { ++ kvm_err("kvm_timer_hyp_init: can't find virtual timer info or " ++ "config virtual timer interrupt\n"); ++ return err; ++ } + -+ vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = vmcr; -+} ++ /* configure IRQ handler */ ++ err = request_percpu_irq(ppi, kvm_arch_timer_handler, ++ "kvm guest timer", kvm_get_running_vcpus()); ++ if (err) { ++ kvm_err("kvm_arch_timer: can't request interrupt %d (%d)\n", ++ ppi, err); ++ goto out; ++ } ++ ++ host_vtimer_irq = ppi; ++ ++ err = __register_cpu_notifier(&kvm_timer_cpu_nb); ++ if (err) { ++ kvm_err("Cannot register timer CPU notifier\n"); ++ goto out_free; ++ } ++ ++ wqueue = create_singlethread_workqueue("kvm_arch_timer"); ++ if (!wqueue) { ++ err = -ENOMEM; ++ goto out_free; ++ } ++ ++ kvm_info("timer IRQ%d\n", ppi); ++ on_each_cpu(kvm_timer_init_interrupt, NULL, 1); ++ ++ goto out; + out_free: +- free_percpu_irq(ppi, kvm_get_running_vcpus()); ++ free_percpu_irq(ppi, kvm_get_running_vcpus()); + out: +- of_node_put(np); +- return err; ++ return err; + } + + void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu) +diff --git a/virt/kvm/arm/vgic-v2.c b/virt/kvm/arm/vgic-v2.c +index 416baed..53bdd33 100644 +--- a/virt/kvm/arm/vgic-v2.c ++++ b/virt/kvm/arm/vgic-v2.c +@@ -19,6 +19,7 @@ + #include <linux/kvm.h> + #include <linux/kvm_host.h> + #include <linux/interrupt.h> ++#include <linux/acpi.h> + #include <linux/io.h> + #include <linux/of.h> + #include <linux/of_address.h> +@@ -26,6 +27,7 @@ + + #include <linux/irqchip/arm-gic.h> + ++#include <asm/acpi.h> + #include <asm/kvm_emulate.h> + #include <asm/kvm_arm.h> + #include <asm/kvm_mmu.h> +@@ -177,7 +179,7 @@ static const struct vgic_ops vgic_v2_ops = { + static struct vgic_params vgic_v2_params; + + /** +- * vgic_v2_probe - probe for a GICv2 compatible interrupt controller in DT ++ * vgic_v2_dt_probe - probe for a GICv2 compatible interrupt controller in DT + * @node: pointer to the DT node + * @ops: address of a pointer to the GICv2 operations + * @params: address of a pointer to HW-specific parameters +@@ -186,7 +188,7 @@ static struct vgic_params vgic_v2_params; + * in *ops and the HW parameters in *params. Returns an error code + * otherwise. + */ +-int vgic_v2_probe(struct device_node *vgic_node, ++int vgic_v2_dt_probe(struct device_node *vgic_node, + const struct vgic_ops **ops, + const struct vgic_params **params) + { +@@ -263,3 +265,72 @@ out: + of_node_put(vgic_node); + return ret; + } + -+static void vgic_v2_enable(struct kvm_vcpu *vcpu) ++struct acpi_madt_generic_interrupt *vgic_acpi; ++static void gic_get_acpi_header(struct acpi_subtable_header *header) +{ -+ /* -+ * By forcing VMCR to zero, the GIC will restore the binary -+ * points to their reset values. Anything else resets to zero -+ * anyway. -+ */ -+ vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0; -+ -+ /* Get the show on the road... */ -+ vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN; ++ vgic_acpi = (struct acpi_madt_generic_interrupt *)header; +} + -+static const struct vgic_ops vgic_v2_ops = { -+ .get_lr = vgic_v2_get_lr, -+ .set_lr = vgic_v2_set_lr, -+ .sync_lr_elrsr = vgic_v2_sync_lr_elrsr, -+ .get_elrsr = vgic_v2_get_elrsr, -+ .get_eisr = vgic_v2_get_eisr, -+ .get_interrupt_status = vgic_v2_get_interrupt_status, -+ .enable_underflow = vgic_v2_enable_underflow, -+ .disable_underflow = vgic_v2_disable_underflow, -+ .get_vmcr = vgic_v2_get_vmcr, -+ .set_vmcr = vgic_v2_set_vmcr, -+ .enable = vgic_v2_enable, -+}; -+ -+static struct vgic_params vgic_v2_params; -+ -+/** -+ * vgic_v2_probe - probe for a GICv2 compatible interrupt controller in DT -+ * @node: pointer to the DT node -+ * @ops: address of a pointer to the GICv2 operations -+ * @params: address of a pointer to HW-specific parameters -+ * -+ * Returns 0 if a GICv2 has been found, with the low level operations -+ * in *ops and the HW parameters in *params. Returns an error code -+ * otherwise. -+ */ -+int vgic_v2_probe(struct device_node *vgic_node, -+ const struct vgic_ops **ops, -+ const struct vgic_params **params) ++int vgic_v2_acpi_probe(const struct vgic_ops **ops, ++ const struct vgic_params **params) +{ -+ int ret; -+ struct resource vctrl_res; -+ struct resource vcpu_res; + struct vgic_params *vgic = &vgic_v2_params; -+ -+ vgic->maint_irq = irq_of_parse_and_map(vgic_node, 0); -+ if (!vgic->maint_irq) { -+ kvm_err("error getting vgic maintenance irq from DT\n"); -+ ret = -ENXIO; ++ int irq_mode, ret; ++ ++ /* MADT table */ ++ ret = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, ++ (acpi_tbl_entry_handler)gic_get_acpi_header, 0); ++ if (!ret) { ++ pr_err("Failed to get MADT VGIC CPU entry\n"); ++ ret = -ENODEV; + goto out; + } + -+ ret = of_address_to_resource(vgic_node, 2, &vctrl_res); -+ if (ret) { -+ kvm_err("Cannot obtain GICH resource\n"); ++ /* IRQ trigger mode */ ++ irq_mode = (vgic_acpi->flags & ACPI_MADT_VGIC_IRQ_MODE) ? ++ ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; ++ /* According to GIC-400 manual, all PPIs are active-LOW, level ++ * sensative. We register IRQ as active-low. ++ */ ++ vgic->maint_irq = acpi_register_gsi(NULL, vgic_acpi->vgic_interrupt, ++ irq_mode, ACPI_ACTIVE_LOW); ++ if (!vgic->maint_irq) { ++ pr_err("Cannot register VGIC ACPI maintenance irq\n"); ++ ret = -ENXIO; + goto out; + } + -+ vgic->vctrl_base = of_iomap(vgic_node, 2); ++ /* GICH resource */ ++ vgic->vctrl_base = ioremap(vgic_acpi->gich_base_address, SZ_8K); + if (!vgic->vctrl_base) { -+ kvm_err("Cannot ioremap GICH\n"); ++ pr_err("cannot ioremap GICH memory\n"); + ret = -ENOMEM; + goto out; + } + -+ vgic->nr_lr = readl_relaxed(vgic->vctrl_base + GICH_VTR); -+ vgic->nr_lr = (vgic->nr_lr & 0x3f) + 1; -+ -+ ret = create_hyp_io_mappings(vgic->vctrl_base, -+ vgic->vctrl_base + resource_size(&vctrl_res), -+ vctrl_res.start); -+ if (ret) { -+ kvm_err("Cannot map VCTRL into hyp\n"); -+ goto out_unmap; -+ } -+ -+ if (of_address_to_resource(vgic_node, 3, &vcpu_res)) { -+ kvm_err("Cannot obtain GICV resource\n"); -+ ret = -ENXIO; -+ goto out_unmap; -+ } -+ -+ if (!PAGE_ALIGNED(vcpu_res.start)) { -+ kvm_err("GICV physical address 0x%llx not page aligned\n", -+ (unsigned long long)vcpu_res.start); -+ ret = -ENXIO; -+ goto out_unmap; -+ } ++ vgic->nr_lr = readl_relaxed(vgic->vctrl_base + GICH_VTR); ++ vgic->nr_lr = (vgic->nr_lr & 0x3f) + 1; + -+ if (!PAGE_ALIGNED(resource_size(&vcpu_res))) { -+ kvm_err("GICV size 0x%llx not a multiple of page size 0x%lx\n", -+ (unsigned long long)resource_size(&vcpu_res), -+ PAGE_SIZE); -+ ret = -ENXIO; -+ goto out_unmap; -+ } ++ ret = create_hyp_io_mappings(vgic->vctrl_base, ++ vgic->vctrl_base + SZ_8K, ++ vgic_acpi->gich_base_address); ++ if (ret) { ++ kvm_err("Cannot map GICH into hyp\n"); ++ goto out; ++ } + -+ vgic->vcpu_base = vcpu_res.start; ++ vgic->vcpu_base = vgic_acpi->gicv_base_address; + -+ kvm_info("%s@%llx IRQ%d\n", vgic_node->name, -+ vgic->vctrl_base, vgic->maint_irq); ++ kvm_info("GICH base=0x%llx, GICV base=0x%llx, IRQ=%d\n", ++ (unsigned long long)vgic_acpi->gich_base_address, ++ (unsigned long long)vgic_acpi->gicv_base_address, ++ vgic->maint_irq); + + vgic->type = VGIC_V2; + *ops = &vgic_v2_ops; + *params = vgic; -+ goto out; + -+out_unmap: -+ iounmap(vgic->vctrl_base); +out: -+ of_node_put(vgic_node); + return ret; +} diff --git a/virt/kvm/arm/vgic-v3.c b/virt/kvm/arm/vgic-v3.c -new file mode 100644 -index 0000000..f01d446 ---- /dev/null +index 1c2c8ee..8b56920 100644 +--- a/virt/kvm/arm/vgic-v3.c +++ b/virt/kvm/arm/vgic-v3.c -@@ -0,0 +1,231 @@ -+/* -+ * Copyright (C) 2013 ARM Limited, All Rights Reserved. -+ * Author: Marc Zyngier <marc.zyngier@arm.com> -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+ -+#include <linux/cpu.h> -+#include <linux/kvm.h> -+#include <linux/kvm_host.h> -+#include <linux/interrupt.h> -+#include <linux/io.h> -+#include <linux/of.h> -+#include <linux/of_address.h> -+#include <linux/of_irq.h> -+ -+#include <linux/irqchip/arm-gic-v3.h> -+ -+#include <asm/kvm_emulate.h> -+#include <asm/kvm_arm.h> -+#include <asm/kvm_mmu.h> -+ -+/* These are for GICv2 emulation only */ -+#define GICH_LR_VIRTUALID (0x3ffUL << 0) -+#define GICH_LR_PHYSID_CPUID_SHIFT (10) -+#define GICH_LR_PHYSID_CPUID (7UL << GICH_LR_PHYSID_CPUID_SHIFT) -+ -+/* -+ * LRs are stored in reverse order in memory. make sure we index them -+ * correctly. -+ */ -+#define LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr) -+ -+static u32 ich_vtr_el2; -+ -+static struct vgic_lr vgic_v3_get_lr(const struct kvm_vcpu *vcpu, int lr) -+{ -+ struct vgic_lr lr_desc; -+ u64 val = vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[LR_INDEX(lr)]; -+ -+ lr_desc.irq = val & GICH_LR_VIRTUALID; -+ if (lr_desc.irq <= 15) -+ lr_desc.source = (val >> GICH_LR_PHYSID_CPUID_SHIFT) & 0x7; -+ else -+ lr_desc.source = 0; -+ lr_desc.state = 0; -+ -+ if (val & ICH_LR_PENDING_BIT) -+ lr_desc.state |= LR_STATE_PENDING; -+ if (val & ICH_LR_ACTIVE_BIT) -+ lr_desc.state |= LR_STATE_ACTIVE; -+ if (val & ICH_LR_EOI) -+ lr_desc.state |= LR_EOI_INT; -+ -+ return lr_desc; -+} -+ -+static void vgic_v3_set_lr(struct kvm_vcpu *vcpu, int lr, -+ struct vgic_lr lr_desc) -+{ -+ u64 lr_val = (((u32)lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT) | -+ lr_desc.irq); -+ -+ if (lr_desc.state & LR_STATE_PENDING) -+ lr_val |= ICH_LR_PENDING_BIT; -+ if (lr_desc.state & LR_STATE_ACTIVE) -+ lr_val |= ICH_LR_ACTIVE_BIT; -+ if (lr_desc.state & LR_EOI_INT) -+ lr_val |= ICH_LR_EOI; -+ -+ vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[LR_INDEX(lr)] = lr_val; -+} -+ -+static void vgic_v3_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr, -+ struct vgic_lr lr_desc) -+{ -+ if (!(lr_desc.state & LR_STATE_MASK)) -+ vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr |= (1U << lr); -+} -+ -+static u64 vgic_v3_get_elrsr(const struct kvm_vcpu *vcpu) -+{ -+ return vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr; -+} -+ -+static u64 vgic_v3_get_eisr(const struct kvm_vcpu *vcpu) -+{ -+ return vcpu->arch.vgic_cpu.vgic_v3.vgic_eisr; -+} -+ -+static u32 vgic_v3_get_interrupt_status(const struct kvm_vcpu *vcpu) -+{ -+ u32 misr = vcpu->arch.vgic_cpu.vgic_v3.vgic_misr; -+ u32 ret = 0; -+ -+ if (misr & ICH_MISR_EOI) -+ ret |= INT_STATUS_EOI; -+ if (misr & ICH_MISR_U) -+ ret |= INT_STATUS_UNDERFLOW; -+ -+ return ret; -+} -+ -+static void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp) -+{ -+ u32 vmcr = vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr; -+ -+ vmcrp->ctlr = (vmcr & ICH_VMCR_CTLR_MASK) >> ICH_VMCR_CTLR_SHIFT; -+ vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT; -+ vmcrp->bpr = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT; -+ vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT; -+} -+ -+static void vgic_v3_enable_underflow(struct kvm_vcpu *vcpu) -+{ -+ vcpu->arch.vgic_cpu.vgic_v3.vgic_hcr |= ICH_HCR_UIE; -+} -+ -+static void vgic_v3_disable_underflow(struct kvm_vcpu *vcpu) -+{ -+ vcpu->arch.vgic_cpu.vgic_v3.vgic_hcr &= ~ICH_HCR_UIE; -+} -+ -+static void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp) -+{ -+ u32 vmcr; -+ -+ vmcr = (vmcrp->ctlr << ICH_VMCR_CTLR_SHIFT) & ICH_VMCR_CTLR_MASK; -+ vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK; -+ vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK; -+ vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK; -+ -+ vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr = vmcr; -+} -+ -+static void vgic_v3_enable(struct kvm_vcpu *vcpu) -+{ -+ /* -+ * By forcing VMCR to zero, the GIC will restore the binary -+ * points to their reset values. Anything else resets to zero -+ * anyway. -+ */ -+ vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr = 0; -+ -+ /* Get the show on the road... */ -+ vcpu->arch.vgic_cpu.vgic_v3.vgic_hcr = ICH_HCR_EN; -+} -+ -+static const struct vgic_ops vgic_v3_ops = { -+ .get_lr = vgic_v3_get_lr, -+ .set_lr = vgic_v3_set_lr, -+ .sync_lr_elrsr = vgic_v3_sync_lr_elrsr, -+ .get_elrsr = vgic_v3_get_elrsr, -+ .get_eisr = vgic_v3_get_eisr, -+ .get_interrupt_status = vgic_v3_get_interrupt_status, -+ .enable_underflow = vgic_v3_enable_underflow, -+ .disable_underflow = vgic_v3_disable_underflow, -+ .get_vmcr = vgic_v3_get_vmcr, -+ .set_vmcr = vgic_v3_set_vmcr, -+ .enable = vgic_v3_enable, -+}; -+ -+static struct vgic_params vgic_v3_params; -+ -+/** -+ * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT -+ * @node: pointer to the DT node -+ * @ops: address of a pointer to the GICv3 operations -+ * @params: address of a pointer to HW-specific parameters -+ * -+ * Returns 0 if a GICv3 has been found, with the low level operations -+ * in *ops and the HW parameters in *params. Returns an error code -+ * otherwise. -+ */ -+int vgic_v3_probe(struct device_node *vgic_node, -+ const struct vgic_ops **ops, -+ const struct vgic_params **params) -+{ -+ int ret = 0; -+ u32 gicv_idx; -+ struct resource vcpu_res; -+ struct vgic_params *vgic = &vgic_v3_params; -+ -+ vgic->maint_irq = irq_of_parse_and_map(vgic_node, 0); -+ if (!vgic->maint_irq) { -+ kvm_err("error getting vgic maintenance irq from DT\n"); -+ ret = -ENXIO; -+ goto out; -+ } -+ -+ ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2); -+ -+ /* -+ * The ListRegs field is 5 bits, but there is a architectural -+ * maximum of 16 list registers. Just ignore bit 4... -+ */ -+ vgic->nr_lr = (ich_vtr_el2 & 0xf) + 1; -+ -+ if (of_property_read_u32(vgic_node, "#redistributor-regions", &gicv_idx)) -+ gicv_idx = 1; -+ -+ gicv_idx += 3; /* Also skip GICD, GICC, GICH */ -+ if (of_address_to_resource(vgic_node, gicv_idx, &vcpu_res)) { -+ kvm_err("Cannot obtain GICV region\n"); -+ ret = -ENXIO; -+ goto out; -+ } -+ vgic->vcpu_base = vcpu_res.start; -+ vgic->vctrl_base = NULL; -+ vgic->type = VGIC_V3; -+ -+ kvm_info("%s@%llx IRQ%d\n", vgic_node->name, -+ vcpu_res.start, vgic->maint_irq); -+ -+ *ops = &vgic_v3_ops; -+ *params = vgic; -+ -+out: -+ of_node_put(vgic_node); -+ return ret; -+} -diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c -index 476d3bf..795ab48 100644 ---- a/virt/kvm/arm/vgic.c -+++ b/virt/kvm/arm/vgic.c -@@ -76,14 +76,6 @@ - #define IMPLEMENTER_ARM 0x43b - #define GICC_ARCH_VERSION_V2 0x2 - --/* Physical address of vgic virtual cpu interface */ --static phys_addr_t vgic_vcpu_base; -- --/* Virtual control interface base address */ --static void __iomem *vgic_vctrl_base; -- --static struct device_node *vgic_node; -- - #define ACCESS_READ_VALUE (1 << 0) - #define ACCESS_READ_RAZ (0 << 0) - #define ACCESS_READ_MASK(x) ((x) & (1 << 0)) -@@ -94,12 +86,17 @@ static struct device_node *vgic_node; - #define ACCESS_WRITE_MASK(x) ((x) & (3 << 1)) - - static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu); -+static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu); - static void vgic_update_state(struct kvm *kvm); - static void vgic_kick_vcpus(struct kvm *kvm); - static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg); --static u32 vgic_nr_lr; -+static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr); -+static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, struct vgic_lr lr_desc); -+static void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); -+static void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); - --static unsigned int vgic_maint_irq; -+static const struct vgic_ops *vgic_ops; -+static const struct vgic_params *vgic; - - static u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x, - int cpuid, u32 offset) -@@ -593,18 +590,6 @@ static bool handle_mmio_sgi_reg(struct kvm_vcpu *vcpu, - return false; - } +@@ -173,7 +173,7 @@ static const struct vgic_ops vgic_v3_ops = { + static struct vgic_params vgic_v3_params; --#define LR_CPUID(lr) \ -- (((lr) & GICH_LR_PHYSID_CPUID) >> GICH_LR_PHYSID_CPUID_SHIFT) --#define LR_IRQID(lr) \ -- ((lr) & GICH_LR_VIRTUALID) -- --static void vgic_retire_lr(int lr_nr, int irq, struct vgic_cpu *vgic_cpu) --{ -- clear_bit(lr_nr, vgic_cpu->lr_used); -- vgic_cpu->vgic_lr[lr_nr] &= ~GICH_LR_STATE; -- vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY; --} -- /** - * vgic_unqueue_irqs - move pending IRQs from LRs to the distributor - * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs -@@ -622,13 +607,10 @@ static void vgic_unqueue_irqs(struct kvm_vcpu *vcpu) - struct vgic_dist *dist = &vcpu->kvm->arch.vgic; - struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; - int vcpu_id = vcpu->vcpu_id; -- int i, irq, source_cpu; -- u32 *lr; -+ int i; - - for_each_set_bit(i, vgic_cpu->lr_used, vgic_cpu->nr_lr) { -- lr = &vgic_cpu->vgic_lr[i]; -- irq = LR_IRQID(*lr); -- source_cpu = LR_CPUID(*lr); -+ struct vgic_lr lr = vgic_get_lr(vcpu, i); - - /* - * There are three options for the state bits: -@@ -640,7 +622,7 @@ static void vgic_unqueue_irqs(struct kvm_vcpu *vcpu) - * If the LR holds only an active interrupt (not pending) then - * just leave it alone. - */ -- if ((*lr & GICH_LR_STATE) == GICH_LR_ACTIVE_BIT) -+ if ((lr.state & LR_STATE_MASK) == LR_STATE_ACTIVE) - continue; - - /* -@@ -649,18 +631,19 @@ static void vgic_unqueue_irqs(struct kvm_vcpu *vcpu) - * is fine, then we are only setting a few bits that were - * already set. - */ -- vgic_dist_irq_set(vcpu, irq); -- if (irq < VGIC_NR_SGIS) -- dist->irq_sgi_sources[vcpu_id][irq] |= 1 << source_cpu; -- *lr &= ~GICH_LR_PENDING_BIT; -+ vgic_dist_irq_set(vcpu, lr.irq); -+ if (lr.irq < VGIC_NR_SGIS) -+ dist->irq_sgi_sources[vcpu_id][lr.irq] |= 1 << lr.source; -+ lr.state &= ~LR_STATE_PENDING; -+ vgic_set_lr(vcpu, i, lr); - - /* - * If there's no state left on the LR (it could still be - * active), then the LR does not hold any useful info and can - * be marked as free for other use. - */ -- if (!(*lr & GICH_LR_STATE)) -- vgic_retire_lr(i, irq, vgic_cpu); -+ if (!(lr.state & LR_STATE_MASK)) -+ vgic_retire_lr(i, lr.irq, vcpu); - - /* Finally update the VGIC state. */ - vgic_update_state(vcpu->kvm); -@@ -989,8 +972,73 @@ static void vgic_update_state(struct kvm *kvm) - } - } - --#define MK_LR_PEND(src, irq) \ -- (GICH_LR_PENDING_BIT | ((src) << GICH_LR_PHYSID_CPUID_SHIFT) | (irq)) -+static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr) -+{ -+ return vgic_ops->get_lr(vcpu, lr); -+} -+ -+static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, -+ struct vgic_lr vlr) -+{ -+ vgic_ops->set_lr(vcpu, lr, vlr); -+} -+ -+static void vgic_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr, -+ struct vgic_lr vlr) -+{ -+ vgic_ops->sync_lr_elrsr(vcpu, lr, vlr); -+} -+ -+static inline u64 vgic_get_elrsr(struct kvm_vcpu *vcpu) -+{ -+ return vgic_ops->get_elrsr(vcpu); -+} -+ -+static inline u64 vgic_get_eisr(struct kvm_vcpu *vcpu) -+{ -+ return vgic_ops->get_eisr(vcpu); -+} -+ -+static inline u32 vgic_get_interrupt_status(struct kvm_vcpu *vcpu) -+{ -+ return vgic_ops->get_interrupt_status(vcpu); -+} -+ -+static inline void vgic_enable_underflow(struct kvm_vcpu *vcpu) -+{ -+ vgic_ops->enable_underflow(vcpu); -+} -+ -+static inline void vgic_disable_underflow(struct kvm_vcpu *vcpu) -+{ -+ vgic_ops->disable_underflow(vcpu); -+} -+ -+static inline void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr) -+{ -+ vgic_ops->get_vmcr(vcpu, vmcr); -+} -+ -+static void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr) -+{ -+ vgic_ops->set_vmcr(vcpu, vmcr); -+} -+ -+static inline void vgic_enable(struct kvm_vcpu *vcpu) -+{ -+ vgic_ops->enable(vcpu); -+} -+ -+static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu) -+{ -+ struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; -+ struct vgic_lr vlr = vgic_get_lr(vcpu, lr_nr); -+ -+ vlr.state = 0; -+ vgic_set_lr(vcpu, lr_nr, vlr); -+ clear_bit(lr_nr, vgic_cpu->lr_used); -+ vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY; -+} - - /* - * An interrupt may have been disabled after being made pending on the -@@ -1006,13 +1054,13 @@ static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu) - struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; - int lr; - -- for_each_set_bit(lr, vgic_cpu->lr_used, vgic_cpu->nr_lr) { -- int irq = vgic_cpu->vgic_lr[lr] & GICH_LR_VIRTUALID; -+ for_each_set_bit(lr, vgic_cpu->lr_used, vgic->nr_lr) { -+ struct vgic_lr vlr = vgic_get_lr(vcpu, lr); - -- if (!vgic_irq_is_enabled(vcpu, irq)) { -- vgic_retire_lr(lr, irq, vgic_cpu); -- if (vgic_irq_is_active(vcpu, irq)) -- vgic_irq_clear_active(vcpu, irq); -+ if (!vgic_irq_is_enabled(vcpu, vlr.irq)) { -+ vgic_retire_lr(lr, vlr.irq, vcpu); -+ if (vgic_irq_is_active(vcpu, vlr.irq)) -+ vgic_irq_clear_active(vcpu, vlr.irq); - } - } - } -@@ -1024,6 +1072,7 @@ static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu) - static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq) - { - struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; -+ struct vgic_lr vlr; - int lr; - - /* Sanitize the input... */ -@@ -1036,28 +1085,34 @@ static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq) - lr = vgic_cpu->vgic_irq_lr_map[irq]; - - /* Do we have an active interrupt for the same CPUID? */ -- if (lr != LR_EMPTY && -- (LR_CPUID(vgic_cpu->vgic_lr[lr]) == sgi_source_id)) { -- kvm_debug("LR%d piggyback for IRQ%d %x\n", -- lr, irq, vgic_cpu->vgic_lr[lr]); -- BUG_ON(!test_bit(lr, vgic_cpu->lr_used)); -- vgic_cpu->vgic_lr[lr] |= GICH_LR_PENDING_BIT; -- return true; -+ if (lr != LR_EMPTY) { -+ vlr = vgic_get_lr(vcpu, lr); -+ if (vlr.source == sgi_source_id) { -+ kvm_debug("LR%d piggyback for IRQ%d\n", lr, vlr.irq); -+ BUG_ON(!test_bit(lr, vgic_cpu->lr_used)); -+ vlr.state |= LR_STATE_PENDING; -+ vgic_set_lr(vcpu, lr, vlr); -+ return true; -+ } - } - - /* Try to use another LR for this interrupt */ - lr = find_first_zero_bit((unsigned long *)vgic_cpu->lr_used, -- vgic_cpu->nr_lr); -- if (lr >= vgic_cpu->nr_lr) -+ vgic->nr_lr); -+ if (lr >= vgic->nr_lr) - return false; - - kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id); -- vgic_cpu->vgic_lr[lr] = MK_LR_PEND(sgi_source_id, irq); - vgic_cpu->vgic_irq_lr_map[irq] = lr; - set_bit(lr, vgic_cpu->lr_used); - -+ vlr.irq = irq; -+ vlr.source = sgi_source_id; -+ vlr.state = LR_STATE_PENDING; - if (!vgic_irq_is_edge(vcpu, irq)) -- vgic_cpu->vgic_lr[lr] |= GICH_LR_EOI; -+ vlr.state |= LR_EOI_INT; -+ -+ vgic_set_lr(vcpu, lr, vlr); - - return true; - } -@@ -1155,9 +1210,9 @@ static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) - - epilog: - if (overflow) { -- vgic_cpu->vgic_hcr |= GICH_HCR_UIE; -+ vgic_enable_underflow(vcpu); - } else { -- vgic_cpu->vgic_hcr &= ~GICH_HCR_UIE; -+ vgic_disable_underflow(vcpu); - /* - * We're about to run this VCPU, and we've consumed - * everything the distributor had in store for -@@ -1170,44 +1225,46 @@ epilog: - - static bool vgic_process_maintenance(struct kvm_vcpu *vcpu) - { -- struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; -+ u32 status = vgic_get_interrupt_status(vcpu); - bool level_pending = false; - -- kvm_debug("MISR = %08x\n", vgic_cpu->vgic_misr); -+ kvm_debug("STATUS = %08x\n", status); - -- if (vgic_cpu->vgic_misr & GICH_MISR_EOI) { -+ if (status & INT_STATUS_EOI) { - /* - * Some level interrupts have been EOIed. Clear their - * active bit. - */ -- int lr, irq; -+ u64 eisr = vgic_get_eisr(vcpu); -+ unsigned long *eisr_ptr = (unsigned long *)&eisr; -+ int lr; - -- for_each_set_bit(lr, (unsigned long *)vgic_cpu->vgic_eisr, -- vgic_cpu->nr_lr) { -- irq = vgic_cpu->vgic_lr[lr] & GICH_LR_VIRTUALID; -+ for_each_set_bit(lr, eisr_ptr, vgic->nr_lr) { -+ struct vgic_lr vlr = vgic_get_lr(vcpu, lr); - -- vgic_irq_clear_active(vcpu, irq); -- vgic_cpu->vgic_lr[lr] &= ~GICH_LR_EOI; -+ vgic_irq_clear_active(vcpu, vlr.irq); -+ WARN_ON(vlr.state & LR_STATE_MASK); -+ vlr.state = 0; -+ vgic_set_lr(vcpu, lr, vlr); - - /* Any additional pending interrupt? */ -- if (vgic_dist_irq_is_pending(vcpu, irq)) { -- vgic_cpu_irq_set(vcpu, irq); -+ if (vgic_dist_irq_is_pending(vcpu, vlr.irq)) { -+ vgic_cpu_irq_set(vcpu, vlr.irq); - level_pending = true; - } else { -- vgic_cpu_irq_clear(vcpu, irq); -+ vgic_cpu_irq_clear(vcpu, vlr.irq); - } - - /* - * Despite being EOIed, the LR may not have - * been marked as empty. - */ -- set_bit(lr, (unsigned long *)vgic_cpu->vgic_elrsr); -- vgic_cpu->vgic_lr[lr] &= ~GICH_LR_ACTIVE_BIT; -+ vgic_sync_lr_elrsr(vcpu, lr, vlr); - } - } - -- if (vgic_cpu->vgic_misr & GICH_MISR_U) -- vgic_cpu->vgic_hcr &= ~GICH_HCR_UIE; -+ if (status & INT_STATUS_UNDERFLOW) -+ vgic_disable_underflow(vcpu); - - return level_pending; - } -@@ -1220,29 +1277,31 @@ static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) +- * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT ++ * vgic_v3_dt_probe - probe for a GICv3 compatible interrupt controller in DT + * @node: pointer to the DT node + * @ops: address of a pointer to the GICv3 operations + * @params: address of a pointer to HW-specific parameters +@@ -182,9 +182,9 @@ static struct vgic_params vgic_v3_params; + * in *ops and the HW parameters in *params. Returns an error code + * otherwise. + */ +-int vgic_v3_probe(struct device_node *vgic_node, +- const struct vgic_ops **ops, +- const struct vgic_params **params) ++int vgic_v3_dt_probe(struct device_node *vgic_node, ++ const struct vgic_ops **ops, ++ const struct vgic_params **params) { - struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; - struct vgic_dist *dist = &vcpu->kvm->arch.vgic; -+ u64 elrsr; -+ unsigned long *elrsr_ptr; - int lr, pending; - bool level_pending; - - level_pending = vgic_process_maintenance(vcpu); -+ elrsr = vgic_get_elrsr(vcpu); -+ elrsr_ptr = (unsigned long *)&elrsr; - - /* Clear mappings for empty LRs */ -- for_each_set_bit(lr, (unsigned long *)vgic_cpu->vgic_elrsr, -- vgic_cpu->nr_lr) { -- int irq; -+ for_each_set_bit(lr, elrsr_ptr, vgic->nr_lr) { -+ struct vgic_lr vlr; - - if (!test_and_clear_bit(lr, vgic_cpu->lr_used)) - continue; - -- irq = vgic_cpu->vgic_lr[lr] & GICH_LR_VIRTUALID; -+ vlr = vgic_get_lr(vcpu, lr); - -- BUG_ON(irq >= VGIC_NR_IRQS); -- vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY; -+ BUG_ON(vlr.irq >= VGIC_NR_IRQS); -+ vgic_cpu->vgic_irq_lr_map[vlr.irq] = LR_EMPTY; - } - - /* Check if we still have something up our sleeve... */ -- pending = find_first_zero_bit((unsigned long *)vgic_cpu->vgic_elrsr, -- vgic_cpu->nr_lr); -- if (level_pending || pending < vgic_cpu->nr_lr) -+ pending = find_first_zero_bit(elrsr_ptr, vgic->nr_lr); -+ if (level_pending || pending < vgic->nr_lr) - set_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu); - } - -@@ -1432,21 +1491,20 @@ int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu) - } - - /* -- * By forcing VMCR to zero, the GIC will restore the binary -- * points to their reset values. Anything else resets to zero -- * anyway. -+ * Store the number of LRs per vcpu, so we don't have to go -+ * all the way to the distributor structure to find out. Only -+ * assembly code should use this one. - */ -- vgic_cpu->vgic_vmcr = 0; -+ vgic_cpu->nr_lr = vgic->nr_lr; - -- vgic_cpu->nr_lr = vgic_nr_lr; -- vgic_cpu->vgic_hcr = GICH_HCR_EN; /* Get the show on the road... */ -+ vgic_enable(vcpu); - - return 0; - } + int ret = 0; + u32 gicv_idx; +diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c +index 73eba79..ca98a3b 100644 +--- a/virt/kvm/arm/vgic.c ++++ b/virt/kvm/arm/vgic.c +@@ -25,9 +25,11 @@ + #include <linux/of_address.h> + #include <linux/of_irq.h> + #include <linux/uaccess.h> ++#include <linux/acpi.h> - static void vgic_init_maintenance_interrupt(void *info) - { -- enable_percpu_irq(vgic_maint_irq, 0); -+ enable_percpu_irq(vgic->maint_irq, 0); - } + #include <linux/irqchip/arm-gic.h> - static int vgic_cpu_notify(struct notifier_block *self, -@@ -1459,7 +1517,7 @@ static int vgic_cpu_notify(struct notifier_block *self, - break; - case CPU_DYING: - case CPU_DYING_FROZEN: -- disable_percpu_irq(vgic_maint_irq); -+ disable_percpu_irq(vgic->maint_irq); - break; - } ++#include <asm/acpi.h> + #include <asm/kvm_emulate.h> + #include <asm/kvm_arm.h> + #include <asm/kvm_mmu.h> +@@ -1549,31 +1551,39 @@ static struct notifier_block vgic_cpu_nb = { + }; -@@ -1470,30 +1528,37 @@ static struct notifier_block vgic_cpu_nb = { - .notifier_call = vgic_cpu_notify, + static const struct of_device_id vgic_ids[] = { +- { .compatible = "arm,cortex-a15-gic", .data = vgic_v2_probe, }, +- { .compatible = "arm,gic-v3", .data = vgic_v3_probe, }, ++ { .compatible = "arm,cortex-a15-gic", .data = vgic_v2_dt_probe, }, ++ { .compatible = "arm,gic-v3", .data = vgic_v3_dt_probe, }, + {}, }; -+static const struct of_device_id vgic_ids[] = { -+ { .compatible = "arm,cortex-a15-gic", .data = vgic_v2_probe, }, -+ { .compatible = "arm,gic-v3", .data = vgic_v3_probe, }, -+ {}, -+}; ++extern int acadia_kvm_acpi; + int kvm_vgic_hyp_init(void) { -+ const struct of_device_id *matched_id; -+ int (*vgic_probe)(struct device_node *,const struct vgic_ops **, -+ const struct vgic_params **); -+ struct device_node *vgic_node; - int ret; -- struct resource vctrl_res; -- struct resource vcpu_res; - -- vgic_node = of_find_compatible_node(NULL, NULL, "arm,cortex-a15-gic"); -+ vgic_node = of_find_matching_node_and_match(NULL, -+ vgic_ids, &matched_id); - if (!vgic_node) { -- kvm_err("error: no compatible vgic node in DT\n"); -+ kvm_err("error: no compatible GIC node found\n"); - return -ENODEV; + const struct of_device_id *matched_id; + int (*vgic_probe)(struct device_node *,const struct vgic_ops **, + const struct vgic_params **); + struct device_node *vgic_node; +- int ret; ++ int ret = -ENODEV; + +- vgic_node = of_find_matching_node_and_match(NULL, +- vgic_ids, &matched_id); +- if (!vgic_node) { +- kvm_err("error: no compatible GIC node found\n"); +- return -ENODEV; ++ /* probe VGIC */ ++ if (vgic_node = of_find_matching_node_and_match(NULL, ++ vgic_ids, &matched_id)) { ++ /* probe VGIC in DT */ ++ vgic_probe = matched_id->data; ++ ret = vgic_probe(vgic_node, &vgic_ops, &vgic); ++ } ++ else if (!acpi_disabled && acadia_kvm_acpi) { ++ /* probe VGIC in ACPI */ ++ ret = vgic_v2_acpi_probe(&vgic_ops, &vgic); } -- vgic_maint_irq = irq_of_parse_and_map(vgic_node, 0); -- if (!vgic_maint_irq) { -- kvm_err("error getting vgic maintenance irq from DT\n"); -- ret = -ENXIO; -- goto out; -- } -+ vgic_probe = matched_id->data; -+ ret = vgic_probe(vgic_node, &vgic_ops, &vgic); -+ if (ret) -+ return ret; +- vgic_probe = matched_id->data; +- ret = vgic_probe(vgic_node, &vgic_ops, &vgic); +- if (ret) ++ if (ret) { ++ kvm_err("error: no compatible GIC info found\n"); + return ret; ++ } -- ret = request_percpu_irq(vgic_maint_irq, vgic_maintenance_handler, -+ ret = request_percpu_irq(vgic->maint_irq, vgic_maintenance_handler, ++ /* configuration */ + ret = request_percpu_irq(vgic->maint_irq, vgic_maintenance_handler, "vgic", kvm_get_running_vcpus()); if (ret) { -- kvm_err("Cannot register interrupt %d\n", vgic_maint_irq); -- goto out; -+ kvm_err("Cannot register interrupt %d\n", vgic->maint_irq); -+ return ret; - } - - ret = __register_cpu_notifier(&vgic_cpu_nb); -@@ -1502,65 +1567,15 @@ int kvm_vgic_hyp_init(void) - goto out_free_irq; - } - -- ret = of_address_to_resource(vgic_node, 2, &vctrl_res); -- if (ret) { -- kvm_err("Cannot obtain VCTRL resource\n"); -- goto out_free_irq; -- } -- -- vgic_vctrl_base = of_iomap(vgic_node, 2); -- if (!vgic_vctrl_base) { -- kvm_err("Cannot ioremap VCTRL\n"); -- ret = -ENOMEM; -- goto out_free_irq; -- } -- -- vgic_nr_lr = readl_relaxed(vgic_vctrl_base + GICH_VTR); -- vgic_nr_lr = (vgic_nr_lr & 0x3f) + 1; -- -- ret = create_hyp_io_mappings(vgic_vctrl_base, -- vgic_vctrl_base + resource_size(&vctrl_res), -- vctrl_res.start); -- if (ret) { -- kvm_err("Cannot map VCTRL into hyp\n"); -- goto out_unmap; -- } -- -- if (of_address_to_resource(vgic_node, 3, &vcpu_res)) { -- kvm_err("Cannot obtain VCPU resource\n"); -- ret = -ENXIO; -- goto out_unmap; -- } -- -- if (!PAGE_ALIGNED(vcpu_res.start)) { -- kvm_err("GICV physical address 0x%llx not page aligned\n", -- (unsigned long long)vcpu_res.start); -- ret = -ENXIO; -- goto out_unmap; -- } -- -- if (!PAGE_ALIGNED(resource_size(&vcpu_res))) { -- kvm_err("GICV size 0x%llx not a multiple of page size 0x%lx\n", -- (unsigned long long)resource_size(&vcpu_res), -- PAGE_SIZE); -- ret = -ENXIO; -- goto out_unmap; -- } -- -- vgic_vcpu_base = vcpu_res.start; -- -- kvm_info("%s@%llx IRQ%d\n", vgic_node->name, -- vctrl_res.start, vgic_maint_irq); - on_each_cpu(vgic_init_maintenance_interrupt, NULL, 1); - -- goto out; -+ /* Callback into for arch code for setup */ -+ vgic_arch_setup(vgic); -+ -+ return 0; - --out_unmap: -- iounmap(vgic_vctrl_base); - out_free_irq: -- free_percpu_irq(vgic_maint_irq, kvm_get_running_vcpus()); --out: -- of_node_put(vgic_node); -+ free_percpu_irq(vgic->maint_irq, kvm_get_running_vcpus()); - return ret; - } - -@@ -1593,7 +1608,7 @@ int kvm_vgic_init(struct kvm *kvm) - } - - ret = kvm_phys_addr_ioremap(kvm, kvm->arch.vgic.vgic_cpu_base, -- vgic_vcpu_base, KVM_VGIC_V2_CPU_SIZE); -+ vgic->vcpu_base, KVM_VGIC_V2_CPU_SIZE); - if (ret) { - kvm_err("Unable to remap VGIC CPU to VCPU\n"); - goto out; -@@ -1639,7 +1654,8 @@ int kvm_vgic_create(struct kvm *kvm) - } - - spin_lock_init(&kvm->arch.vgic.lock); -- kvm->arch.vgic.vctrl_base = vgic_vctrl_base; -+ kvm->arch.vgic.in_kernel = true; -+ kvm->arch.vgic.vctrl_base = vgic->vctrl_base; - kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF; - kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF; - -@@ -1738,39 +1754,40 @@ int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write) - static bool handle_cpu_mmio_misc(struct kvm_vcpu *vcpu, - struct kvm_exit_mmio *mmio, phys_addr_t offset) - { -- struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; -- u32 reg, mask = 0, shift = 0; - bool updated = false; -+ struct vgic_vmcr vmcr; -+ u32 *vmcr_field; -+ u32 reg; -+ -+ vgic_get_vmcr(vcpu, &vmcr); - - switch (offset & ~0x3) { - case GIC_CPU_CTRL: -- mask = GICH_VMCR_CTRL_MASK; -- shift = GICH_VMCR_CTRL_SHIFT; -+ vmcr_field = &vmcr.ctlr; - break; - case GIC_CPU_PRIMASK: -- mask = GICH_VMCR_PRIMASK_MASK; -- shift = GICH_VMCR_PRIMASK_SHIFT; -+ vmcr_field = &vmcr.pmr; - break; - case GIC_CPU_BINPOINT: -- mask = GICH_VMCR_BINPOINT_MASK; -- shift = GICH_VMCR_BINPOINT_SHIFT; -+ vmcr_field = &vmcr.bpr; - break; - case GIC_CPU_ALIAS_BINPOINT: -- mask = GICH_VMCR_ALIAS_BINPOINT_MASK; -- shift = GICH_VMCR_ALIAS_BINPOINT_SHIFT; -+ vmcr_field = &vmcr.abpr; - break; -+ default: -+ BUG(); - } - - if (!mmio->is_write) { -- reg = (vgic_cpu->vgic_vmcr & mask) >> shift; -+ reg = *vmcr_field; - mmio_data_write(mmio, ~0, reg); - } else { - reg = mmio_data_read(mmio, ~0); -- reg = (reg << shift) & mask; -- if (reg != (vgic_cpu->vgic_vmcr & mask)) -+ if (reg != *vmcr_field) { -+ *vmcr_field = reg; -+ vgic_set_vmcr(vcpu, &vmcr); - updated = true; -- vgic_cpu->vgic_vmcr &= ~mask; -- vgic_cpu->vgic_vmcr |= reg; -+ } - } - return updated; - } diff --git a/kernel.spec b/kernel.spec index 63251464..8e8dc25f 100644 --- a/kernel.spec +++ b/kernel.spec @@ -42,19 +42,19 @@ Summary: The Linux kernel # For non-released -rc kernels, this will be appended after the rcX and # gitX tags, so a 3 here would become part of release "0.rcX.gitX.3" # -%global baserelease 302 +%global baserelease 300 %global fedora_build %{baserelease} # base_sublevel is the kernel version we're starting with and patching # on top of -- for example, 3.1-rc7-git1 starts with a 3.0 base, # which yields a base_sublevel of 0. -%define base_sublevel 16 +%define base_sublevel 17 ## If this is a released kernel ## %if 0%{?released_kernel} # Do we have a -stable update to apply? -%define stable_update 3 +%define stable_update 0 # Set rpm version accordingly %if 0%{?stable_update} %define stablerev %{stable_update} @@ -493,7 +493,7 @@ Patch00: patch-3.%{base_sublevel}-git%{gitrev}.xz Patch04: compile-fixes.patch # build tweak for build ID magic, even for -vanilla -Patch05: makefile-after_link.patch +Patch05: kbuild-AFTER_LINK.patch %if !%{nopatches} @@ -511,20 +511,38 @@ Patch470: die-floppy-die.patch Patch500: Revert-Revert-ACPI-video-change-acpi-video-brightnes.patch -Patch510: silence-noise.patch +Patch510: input-silence-i8042-noise.patch Patch530: silence-fbcon-logo.patch -Patch600: 0001-lib-cpumask-Make-CPUMASK_OFFSTACK-usable-without-deb.patch +Patch600: lib-cpumask-Make-CPUMASK_OFFSTACK-usable-without-deb.patch Patch800: crash-driver.patch # crypto/ # secure boot -Patch1000: secure-modules.patch -Patch1001: modsign-uefi.patch -# atch1002: sb-hibernate.patch -Patch1003: sysrq-secure-boot.patch +Patch1000: Add-secure_modules-call.patch +Patch1001: PCI-Lock-down-BAR-access-when-module-security-is-ena.patch +Patch1002: x86-Lock-down-IO-port-access-when-module-security-is.patch +Patch1003: ACPI-Limit-access-to-custom_method.patch +Patch1004: asus-wmi-Restrict-debugfs-interface-when-module-load.patch +Patch1005: Restrict-dev-mem-and-dev-kmem-when-module-loading-is.patch +Patch1006: acpi-Ignore-acpi_rsdp-kernel-parameter-when-module-l.patch +Patch1007: kexec-Disable-at-runtime-if-the-kernel-enforces-modu.patch +Patch1008: x86-Restrict-MSR-access-when-module-loading-is-restr.patch +Patch1009: Add-option-to-automatically-enforce-module-signature.patch +Patch1010: efi-Disable-secure-boot-if-shim-is-in-insecure-mode.patch +Patch1011: efi-Make-EFI_SECURE_BOOT_SIG_ENFORCE-depend-on-EFI.patch +Patch1012: efi-Add-EFI_SECURE_BOOT-bit.patch +Patch1013: hibernate-Disable-in-a-signed-modules-environment.patch + +Patch1014: Add-EFI-signature-data-types.patch +Patch1015: Add-an-EFI-signature-blob-parser-and-key-loader.patch +Patch1016: KEYS-Add-a-system-blacklist-keyring.patch +Patch1017: MODSIGN-Import-certificates-from-UEFI-Secure-Boot.patch +Patch1018: MODSIGN-Support-not-importing-certs-from-db.patch + +Patch1019: Add-sysrq-option-to-disable-secure-boot-mode.patch # virt + ksm patches @@ -547,17 +565,25 @@ Patch14000: hibernate-freeze-filesystems.patch Patch14010: lis3-improve-handling-of-null-rate.patch -Patch15000: nowatchdog-on-virt.patch +Patch15000: watchdog-Disable-watchdog-on-virtual-machines.patch +# PPC +Patch18000: ppc64-fixtools.patch # ARM64 # ARMv7 -Patch21020: arm-tegra-usb-no-reset-linux33.patch -Patch21021: arm-beagle.patch -Patch21022: arm-imx6-utilite.patch -# http://www.spinics.net/lists/linux-tegra/msg17948.html -Patch21023: arm-tegra-drmdetection.patch -Patch21024: arm-qemu-fixdisplay.patch +Patch21020: ARM-tegra-usb-no-reset.patch +Patch21021: arm-dts-am335x-boneblack-lcdc-add-panel-info.patch +Patch21022: arm-dts-am335x-boneblack-add-cpu0-opp-points.patch +Patch21023: arm-dts-am335x-bone-common-enable-and-use-i2c2.patch +Patch21024: arm-dts-am335x-bone-common-setup-default-pinmux-http.patch +Patch21025: arm-dts-am335x-bone-common-add-uart2_pins-uart4_pins.patch +Patch21026: pinctrl-pinctrl-single-must-be-initialized-early.patch + +Patch21028: arm-i.MX6-Utilite-device-dtb.patch +Patch21029: arm-dts-sun7i-bananapi.patch + +Patch21100: arm-highbank-l2-reverts.patch #rhbz 754518 Patch21235: scsi-sd_revalidate_disk-prevent-NULL-ptr-deref.patch @@ -566,7 +592,7 @@ Patch21235: scsi-sd_revalidate_disk-prevent-NULL-ptr-deref.patch Patch21242: criu-no-expert.patch #rhbz 892811 -Patch21247: ath9k_rx_dma_stop_check.patch +Patch21247: ath9k-rx-dma-stop-check.patch Patch22000: weird-root-dentry-name-debug.patch @@ -574,45 +600,31 @@ Patch22000: weird-root-dentry-name-debug.patch Patch25063: disable-libdw-unwind-on-non-x86.patch #rhbz 983342 1093120 -Patch25069: 0001-acpi-video-Add-4-new-models-to-the-use_native_backli.patch +Patch25069: acpi-video-Add-4-new-models-to-the-use_native_backli.patch -Patch26000: perf-lib64.patch +Patch26000: perf-install-trace-event-plugins.patch # Patch series from Hans for various backlight and platform driver fixes Patch26002: samsung-laptop-Add-broken-acpi-video-quirk-for-NC210.patch -Patch26004: asus-wmi-Add-a-no-backlight-quirk.patch -Patch26005: eeepc-wmi-Add-no-backlight-quirk-for-Asus-H87I-PLUS-.patch Patch26013: acpi-video-Add-use-native-backlight-quirk-for-the-Th.patch Patch26014: acpi-video-Add-use_native_backlight-quirk-for-HP-Pro.patch -Patch25109: revert-input-wacom-testing-result-shows-get_report-is-unnecessary.patch - -#rhbz 1021036, submitted upstream -Patch25110: 0001-ideapad-laptop-Change-Lenovo-Yoga-2-series-rfkill-ha.patch - #rhbz 1134969 -Patch26019: Input-wacom-Add-support-for-the-Cintiq-Companion.patch +Patch26016: HID-wacom-Add-support-for-the-Cintiq-Companion.patch #rhbz 1110011 -Patch26021: i8042-Also-store-the-aux-firmware-id-in-multi-plexed.patch -Patch26022: psmouse-Add-psmouse_matches_pnp_id-helper-function.patch -Patch26023: psmouse-Add-support-for-detecting-FocalTech-PS-2-tou.patch - -#CVE-2014-3181 rhbz 1141179 1141173 -Patch26024: HID-magicmouse-sanity-check-report-size-in-raw_event.patch +Patch26019: psmouse-Add-psmouse_matches_pnp_id-helper-function.patch +Patch26020: psmouse-Add-support-for-detecting-FocalTech-PS-2-tou.patch -#CVE-2014-3186 rhbz 1141407 1141410 -Patch26025: HID-picolcd-sanity-check-report-size-in-raw_event-ca.patch - -#CVE-2014-6410 rhbz 1141809 1141810 -Patch26026: udf-Avoid-infinite-loop-when-processing-indirect-ICB.patch - -#rhbz 1143812 -Patch26027: HID-i2c-hid-call-the-hid-driver-s-suspend-and-resume.patch +#rhbz 1138759 +Patch26021: drm-vmwgfx-Fix-drm.h-include.patch #rhbz 1123584 Patch26028: HID-rmi-check-sanity-of-incoming-report.patch +#rhbz 1145318 +Patch26029: KEYS-Reinstate-EPERM-for-a-key-type-name-beginning-w.patch + # git clone ssh://git.fedorahosted.org/git/kernel-arm64.git, git diff master...devel Patch30000: kernel-arm64.patch @@ -1169,7 +1181,7 @@ do done %endif -ApplyPatch makefile-after_link.patch +ApplyPatch kbuild-AFTER_LINK.patch # # misc small stuff to make things compile @@ -1183,18 +1195,29 @@ ApplyOptionalPatch upstream-reverts.patch -R # Architecture patches # x86(-64) -ApplyPatch 0001-lib-cpumask-Make-CPUMASK_OFFSTACK-usable-without-deb.patch +ApplyPatch lib-cpumask-Make-CPUMASK_OFFSTACK-usable-without-deb.patch + +# PPC +ApplyPatch ppc64-fixtools.patch # ARM64 # # ARM # -ApplyPatch arm-tegra-usb-no-reset-linux33.patch -ApplyPatch arm-beagle.patch -ApplyPatch arm-imx6-utilite.patch -ApplyPatch arm-tegra-drmdetection.patch -ApplyPatch arm-qemu-fixdisplay.patch +ApplyPatch ARM-tegra-usb-no-reset.patch + +ApplyPatch arm-dts-am335x-boneblack-lcdc-add-panel-info.patch +ApplyPatch arm-dts-am335x-boneblack-add-cpu0-opp-points.patch +ApplyPatch arm-dts-am335x-bone-common-enable-and-use-i2c2.patch +ApplyPatch arm-dts-am335x-bone-common-setup-default-pinmux-http.patch +ApplyPatch arm-dts-am335x-bone-common-add-uart2_pins-uart4_pins.patch +ApplyPatch pinctrl-pinctrl-single-must-be-initialized-early.patch + +ApplyPatch arm-i.MX6-Utilite-device-dtb.patch +ApplyPatch arm-dts-sun7i-bananapi.patch + +ApplyPatch arm-highbank-l2-reverts.patch # # bugfixes to drivers and filesystems @@ -1242,7 +1265,7 @@ ApplyPatch die-floppy-die.patch ApplyPatch no-pcspkr-modalias.patch # Silence some useless messages that still get printed with 'quiet' -ApplyPatch silence-noise.patch +ApplyPatch input-silence-i8042-noise.patch # Make fbcon not show the penguins with 'quiet' ApplyPatch silence-fbcon-logo.patch @@ -1255,10 +1278,28 @@ ApplyPatch crash-driver.patch # crypto/ # secure boot -ApplyPatch secure-modules.patch -ApplyPatch modsign-uefi.patch -# pplyPatch sb-hibernate.patch -ApplyPatch sysrq-secure-boot.patch +ApplyPatch Add-secure_modules-call.patch +ApplyPatch PCI-Lock-down-BAR-access-when-module-security-is-ena.patch +ApplyPatch x86-Lock-down-IO-port-access-when-module-security-is.patch +ApplyPatch ACPI-Limit-access-to-custom_method.patch +ApplyPatch asus-wmi-Restrict-debugfs-interface-when-module-load.patch +ApplyPatch Restrict-dev-mem-and-dev-kmem-when-module-loading-is.patch +ApplyPatch acpi-Ignore-acpi_rsdp-kernel-parameter-when-module-l.patch +ApplyPatch kexec-Disable-at-runtime-if-the-kernel-enforces-modu.patch +ApplyPatch x86-Restrict-MSR-access-when-module-loading-is-restr.patch +ApplyPatch Add-option-to-automatically-enforce-module-signature.patch +ApplyPatch efi-Disable-secure-boot-if-shim-is-in-insecure-mode.patch +ApplyPatch efi-Make-EFI_SECURE_BOOT_SIG_ENFORCE-depend-on-EFI.patch +ApplyPatch efi-Add-EFI_SECURE_BOOT-bit.patch +ApplyPatch hibernate-Disable-in-a-signed-modules-environment.patch + +ApplyPatch Add-EFI-signature-data-types.patch +ApplyPatch Add-an-EFI-signature-blob-parser-and-key-loader.patch +ApplyPatch KEYS-Add-a-system-blacklist-keyring.patch +ApplyPatch MODSIGN-Import-certificates-from-UEFI-Secure-Boot.patch +ApplyPatch MODSIGN-Support-not-importing-certs-from-db.patch + +ApplyPatch Add-sysrq-option-to-disable-secure-boot-mode.patch # Assorted Virt Fixes @@ -1280,7 +1321,7 @@ ApplyPatch disable-i8042-check-on-apple-mac.patch ApplyPatch lis3-improve-handling-of-null-rate.patch # Disable watchdog on virtual machines. -ApplyPatch nowatchdog-on-virt.patch +ApplyPatch watchdog-Disable-watchdog-on-virtual-machines.patch #rhbz 754518 ApplyPatch scsi-sd_revalidate_disk-prevent-NULL-ptr-deref.patch @@ -1291,51 +1332,37 @@ ApplyPatch scsi-sd_revalidate_disk-prevent-NULL-ptr-deref.patch ApplyPatch criu-no-expert.patch #rhbz 892811 -ApplyPatch ath9k_rx_dma_stop_check.patch +ApplyPatch ath9k-rx-dma-stop-check.patch #rhbz 1025603 ApplyPatch disable-libdw-unwind-on-non-x86.patch #rhbz 983342 1093120 -ApplyPatch 0001-acpi-video-Add-4-new-models-to-the-use_native_backli.patch +ApplyPatch acpi-video-Add-4-new-models-to-the-use_native_backli.patch -ApplyPatch perf-lib64.patch +ApplyPatch perf-install-trace-event-plugins.patch # Patch series from Hans for various backlight and platform driver fixes ApplyPatch samsung-laptop-Add-broken-acpi-video-quirk-for-NC210.patch -ApplyPatch asus-wmi-Add-a-no-backlight-quirk.patch -ApplyPatch eeepc-wmi-Add-no-backlight-quirk-for-Asus-H87I-PLUS-.patch ApplyPatch acpi-video-Add-use-native-backlight-quirk-for-the-Th.patch ApplyPatch acpi-video-Add-use_native_backlight-quirk-for-HP-Pro.patch -ApplyPatch revert-input-wacom-testing-result-shows-get_report-is-unnecessary.patch - -#rhbz 1021036, submitted upstream -ApplyPatch 0001-ideapad-laptop-Change-Lenovo-Yoga-2-series-rfkill-ha.patch - #rhbz 1134969 -ApplyPatch Input-wacom-Add-support-for-the-Cintiq-Companion.patch +ApplyPatch HID-wacom-Add-support-for-the-Cintiq-Companion.patch #rhbz 1110011 -ApplyPatch i8042-Also-store-the-aux-firmware-id-in-multi-plexed.patch ApplyPatch psmouse-Add-psmouse_matches_pnp_id-helper-function.patch ApplyPatch psmouse-Add-support-for-detecting-FocalTech-PS-2-tou.patch -#CVE-2014-3181 rhbz 1141179 1141173 -ApplyPatch HID-magicmouse-sanity-check-report-size-in-raw_event.patch - -#CVE-2014-3186 rhbz 1141407 1141410 -ApplyPatch HID-picolcd-sanity-check-report-size-in-raw_event-ca.patch - -#CVE-2014-6410 rhbz 1141809 1141810 -ApplyPatch udf-Avoid-infinite-loop-when-processing-indirect-ICB.patch - -#rhbz 1143812 -ApplyPatch HID-i2c-hid-call-the-hid-driver-s-suspend-and-resume.patch +#rhbz 1138759 +ApplyPatch drm-vmwgfx-Fix-drm.h-include.patch #rhbz 1123584 ApplyPatch HID-rmi-check-sanity-of-incoming-report.patch +#rhbz 1145318 +ApplyPatch KEYS-Reinstate-EPERM-for-a-key-type-name-beginning-w.patch + %if 0%{?aarch64patches} ApplyPatch kernel-arm64.patch %ifnarch aarch64 # this is stupid, but i want to notice before secondary koji does. @@ -2204,6 +2231,9 @@ fi # ||----w | # || || %changelog +* Mon Oct 06 2014 Josh Boyer <jwboyer@fedoraproject.org> - 3.17.0-300 +- Linux v3.17 + * Thu Sep 25 2014 Josh Boyer <jwboyer@fedoraproject.org> - 3.16.3-302 - Enable early microcode loading (rhbz 1083716) - Bump prereq on dracut that defaults to early microcode diff --git a/kexec-Disable-at-runtime-if-the-kernel-enforces-modu.patch b/kexec-Disable-at-runtime-if-the-kernel-enforces-modu.patch new file mode 100644 index 00000000..b3321373 --- /dev/null +++ b/kexec-Disable-at-runtime-if-the-kernel-enforces-modu.patch @@ -0,0 +1,43 @@ +From: Matthew Garrett <matthew.garrett@nebula.com> +Date: Fri, 9 Aug 2013 03:33:56 -0400 +Subject: [PATCH] kexec: Disable at runtime if the kernel enforces module + loading restrictions + +kexec permits the loading and execution of arbitrary code in ring 0, which +is something that module signing enforcement is meant to prevent. It makes +sense to disable kexec in this situation. + +Signed-off-by: Matthew Garrett <matthew.garrett@nebula.com> +--- + kernel/kexec.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/kernel/kexec.c b/kernel/kexec.c +index 2bee072268d9..891477dbfee0 100644 +--- a/kernel/kexec.c ++++ b/kernel/kexec.c +@@ -36,6 +36,7 @@ + #include <linux/syscore_ops.h> + #include <linux/compiler.h> + #include <linux/hugetlb.h> ++#include <linux/module.h> + + #include <asm/page.h> + #include <asm/uaccess.h> +@@ -1251,6 +1252,13 @@ SYSCALL_DEFINE4(kexec_load, unsigned long, entry, unsigned long, nr_segments, + return -EPERM; + + /* ++ * kexec can be used to circumvent module loading restrictions, so ++ * prevent loading in that case ++ */ ++ if (secure_modules()) ++ return -EPERM; ++ ++ /* + * Verify we have a legal set of flags + * This leaves us room for future extensions. + */ +-- +1.9.3 + diff --git a/lib-cpumask-Make-CPUMASK_OFFSTACK-usable-without-deb.patch b/lib-cpumask-Make-CPUMASK_OFFSTACK-usable-without-deb.patch new file mode 100644 index 00000000..73eb3432 --- /dev/null +++ b/lib-cpumask-Make-CPUMASK_OFFSTACK-usable-without-deb.patch @@ -0,0 +1,37 @@ +From: Josh Boyer <jwboyer@fedoraproject.org> +Date: Mon, 11 Nov 2013 08:39:16 -0500 +Subject: [PATCH] lib/cpumask: Make CPUMASK_OFFSTACK usable without debug + dependency + +When CPUMASK_OFFSTACK was added in 2008, it was dependent upon +DEBUG_PER_CPU_MAPS being enabled, or an architecture could select it. +The debug dependency adds additional overhead that isn't required for +operation of the feature, and we need CPUMASK_OFFSTACK to increase the +NR_CPUS value beyond 512 on x86. We drop the current dependency and make +sure SMP is set. + +Bugzilla: N/A +Upstream-status: Nak'd, supposedly replacement coming to auto-select + +Signed-off-by: Josh Boyer <jwboyer@fedoraproject.org> +--- + lib/Kconfig | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/lib/Kconfig b/lib/Kconfig +index 54cf309a92a5..64f8bb4882fb 100644 +--- a/lib/Kconfig ++++ b/lib/Kconfig +@@ -382,7 +382,8 @@ config CHECK_SIGNATURE + bool + + config CPUMASK_OFFSTACK +- bool "Force CPU masks off stack" if DEBUG_PER_CPU_MAPS ++ bool "Force CPU masks off stack" ++ depends on SMP + help + Use dynamic allocation for cpumask_var_t, instead of putting + them on the stack. This is a bit more expensive, but avoids +-- +1.9.3 + diff --git a/lis3-improve-handling-of-null-rate.patch b/lis3-improve-handling-of-null-rate.patch index ead58ce2..e3d3f4ee 100644 --- a/lis3-improve-handling-of-null-rate.patch +++ b/lis3-improve-handling-of-null-rate.patch @@ -1,13 +1,6 @@ -Bugzilla: 785814 -Upstream-status: ?? - ->From 56fb161a9ca0129f8e266e4dbe79346552ff8089 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=89ric=20Piel?= <eric.piel@tremplin-utc.net> Date: Thu, 3 Nov 2011 16:22:40 +0100 -Subject: [PATCH] lis3: Improve handling of null rate -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit +Subject: [PATCH] lis3: improve handling of null rate When obtaining a rate of 0, we would disable the device supposely because it seems to behave incorectly. It actually only comes from the @@ -15,16 +8,19 @@ fact that the device is off and on lis3dc it's reflected in the rate. So handle this nicely by just waiting a safe time, and then using the device as normally. +Bugzilla: 785814 +Upstream-status: ?? + Signed-off-by: ??ric Piel <eric.piel@tremplin-utc.net> --- - drivers/misc/lis3lv02d/lis3lv02d.c | 16 ++++++++-------- - 1 files changed, 8 insertions(+), 8 deletions(-) + drivers/misc/lis3lv02d/lis3lv02d.c | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/misc/lis3lv02d/lis3lv02d.c b/drivers/misc/lis3lv02d/lis3lv02d.c -index 35c67e0..42dce2a 100644 +index 3ef4627f9cb1..2b2d2e8e5eeb 100644 --- a/drivers/misc/lis3lv02d/lis3lv02d.c +++ b/drivers/misc/lis3lv02d/lis3lv02d.c -@@ -188,7 +188,8 @@ static void lis3lv02d_get_xyz(struct lis3lv02d *lis3, int *x, int *y, int *z) +@@ -216,7 +216,8 @@ static void lis3lv02d_get_xyz(struct lis3lv02d *lis3, int *x, int *y, int *z) /* conversion btw sampling rate and the register values */ static int lis3_12_rates[4] = {40, 160, 640, 2560}; static int lis3_8_rates[2] = {100, 400}; @@ -34,7 +30,7 @@ index 35c67e0..42dce2a 100644 static int lis3_3dlh_rates[4] = {50, 100, 400, 1000}; /* ODR is Output Data Rate */ -@@ -202,12 +203,11 @@ static int lis3lv02d_get_odr(struct lis3lv02d *lis3) +@@ -231,12 +232,11 @@ static int lis3lv02d_get_odr(struct lis3lv02d *lis3) return lis3->odrs[(ctrl >> shift)]; } @@ -50,7 +46,7 @@ index 35c67e0..42dce2a 100644 /* LIS3 power on delay is quite long */ msleep(lis3->pwron_delay / div); -@@ -274,7 +274,7 @@ static int lis3lv02d_selftest(struct lis3lv02d *lis3, s16 results[3]) +@@ -303,7 +303,7 @@ static int lis3lv02d_selftest(struct lis3lv02d *lis3, s16 results[3]) lis3->read(lis3, ctlreg, ®); lis3->write(lis3, ctlreg, (reg | selftest)); @@ -59,7 +55,7 @@ index 35c67e0..42dce2a 100644 if (ret) goto fail; -@@ -285,7 +285,7 @@ static int lis3lv02d_selftest(struct lis3lv02d *lis3, s16 results[3]) +@@ -314,7 +314,7 @@ static int lis3lv02d_selftest(struct lis3lv02d *lis3, s16 results[3]) /* back to normal settings */ lis3->write(lis3, ctlreg, reg); @@ -68,8 +64,8 @@ index 35c67e0..42dce2a 100644 if (ret) goto fail; -@@ -397,7 +397,7 @@ int lis3lv02d_poweron(struct lis3lv02d *lis3) - lis3->write(lis3, CTRL_REG2, reg); +@@ -434,7 +434,7 @@ int lis3lv02d_poweron(struct lis3lv02d *lis3) + } } - err = lis3lv02d_get_pwron_wait(lis3); @@ -78,5 +74,5 @@ index 35c67e0..42dce2a 100644 return err; -- -1.7.7.1 +1.9.3 diff --git a/modsign-uefi.patch b/modsign-uefi.patch deleted file mode 100644 index 5f8cc331..00000000 --- a/modsign-uefi.patch +++ /dev/null @@ -1,624 +0,0 @@ -Bugzilla: N/A -Upstream-status: Fedora mustard for now - -From fa2bfe718da40bf24f92c85846577e9bc788882c Mon Sep 17 00:00:00 2001 -From: Dave Howells <dhowells@redhat.com> -Date: Tue, 23 Oct 2012 09:30:54 -0400 -Subject: [PATCH 1/5] Add EFI signature data types - -Add the data types that are used for containing hashes, keys and certificates -for cryptographic verification. - -Signed-off-by: David Howells <dhowells@redhat.com> ---- - include/linux/efi.h | 20 ++++++++++++++++++++ - 1 file changed, 20 insertions(+) - -diff --git a/include/linux/efi.h b/include/linux/efi.h -index e73f391fd3c8..3d66a61bbbca 100644 ---- a/include/linux/efi.h -+++ b/include/linux/efi.h -@@ -578,6 +578,12 @@ typedef efi_status_t efi_query_variable_store_t(u32 attributes, unsigned long si - #define DEVICE_TREE_GUID \ - EFI_GUID( 0xb1b621d5, 0xf19c, 0x41a5, 0x83, 0x0b, 0xd9, 0x15, 0x2c, 0x69, 0xaa, 0xe0 ) - -+#define EFI_CERT_SHA256_GUID \ -+ EFI_GUID( 0xc1c41626, 0x504c, 0x4092, 0xac, 0xa9, 0x41, 0xf9, 0x36, 0x93, 0x43, 0x28 ) -+ -+#define EFI_CERT_X509_GUID \ -+ EFI_GUID( 0xa5c059a1, 0x94e4, 0x4aa7, 0x87, 0xb5, 0xab, 0x15, 0x5c, 0x2b, 0xf0, 0x72 ) -+ - typedef struct { - efi_guid_t guid; - u64 table; -@@ -793,6 +799,20 @@ typedef struct _efi_file_io_interface { - - #define EFI_INVALID_TABLE_ADDR (~0UL) - -+typedef struct { -+ efi_guid_t signature_owner; -+ u8 signature_data[]; -+} efi_signature_data_t; -+ -+typedef struct { -+ efi_guid_t signature_type; -+ u32 signature_list_size; -+ u32 signature_header_size; -+ u32 signature_size; -+ u8 signature_header[]; -+ /* efi_signature_data_t signatures[][] */ -+} efi_signature_list_t; -+ - /* - * All runtime access to EFI goes through this structure: - */ --- -1.9.3 - - -From 922e0512ce70101b596558d5bb075cd40a450322 Mon Sep 17 00:00:00 2001 -From: Dave Howells <dhowells@redhat.com> -Date: Tue, 23 Oct 2012 09:36:28 -0400 -Subject: [PATCH 2/5] Add an EFI signature blob parser and key loader. - -X.509 certificates are loaded into the specified keyring as asymmetric type -keys. - -Signed-off-by: David Howells <dhowells@redhat.com> ---- - crypto/asymmetric_keys/Kconfig | 8 +++ - crypto/asymmetric_keys/Makefile | 1 + - crypto/asymmetric_keys/efi_parser.c | 109 ++++++++++++++++++++++++++++++++++++ - include/linux/efi.h | 4 ++ - 4 files changed, 122 insertions(+) - create mode 100644 crypto/asymmetric_keys/efi_parser.c - -diff --git a/crypto/asymmetric_keys/Kconfig b/crypto/asymmetric_keys/Kconfig -index 03a6eb95ab50..6306ffc2a7fe 100644 ---- a/crypto/asymmetric_keys/Kconfig -+++ b/crypto/asymmetric_keys/Kconfig -@@ -37,4 +37,12 @@ config X509_CERTIFICATE_PARSER - data and provides the ability to instantiate a crypto key from a - public key packet found inside the certificate. - -+config EFI_SIGNATURE_LIST_PARSER -+ bool "EFI signature list parser" -+ depends on EFI -+ select X509_CERTIFICATE_PARSER -+ help -+ This option provides support for parsing EFI signature lists for -+ X.509 certificates and turning them into keys. -+ - endif # ASYMMETRIC_KEY_TYPE -diff --git a/crypto/asymmetric_keys/Makefile b/crypto/asymmetric_keys/Makefile -index 0727204aab68..cd8388e5f2f1 100644 ---- a/crypto/asymmetric_keys/Makefile -+++ b/crypto/asymmetric_keys/Makefile -@@ -8,6 +8,7 @@ asymmetric_keys-y := asymmetric_type.o signature.o - - obj-$(CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE) += public_key.o - obj-$(CONFIG_PUBLIC_KEY_ALGO_RSA) += rsa.o -+obj-$(CONFIG_EFI_SIGNATURE_LIST_PARSER) += efi_parser.o - - # - # X.509 Certificate handling -diff --git a/crypto/asymmetric_keys/efi_parser.c b/crypto/asymmetric_keys/efi_parser.c -new file mode 100644 -index 000000000000..424896a0b169 ---- /dev/null -+++ b/crypto/asymmetric_keys/efi_parser.c -@@ -0,0 +1,109 @@ -+/* EFI signature/key/certificate list parser -+ * -+ * Copyright (C) 2012 Red Hat, Inc. All Rights Reserved. -+ * Written by David Howells (dhowells@redhat.com) -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public Licence -+ * as published by the Free Software Foundation; either version -+ * 2 of the Licence, or (at your option) any later version. -+ */ -+ -+#define pr_fmt(fmt) "EFI: "fmt -+#include <linux/module.h> -+#include <linux/printk.h> -+#include <linux/err.h> -+#include <linux/efi.h> -+#include <keys/asymmetric-type.h> -+ -+static __initdata efi_guid_t efi_cert_x509_guid = EFI_CERT_X509_GUID; -+ -+/** -+ * parse_efi_signature_list - Parse an EFI signature list for certificates -+ * @data: The data blob to parse -+ * @size: The size of the data blob -+ * @keyring: The keyring to add extracted keys to -+ */ -+int __init parse_efi_signature_list(const void *data, size_t size, struct key *keyring) -+{ -+ unsigned offs = 0; -+ size_t lsize, esize, hsize, elsize; -+ -+ pr_devel("-->%s(,%zu)\n", __func__, size); -+ -+ while (size > 0) { -+ efi_signature_list_t list; -+ const efi_signature_data_t *elem; -+ key_ref_t key; -+ -+ if (size < sizeof(list)) -+ return -EBADMSG; -+ -+ memcpy(&list, data, sizeof(list)); -+ pr_devel("LIST[%04x] guid=%pUl ls=%x hs=%x ss=%x\n", -+ offs, -+ list.signature_type.b, list.signature_list_size, -+ list.signature_header_size, list.signature_size); -+ -+ lsize = list.signature_list_size; -+ hsize = list.signature_header_size; -+ esize = list.signature_size; -+ elsize = lsize - sizeof(list) - hsize; -+ -+ if (lsize > size) { -+ pr_devel("<--%s() = -EBADMSG [overrun @%x]\n", -+ __func__, offs); -+ return -EBADMSG; -+ } -+ if (lsize < sizeof(list) || -+ lsize - sizeof(list) < hsize || -+ esize < sizeof(*elem) || -+ elsize < esize || -+ elsize % esize != 0) { -+ pr_devel("- bad size combo @%x\n", offs); -+ return -EBADMSG; -+ } -+ -+ if (efi_guidcmp(list.signature_type, efi_cert_x509_guid) != 0) { -+ data += lsize; -+ size -= lsize; -+ offs += lsize; -+ continue; -+ } -+ -+ data += sizeof(list) + hsize; -+ size -= sizeof(list) + hsize; -+ offs += sizeof(list) + hsize; -+ -+ for (; elsize > 0; elsize -= esize) { -+ elem = data; -+ -+ pr_devel("ELEM[%04x]\n", offs); -+ -+ key = key_create_or_update( -+ make_key_ref(keyring, 1), -+ "asymmetric", -+ NULL, -+ &elem->signature_data, -+ esize - sizeof(*elem), -+ (KEY_POS_ALL & ~KEY_POS_SETATTR) | -+ KEY_USR_VIEW, -+ KEY_ALLOC_NOT_IN_QUOTA | -+ KEY_ALLOC_TRUSTED); -+ -+ if (IS_ERR(key)) -+ pr_err("Problem loading in-kernel X.509 certificate (%ld)\n", -+ PTR_ERR(key)); -+ else -+ pr_notice("Loaded cert '%s' linked to '%s'\n", -+ key_ref_to_ptr(key)->description, -+ keyring->description); -+ -+ data += esize; -+ size -= esize; -+ offs += esize; -+ } -+ } -+ -+ return 0; -+} -diff --git a/include/linux/efi.h b/include/linux/efi.h -index 3d66a61bbbca..7854ff3c0f11 100644 ---- a/include/linux/efi.h -+++ b/include/linux/efi.h -@@ -901,6 +901,10 @@ extern struct efi_memory_map memmap; - (md) <= (efi_memory_desc_t *)((m)->map_end - (m)->desc_size); \ - (md) = (void *)(md) + (m)->desc_size) - -+struct key; -+extern int __init parse_efi_signature_list(const void *data, size_t size, -+ struct key *keyring); -+ - /** - * efi_range_is_wc - check the WC bit on an address range - * @start: starting kvirt address --- -1.9.3 - - -From 2534dedee545507c00973279d5db515e122b5104 Mon Sep 17 00:00:00 2001 -From: Josh Boyer <jwboyer@fedoraproject.org> -Date: Fri, 26 Oct 2012 12:36:24 -0400 -Subject: [PATCH 3/5] KEYS: Add a system blacklist keyring - -This adds an additional keyring that is used to store certificates that -are blacklisted. This keyring is searched first when loading signed modules -and if the module's certificate is found, it will refuse to load. This is -useful in cases where third party certificates are used for module signing. - -Signed-off-by: Josh Boyer <jwboyer@fedoraproject.org> ---- - include/keys/system_keyring.h | 4 ++++ - init/Kconfig | 9 +++++++++ - kernel/module_signing.c | 12 ++++++++++++ - kernel/system_keyring.c | 17 +++++++++++++++++ - 4 files changed, 42 insertions(+) - -diff --git a/include/keys/system_keyring.h b/include/keys/system_keyring.h -index 8dabc399bd1d..e466de10ceec 100644 ---- a/include/keys/system_keyring.h -+++ b/include/keys/system_keyring.h -@@ -18,6 +18,10 @@ - - extern struct key *system_trusted_keyring; - -+#ifdef CONFIG_SYSTEM_BLACKLIST_KEYRING -+extern struct key *system_blacklist_keyring; -+#endif -+ - #endif - - #endif /* _KEYS_SYSTEM_KEYRING_H */ -diff --git a/init/Kconfig b/init/Kconfig -index 9d76b99af1b9..ac5f580437a0 100644 ---- a/init/Kconfig -+++ b/init/Kconfig -@@ -1677,6 +1677,15 @@ config SYSTEM_TRUSTED_KEYRING - - Keys in this keyring are used by module signature checking. - -+config SYSTEM_BLACKLIST_KEYRING -+ bool "Provide system-wide ring of blacklisted keys" -+ depends on KEYS -+ help -+ Provide a system keyring to which blacklisted keys can be added. -+ Keys in the keyring are considered entirely untrusted. Keys in this -+ keyring are used by the module signature checking to reject loading -+ of modules signed with a blacklisted key. -+ - config PROFILING - bool "Profiling support" - help -diff --git a/kernel/module_signing.c b/kernel/module_signing.c -index be5b8fac4bd0..fed815fcdaf2 100644 ---- a/kernel/module_signing.c -+++ b/kernel/module_signing.c -@@ -158,6 +158,18 @@ static struct key *request_asymmetric_key(const char *signer, size_t signer_len, - - pr_debug("Look up: \"%s\"\n", id); - -+#ifdef CONFIG_SYSTEM_BLACKLIST_KEYRING -+ key = keyring_search(make_key_ref(system_blacklist_keyring, 1), -+ &key_type_asymmetric, id); -+ if (!IS_ERR(key)) { -+ /* module is signed with a cert in the blacklist. reject */ -+ pr_err("Module key '%s' is in blacklist\n", id); -+ key_ref_put(key); -+ kfree(id); -+ return ERR_PTR(-EKEYREJECTED); -+ } -+#endif -+ - key = keyring_search(make_key_ref(system_trusted_keyring, 1), - &key_type_asymmetric, id); - if (IS_ERR(key)) -diff --git a/kernel/system_keyring.c b/kernel/system_keyring.c -index 52ebc70263f4..478c4f8ec908 100644 ---- a/kernel/system_keyring.c -+++ b/kernel/system_keyring.c -@@ -20,6 +20,9 @@ - - struct key *system_trusted_keyring; - EXPORT_SYMBOL_GPL(system_trusted_keyring); -+#ifdef CONFIG_SYSTEM_BLACKLIST_KEYRING -+struct key *system_blacklist_keyring; -+#endif - - extern __initconst const u8 system_certificate_list[]; - extern __initconst const unsigned long system_certificate_list_size; -@@ -41,6 +44,20 @@ static __init int system_trusted_keyring_init(void) - panic("Can't allocate system trusted keyring\n"); - - set_bit(KEY_FLAG_TRUSTED_ONLY, &system_trusted_keyring->flags); -+ -+#ifdef CONFIG_SYSTEM_BLACKLIST_KEYRING -+ system_blacklist_keyring = keyring_alloc(".system_blacklist_keyring", -+ KUIDT_INIT(0), KGIDT_INIT(0), -+ current_cred(), -+ (KEY_POS_ALL & ~KEY_POS_SETATTR) | -+ KEY_USR_VIEW | KEY_USR_READ, -+ KEY_ALLOC_NOT_IN_QUOTA, NULL); -+ if (IS_ERR(system_blacklist_keyring)) -+ panic("Can't allocate system blacklist keyring\n"); -+ -+ set_bit(KEY_FLAG_TRUSTED_ONLY, &system_blacklist_keyring->flags); -+#endif -+ - return 0; - } - --- -1.9.3 - - -From a72ed58241f0d62b7f9fbf4e1fbbcc1e02145098 Mon Sep 17 00:00:00 2001 -From: Josh Boyer <jwboyer@fedoraproject.org> -Date: Fri, 26 Oct 2012 12:42:16 -0400 -Subject: [PATCH 4/5] MODSIGN: Import certificates from UEFI Secure Boot - -Secure Boot stores a list of allowed certificates in the 'db' variable. -This imports those certificates into the system trusted keyring. This -allows for a third party signing certificate to be used in conjunction -with signed modules. By importing the public certificate into the 'db' -variable, a user can allow a module signed with that certificate to -load. The shim UEFI bootloader has a similar certificate list stored -in the 'MokListRT' variable. We import those as well. - -In the opposite case, Secure Boot maintains a list of disallowed -certificates in the 'dbx' variable. We load those certificates into -the newly introduced system blacklist keyring and forbid any module -signed with those from loading. - -Signed-off-by: Josh Boyer <jwboyer@fedoraproject.org> ---- - include/linux/efi.h | 6 ++++ - init/Kconfig | 9 +++++ - kernel/Makefile | 3 ++ - kernel/modsign_uefi.c | 92 +++++++++++++++++++++++++++++++++++++++++++++++++++ - 4 files changed, 110 insertions(+) - create mode 100644 kernel/modsign_uefi.c - -diff --git a/include/linux/efi.h b/include/linux/efi.h -index 7854ff3c0f11..31fd75e7230b 100644 ---- a/include/linux/efi.h -+++ b/include/linux/efi.h -@@ -584,6 +584,12 @@ typedef efi_status_t efi_query_variable_store_t(u32 attributes, unsigned long si - #define EFI_CERT_X509_GUID \ - EFI_GUID( 0xa5c059a1, 0x94e4, 0x4aa7, 0x87, 0xb5, 0xab, 0x15, 0x5c, 0x2b, 0xf0, 0x72 ) - -+#define EFI_IMAGE_SECURITY_DATABASE_GUID \ -+ EFI_GUID( 0xd719b2cb, 0x3d3a, 0x4596, 0xa3, 0xbc, 0xda, 0xd0, 0x0e, 0x67, 0x65, 0x6f ) -+ -+#define EFI_SHIM_LOCK_GUID \ -+ EFI_GUID( 0x605dab50, 0xe046, 0x4300, 0xab, 0xb6, 0x3d, 0xd8, 0x10, 0xdd, 0x8b, 0x23 ) -+ - typedef struct { - efi_guid_t guid; - u64 table; -diff --git a/init/Kconfig b/init/Kconfig -index ac5f580437a0..ca7268b594aa 100644 ---- a/init/Kconfig -+++ b/init/Kconfig -@@ -1831,6 +1831,15 @@ config MODULE_SIG_ALL - comment "Do not forget to sign required modules with scripts/sign-file" - depends on MODULE_SIG_FORCE && !MODULE_SIG_ALL - -+config MODULE_SIG_UEFI -+ bool "Allow modules signed with certs stored in UEFI" -+ depends on MODULE_SIG && SYSTEM_BLACKLIST_KEYRING && EFI -+ select EFI_SIGNATURE_LIST_PARSER -+ help -+ This will import certificates stored in UEFI and allow modules -+ signed with those to be loaded. It will also disallow loading -+ of modules stored in the UEFI dbx variable. -+ - choice - prompt "Which hash algorithm should modules be signed with?" - depends on MODULE_SIG -diff --git a/kernel/Makefile b/kernel/Makefile -index f2a8b6246ce9..706e7952bde5 100644 ---- a/kernel/Makefile -+++ b/kernel/Makefile -@@ -46,6 +46,7 @@ obj-$(CONFIG_UID16) += uid16.o - obj-$(CONFIG_SYSTEM_TRUSTED_KEYRING) += system_keyring.o system_certificates.o - obj-$(CONFIG_MODULES) += module.o - obj-$(CONFIG_MODULE_SIG) += module_signing.o -+obj-$(CONFIG_MODULE_SIG_UEFI) += modsign_uefi.o - obj-$(CONFIG_KALLSYMS) += kallsyms.o - obj-$(CONFIG_BSD_PROCESS_ACCT) += acct.o - obj-$(CONFIG_KEXEC) += kexec.o -@@ -99,6 +100,8 @@ obj-$(CONFIG_TORTURE_TEST) += torture.o - - $(obj)/configs.o: $(obj)/config_data.h - -+$(obj)/modsign_uefi.o: KBUILD_CFLAGS += -fshort-wchar -+ - # config_data.h contains the same information as ikconfig.h but gzipped. - # Info from config_data can be extracted from /proc/config* - targets += config_data.gz -diff --git a/kernel/modsign_uefi.c b/kernel/modsign_uefi.c -new file mode 100644 -index 000000000000..94b0eb38a284 ---- /dev/null -+++ b/kernel/modsign_uefi.c -@@ -0,0 +1,92 @@ -+#include <linux/kernel.h> -+#include <linux/sched.h> -+#include <linux/cred.h> -+#include <linux/err.h> -+#include <linux/efi.h> -+#include <linux/slab.h> -+#include <keys/asymmetric-type.h> -+#include <keys/system_keyring.h> -+#include "module-internal.h" -+ -+static __init void *get_cert_list(efi_char16_t *name, efi_guid_t *guid, unsigned long *size) -+{ -+ efi_status_t status; -+ unsigned long lsize = 4; -+ unsigned long tmpdb[4]; -+ void *db = NULL; -+ -+ status = efi.get_variable(name, guid, NULL, &lsize, &tmpdb); -+ if (status != EFI_BUFFER_TOO_SMALL) { -+ pr_err("Couldn't get size: 0x%lx\n", status); -+ return NULL; -+ } -+ -+ db = kmalloc(lsize, GFP_KERNEL); -+ if (!db) { -+ pr_err("Couldn't allocate memory for uefi cert list\n"); -+ goto out; -+ } -+ -+ status = efi.get_variable(name, guid, NULL, &lsize, db); -+ if (status != EFI_SUCCESS) { -+ kfree(db); -+ db = NULL; -+ pr_err("Error reading db var: 0x%lx\n", status); -+ } -+out: -+ *size = lsize; -+ return db; -+} -+ -+/* -+ * * Load the certs contained in the UEFI databases -+ * */ -+static int __init load_uefi_certs(void) -+{ -+ efi_guid_t secure_var = EFI_IMAGE_SECURITY_DATABASE_GUID; -+ efi_guid_t mok_var = EFI_SHIM_LOCK_GUID; -+ void *db = NULL, *dbx = NULL, *mok = NULL; -+ unsigned long dbsize = 0, dbxsize = 0, moksize = 0; -+ int rc = 0; -+ -+ /* Check if SB is enabled and just return if not */ -+ if (!efi_enabled(EFI_SECURE_BOOT)) -+ return 0; -+ -+ /* Get db, MokListRT, and dbx. They might not exist, so it isn't -+ * an error if we can't get them. -+ */ -+ db = get_cert_list(L"db", &secure_var, &dbsize); -+ if (!db) { -+ pr_err("MODSIGN: Couldn't get UEFI db list\n"); -+ } else { -+ rc = parse_efi_signature_list(db, dbsize, system_trusted_keyring); -+ if (rc) -+ pr_err("Couldn't parse db signatures: %d\n", rc); -+ kfree(db); -+ } -+ -+ mok = get_cert_list(L"MokListRT", &mok_var, &moksize); -+ if (!mok) { -+ pr_info("MODSIGN: Couldn't get UEFI MokListRT\n"); -+ } else { -+ rc = parse_efi_signature_list(mok, moksize, system_trusted_keyring); -+ if (rc) -+ pr_err("Couldn't parse MokListRT signatures: %d\n", rc); -+ kfree(mok); -+ } -+ -+ dbx = get_cert_list(L"dbx", &secure_var, &dbxsize); -+ if (!dbx) { -+ pr_info("MODSIGN: Couldn't get UEFI dbx list\n"); -+ } else { -+ rc = parse_efi_signature_list(dbx, dbxsize, -+ system_blacklist_keyring); -+ if (rc) -+ pr_err("Couldn't parse dbx signatures: %d\n", rc); -+ kfree(dbx); -+ } -+ -+ return rc; -+} -+late_initcall(load_uefi_certs); --- -1.9.3 - - -From 11bb98e3a62de77fc66a3e2197578dd9d891b998 Mon Sep 17 00:00:00 2001 -From: Josh Boyer <jwboyer@fedoraproject.org> -Date: Thu, 3 Oct 2013 10:14:23 -0400 -Subject: [PATCH 5/5] MODSIGN: Support not importing certs from db - -If a user tells shim to not use the certs/hashes in the UEFI db variable -for verification purposes, shim will set a UEFI variable called MokIgnoreDB. -Have the uefi import code look for this and not import things from the db -variable. - -Signed-off-by: Josh Boyer <jwboyer@fedoraproject.org> ---- - kernel/modsign_uefi.c | 40 +++++++++++++++++++++++++++++++--------- - 1 file changed, 31 insertions(+), 9 deletions(-) - -diff --git a/kernel/modsign_uefi.c b/kernel/modsign_uefi.c -index 94b0eb38a284..ae28b974d49a 100644 ---- a/kernel/modsign_uefi.c -+++ b/kernel/modsign_uefi.c -@@ -8,6 +8,23 @@ - #include <keys/system_keyring.h> - #include "module-internal.h" - -+static __init int check_ignore_db(void) -+{ -+ efi_status_t status; -+ unsigned int db = 0; -+ unsigned long size = sizeof(db); -+ efi_guid_t guid = EFI_SHIM_LOCK_GUID; -+ -+ /* Check and see if the MokIgnoreDB variable exists. If that fails -+ * then we don't ignore DB. If it succeeds, we do. -+ */ -+ status = efi.get_variable(L"MokIgnoreDB", &guid, NULL, &size, &db); -+ if (status != EFI_SUCCESS) -+ return 0; -+ -+ return 1; -+} -+ - static __init void *get_cert_list(efi_char16_t *name, efi_guid_t *guid, unsigned long *size) - { - efi_status_t status; -@@ -47,23 +64,28 @@ static int __init load_uefi_certs(void) - efi_guid_t mok_var = EFI_SHIM_LOCK_GUID; - void *db = NULL, *dbx = NULL, *mok = NULL; - unsigned long dbsize = 0, dbxsize = 0, moksize = 0; -- int rc = 0; -+ int ignore_db, rc = 0; - - /* Check if SB is enabled and just return if not */ - if (!efi_enabled(EFI_SECURE_BOOT)) - return 0; - -+ /* See if the user has setup Ignore DB mode */ -+ ignore_db = check_ignore_db(); -+ - /* Get db, MokListRT, and dbx. They might not exist, so it isn't - * an error if we can't get them. - */ -- db = get_cert_list(L"db", &secure_var, &dbsize); -- if (!db) { -- pr_err("MODSIGN: Couldn't get UEFI db list\n"); -- } else { -- rc = parse_efi_signature_list(db, dbsize, system_trusted_keyring); -- if (rc) -- pr_err("Couldn't parse db signatures: %d\n", rc); -- kfree(db); -+ if (!ignore_db) { -+ db = get_cert_list(L"db", &secure_var, &dbsize); -+ if (!db) { -+ pr_err("MODSIGN: Couldn't get UEFI db list\n"); -+ } else { -+ rc = parse_efi_signature_list(db, dbsize, system_trusted_keyring); -+ if (rc) -+ pr_err("Couldn't parse db signatures: %d\n", rc); -+ kfree(db); -+ } - } - - mok = get_cert_list(L"MokListRT", &mok_var, &moksize); --- -1.9.3 - diff --git a/no-pcspkr-modalias.patch b/no-pcspkr-modalias.patch index 701178b5..15bbe14d 100644 --- a/no-pcspkr-modalias.patch +++ b/no-pcspkr-modalias.patch @@ -1,11 +1,18 @@ +From: "kernel-team@fedoraproject.org" <kernel-team@fedoraproject.org> +Date: Thu, 29 Jul 2010 16:46:31 -0700 +Subject: [PATCH] no pcspkr modalias + Bugzilla: N/A Upstream-status: Fedora mustard +--- + drivers/input/misc/pcspkr.c | 1 - + 1 file changed, 1 deletion(-) diff --git a/drivers/input/misc/pcspkr.c b/drivers/input/misc/pcspkr.c -index 34f4d2e..3e40c70 100644 +index 674a2cfc3c0e..9a2807227c69 100644 --- a/drivers/input/misc/pcspkr.c +++ b/drivers/input/misc/pcspkr.c -@@ -24,7 +24,6 @@ +@@ -23,7 +23,6 @@ MODULE_AUTHOR("Vojtech Pavlik <vojtech@ucw.cz>"); MODULE_DESCRIPTION("PC Speaker beeper driver"); MODULE_LICENSE("GPL"); @@ -13,3 +20,6 @@ index 34f4d2e..3e40c70 100644 static int pcspkr_event(struct input_dev *dev, unsigned int type, unsigned int code, int value) { +-- +1.9.3 + diff --git a/perf-install-trace-event-plugins.patch b/perf-install-trace-event-plugins.patch new file mode 100644 index 00000000..9a7ad3aa --- /dev/null +++ b/perf-install-trace-event-plugins.patch @@ -0,0 +1,30 @@ +From: Kyle McMartin <kmcmarti@redhat.com> +Date: Mon, 2 Jun 2014 15:11:01 -0400 +Subject: [PATCH] perf: install trace-event plugins + +perf hardcodes $libdir to be lib for all but x86_64, so kludge around it +until upstream gets their act together. +--- + tools/perf/config/Makefile | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/tools/perf/config/Makefile b/tools/perf/config/Makefile +index 86c21a24da46..bf0fe97bd358 100644 +--- a/tools/perf/config/Makefile ++++ b/tools/perf/config/Makefile +@@ -642,8 +642,12 @@ endif + ifeq ($(IS_X86_64),1) + lib = lib64 + else ++ifdef MULTILIBDIR ++lib = $(MULTILIBDIR) ++else + lib = lib + endif ++endif + libdir = $(prefix)/$(lib) + + # Shell quote (do not use $(call) to accommodate ancient setups); +-- +1.9.3 + diff --git a/perf-lib64.patch b/perf-lib64.patch deleted file mode 100644 index 85790ba9..00000000 --- a/perf-lib64.patch +++ /dev/null @@ -1,17 +0,0 @@ -diff --git a/tools/perf/config/Makefile b/tools/perf/config/Makefile -index 802cf54..7f30bfa 100644 ---- a/tools/perf/config/Makefile -+++ b/tools/perf/config/Makefile -@@ -621,8 +621,12 @@ endif - ifeq ($(IS_X86_64),1) - lib = lib64 - else -+ifdef MULTILIBDIR -+lib = $(MULTILIBDIR) -+else - lib = lib - endif -+endif - libdir = $(prefix)/$(lib) - - # Shell quote (do not use $(call) to accommodate ancient setups); diff --git a/pinctrl-pinctrl-single-must-be-initialized-early.patch b/pinctrl-pinctrl-single-must-be-initialized-early.patch new file mode 100644 index 00000000..d19b75f5 --- /dev/null +++ b/pinctrl-pinctrl-single-must-be-initialized-early.patch @@ -0,0 +1,37 @@ +From: Pantelis Antoniou <panto@antoniou-consulting.com> +Date: Sat, 15 Sep 2012 12:00:41 +0300 +Subject: [PATCH] pinctrl: pinctrl-single must be initialized early. + +When using pinctrl-single to handle i2c initialization, it has +to be done early. Whether this is the best way to do so, is an +exercise left to the reader. +--- + drivers/pinctrl/pinctrl-single.c | 12 +++++++++++- + 1 file changed, 11 insertions(+), 1 deletion(-) + +diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c +index 95dd9cf55cb3..800fc34d7ea9 100644 +--- a/drivers/pinctrl/pinctrl-single.c ++++ b/drivers/pinctrl/pinctrl-single.c +@@ -2012,7 +2012,17 @@ static struct platform_driver pcs_driver = { + #endif + }; + +-module_platform_driver(pcs_driver); ++static int __init pcs_init(void) ++{ ++ return platform_driver_register(&pcs_driver); ++} ++postcore_initcall(pcs_init); ++ ++static void __exit pcs_exit(void) ++{ ++ platform_driver_unregister(&pcs_driver); ++} ++module_exit(pcs_exit); + + MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>"); + MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver"); +-- +1.9.3 + diff --git a/ppc64-fixtools.patch b/ppc64-fixtools.patch new file mode 100644 index 00000000..f461d298 --- /dev/null +++ b/ppc64-fixtools.patch @@ -0,0 +1,12 @@ +diff --git a/tools/perf/arch/powerpc/util/skip-callchain-idx.c b/tools/perf/arch/powerpc/util/skip-callchain-idx.c +index a7c23a4..d73ef8b 100644 +--- a/tools/perf/arch/powerpc/util/skip-callchain-idx.c ++++ b/tools/perf/arch/powerpc/util/skip-callchain-idx.c +@@ -15,6 +15,7 @@ + + #include "util/thread.h" + #include "util/callchain.h" ++#include "util/debug.h" + + /* + * When saving the callchain on Power, the kernel conservatively saves diff --git a/psmouse-Add-psmouse_matches_pnp_id-helper-function.patch b/psmouse-Add-psmouse_matches_pnp_id-helper-function.patch index 899a20b5..59adceda 100644 --- a/psmouse-Add-psmouse_matches_pnp_id-helper-function.patch +++ b/psmouse-Add-psmouse_matches_pnp_id-helper-function.patch @@ -1,7 +1,6 @@ -From d0d1fbdb2d34a669ffbec814893696909381ac0e Mon Sep 17 00:00:00 2001 From: Hans de Goede <hdegoede@redhat.com> Date: Fri, 27 Jun 2014 18:46:42 +0200 -Subject: [PATCH 2/3] psmouse: Add psmouse_matches_pnp_id helper function +Subject: [PATCH] psmouse: Add psmouse_matches_pnp_id helper function The matches_pnp_id function from the synaptics driver is useful for other drivers too. Make it a generic psmouse helper function. @@ -17,7 +16,7 @@ Signed-off-by: Hans de Goede <hdegoede@redhat.com> 3 files changed, 18 insertions(+), 14 deletions(-) diff --git a/drivers/input/mouse/psmouse-base.c b/drivers/input/mouse/psmouse-base.c -index cff065f6261c..bc1bc2653f15 100644 +index b4e1f014ddc2..02e68c3008a3 100644 --- a/drivers/input/mouse/psmouse-base.c +++ b/drivers/input/mouse/psmouse-base.c @@ -462,6 +462,20 @@ static int psmouse_poll(struct psmouse *psmouse) @@ -54,7 +53,7 @@ index 2f0b39d59a9b..f4cf664c7db3 100644 struct psmouse_attribute { struct device_attribute dattr; diff --git a/drivers/input/mouse/synaptics.c b/drivers/input/mouse/synaptics.c -index e8573c68f77e..854caca6e86e 100644 +index fd23181c1fb7..6394d9b5bfd3 100644 --- a/drivers/input/mouse/synaptics.c +++ b/drivers/input/mouse/synaptics.c @@ -185,18 +185,6 @@ static const char * const topbuttonpad_pnp_ids[] = { @@ -86,7 +85,7 @@ index e8573c68f77e..854caca6e86e 100644 priv->x_min = min_max_pnpid_table[i].x_min; priv->x_max = min_max_pnpid_table[i].x_max; priv->y_min = min_max_pnpid_table[i].y_min; -@@ -1456,7 +1445,7 @@ static void set_input_params(struct psmouse *psmouse, +@@ -1492,7 +1481,7 @@ static void set_input_params(struct psmouse *psmouse, if (SYN_CAP_CLICKPAD(priv->ext_cap_0c)) { __set_bit(INPUT_PROP_BUTTONPAD, dev->propbit); diff --git a/psmouse-Add-support-for-detecting-FocalTech-PS-2-tou.patch b/psmouse-Add-support-for-detecting-FocalTech-PS-2-tou.patch index 3282cc6b..0d0583d5 100644 --- a/psmouse-Add-support-for-detecting-FocalTech-PS-2-tou.patch +++ b/psmouse-Add-support-for-detecting-FocalTech-PS-2-tou.patch @@ -1,8 +1,6 @@ -From 4ab16f30317966f892342e8821a6dc26070d1a06 Mon Sep 17 00:00:00 2001 From: Hans de Goede <hdegoede@redhat.com> Date: Fri, 27 Jun 2014 18:50:33 +0200 -Subject: [PATCH 3/3] psmouse: Add support for detecting FocalTech PS/2 - touchpads +Subject: [PATCH] psmouse: Add support for detecting FocalTech PS/2 touchpads The Asus X450 and X550 laptops use a PS/2 touchpad from a new manufacturer called FocalTech: @@ -120,7 +118,7 @@ index 000000000000..0d0fc49451fe + +#endif diff --git a/drivers/input/mouse/psmouse-base.c b/drivers/input/mouse/psmouse-base.c -index bc1bc2653f15..0730209cddb0 100644 +index 02e68c3008a3..2c8c8e2172a2 100644 --- a/drivers/input/mouse/psmouse-base.c +++ b/drivers/input/mouse/psmouse-base.c @@ -35,6 +35,7 @@ @@ -131,7 +129,7 @@ index bc1bc2653f15..0730209cddb0 100644 #define DRIVER_DESC "PS/2 mouse driver" -@@ -720,6 +721,13 @@ static int psmouse_extensions(struct psmouse *psmouse, +@@ -722,6 +723,13 @@ static int psmouse_extensions(struct psmouse *psmouse, { bool synaptics_hardware = false; @@ -145,7 +143,7 @@ index bc1bc2653f15..0730209cddb0 100644 /* * We always check for lifebook because it does not disturb mouse * (it only checks DMI information). -@@ -871,6 +879,8 @@ static int psmouse_extensions(struct psmouse *psmouse, +@@ -873,6 +881,8 @@ static int psmouse_extensions(struct psmouse *psmouse, } } diff --git a/revert-input-wacom-testing-result-shows-get_report-is-unnecessary.patch b/revert-input-wacom-testing-result-shows-get_report-is-unnecessary.patch deleted file mode 100644 index f9f4a72a..00000000 --- a/revert-input-wacom-testing-result-shows-get_report-is-unnecessary.patch +++ /dev/null @@ -1,40 +0,0 @@ -Bugzilla: N/A -Upstream-status: Sent upstream - -This reverts commit 1b2faaf7e219fc2905d75afcd4c815e5d39eda80. - -The Intuos4 series presents a bug in which it hangs if it receives -a set feature command while switching to the enhanced mode. -This bug is triggered when plugging an Intuos 4 while having -a gnome user session up and running. - -Signed-off-by: Benjamin Tissoires <benjamin.tissoires@xxxxxxxxxx> ---- - -Hi Aris, - -actually, you bisected the bug, so can I consider that I have your signed-off-by? - -Cheers, -Benjamin - - drivers/input/tablet/wacom_sys.c | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/drivers/input/tablet/wacom_sys.c b/drivers/input/tablet/wacom_sys.c -index 7087b33..319a3ff 100644 ---- a/drivers/input/tablet/wacom_sys.c -+++ b/drivers/input/tablet/wacom_sys.c -@@ -536,6 +536,9 @@ static int wacom_set_device_mode(struct usb_interface *intf, int report_id, int - - error = wacom_set_report(intf, WAC_HID_FEATURE_REPORT, - report_id, rep_data, length, 1); -+ if (error >= 0) -+ error = wacom_get_report(intf, WAC_HID_FEATURE_REPORT, -+ report_id, rep_data, length, 1); - } while ((error < 0 || rep_data[1] != mode) && limit++ < WAC_MSG_RETRIES); - - kfree(rep_data); --- -1.9.0 - diff --git a/samsung-laptop-Add-broken-acpi-video-quirk-for-NC210.patch b/samsung-laptop-Add-broken-acpi-video-quirk-for-NC210.patch index 93c4073c..3dd7bc14 100644 --- a/samsung-laptop-Add-broken-acpi-video-quirk-for-NC210.patch +++ b/samsung-laptop-Add-broken-acpi-video-quirk-for-NC210.patch @@ -1,21 +1,18 @@ -Bugzilla: 861573 -Upstream-status: Waiting for feedback from reporter - -From 2fa2078cdd4198b49c02cb03087158d398476463 Mon Sep 17 00:00:00 2001 From: Hans de Goede <hdegoede@redhat.com> Date: Mon, 2 Jun 2014 17:40:59 +0200 -Subject: [PATCH 02/14] samsung-laptop: Add broken-acpi-video quirk for - NC210/NC110 +Subject: [PATCH] samsung-laptop: Add broken-acpi-video quirk for NC210/NC110 Reported (and tested) here: https://bugzilla.redhat.com/show_bug.cgi?id=861573 +Bugzilla: 861573 +Upstream-status: Waiting for feedback from reporter + Signed-off-by: Hans de Goede <hdegoede@redhat.com> --- drivers/platform/x86/samsung-laptop.c | 10 ++++++++++ 1 file changed, 10 insertions(+) - diff --git a/drivers/platform/x86/samsung-laptop.c b/drivers/platform/x86/samsung-laptop.c index 5a5966512277..0d7954e0fc74 100644 --- a/drivers/platform/x86/samsung-laptop.c @@ -37,3 +34,6 @@ index 5a5966512277..0d7954e0fc74 100644 { }, }; MODULE_DEVICE_TABLE(dmi, samsung_dmi_table); +-- +1.9.3 + diff --git a/scsi-sd_revalidate_disk-prevent-NULL-ptr-deref.patch b/scsi-sd_revalidate_disk-prevent-NULL-ptr-deref.patch index 2cdbc31f..9dad35ce 100644 --- a/scsi-sd_revalidate_disk-prevent-NULL-ptr-deref.patch +++ b/scsi-sd_revalidate_disk-prevent-NULL-ptr-deref.patch @@ -1,16 +1,25 @@ +From: "kernel-team@fedoraproject.org" <kernel-team@fedoraproject.org> +Date: Fri, 10 Feb 2012 14:56:13 -0500 +Subject: [PATCH] scsi: sd_revalidate_disk prevent NULL ptr deref + Bugzilla: 754518 Upstream-status: Fedora mustard (might be worth dropping...) +--- + drivers/scsi/sd.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) ---- a/drivers/scsi/sd.c -+++ a/drivers/scsi/sd.c -@@ -2362,13 +2362,18 @@ static int sd_try_extended_inquiry(struct scsi_device *sdp) +diff --git a/drivers/scsi/sd.c b/drivers/scsi/sd.c +index 2c2041ca4b70..e10812d985af 100644 +--- a/drivers/scsi/sd.c ++++ b/drivers/scsi/sd.c +@@ -2749,13 +2749,18 @@ static int sd_try_extended_inquiry(struct scsi_device *sdp) static int sd_revalidate_disk(struct gendisk *disk) { struct scsi_disk *sdkp = scsi_disk(disk); - struct scsi_device *sdp = sdkp->device; + struct scsi_device *sdp; unsigned char *buffer; - unsigned flush = 0; + unsigned int max_xfer; SCSI_LOG_HLQUEUE(3, sd_printk(KERN_INFO, sdkp, "sd_revalidate_disk\n")); @@ -23,3 +32,6 @@ Upstream-status: Fedora mustard (might be worth dropping...) /* * If the device is offline, don't try and read capacity or any * of the other niceties. +-- +1.9.3 + diff --git a/secure-modules.patch b/secure-modules.patch deleted file mode 100644 index 2d3174c2..00000000 --- a/secure-modules.patch +++ /dev/null @@ -1,877 +0,0 @@ -Bugzilla: N/A -Upstream-status: Fedora mustard. Replaced by securelevels, but that was nak'd - -From 952dbcbea4cffb1a05773af3b5f41e8ed477c5fe Mon Sep 17 00:00:00 2001 -From: Matthew Garrett <matthew.garrett@nebula.com> -Date: Fri, 9 Aug 2013 17:58:15 -0400 -Subject: [PATCH 01/14] Add secure_modules() call - -Provide a single call to allow kernel code to determine whether the system -has been configured to either disable module loading entirely or to load -only modules signed with a trusted key. - -Signed-off-by: Matthew Garrett <matthew.garrett@nebula.com> ---- - include/linux/module.h | 7 +++++++ - kernel/module.c | 10 ++++++++++ - 2 files changed, 17 insertions(+) - -diff --git a/include/linux/module.h b/include/linux/module.h -index f520a767c86c..fc9b54eb779e 100644 ---- a/include/linux/module.h -+++ b/include/linux/module.h -@@ -509,6 +509,8 @@ int unregister_module_notifier(struct notifier_block *nb); - - extern void print_modules(void); - -+extern bool secure_modules(void); -+ - #else /* !CONFIG_MODULES... */ - - /* Given an address, look for it in the exception tables. */ -@@ -619,6 +621,11 @@ static inline int unregister_module_notifier(struct notifier_block *nb) - static inline void print_modules(void) - { - } -+ -+static inline bool secure_modules(void) -+{ -+ return false; -+} - #endif /* CONFIG_MODULES */ - - #ifdef CONFIG_SYSFS -diff --git a/kernel/module.c b/kernel/module.c -index 81e727cf6df9..fc14f48915dd 100644 ---- a/kernel/module.c -+++ b/kernel/module.c -@@ -3843,3 +3843,13 @@ void module_layout(struct module *mod, - } - EXPORT_SYMBOL(module_layout); - #endif -+ -+bool secure_modules(void) -+{ -+#ifdef CONFIG_MODULE_SIG -+ return (sig_enforce || modules_disabled); -+#else -+ return modules_disabled; -+#endif -+} -+EXPORT_SYMBOL(secure_modules); --- -1.9.3 - - -From 3b451a12e60a47d152ecce1c02634c4d7320b024 Mon Sep 17 00:00:00 2001 -From: Matthew Garrett <matthew.garrett@nebula.com> -Date: Thu, 8 Mar 2012 10:10:38 -0500 -Subject: [PATCH 02/14] PCI: Lock down BAR access when module security is - enabled - -Any hardware that can potentially generate DMA has to be locked down from -userspace in order to avoid it being possible for an attacker to modify -kernel code, allowing them to circumvent disabled module loading or module -signing. Default to paranoid - in future we can potentially relax this for -sufficiently IOMMU-isolated devices. - -Signed-off-by: Matthew Garrett <matthew.garrett@nebula.com> ---- - drivers/pci/pci-sysfs.c | 10 ++++++++++ - drivers/pci/proc.c | 8 +++++++- - drivers/pci/syscall.c | 3 ++- - 3 files changed, 19 insertions(+), 2 deletions(-) - -diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c -index 9ff0a901ecf7..8d0d5d92b8d9 100644 ---- a/drivers/pci/pci-sysfs.c -+++ b/drivers/pci/pci-sysfs.c -@@ -30,6 +30,7 @@ - #include <linux/vgaarb.h> - #include <linux/pm_runtime.h> - #include <linux/of.h> -+#include <linux/module.h> - #include "pci.h" - - static int sysfs_initialized; /* = 0 */ -@@ -704,6 +705,9 @@ static ssize_t pci_write_config(struct file *filp, struct kobject *kobj, - loff_t init_off = off; - u8 *data = (u8 *) buf; - -+ if (secure_modules()) -+ return -EPERM; -+ - if (off > dev->cfg_size) - return 0; - if (off + count > dev->cfg_size) { -@@ -998,6 +1002,9 @@ static int pci_mmap_resource(struct kobject *kobj, struct bin_attribute *attr, - resource_size_t start, end; - int i; - -+ if (secure_modules()) -+ return -EPERM; -+ - for (i = 0; i < PCI_ROM_RESOURCE; i++) - if (res == &pdev->resource[i]) - break; -@@ -1099,6 +1106,9 @@ static ssize_t pci_write_resource_io(struct file *filp, struct kobject *kobj, - struct bin_attribute *attr, char *buf, - loff_t off, size_t count) - { -+ if (secure_modules()) -+ return -EPERM; -+ - return pci_resource_io(filp, kobj, attr, buf, off, count, true); - } - -diff --git a/drivers/pci/proc.c b/drivers/pci/proc.c -index 3f155e78513f..4265ea07e3b0 100644 ---- a/drivers/pci/proc.c -+++ b/drivers/pci/proc.c -@@ -116,6 +116,9 @@ static ssize_t proc_bus_pci_write(struct file *file, const char __user *buf, - int size = dev->cfg_size; - int cnt; - -+ if (secure_modules()) -+ return -EPERM; -+ - if (pos >= size) - return 0; - if (nbytes >= size) -@@ -195,6 +198,9 @@ static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd, - #endif /* HAVE_PCI_MMAP */ - int ret = 0; - -+ if (secure_modules()) -+ return -EPERM; -+ - switch (cmd) { - case PCIIOC_CONTROLLER: - ret = pci_domain_nr(dev->bus); -@@ -233,7 +239,7 @@ static int proc_bus_pci_mmap(struct file *file, struct vm_area_struct *vma) - struct pci_filp_private *fpriv = file->private_data; - int i, ret; - -- if (!capable(CAP_SYS_RAWIO)) -+ if (!capable(CAP_SYS_RAWIO) || secure_modules()) - return -EPERM; - - /* Make sure the caller is mapping a real resource for this device */ -diff --git a/drivers/pci/syscall.c b/drivers/pci/syscall.c -index b91c4da68365..98f5637304d1 100644 ---- a/drivers/pci/syscall.c -+++ b/drivers/pci/syscall.c -@@ -10,6 +10,7 @@ - #include <linux/errno.h> - #include <linux/pci.h> - #include <linux/syscalls.h> -+#include <linux/module.h> - #include <asm/uaccess.h> - #include "pci.h" - -@@ -92,7 +93,7 @@ SYSCALL_DEFINE5(pciconfig_write, unsigned long, bus, unsigned long, dfn, - u32 dword; - int err = 0; - -- if (!capable(CAP_SYS_ADMIN)) -+ if (!capable(CAP_SYS_ADMIN) || secure_modules()) - return -EPERM; - - dev = pci_get_bus_and_slot(bus, dfn); --- -1.9.3 - - -From 42a620055ac873fb378ec69731c7a2200f6779cc Mon Sep 17 00:00:00 2001 -From: Matthew Garrett <matthew.garrett@nebula.com> -Date: Thu, 8 Mar 2012 10:35:59 -0500 -Subject: [PATCH 03/14] x86: Lock down IO port access when module security is - enabled - -IO port access would permit users to gain access to PCI configuration -registers, which in turn (on a lot of hardware) give access to MMIO register -space. This would potentially permit root to trigger arbitrary DMA, so lock -it down by default. - -Signed-off-by: Matthew Garrett <matthew.garrett@nebula.com> ---- - arch/x86/kernel/ioport.c | 5 +++-- - drivers/char/mem.c | 4 ++++ - 2 files changed, 7 insertions(+), 2 deletions(-) - -diff --git a/arch/x86/kernel/ioport.c b/arch/x86/kernel/ioport.c -index 4ddaf66ea35f..00b440307419 100644 ---- a/arch/x86/kernel/ioport.c -+++ b/arch/x86/kernel/ioport.c -@@ -15,6 +15,7 @@ - #include <linux/thread_info.h> - #include <linux/syscalls.h> - #include <linux/bitmap.h> -+#include <linux/module.h> - #include <asm/syscalls.h> - - /* -@@ -28,7 +29,7 @@ asmlinkage long sys_ioperm(unsigned long from, unsigned long num, int turn_on) - - if ((from + num <= from) || (from + num > IO_BITMAP_BITS)) - return -EINVAL; -- if (turn_on && !capable(CAP_SYS_RAWIO)) -+ if (turn_on && (!capable(CAP_SYS_RAWIO) || secure_modules())) - return -EPERM; - - /* -@@ -103,7 +104,7 @@ SYSCALL_DEFINE1(iopl, unsigned int, level) - return -EINVAL; - /* Trying to gain more privileges? */ - if (level > old) { -- if (!capable(CAP_SYS_RAWIO)) -+ if (!capable(CAP_SYS_RAWIO) || secure_modules()) - return -EPERM; - } - regs->flags = (regs->flags & ~X86_EFLAGS_IOPL) | (level << 12); -diff --git a/drivers/char/mem.c b/drivers/char/mem.c -index 917403fe10da..cdf839f9defe 100644 ---- a/drivers/char/mem.c -+++ b/drivers/char/mem.c -@@ -27,6 +27,7 @@ - #include <linux/export.h> - #include <linux/io.h> - #include <linux/aio.h> -+#include <linux/module.h> - - #include <asm/uaccess.h> - -@@ -568,6 +569,9 @@ static ssize_t write_port(struct file *file, const char __user *buf, - unsigned long i = *ppos; - const char __user *tmp = buf; - -+ if (secure_modules()) -+ return -EPERM; -+ - if (!access_ok(VERIFY_READ, buf, count)) - return -EFAULT; - while (count-- > 0 && i < 65536) { --- -1.9.3 - - -From 8019fb7c7b5f18b19f7c980987953680ee218c9f Mon Sep 17 00:00:00 2001 -From: Matthew Garrett <matthew.garrett@nebula.com> -Date: Fri, 9 Mar 2012 08:39:37 -0500 -Subject: [PATCH 04/14] ACPI: Limit access to custom_method - -custom_method effectively allows arbitrary access to system memory, making -it possible for an attacker to circumvent restrictions on module loading. -Disable it if any such restrictions have been enabled. - -Signed-off-by: Matthew Garrett <matthew.garrett@nebula.com> ---- - drivers/acpi/custom_method.c | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/drivers/acpi/custom_method.c b/drivers/acpi/custom_method.c -index c68e72414a67..4277938af700 100644 ---- a/drivers/acpi/custom_method.c -+++ b/drivers/acpi/custom_method.c -@@ -29,6 +29,9 @@ static ssize_t cm_write(struct file *file, const char __user * user_buf, - struct acpi_table_header table; - acpi_status status; - -+ if (secure_modules()) -+ return -EPERM; -+ - if (!(*ppos)) { - /* parse the table header to get the table length */ - if (count <= sizeof(struct acpi_table_header)) --- -1.9.3 - - -From bf84e9e1022b2d3d0c97ae48fb8b61e5336c50f8 Mon Sep 17 00:00:00 2001 -From: Matthew Garrett <matthew.garrett@nebula.com> -Date: Fri, 9 Mar 2012 08:46:50 -0500 -Subject: [PATCH 05/14] asus-wmi: Restrict debugfs interface when module - loading is restricted - -We have no way of validating what all of the Asus WMI methods do on a -given machine, and there's a risk that some will allow hardware state to -be manipulated in such a way that arbitrary code can be executed in the -kernel, circumventing module loading restrictions. Prevent that if any of -these features are enabled. - -Signed-off-by: Matthew Garrett <matthew.garrett@nebula.com> ---- - drivers/platform/x86/asus-wmi.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/drivers/platform/x86/asus-wmi.c b/drivers/platform/x86/asus-wmi.c -index 3c6ccedc82b6..960c46536c65 100644 ---- a/drivers/platform/x86/asus-wmi.c -+++ b/drivers/platform/x86/asus-wmi.c -@@ -1592,6 +1592,9 @@ static int show_dsts(struct seq_file *m, void *data) - int err; - u32 retval = -1; - -+ if (secure_modules()) -+ return -EPERM; -+ - err = asus_wmi_get_devstate(asus, asus->debug.dev_id, &retval); - - if (err < 0) -@@ -1608,6 +1611,9 @@ static int show_devs(struct seq_file *m, void *data) - int err; - u32 retval = -1; - -+ if (secure_modules()) -+ return -EPERM; -+ - err = asus_wmi_set_devstate(asus->debug.dev_id, asus->debug.ctrl_param, - &retval); - -@@ -1632,6 +1638,9 @@ static int show_call(struct seq_file *m, void *data) - union acpi_object *obj; - acpi_status status; - -+ if (secure_modules()) -+ return -EPERM; -+ - status = wmi_evaluate_method(ASUS_WMI_MGMT_GUID, - 1, asus->debug.method_id, - &input, &output); --- -1.9.3 - - -From 9a56e8715d3b6dc84989997f34b6b5d407cabad2 Mon Sep 17 00:00:00 2001 -From: Matthew Garrett <matthew.garrett@nebula.com> -Date: Fri, 9 Mar 2012 09:28:15 -0500 -Subject: [PATCH 06/14] Restrict /dev/mem and /dev/kmem when module loading is - restricted - -Allowing users to write to address space makes it possible for the kernel -to be subverted, avoiding module loading restrictions. Prevent this when -any restrictions have been imposed on loading modules. - -Signed-off-by: Matthew Garrett <matthew.garrett@nebula.com> ---- - drivers/char/mem.c | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/drivers/char/mem.c b/drivers/char/mem.c -index cdf839f9defe..c63cf93b00eb 100644 ---- a/drivers/char/mem.c -+++ b/drivers/char/mem.c -@@ -164,6 +164,9 @@ static ssize_t write_mem(struct file *file, const char __user *buf, - if (p != *ppos) - return -EFBIG; - -+ if (secure_modules()) -+ return -EPERM; -+ - if (!valid_phys_addr_range(p, count)) - return -EFAULT; - -@@ -502,6 +505,9 @@ static ssize_t write_kmem(struct file *file, const char __user *buf, - char *kbuf; /* k-addr because vwrite() takes vmlist_lock rwlock */ - int err = 0; - -+ if (secure_modules()) -+ return -EPERM; -+ - if (p < (unsigned long) high_memory) { - unsigned long to_write = min_t(unsigned long, count, - (unsigned long)high_memory - p); --- -1.9.3 - - -From 8d6faa19bbbaa4df411becda7e40c4ea0684c134 Mon Sep 17 00:00:00 2001 -From: Josh Boyer <jwboyer@redhat.com> -Date: Mon, 25 Jun 2012 19:57:30 -0400 -Subject: [PATCH 07/14] acpi: Ignore acpi_rsdp kernel parameter when module - loading is restricted - -This option allows userspace to pass the RSDP address to the kernel, which -makes it possible for a user to circumvent any restrictions imposed on -loading modules. Disable it in that case. - -Signed-off-by: Josh Boyer <jwboyer@redhat.com> ---- - drivers/acpi/osl.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c -index bad25b070fe0..0606585e8b93 100644 ---- a/drivers/acpi/osl.c -+++ b/drivers/acpi/osl.c -@@ -44,6 +44,7 @@ - #include <linux/list.h> - #include <linux/jiffies.h> - #include <linux/semaphore.h> -+#include <linux/module.h> - - #include <asm/io.h> - #include <asm/uaccess.h> -@@ -245,7 +246,7 @@ early_param("acpi_rsdp", setup_acpi_rsdp); - acpi_physical_address __init acpi_os_get_root_pointer(void) - { - #ifdef CONFIG_KEXEC -- if (acpi_rsdp) -+ if (acpi_rsdp && !secure_modules()) - return acpi_rsdp; - #endif - --- -1.9.3 - - -From 1ff86ddea019f543f6668b56889f86811028f303 Mon Sep 17 00:00:00 2001 -From: Matthew Garrett <matthew.garrett@nebula.com> -Date: Fri, 9 Aug 2013 03:33:56 -0400 -Subject: [PATCH 08/14] kexec: Disable at runtime if the kernel enforces module - loading restrictions - -kexec permits the loading and execution of arbitrary code in ring 0, which -is something that module signing enforcement is meant to prevent. It makes -sense to disable kexec in this situation. - -Signed-off-by: Matthew Garrett <matthew.garrett@nebula.com> ---- - kernel/kexec.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/kernel/kexec.c b/kernel/kexec.c -index 4b8f0c925884..df14daa323a9 100644 ---- a/kernel/kexec.c -+++ b/kernel/kexec.c -@@ -34,6 +34,7 @@ - #include <linux/syscore_ops.h> - #include <linux/compiler.h> - #include <linux/hugetlb.h> -+#include <linux/module.h> - - #include <asm/page.h> - #include <asm/uaccess.h> -@@ -947,6 +948,13 @@ SYSCALL_DEFINE4(kexec_load, unsigned long, entry, unsigned long, nr_segments, - return -EPERM; - - /* -+ * kexec can be used to circumvent module loading restrictions, so -+ * prevent loading in that case -+ */ -+ if (secure_modules()) -+ return -EPERM; -+ -+ /* - * Verify we have a legal set of flags - * This leaves us room for future extensions. - */ --- -1.9.3 - - -From 4d56368f1364b45c18067bab1d6abc5ce0f67183 Mon Sep 17 00:00:00 2001 -From: Matthew Garrett <matthew.garrett@nebula.com> -Date: Fri, 8 Feb 2013 11:12:13 -0800 -Subject: [PATCH 09/14] x86: Restrict MSR access when module loading is - restricted - -Writing to MSRs should not be allowed if module loading is restricted, -since it could lead to execution of arbitrary code in kernel mode. Based -on a patch by Kees Cook. - -Cc: Kees Cook <keescook@chromium.org> -Signed-off-by: Matthew Garrett <matthew.garrett@nebula.com> ---- - arch/x86/kernel/msr.c | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/arch/x86/kernel/msr.c b/arch/x86/kernel/msr.c -index c9603ac80de5..8bef43fc3f40 100644 ---- a/arch/x86/kernel/msr.c -+++ b/arch/x86/kernel/msr.c -@@ -103,6 +103,9 @@ static ssize_t msr_write(struct file *file, const char __user *buf, - int err = 0; - ssize_t bytes = 0; - -+ if (secure_modules()) -+ return -EPERM; -+ - if (count % 8) - return -EINVAL; /* Invalid chunk size */ - -@@ -150,6 +153,10 @@ static long msr_ioctl(struct file *file, unsigned int ioc, unsigned long arg) - err = -EBADF; - break; - } -+ if (secure_modules()) { -+ err = -EPERM; -+ break; -+ } - if (copy_from_user(®s, uregs, sizeof regs)) { - err = -EFAULT; - break; --- -1.9.3 - - -From aab8ba85241a85a0b2ed622edd7874c74cafa496 Mon Sep 17 00:00:00 2001 -From: Matthew Garrett <matthew.garrett@nebula.com> -Date: Fri, 9 Aug 2013 18:36:30 -0400 -Subject: [PATCH 10/14] Add option to automatically enforce module signatures - when in Secure Boot mode - -UEFI Secure Boot provides a mechanism for ensuring that the firmware will -only load signed bootloaders and kernels. Certain use cases may also -require that all kernel modules also be signed. Add a configuration option -that enforces this automatically when enabled. - -Signed-off-by: Matthew Garrett <matthew.garrett@nebula.com> ---- - Documentation/x86/zero-page.txt | 2 ++ - arch/x86/Kconfig | 10 ++++++++++ - arch/x86/boot/compressed/eboot.c | 36 +++++++++++++++++++++++++++++++++++ - arch/x86/include/uapi/asm/bootparam.h | 3 ++- - arch/x86/kernel/setup.c | 6 ++++++ - include/linux/module.h | 6 ++++++ - kernel/module.c | 7 +++++++ - 7 files changed, 69 insertions(+), 1 deletion(-) - -diff --git a/Documentation/x86/zero-page.txt b/Documentation/x86/zero-page.txt -index 199f453cb4de..ec38acf00b40 100644 ---- a/Documentation/x86/zero-page.txt -+++ b/Documentation/x86/zero-page.txt -@@ -30,6 +30,8 @@ Offset Proto Name Meaning - 1E9/001 ALL eddbuf_entries Number of entries in eddbuf (below) - 1EA/001 ALL edd_mbr_sig_buf_entries Number of entries in edd_mbr_sig_buffer - (below) -+1EB/001 ALL kbd_status Numlock is enabled -+1EC/001 ALL secure_boot Secure boot is enabled in the firmware - 1EF/001 ALL sentinel Used to detect broken bootloaders - 290/040 ALL edd_mbr_sig_buffer EDD MBR signatures - 2D0/A00 ALL e820_map E820 memory map table -diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig -index d24887b645dc..870aac9520b3 100644 ---- a/arch/x86/Kconfig -+++ b/arch/x86/Kconfig -@@ -1557,6 +1557,16 @@ config EFI_MIXED - - If unsure, say N. - -+config EFI_SECURE_BOOT_SIG_ENFORCE -+ def_bool n -+ prompt "Force module signing when UEFI Secure Boot is enabled" -+ ---help--- -+ UEFI Secure Boot provides a mechanism for ensuring that the -+ firmware will only load signed bootloaders and kernels. Certain -+ use cases may also require that all kernel modules also be signed. -+ Say Y here to automatically enable module signature enforcement -+ when a system boots with UEFI Secure Boot enabled. -+ - config SECCOMP - def_bool y - prompt "Enable seccomp to safely compute untrusted bytecode" -diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c -index 0331d765c2bb..85defaf5a27c 100644 ---- a/arch/x86/boot/compressed/eboot.c -+++ b/arch/x86/boot/compressed/eboot.c -@@ -12,6 +12,7 @@ - #include <asm/efi.h> - #include <asm/setup.h> - #include <asm/desc.h> -+#include <asm/bootparam_utils.h> - - #undef memcpy /* Use memcpy from misc.c */ - -@@ -809,6 +810,37 @@ out: - return status; - } - -+static int get_secure_boot(void) -+{ -+ u8 sb, setup; -+ unsigned long datasize = sizeof(sb); -+ efi_guid_t var_guid = EFI_GLOBAL_VARIABLE_GUID; -+ efi_status_t status; -+ -+ status = efi_early->call((unsigned long)sys_table->runtime->get_variable, -+ L"SecureBoot", &var_guid, NULL, &datasize, &sb); -+ -+ if (status != EFI_SUCCESS) -+ return 0; -+ -+ if (sb == 0) -+ return 0; -+ -+ -+ status = efi_early->call((unsigned long)sys_table->runtime->get_variable, -+ L"SetupMode", &var_guid, NULL, &datasize, -+ &setup); -+ -+ if (status != EFI_SUCCESS) -+ return 0; -+ -+ if (setup == 1) -+ return 0; -+ -+ return 1; -+} -+ -+ - /* - * See if we have Graphics Output Protocol - */ -@@ -1372,6 +1404,10 @@ struct boot_params *efi_main(struct efi_config *c, - else - setup_boot_services32(efi_early); - -+ sanitize_boot_params(boot_params); -+ -+ boot_params->secure_boot = get_secure_boot(); -+ - setup_graphics(boot_params); - - setup_efi_pci(boot_params); -diff --git a/arch/x86/include/uapi/asm/bootparam.h b/arch/x86/include/uapi/asm/bootparam.h -index 225b0988043a..90dbfb73e11f 100644 ---- a/arch/x86/include/uapi/asm/bootparam.h -+++ b/arch/x86/include/uapi/asm/bootparam.h -@@ -133,7 +133,8 @@ struct boot_params { - __u8 eddbuf_entries; /* 0x1e9 */ - __u8 edd_mbr_sig_buf_entries; /* 0x1ea */ - __u8 kbd_status; /* 0x1eb */ -- __u8 _pad5[3]; /* 0x1ec */ -+ __u8 secure_boot; /* 0x1ec */ -+ __u8 _pad5[2]; /* 0x1ed */ - /* - * The sentinel is set to a nonzero value (0xff) in header.S. - * -diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c -index 78a0e6298922..8ecfec85e527 100644 ---- a/arch/x86/kernel/setup.c -+++ b/arch/x86/kernel/setup.c -@@ -1142,6 +1142,12 @@ void __init setup_arch(char **cmdline_p) - - io_delay_init(); - -+#ifdef CONFIG_EFI_SECURE_BOOT_SIG_ENFORCE -+ if (boot_params.secure_boot) { -+ enforce_signed_modules(); -+ } -+#endif -+ - /* - * Parse the ACPI tables for possible boot-time SMP configuration. - */ -diff --git a/include/linux/module.h b/include/linux/module.h -index fc9b54eb779e..7377bc851461 100644 ---- a/include/linux/module.h -+++ b/include/linux/module.h -@@ -188,6 +188,12 @@ const struct exception_table_entry *search_exception_tables(unsigned long add); - - struct notifier_block; - -+#ifdef CONFIG_MODULE_SIG -+extern void enforce_signed_modules(void); -+#else -+static inline void enforce_signed_modules(void) {}; -+#endif -+ - #ifdef CONFIG_MODULES - - extern int modules_disabled; /* for sysctl */ -diff --git a/kernel/module.c b/kernel/module.c -index fc14f48915dd..2d68d276f3b6 100644 ---- a/kernel/module.c -+++ b/kernel/module.c -@@ -3844,6 +3844,13 @@ void module_layout(struct module *mod, - EXPORT_SYMBOL(module_layout); - #endif - -+#ifdef CONFIG_MODULE_SIG -+void enforce_signed_modules(void) -+{ -+ sig_enforce = true; -+} -+#endif -+ - bool secure_modules(void) - { - #ifdef CONFIG_MODULE_SIG --- -1.9.3 - - -From eae8a80ddc185b3f233e2620dbfc6454b6f0c3a6 Mon Sep 17 00:00:00 2001 -From: Josh Boyer <jwboyer@fedoraproject.org> -Date: Tue, 5 Feb 2013 19:25:05 -0500 -Subject: [PATCH 11/14] efi: Disable secure boot if shim is in insecure mode - -A user can manually tell the shim boot loader to disable validation of -images it loads. When a user does this, it creates a UEFI variable called -MokSBState that does not have the runtime attribute set. Given that the -user explicitly disabled validation, we can honor that and not enable -secure boot mode if that variable is set. - -Signed-off-by: Josh Boyer <jwboyer@fedoraproject.org> ---- - arch/x86/boot/compressed/eboot.c | 20 +++++++++++++++++++- - 1 file changed, 19 insertions(+), 1 deletion(-) - -diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c -index 85defaf5a27c..b4013a4ba005 100644 ---- a/arch/x86/boot/compressed/eboot.c -+++ b/arch/x86/boot/compressed/eboot.c -@@ -812,8 +812,9 @@ out: - - static int get_secure_boot(void) - { -- u8 sb, setup; -+ u8 sb, setup, moksbstate; - unsigned long datasize = sizeof(sb); -+ u32 attr; - efi_guid_t var_guid = EFI_GLOBAL_VARIABLE_GUID; - efi_status_t status; - -@@ -837,6 +838,23 @@ static int get_secure_boot(void) - if (setup == 1) - return 0; - -+ /* See if a user has put shim into insecure_mode. If so, and the variable -+ * doesn't have the runtime attribute set, we might as well honor that. -+ */ -+ var_guid = EFI_SHIM_LOCK_GUID; -+ status = efi_early->call((unsigned long)sys_table->runtime->get_variable, -+ L"MokSBState", &var_guid, &attr, &datasize, -+ &moksbstate); -+ -+ /* If it fails, we don't care why. Default to secure */ -+ if (status != EFI_SUCCESS) -+ return 1; -+ -+ if (!(attr & EFI_VARIABLE_RUNTIME_ACCESS)) { -+ if (moksbstate == 1) -+ return 0; -+ } -+ - return 1; - } - --- -1.9.3 - - -From 9728a4f49b284b7354876e1d77174d5838306e21 Mon Sep 17 00:00:00 2001 -From: Josh Boyer <jwboyer@fedoraproject.org> -Date: Tue, 27 Aug 2013 13:28:43 -0400 -Subject: [PATCH 12/14] efi: Make EFI_SECURE_BOOT_SIG_ENFORCE depend on EFI - -The functionality of the config option is dependent upon the platform being -UEFI based. Reflect this in the config deps. - -Signed-off-by: Josh Boyer <jwboyer@fedoraproject.org> ---- - arch/x86/Kconfig | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig -index 870aac9520b3..7aecd3f9f8ee 100644 ---- a/arch/x86/Kconfig -+++ b/arch/x86/Kconfig -@@ -1558,7 +1558,8 @@ config EFI_MIXED - If unsure, say N. - - config EFI_SECURE_BOOT_SIG_ENFORCE -- def_bool n -+ def_bool n -+ depends on EFI - prompt "Force module signing when UEFI Secure Boot is enabled" - ---help--- - UEFI Secure Boot provides a mechanism for ensuring that the --- -1.9.3 - - -From 4211b4919b8ccecc4f4cdc0a46ead7294478b687 Mon Sep 17 00:00:00 2001 -From: Josh Boyer <jwboyer@fedoraproject.org> -Date: Tue, 27 Aug 2013 13:33:03 -0400 -Subject: [PATCH 13/14] efi: Add EFI_SECURE_BOOT bit - -UEFI machines can be booted in Secure Boot mode. Add a EFI_SECURE_BOOT bit -for use with efi_enabled. - -Signed-off-by: Josh Boyer <jwboyer@fedoraproject.org> ---- - arch/x86/kernel/setup.c | 2 ++ - include/linux/efi.h | 1 + - 2 files changed, 3 insertions(+) - -diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c -index 8ecfec85e527..5ce785fc9f05 100644 ---- a/arch/x86/kernel/setup.c -+++ b/arch/x86/kernel/setup.c -@@ -1144,7 +1144,9 @@ void __init setup_arch(char **cmdline_p) - - #ifdef CONFIG_EFI_SECURE_BOOT_SIG_ENFORCE - if (boot_params.secure_boot) { -+ set_bit(EFI_SECURE_BOOT, &efi.flags); - enforce_signed_modules(); -+ pr_info("Secure boot enabled\n"); - } - #endif - -diff --git a/include/linux/efi.h b/include/linux/efi.h -index 41bbf8ba4ba8..e73f391fd3c8 100644 ---- a/include/linux/efi.h -+++ b/include/linux/efi.h -@@ -917,6 +917,7 @@ extern int __init efi_setup_pcdp_console(char *); - #define EFI_MEMMAP 4 /* Can we use EFI memory map? */ - #define EFI_64BIT 5 /* Is the firmware 64-bit? */ - #define EFI_ARCH_1 6 /* First arch-specific bit */ -+#define EFI_SECURE_BOOT 7 /* Are we in Secure Boot mode? */ - - #ifdef CONFIG_EFI - /* --- -1.9.3 - - -From 18b50c6f0597b606cb03cbd8a9fdef7478cb2b21 Mon Sep 17 00:00:00 2001 -From: Josh Boyer <jwboyer@fedoraproject.org> -Date: Fri, 20 Jun 2014 08:53:24 -0400 -Subject: [PATCH 14/14] hibernate: Disable in a signed modules environment - -There is currently no way to verify the resume image when returning -from hibernate. This might compromise the signed modules trust model, -so until we can work with signed hibernate images we disable it in -a secure modules environment. - -Signed-off-by: Josh Boyer <jwboyer@fedoraproject.org> ---- - kernel/power/hibernate.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/kernel/power/hibernate.c b/kernel/power/hibernate.c -index fcc2611d3f14..61711801a9c4 100644 ---- a/kernel/power/hibernate.c -+++ b/kernel/power/hibernate.c -@@ -28,6 +28,7 @@ - #include <linux/syscore_ops.h> - #include <linux/ctype.h> - #include <linux/genhd.h> -+#include <linux/module.h> - #include <trace/events/power.h> - - #include "power.h" -@@ -65,7 +66,7 @@ static const struct platform_hibernation_ops *hibernation_ops; - - bool hibernation_available(void) - { -- return (nohibernate == 0); -+ return ((nohibernate == 0) && !secure_modules()); - } - - /** --- -1.9.3 - diff --git a/silence-fbcon-logo.patch b/silence-fbcon-logo.patch index ccb76386..2b907f90 100644 --- a/silence-fbcon-logo.patch +++ b/silence-fbcon-logo.patch @@ -1,11 +1,18 @@ +From: "kernel-team@fedoraproject.org" <kernel-team@fedoraproject.org> +Date: Thu, 29 Jul 2010 16:46:31 -0700 +Subject: [PATCH] silence fbcon logo + Bugzilla: N/A Upstream-status: Fedora mustard +--- + drivers/video/console/fbcon.c | 24 +++++++++++++++++------- + 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/video/console/fbcon.c b/drivers/video/console/fbcon.c -index 1657b96..4c5c2be 100644 +index 57b1d44acbfe..31048a85713d 100644 --- a/drivers/video/console/fbcon.c +++ b/drivers/video/console/fbcon.c -@@ -631,13 +631,15 @@ static void fbcon_prepare_logo(struct vc_data *vc, struct fb_info *info, +@@ -638,13 +638,15 @@ static void fbcon_prepare_logo(struct vc_data *vc, struct fb_info *info, kfree(save); } @@ -28,7 +35,7 @@ index 1657b96..4c5c2be 100644 } } #endif /* MODULE */ -@@ -3489,6 +3491,14 @@ static int __init fb_console_init(void) +@@ -3625,6 +3627,14 @@ static int __init fb_console_init(void) return 0; } @@ -43,3 +50,6 @@ index 1657b96..4c5c2be 100644 module_init(fb_console_init); #ifdef MODULE +-- +1.9.3 + @@ -1,3 +1,2 @@ -5c569ed649a0c9711879f333e90c5386 linux-3.16.tar.xz -49868ce6467b35cd9ffea1120d129462 perf-man-3.16.tar.gz -387a93e4833df73217c6b9b92153aa7c patch-3.16.3.xz +fb30d0f29214d75cddd2faa94f73d5cf linux-3.17.tar.xz +159e969cbc27201d8e2fa0f609dc722f perf-man-3.17.tar.gz diff --git a/udf-Avoid-infinite-loop-when-processing-indirect-ICB.patch b/udf-Avoid-infinite-loop-when-processing-indirect-ICB.patch deleted file mode 100644 index a8839661..00000000 --- a/udf-Avoid-infinite-loop-when-processing-indirect-ICB.patch +++ /dev/null @@ -1,92 +0,0 @@ -From a45318b5ff8c505afcbf04a1c5fa7dbe426d9588 Mon Sep 17 00:00:00 2001 -From: Jan Kara <jack@suse.cz> -Date: Thu, 4 Sep 2014 14:06:55 +0200 -Subject: [PATCH] udf: Avoid infinite loop when processing indirect ICBs - -We did not implement any bound on number of indirect ICBs we follow when -loading inode. Thus corrupted medium could cause kernel to go into an -infinite loop, possibly causing a stack overflow. - -Fix the possible stack overflow by removing recursion from -__udf_read_inode() and limit number of indirect ICBs we follow to avoid -infinite loops. - -Bugzilla: 1141810 -Upstream-status: 3.17 - -Signed-off-by: Jan Kara <jack@suse.cz> ---- - fs/udf/inode.c | 35 +++++++++++++++++++++-------------- - 1 file changed, 21 insertions(+), 14 deletions(-) - -diff --git a/fs/udf/inode.c b/fs/udf/inode.c -index 236cd48184c2..a932f7740b51 100644 ---- a/fs/udf/inode.c -+++ b/fs/udf/inode.c -@@ -1271,13 +1271,22 @@ update_time: - return 0; - } - -+/* -+ * Maximum length of linked list formed by ICB hierarchy. The chosen number is -+ * arbitrary - just that we hopefully don't limit any real use of rewritten -+ * inode on write-once media but avoid looping for too long on corrupted media. -+ */ -+#define UDF_MAX_ICB_NESTING 1024 -+ - static void __udf_read_inode(struct inode *inode) - { - struct buffer_head *bh = NULL; - struct fileEntry *fe; - uint16_t ident; - struct udf_inode_info *iinfo = UDF_I(inode); -+ unsigned int indirections = 0; - -+reread: - /* - * Set defaults, but the inode is still incomplete! - * Note: get_new_inode() sets the following on a new inode: -@@ -1314,28 +1323,26 @@ static void __udf_read_inode(struct inode *inode) - ibh = udf_read_ptagged(inode->i_sb, &iinfo->i_location, 1, - &ident); - if (ident == TAG_IDENT_IE && ibh) { -- struct buffer_head *nbh = NULL; - struct kernel_lb_addr loc; - struct indirectEntry *ie; - - ie = (struct indirectEntry *)ibh->b_data; - loc = lelb_to_cpu(ie->indirectICB.extLocation); - -- if (ie->indirectICB.extLength && -- (nbh = udf_read_ptagged(inode->i_sb, &loc, 0, -- &ident))) { -- if (ident == TAG_IDENT_FE || -- ident == TAG_IDENT_EFE) { -- memcpy(&iinfo->i_location, -- &loc, -- sizeof(struct kernel_lb_addr)); -- brelse(bh); -- brelse(ibh); -- brelse(nbh); -- __udf_read_inode(inode); -+ if (ie->indirectICB.extLength) { -+ brelse(bh); -+ brelse(ibh); -+ memcpy(&iinfo->i_location, &loc, -+ sizeof(struct kernel_lb_addr)); -+ if (++indirections > UDF_MAX_ICB_NESTING) { -+ udf_err(inode->i_sb, -+ "too many ICBs in ICB hierarchy" -+ " (max %d supported)\n", -+ UDF_MAX_ICB_NESTING); -+ make_bad_inode(inode); - return; - } -- brelse(nbh); -+ goto reread; - } - } - brelse(ibh); --- -2.1.0 - diff --git a/nowatchdog-on-virt.patch b/watchdog-Disable-watchdog-on-virtual-machines.patch index d8cf8795..23a17c05 100644 --- a/nowatchdog-on-virt.patch +++ b/watchdog-Disable-watchdog-on-virtual-machines.patch @@ -1,10 +1,6 @@ -Bugzilla: 971139 -Upstream-status: Fedora mustard for now - -From 17109685bfce322c73a816e097b137458fbd55ae Mon Sep 17 00:00:00 2001 From: Dave Jones <davej@redhat.com> Date: Tue, 24 Jun 2014 08:43:34 -0400 -Subject: [PATCH] Disable watchdog on virtual machines. +Subject: [PATCH] watchdog: Disable watchdog on virtual machines. For various reasons, VMs seem to trigger the soft lockup detector a lot, in cases where it's just not possible for a lockup to occur. @@ -15,13 +11,16 @@ the VM for a very long time (Could be the host was under heavy load). Just disable the detector on VMs. +Bugzilla: 971139 +Upstream-status: Fedora mustard for now + Signed-off-by: Dave Jones <davej@redhat.com> --- kernel/watchdog.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/kernel/watchdog.c b/kernel/watchdog.c -index c3319bd1b040..0e3687675aaa 100644 +index a8d6914030fe..d0a8c308170d 100644 --- a/kernel/watchdog.c +++ b/kernel/watchdog.c @@ -24,6 +24,7 @@ @@ -65,7 +64,7 @@ index c3319bd1b040..0e3687675aaa 100644 /* * Hard-lockup warnings should be triggered after just a few seconds. Soft- * lockups can have false positives under extreme conditions. So we generally -@@ -641,6 +668,8 @@ out: +@@ -644,6 +671,8 @@ out: void __init lockup_detector_init(void) { diff --git a/x86-Lock-down-IO-port-access-when-module-security-is.patch b/x86-Lock-down-IO-port-access-when-module-security-is.patch new file mode 100644 index 00000000..327c65ef --- /dev/null +++ b/x86-Lock-down-IO-port-access-when-module-security-is.patch @@ -0,0 +1,70 @@ +From: Matthew Garrett <matthew.garrett@nebula.com> +Date: Thu, 8 Mar 2012 10:35:59 -0500 +Subject: [PATCH] x86: Lock down IO port access when module security is enabled + +IO port access would permit users to gain access to PCI configuration +registers, which in turn (on a lot of hardware) give access to MMIO register +space. This would potentially permit root to trigger arbitrary DMA, so lock +it down by default. + +Signed-off-by: Matthew Garrett <matthew.garrett@nebula.com> +--- + arch/x86/kernel/ioport.c | 5 +++-- + drivers/char/mem.c | 4 ++++ + 2 files changed, 7 insertions(+), 2 deletions(-) + +diff --git a/arch/x86/kernel/ioport.c b/arch/x86/kernel/ioport.c +index 4ddaf66ea35f..00b440307419 100644 +--- a/arch/x86/kernel/ioport.c ++++ b/arch/x86/kernel/ioport.c +@@ -15,6 +15,7 @@ + #include <linux/thread_info.h> + #include <linux/syscalls.h> + #include <linux/bitmap.h> ++#include <linux/module.h> + #include <asm/syscalls.h> + + /* +@@ -28,7 +29,7 @@ asmlinkage long sys_ioperm(unsigned long from, unsigned long num, int turn_on) + + if ((from + num <= from) || (from + num > IO_BITMAP_BITS)) + return -EINVAL; +- if (turn_on && !capable(CAP_SYS_RAWIO)) ++ if (turn_on && (!capable(CAP_SYS_RAWIO) || secure_modules())) + return -EPERM; + + /* +@@ -103,7 +104,7 @@ SYSCALL_DEFINE1(iopl, unsigned int, level) + return -EINVAL; + /* Trying to gain more privileges? */ + if (level > old) { +- if (!capable(CAP_SYS_RAWIO)) ++ if (!capable(CAP_SYS_RAWIO) || secure_modules()) + return -EPERM; + } + regs->flags = (regs->flags & ~X86_EFLAGS_IOPL) | (level << 12); +diff --git a/drivers/char/mem.c b/drivers/char/mem.c +index 917403fe10da..cdf839f9defe 100644 +--- a/drivers/char/mem.c ++++ b/drivers/char/mem.c +@@ -27,6 +27,7 @@ + #include <linux/export.h> + #include <linux/io.h> + #include <linux/aio.h> ++#include <linux/module.h> + + #include <asm/uaccess.h> + +@@ -568,6 +569,9 @@ static ssize_t write_port(struct file *file, const char __user *buf, + unsigned long i = *ppos; + const char __user *tmp = buf; + ++ if (secure_modules()) ++ return -EPERM; ++ + if (!access_ok(VERIFY_READ, buf, count)) + return -EFAULT; + while (count-- > 0 && i < 65536) { +-- +1.9.3 + diff --git a/x86-Restrict-MSR-access-when-module-loading-is-restr.patch b/x86-Restrict-MSR-access-when-module-loading-is-restr.patch new file mode 100644 index 00000000..f21c9382 --- /dev/null +++ b/x86-Restrict-MSR-access-when-module-loading-is-restr.patch @@ -0,0 +1,42 @@ +From: Matthew Garrett <matthew.garrett@nebula.com> +Date: Fri, 8 Feb 2013 11:12:13 -0800 +Subject: [PATCH] x86: Restrict MSR access when module loading is restricted + +Writing to MSRs should not be allowed if module loading is restricted, +since it could lead to execution of arbitrary code in kernel mode. Based +on a patch by Kees Cook. + +Cc: Kees Cook <keescook@chromium.org> +Signed-off-by: Matthew Garrett <matthew.garrett@nebula.com> +--- + arch/x86/kernel/msr.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/x86/kernel/msr.c b/arch/x86/kernel/msr.c +index c9603ac80de5..8bef43fc3f40 100644 +--- a/arch/x86/kernel/msr.c ++++ b/arch/x86/kernel/msr.c +@@ -103,6 +103,9 @@ static ssize_t msr_write(struct file *file, const char __user *buf, + int err = 0; + ssize_t bytes = 0; + ++ if (secure_modules()) ++ return -EPERM; ++ + if (count % 8) + return -EINVAL; /* Invalid chunk size */ + +@@ -150,6 +153,10 @@ static long msr_ioctl(struct file *file, unsigned int ioc, unsigned long arg) + err = -EBADF; + break; + } ++ if (secure_modules()) { ++ err = -EPERM; ++ break; ++ } + if (copy_from_user(®s, uregs, sizeof regs)) { + err = -EFAULT; + break; +-- +1.9.3 + |