/*
* board/renesas/alt/qos.c
*
* Copyright (C) 2014 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <asm/arch/rmobile.h>
#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
/* QoS version 0.11 */
enum {
DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
DBSC3_15,
DBSC3_NR,
};
static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
[DBSC3_00] = DBSC3_0_QOS_R0_BASE,
[DBSC3_01] = DBSC3_0_QOS_R1_BASE,
[DBSC3_02] = DBSC3_0_QOS_R2_BASE,
[DBSC3_03] = DBSC3_0_QOS_R3_BASE,
[DBSC3_04] = DBSC3_0_QOS_R4_BASE,
[DBSC3_05] = DBSC3_0_QOS_R5_BASE,
[DBSC3_06] = DBSC3_0_QOS_R6_BASE,
[DBSC3_07] = DBSC3_0_QOS_R7_BASE,
[DBSC3_08] = DBSC3_0_QOS_R8_BASE,
[DBSC3_09] = DBSC3_0_QOS_R9_BASE,
[DBSC3_10] = DBSC3_0_QOS_R10_BASE,
[DBSC3_11] = DBSC3_0_QOS_R11_BASE,
[DBSC3_12] = DBSC3_0_QOS_R12_BASE,
[DBSC3_13] = DBSC3_0_QOS_R13_BASE,
[DBSC3_14] = DBSC3_0_QOS_R14_BASE,
[DBSC3_15] = DBSC3_0_QOS_R15_BASE,
};
static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
[DBSC3_00] = DBSC3_0_QOS_W0_BASE,
[DBSC3_01] = DBSC3_0_QOS_W1_BASE,
[DBSC3_02] = DBSC3_0_QOS_W2_BASE,
[DBSC3_03] = DBSC3_0_QOS_W3_BASE,
[DBSC3_04] = DBSC3_0_QOS_W4_BASE,
[DBSC3_05] = DBSC3_0_QOS_W5_BASE,
[DBSC3_06] = DBSC3_0_QOS_W6_BASE,
[DBSC3_07] = DBSC3_0_QOS_W7_BASE,
[DBSC3_08] = DBSC3_0_QOS_W8_BASE,
[DBSC3_09] = DBSC3_0_QOS_W9_BASE,
[DBSC3_10] = DBSC3_0_QOS_W10_BASE,
[DBSC3_11] = DBSC3_0_QOS_W11_BASE,
[DBSC3_12] = DBSC3_0_QOS_W12_BASE,
[DBSC3_13] = DBSC3_0_QOS_W13_BASE,
[DBSC3_14] = DBSC3_0_QOS_W14_BASE,
[DBSC3_15] = DBSC3_0_QOS_W15_BASE,
};
void qos_init(void)
{
int i;
struct rcar_s3c *s3c;
struct rcar_s3c_qos *s3c_qos;
struct rcar_dbsc3_qos *qos_addr;
struct rcar_mxi *mxi;
struct rcar_mxi_qos *mxi_qos;
struct rcar_axi_qos *axi_qos;
/* DBSC DBADJ2 */
writel(0x20042004, DBSC3_0_DBADJ2);
/* S3C -QoS */
s3c = (struct rcar_s3c *)S3C_BASE;
writel(0x1F0D0B0A, &s3c->s3crorr);
writel(0x1F0D0B09, &s3c->s3cworr);
/* QoS Control Registers */
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
writel(0x00890089, &s3c_qos->s3cqos0);
writel(0x20960010, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
writel(0x20AA2200, &s3c_qos->s3cqos3);
writel(0x00002032, &s3c_qos->s3cqos4);
writel(0x20960010, &s3c_qos->s3cqos5);
writel(0x20302030, &s3c_qos->s3cqos6);
writel(0x20AA2200, &s3c_qos->s3cqos7);
writel(0x00002032, &s3c_qos->s3cqos8);
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
writel(0x00890089, &s3c_qos->s3cqos0);
writel(0x20960010, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
writel(0x20AA2200, &s3c_qos->s3cqos3);
writel(0x00002032, &s3c_qos->s3cqos4);
writel(0x20960010, &s3c_qos->s3cqos5);
writel(0x20302030, &s3c_qos->s3cqos6);
writel(0x20AA2200, &s3c_qos->s3cqos7);
writel(0x00002032, &s3c_qos->s3cqos8);
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