include/andestech/andes_pcu.h


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/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2011 Andes Technology Corp
 * Macpaul Lin <macpaul@andestech.com>
 */

/*
 * Andes Power Control Unit
 */
#ifndef __ANDES_PCU_H
#define __ANDES_PCU_H

#ifndef __ASSEMBLY__

struct pcs {
	unsigned int	cr;		/* PCSx Configuration (clock scaling) */
	unsigned int	parm;		/* PCSx Parameter*/
	unsigned int	stat1;		/* PCSx Status 1 */
	unsigned int	stat2;		/* PCSx Stusts 2 */
	unsigned int	pdd;		/* PCSx PDD */
};

struct andes_pcu {
	unsigned int	rev;		/* 0x00 - PCU Revision */
	unsigned int	spinfo;		/* 0x04 - Scratch Pad Info */
	unsigned int	rsvd1[2];	/* 0x08-0x0C: Reserved */
	unsigned int	soc_id;		/* 0x10 - SoC ID */
	unsigned int	soc_ahb;	/* 0x14 - SoC AHB configuration */
	unsigned int	soc_apb;	/* 0x18 - SoC APB configuration */
	unsigned int	rsvd2;		/* 0x1C */
	unsigned int	dcsrcr0;	/* 0x20 - Driving Capability
						and Slew Rate Control 0 */
	unsigned int	dcsrcr1;	/* 0x24 - Driving Capability
						and Slew Rate Control 1 */
	unsigned int	dcsrcr2;	/* 0x28 - Driving Capability
						and Slew Rate Control 2 */
	unsigned int	rsvd3;		/* 0x2C */
	unsigned int	mfpsr0;		/* 0x30 - Multi-Func Port Setting 0 */
	unsigned int	mfpsr1;		/* 0x34 - Multi-Func Port Setting 1 */
	unsigned int	dmaes;		/* 0x38 - DMA Engine Selection */
	unsigned int	rsvd4;		/* 0x3C */
	unsigned int	oscc;		/* 0x40 - OSC Control */
	unsigned int	pwmcd;		/* 0x44 - PWM Clock divider */
	unsigned int	socmisc;	/* 0x48 - SoC Misc. */
	unsigned int	rsvd5[13];	/* 0x4C-0x7C: Reserved */
	unsigned int	bsmcr;		/* 0x80 - BSM Controrl */
	unsigned int	bsmst;		/* 0x84 - BSM Status */
	unsigned int	wes;		/* 0x88 - Wakeup Event Sensitivity*/
	unsigned int	west;		/* 0x8C - Wakeup Event Status */
	unsigned int	rsttiming;	/* 0x90 - Reset Timing  */
	unsigned int	intr_st;	/* 0x94 - PCU Interrupt Status */
	unsigned int	rsvd6[2];	/* 0x98-0x9C: Reserved */
	struct pcs	pcs1;		/* 0xA0-0xB0: PCS1 (clock scaling) */
	unsigned int	pcsrsvd1[3];	/* 0xB4-0xBC: Reserved */
	struct pcs	pcs2;		/* 0xC0-0xD0: PCS2 (AHB clock gating) */
	unsigned int	pcsrsvd2[3];	/* 0xD4-0xDC: Reserved */
	struct pcs	pcs3;		/* 0xE0-0xF0: PCS3 (APB clock gating) */
	unsigned int	pcsrsvd3[3];	/* 0xF4-0xFC: Reserved */
	struct pcs	pcs4;		/* 0x100-0x110: PCS4 main PLL scaling */
	unsigned int	pcsrsvd4[3];	/* 0x114-0x11C: Reserved */
	struct pcs	pcs5;		/* 0x120-0x130: PCS5 PCI PLL scaling */
	unsigned int	pcsrsvd5[3];	/* 0x134-0x13C: Reserved */
	struct pcs	pcs6;		/* 0x140-0x150: PCS6 AC97 PLL scaling */
	unsigned int	pcsrsvd6[3];	/* 0x154-0x15C: Reserved */
	struct pcs	pcs7;		/* 0x160-0x170: PCS7 GMAC PLL scaling */
	unsigned int	pcsrsvd7[3];	/* 0x174-0x17C: Reserved */
	struct pcs	pcs8;		/* 0x180-0x190: PCS8 voltage scaling */
	unsigned int	pcsrsvd8[3];	/* 0x194-0x19C: Reserved */
	struct pcs	pcs9;		/* 0x1A0-0x1B0: PCS9 power control */
	unsigned int	pcsrsvd9[93];	/* 0x1B4-0x3FC: Reserved */
	unsigned int	pmspdm[40];	/* 0x400-0x4fC: Power Manager
							Scratch Pad Memory 0 */
};
#endif /* __ASSEMBLY__ */