// SPDX-License-Identifier: GPL-2.0+/* * (C) Copyright 2015 * Elecsys Corporation <www.elecsyscorp.com> * Kevin Smith <kevin.smith@elecsyscorp.com> * * Original driver: * (C) Copyright 2009 * Marvell Semiconductor <www.marvell.com> * Prafulla Wadaskar <prafulla@marvell.com> *//* * PHY driver for mv88e61xx ethernet switches. * * This driver configures the mv88e61xx for basic use as a PHY. The switch * supports a VLAN configuration that determines how traffic will be routed * between the ports. This driver uses a simple configuration that routes * traffic from each PHY port only to the CPU port, and from the CPU port to * any PHY port. * * The configuration determines which PHY ports to activate using the * CONFIG_MV88E61XX_PHY_PORTS bitmask. Setting bit 0 will activate port 0, bit * 1 activates port 1, etc. Do not set the bit for the port the CPU is * connected to unless it is connected over a PHY interface (not MII). * * This driver was written for and tested on the mv88e6176 with an SGMII * connection. Other configurations should be supported, but some additions or * changes may be required. */#include <common.h>#include <bitfield.h>#include <errno.h>