/******************************************************************************
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init_gpl.c
*
* This file is automatically generated
*
*****************************************************************************/
#include "ps7_init_gpl.h"
unsigned long ps7_pll_init_data_3_0[] = {
// START: top
// .. START: SLCR SETTINGS
// .. UNLOCK_KEY = 0XDF0D
// .. ==> 0XF8000008[15:0] = 0x0000DF0DU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
// ..
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
// .. FINISH: SLCR SETTINGS
// .. START: PLL SLCR REGISTERS
// .. .. START: ARM PLL INIT
// .. .. PLL_RES = 0x2
// .. .. ==> 0XF8000110[7:4] = 0x00000002U
// .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
// .. .. PLL_CP = 0x2
// .. .. ==> 0XF8000110[11:8] = 0x00000002U
// .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
// .. .. LOCK_CNT = 0xfa
// .. .. ==> 0XF8000110[21:12] = 0x000000FAU
// .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
// .. ..
EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
// .. .. .. START: UPDATE FB_DIV
// .. .. .. PLL_FDIV = 0x28
// .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
// .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
// .. .. ..
EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
// .. .. .. FINISH: UPDATE FB_DIV
// .. .. .. START: BY PASS PLL
// .. .. .. PLL_BYPASS_FORCE = 1
// .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
// .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
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