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* dmaengine: at_hdmac: take maxburst from slave configurationNicolas Ferre2012-05-151-3/+4
| | | | | | | | | | | | | The maxburst/chunk size was taken from the private slave DMA data structure. Use the common API provided by DMA_SLAVE_CONFIG to setup src/dst maxburst values. The ctrla field is not needed anymore in the slave private structure nor the header constants that were located in an architecture specific directory. The at91sam9g45_devices.c file that was using this platform data is also modified to remove this now useless data. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine: at_hdmac: remove ATC_DEFAULT_CTRLA constantNicolas Ferre2012-05-151-7/+5
| | | | | | | Not needed constant that was set to 0. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine: fix cyclic dma usageVinod Koul2012-05-151-1/+3
| | | | | | | | | | for cyclic dma, dont makr the descriptor as complte. Fix the remaining users of cyclic dma which do so Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com> Tested-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Tested-by: Mika Westerberg <mika.westerberg@iki.fi>
* dmaengine: at_hdmac: remove clear-on-read in atc_dostart()Nicolas Ferre2012-04-201-4/+0
| | | | | | | | | | | | | This loop on EBCISR register was designed to clear IRQ sources before enabling a DMA channel. This register is clear-on-read so a race condition can appear if another channel is already active and has just finished its transfer. Removing this read on EBCISR is fixing the issue as there is no case where an IRQ could be pending: we already make sure that this register is drained at probe() time and during resume. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: stable <stable@vger.kernel.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine: at_hdmac: add slave config operationNicolas Ferre2012-03-211-13/+43
| | | | | | | | | | | | | | | | | | | | | | This patch introduces DMA_SLAVE_CONFIG to at_hdmac Atmel DMA driver. It is needed to fix a regression in the use of atmel-mci.c driver on Atmel AT91 platforms brouth by e2b35f3: "dmaengine/dw_dmac: Fix dw_dmac user drivers to adapt to slave_config changes" We remove some parts of the private structure "at_dma_slave" and use the information provided by "struct dma_slave_config": source/destination peripheral registers and access width. AT_DMA_SLAVE_WIDTH_* values used previously are not needed anymore as we now use the standard ones. Although some conversion functions are needed to match register expected values. Some AT91 sub-architecture specific files are slightly touched by this patch but it cannot be split because it can break compilation. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine: add context parameter to prep_slave_sg and prep_dma_cyclicAlexandre Bounine2012-03-211-2/+5
| | | | | | | | | | | | Add context parameter to device_prep_slave_sg() and device_prep_dma_cyclic() interfaces to allow passing client/target specific information associated with the data transfer. Modify all affected DMA engine drivers. Signed-off-by: Alexandre Bounine <alexandre.bounine@idt.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine: consolidate initialization of cookiesRussell King - ARM Linux2012-03-131-2/+2
| | | | | | | | | | | | Provide a common function to initialize a channels cookie values. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> [imx-sdma.c & mxs-dma.c] Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine: consolidate tx_status functionsRussell King - ARM Linux2012-03-131-12/+6
| | | | | | | | | | | | | | | | Now that we have the completed cookie in the dma_chan structure, we can consolidate the tx_status functions by providing a function to set the txstate structure and returning the DMA status. We also provide a separate helper to set the residue for cookies which are still in progress. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> [imx-sdma.c & mxs-dma.c] Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine: provide a common function for completing a dma descriptorRussell King - ARM Linux2012-03-131-1/+1
| | | | | | | | | | | | | Provide a common function to do the cookie mechanics for completing a DMA descriptor. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> [imx-sdma.c & mxs-dma.c] Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine: consolidate assignment of DMA cookiesRussell King - ARM Linux2012-03-131-22/+1
| | | | | | | | | | | | | | Everyone deals with assigning DMA cookies in the same way (it's part of the API so they should be), so lets consolidate the common code into a helper function to avoid this duplication. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> [imx-sdma.c & mxs-dma.c] Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine: add private header fileRussell King - ARM Linux2012-03-131-0/+1
| | | | | | | | | | | | | | | | Add a local private header file to contain definitions and declarations which should only be used by DMA engine drivers. We also fix linux/dmaengine.h to use LINUX_DMAENGINE_H to guard against multiple inclusion. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> [imx-sdma.c & mxs-dma.c] Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine: move last completed cookie into generic dma_chan structureRussell King - ARM Linux2012-03-131-5/+5
| | | | | | | | | | | | | | | Every DMA engine implementation declares a last completed dma cookie in their private dma channel structures. This is pointless, and forces driver specific code. Move this out into the common dma_chan structure. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> [imx-sdma.c & mxs-dma.c] Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* at_hdmac: bugfix for enabling channel irqNikolaus Voss2012-01-311-2/+2
| | | | | | | | | | | | | | | | | commit 463894705e4089d0ff69e7d877312d496ac70e5b deleted redundant chan_id and chancnt initialization in dma drivers as this is done in dma_async_device_register(). However, atc_enable_irq() relied on chan_id set before registering the device, what left only channel 0 functional for this driver. This patch introduces atc_enable/disable_chan_irq() as a variant of atc_enable/disable_irq() with the channel as explicit argument. Signed-off-by: Nikolaus Voss <n.voss@weinmann.de> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: stable <stable@vger.kernel.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine: at_hdmac: simplify device selection from platform data or DTNicolas Ferre2011-11-281-32/+31
| | | | | | | | | | | | Using a configuration structure simplify the finding of SoC dependent parameters. Both platform data and device tree ids are using these structures. This will separate data from code and remove the need for an enum. Idea from Grant Likely. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine: at_hdmac: empty entry shape modificationNicolas Ferre2011-11-281-1/+3
| | | | | | | Trivial form modification to unify structure look. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine: at_hdmac: add const to struct platform_device_id definitionNicolas Ferre2011-11-281-1/+1
| | | | | Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* Merge branch 'dma_slave_direction' into next_test_dirnVinod Koul2011-11-171-11/+11
|\ | | | | | | | | resolved conflicts: drivers/media/video/mx3_camera.c
| * dmaengine: move drivers to dma_transfer_directionVinod Koul2011-10-271-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fixup usage of dma direction by introducing dma_transfer_direction, this patch moves dma/drivers/* to use new enum Cc: Jassi Brar <jaswinder.singh@linaro.org> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Viresh Kumar <viresh.kumar@st.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Mika Westerberg <mika.westerberg@iki.fi> Cc: H Hartley Sweeten <hartleys@visionengravers.com> Cc: Li Yang <leoli@freescale.com> Cc: Zhang Wei <zw@zh-kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Cc: Shawn Guo <shawn.guo@freescale.com> Cc: Yong Wang <yong.y.wang@intel.com> Cc: Tomoya MORINAGA <tomoya-linux@dsn.lapis-semi.com> Cc: Boojin Kim <boojin.kim@samsung.com> Cc: Barry Song <Baohua.Song@csr.com> Acked-by: Mika Westerberg <mika.westerberg@iki.fi> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Viresh Kumar <viresh.kumar@st.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* | dmaengine: at_hdmac: add device tree supportNicolas Ferre2011-11-101-1/+31
| | | | | | | | | | | | | | | | | | Add device tree probe support for atmel at_hdmac DMA driver. Bindings are added to specify DMA controller configuration. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* | dmaengine: at_hdmac: platform data move to use .id_tableNicolas Ferre2011-11-101-10/+38
|/ | | | | | | | | | | We remove the use of platform data from DMA controller driver. We now use of .id_table to distinguish between compatible types. The two implementations allow to determine the number of channels and the capabilities of the controller. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* dmaengine: delete redundant chan_id and chancnt initialization in dma driversBarry Song2011-09-201-3/+2
| | | | | | | | | | | | | | | | | dma_async_device_register will re-init chan_id and chancnt, so whatever chan_id and chancnt are set in drivers, they will be re-written by dma_async_device_register. Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Viresh Kumar <viresh.kumar@st.com> Cc: Vinod Koul <vinod.koul@intel.com> Cc: Piotr Ziecik <kosmo@semihalf.com> Cc: Yong Wang <yong.y.wang@intel.com> Cc: Jaswinder Singh <jassi.brar@samsung.com> Cc: Pelagicore AB <info@pelagicore.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Acked-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: at_hdmac: fix way to specify cyclic capabilityNicolas Ferre2011-08-191-6/+4
| | | | | | | | | In this driver, we can trigger cyclic transfer on peripherals-DMA interfaces. It is dependent on driver implementation but cannot depend on a platform property: we remove the dma_has_cap(DMA_CYCLIC, ) test which has no meaning. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: at_hdmac: add wrappers for testing channel stateNicolas Ferre2011-08-191-10/+9
| | | | | | | | Cyclic property and paused state are encoded as bits in the channel status bitfield. Tests of those bits are wrapped in convenient helper functions. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: at_hdmac: improve power management routinesNicolas Ferre2011-08-191-1/+87
| | | | | | | | | | | Save/restore dma controller state across a suspend-resume sequence. The prepare() function will wait for the non-cyclic channels to become idle. It also deals with cyclic operations with the start at next period while resuming. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: at_hdmac: replace spin_lock* with irqsave variantsNicolas Ferre2011-08-191-22/+30
| | | | | | | | | | | | | | | | | dmaengine routines can be called from interrupt context and with interrupts disabled. Whereas spin_unlock_bh can't be called from such contexts. So this patch converts all spin_lock* routines to irqsave variants. Also, spin_lock() used in tasklet is converted to irqsave variants, as tasklet can be interrupted, and dma requests from such interruptions may also call spin_lock. Idea from dw_dmac patch by Viresh Kumar. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dma: at_hdmac.c: use resource_sizeH Hartley Sweeten2011-06-061-2/+2
| | | | | | | Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* Merge branch 'next' of ↵Linus Torvalds2011-05-281-85/+291
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (33 commits) x86: poll waiting for I/OAT DMA channel status maintainers: add dma engine tree details dmaengine: add TODO items for future work on dma drivers dmaengine: Add API documentation for slave dma usage dmaengine/dw_dmac: Update maintainer-ship dmaengine: move link order dmaengine/dw_dmac: implement pause and resume in dwc_control dmaengine/dw_dmac: Replace spin_lock* with irqsave variants and enable submission from callback dmaengine/dw_dmac: Divide one sg to many desc, if sg len is greater than DWC_MAX_COUNT dmaengine/dw_dmac: set residue as total len in dwc_tx_status if status is !DMA_SUCCESS dmaengine/dw_dmac: don't call callback routine in case dmaengine_terminate_all() is called dmaengine: at_hdmac: pause: no need to wait for FIFO empty pch_dma: modify pci device table definition pch_dma: Support new device ML7223 IOH pch_dma: Support I2S for ML7213 IOH pch_dma: Fix DMA setting issue pch_dma: modify for checkpatch pch_dma: fix dma direction issue for ML7213 IOH video-in dmaengine: at_hdmac: use descriptor chaining help function dmaengine: at_hdmac: implement pause and resume in atc_control ... Fix up trivial conflict in drivers/dma/dw_dmac.c
| * dmaengine: at_hdmac: pause: no need to wait for FIFO emptyNicolas Ferre2011-05-121-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the addition of the "pause" feature, an active wait was introduced to check the "FIFO empty" event. This event was not always happening and a timout contition was needed. But, in some cases, this event depend on the peripheral connected to the channel that is paused: FIFO becomes empty if the peripheral consumes data. The timeout is pretty difficult to evaluate. Moreover, this check is not needed. In conclusion, it seems sensible to entirely remove the checking of "FIFO empty" status when pausing. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> [commit msg edited for grammer] Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: at_hdmac: use descriptor chaining help functionNicolas Ferre2011-05-091-30/+3
| | | | | | | | | | | | | | | | | | A little function helps to chain descriptors: it is already used in cyclic dma operations, now use it in memcpy and slave_sg preparation functions. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: at_hdmac: implement pause and resume in atc_controlNicolas Ferre2011-05-091-27/+70
| | | | | | | | | | | | | | | | | | | | | | Pause and resume controls are useful for audio devices. This also returns correct status from atc_tx_status() in case chan is paused. Idea from dw_dmac patch by Linus Walleij. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: at_hdmac: set residue as total len in atc_tx_statusNicolas Ferre2011-05-091-1/+6
| | | | | | | | | | | | | | | | | | | | If transfer status is !=DMA_SUCCESS, return total transfer len as residue, instead of zero. Idea from dw_dmac patch by Viresh Kumar. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: at_hdmac: specialize AHB interfaces to optimize transfersNicolas Ferre2011-05-021-11/+15
| | | | | | | | | | | | | | | | | | | | | | DMA controller has two AHB interfaces on the SOC internal matrix. It is more efficient to specialize each interface as the access to memory can introduce latencies that are not compatible with peripheral accesses requirements. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: at_hdmac: remove channel status testing in taskletNicolas Ferre2011-05-021-7/+0
| | | | | | | | | | | | | | | | | | | | There is no need to test if channel is enabled in tasklet: - in error path, channel is disabled in interrupt routine - in normal path, this test is performed in sub functions to report a misuse of the engine. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: at_hdmac: debug information sg_len for prep_slave_sgNicolas Ferre2011-05-021-1/+2
| | | | | | | | | | Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: at_hdmac: add cyclic DMA operation supportNicolas Ferre2011-05-021-14/+217
| | | | | | | | | | Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: at_hdmac: modify way to use interruptsNicolas Ferre2011-05-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | Now we use Buffer Transfer Completed interrupts. If we want a chained buffer completed information, we setup the ATC_IEN bit in CTRLB register in the lli. This is done by set_desc_eol() function and used by memcpy/slave_sg functions. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* | Fix common misspellingsLucas De Marchi2011-03-311-1/+1
|/ | | | | | Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
* Merge branch 'next' of ↵Linus Torvalds2011-01-171-10/+9
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (63 commits) ARM: PL08x: cleanup comments Update CONFIG_MD_RAID6_PQ to CONFIG_RAID6_PQ in drivers/dma/iop-adma.c ARM: PL08x: fix a warning Fix dmaengine_submit() return type dmaengine: at_hdmac: fix race while monitoring channel status dmaengine: at_hdmac: flags located in first descriptor dmaengine: at_hdmac: use subsys_initcall instead of module_init dmaengine: at_hdmac: no need set ACK in new descriptor dmaengine: at_hdmac: trivial add precision to unmapping comment dmaengine: at_hdmac: use dma_address to program DMA hardware pch_dma: support new device ML7213 IOH ARM: PL08x: prevent dma_set_runtime_config() reconfiguring memcpy channels ARM: PL08x: allow dma_set_runtime_config() to return errors ARM: PL08x: fix locking between prepare function and submit function ARM: PL08x: introduce 'phychan_hold' to hold on to physical channels ARM: PL08x: put txd's on the pending list in pl08x_tx_submit() ARM: PL08x: rename 'desc_list' as 'pend_list' ARM: PL08x: implement unmapping of memcpy buffers ARM: PL08x: store prep_* flags in async_tx structure ARM: PL08x: shrink srcbus/dstbus in txd structure ...
| * dmaengine: at_hdmac: fix race while monitoring channel statusNicolas Ferre2011-01-141-2/+2
| | | | | | | | | | | | | | | | We were reading channel status then taking a lock. This lead to a race because this lock may delay us and then make this channel not idle anymore. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * dmaengine: at_hdmac: flags located in first descriptorNicolas Ferre2011-01-141-3/+3
| | | | | | | | | | | | | | | | Place flags on first descriptor of chain instead of last. This is the one used by atc_chain_complete() function while unmapping. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * dmaengine: at_hdmac: use subsys_initcall instead of module_initEric Xu2011-01-141-1/+1
| | | | | | | | | | | | | | | | | | Use subsys_initcall instead of module_init in order to keep DMA engine rolling before other peripheral drivers. Signed-off-by: Eric Xu <hong.xu@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * dmaengine: at_hdmac: no need set ACK in new descriptorNicolas Ferre2011-01-141-1/+0
| | | | | | | | | | | | | | | | Following descriptor flow in at_hdmac driver, descriptor comming from atc_desc_get() as already DMA_CTRL_ACK flag set. No need to set it again. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * dmaengine: at_hdmac: trivial add precision to unmapping commentNicolas Ferre2011-01-141-1/+1
| | | | | | | | | | Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * dmaengine: at_hdmac: use dma_address to program DMA hardwareNicolas Ferre2011-01-141-2/+2
| | | | | | | | | | | | | | | | | | In atc_prep_slave_sg() function we use dma_address field of scatterlist with sg_dma_address() macro instead of sg_phys(). DMA address is already computed by dma_map_sg() or another mapping function in calling driver. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* | dmaengine: at_hdmac: fix buffer transfer size specificationNicolas Ferre2010-12-141-1/+1
|/ | | | | | | | | | Buffer transfer size is the number of transfers to be performed in relation with the width of the _source_ interface. So in the DMA_FROM_DEVICE case, it should be the register width that should be taken into account. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* Merge branch 'next' of ↵Linus Torvalds2010-08-091-2/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (30 commits) DMAENGINE: at_hdmac: locking fixlet DMAENGINE: pch_dma: kill another usage of __raw_{read|write}l dma: dmatest: fix potential sign bug ioat2: catch and recover from broken vtd configurations v6 DMAENGINE: add runtime slave control to COH 901 318 v3 DMAENGINE: add runtime slave config to DMA40 v3 DMAENGINE: generic slave channel control v3 dmaengine: Driver for Topcliff PCH DMA controller intel_mid: Add Mrst & Mfld DMA Drivers drivers/dma: Eliminate a NULL pointer dereference dma/timb_dma: compile warning on 32 bit DMAENGINE: ste_dma40: support older silicon DMAENGINE: ste_dma40: support disabling physical channels DMAENGINE: ste_dma40: no disabled phy channels on ux500 DMAENGINE: ste_dma40: fix suspend bug DMAENGINE: ste_dma40: add DB8500 memcpy channels DMAENGINE: ste_dma40: no flow control on memcpy DMAENGINE: ste_dma40: arch updates for LCLA and LCPA DMAENGINE: ste_dma40: allocate LCLA dynamically DMAENGINE: ste_dma40: no premature stop ... Fix up trivial conflicts in arch/arm/mach-ux500/devices-db8500.c
| * DMAENGINE: at_hdmac: locking fixletYong Wang2010-08-041-2/+2
| | | | | | | | | | | | | | | | atc_chain_complete shall be called with atchan->lock held and bh disabled. Signed-off-by: Yong Wang <yong.y.wang@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* | Merge branch 'master' into for-nextJiri Kosina2010-06-161-16/+19
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| * Merge branch 'ioat' into dmaengineDan Williams2010-05-171-0/+1
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| * | DMAENGINE: extend the control command to include an argLinus Walleij2010-05-171-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds an argument to the DMAengine control function, so that we can later provide control commands that need some external data passed in through an argument akin to the ioctl() operation prototype. [dan.j.williams@intel.com: fix up some missed conversions] Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
generated by cgit (git 2.34.1) at 2024-06-17 18:43:56 +0000