| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on ASID-capable CPUs | Catalin Marinas | 2012-04-17 | 1 | -3/+0 |
| * | ARM: Use TTBR1 instead of reserved context ID | Will Deacon | 2012-04-17 | 1 | -6/+4 |
| * | ARM: LPAE: Factor out classic-MMU specific code into proc-v7-2level.S | Catalin Marinas | 2011-12-08 | 1 | -0/+171 |
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