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authorBen Skeggs <bskeggs@redhat.com>2012-02-06 16:20:30 +1000
committerBen Skeggs <bskeggs@redhat.com>2012-05-24 16:31:36 +1000
commit78c20186581c7558429b591fb2942be44b47d59f (patch)
tree44eb50599b8142f1a3a8088bf5db3e9ec879763b /drivers/gpu
parent9d6ba0b58c5f1ea52b641c36178a27e876b80011 (diff)
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drm/nouveau/pm: some more delays for ddr3 reclocking
These numbers from the binary driver's daemon scripts, and fix the transition to perflvl 3 on my T510. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_mem.c3
-rw-r--r--drivers/gpu/drm/nouveau/nva3_pm.c1
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index ec4c53f41171..585dcbeafcda 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -978,6 +978,8 @@ nouveau_mem_exec(struct nouveau_mem_exec_func *exec,
break;
case NV_MEM_TYPE_DDR3:
tDLLK = 12000;
+ tCKSRE = 2000;
+ tXS = 1000;
mr1_dlloff = 0x00000001;
break;
case NV_MEM_TYPE_GDDR3:
@@ -1024,6 +1026,7 @@ nouveau_mem_exec(struct nouveau_mem_exec_func *exec,
exec->refresh_self(exec, false);
exec->refresh_auto(exec, true);
exec->wait(exec, tXS);
+ exec->wait(exec, tXS);
/* update MRs */
if (mr[2] != info->mr[2]) {
diff --git a/drivers/gpu/drm/nouveau/nva3_pm.c b/drivers/gpu/drm/nouveau/nva3_pm.c
index d51e8f86b4d5..798829353fb6 100644
--- a/drivers/gpu/drm/nouveau/nva3_pm.c
+++ b/drivers/gpu/drm/nouveau/nva3_pm.c
@@ -344,6 +344,7 @@ mclk_refresh_self(struct nouveau_mem_exec_func *exec, bool enable)
static void
mclk_wait(struct nouveau_mem_exec_func *exec, u32 nsec)
{
+ volatile u32 post = nv_rd32(exec->dev, 0); (void)post;
udelay((nsec + 500) / 1000);
}