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| author | Martin Peres <martin.peres@ensi-bourges.fr> | 2011-07-10 00:08:41 +0200 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2011-12-21 19:01:23 +1000 |
| commit | dd1da8de172057b36860f427777ecfa293bb8f6c (patch) | |
| tree | d31ad5ed9528cb74843a58dc084e9bcdbe2e7587 /drivers/gpu/drm/nouveau/nv40_pm.c | |
| parent | 6109183794a711d80c08705d477d2a19b437d5c1 (diff) | |
| download | linux-dd1da8de172057b36860f427777ecfa293bb8f6c.tar.gz linux-dd1da8de172057b36860f427777ecfa293bb8f6c.tar.xz linux-dd1da8de172057b36860f427777ecfa293bb8f6c.zip | |
drm/nouveau/pm: make clocks_set return an error code clocks_set can fail.
Reporting an error is better than silently refusing to reclock.
V2: Use the same logic on nv40
Signed-off-by: Martin Peres <martin.peres@labri.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv40_pm.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nv40_pm.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/gpu/drm/nouveau/nv40_pm.c b/drivers/gpu/drm/nouveau/nv40_pm.c index 02d5be8bff1b..3d5a5a7856e6 100644 --- a/drivers/gpu/drm/nouveau/nv40_pm.c +++ b/drivers/gpu/drm/nouveau/nv40_pm.c @@ -222,7 +222,7 @@ nv40_pm_gr_idle(void *data) return true; } -void +int nv40_pm_clocks_set(struct drm_device *dev, void *pre_state) { struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -231,7 +231,7 @@ nv40_pm_clocks_set(struct drm_device *dev, void *pre_state) struct bit_entry M; u32 crtc_mask = 0; u8 sr1[2]; - int i; + int i, ret = -EAGAIN; /* determine which CRTCs are active, fetch VGA_SR1 for each */ for (i = 0; i < 2; i++) { @@ -263,6 +263,8 @@ nv40_pm_clocks_set(struct drm_device *dev, void *pre_state) if (!nv_wait_cb(dev, nv40_pm_gr_idle, dev)) goto resume; + ret = 0; + /* set engine clocks */ nv_mask(dev, 0x00c040, 0x00000333, 0x00000000); nv_wr32(dev, 0x004004, info->npll_coef); @@ -345,6 +347,7 @@ resume: spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); kfree(info); + return ret; } int |