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| author | Ben Skeggs <bskeggs@redhat.com> | 2012-05-01 10:14:07 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2012-05-24 16:56:00 +1000 |
| commit | 67b342efc761046a22b73c327837479b58613a41 (patch) | |
| tree | 86a7d34699e48b855a8a99d8aaab3465cd2f8cd3 /drivers/gpu/drm/nouveau/nouveau_drv.c | |
| parent | 906c033e276877c1374c9159976b05746af3c86d (diff) | |
| download | linux-67b342efc761046a22b73c327837479b58613a41.tar.gz linux-67b342efc761046a22b73c327837479b58613a41.tar.xz linux-67b342efc761046a22b73c327837479b58613a41.zip | |
drm/nouveau/fifo: remove all the "special" engine hooks
All the places this stuff is actually needed tends to be chipset-specific
anyway, so we're able to just inline the register bashing instead.
The parts of the common code that still directly touch PFIFO temporarily
have conditionals, these will be removed in subsequent commits that will
refactor the fifo modules into engine modules like graph/mpeg etc.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_drv.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_drv.c | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.c b/drivers/gpu/drm/nouveau/nouveau_drv.c index b394ecf787f6..adc6502d296c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.c +++ b/drivers/gpu/drm/nouveau/nouveau_drv.c @@ -221,8 +221,12 @@ nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state) nouveau_channel_idle(chan); } - pfifo->reassign(dev, false); - pfifo->disable(dev); + if (dev_priv->card_type < NV_C0) { + nv_wr32(dev, NV03_PFIFO_CACHES, 0); + nv_mask(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001, 0); + nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 0); + nv_mask(dev, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0); + } pfifo->unload_context(dev); for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) { @@ -265,8 +269,11 @@ out_abort: if (dev_priv->eng[e]) dev_priv->eng[e]->init(dev, e); } - pfifo->enable(dev); - pfifo->reassign(dev, true); + if (dev_priv->card_type < NV_C0) { + nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 1); + nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1); + nv_wr32(dev, NV03_PFIFO_CACHES, 1); + } return ret; } |