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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2010-09-13 14:19:16 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2010-09-13 14:32:18 +0100 |
| commit | f7abfe8b281991c66406c42c1a6c6c9ee0daa0ff (patch) | |
| tree | 22ac64e9f3e5e7ec7044abafefa23e1b0ae14f63 /drivers/gpu/drm/i915/intel_overlay.c | |
| parent | 6b383a7f6378f193c30200435d8170f95916b5f0 (diff) | |
| download | linux-f7abfe8b281991c66406c42c1a6c6c9ee0daa0ff.tar.gz linux-f7abfe8b281991c66406c42c1a6c6c9ee0daa0ff.tar.xz linux-f7abfe8b281991c66406c42c1a6c6c9ee0daa0ff.zip | |
drm/i915: Fix an overlay regression from 7e7d76c
When separating out the prepare/commit into its own separate functions
we overlooked that the intel_crtc->dpms_mode was being used elsewhere to
check on the actual status of the pipe.
Track that bit of logic separately from the actual dpms mode, so there
is no confusion should we be able to handle multiple dpms modes, nor
any semantic conflict between prepare/commit and dpms.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_overlay.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_overlay.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c index 3dff16118ee5..c4699c916698 100644 --- a/drivers/gpu/drm/i915/intel_overlay.c +++ b/drivers/gpu/drm/i915/intel_overlay.c @@ -875,15 +875,13 @@ static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, struct intel_crtc *crtc) { drm_i915_private_t *dev_priv = overlay->dev->dev_private; - u32 pipeconf; - if (!crtc->base.enabled || crtc->dpms_mode != DRM_MODE_DPMS_ON) + if (!crtc->active) return -EINVAL; - pipeconf = I915_READ(PIPECONF(crtc->pipe)); - /* can't use the overlay with double wide pipe */ - if (!IS_I965G(overlay->dev) && pipeconf & PIPECONF_DOUBLE_WIDE) + if (!IS_I965G(overlay->dev) && + (I915_READ(PIPECONF(crtc->pipe)) & (PIPECONF_DOUBLE_WIDE | PIPECONF_ENABLE)) != PIPECONF_ENABLE) return -EINVAL; return 0; |