/*------------------------------------------------------------------------
 . smc91111.h - macros for the LAN91C111 Ethernet Driver
 .
 . (C) Copyright 2002
 . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 . Rolf Offermanns <rof@sysgo.de>
 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
 .       Developed by Simple Network Magic Corporation (SNMC)
 . Copyright (C) 1996 by Erik Stahlman (ES)
 .
  * SPDX-License-Identifier:	GPL-2.0+
 .
 . This file contains register information and access macros for
 . the LAN91C111 single chip ethernet controller.  It is a modified
 . version of the smc9194.h file.
 .
 . Information contained in this file was obtained from the LAN91C111
 . manual from SMC.  To get a copy, if you really want one, you can find
 . information under www.smsc.com.
 .
 . Authors
 .	Erik Stahlman				( erik@vt.edu )
 .	Daris A Nevil				( dnevil@snmc.com )
 .
 . History
 . 03/16/01		Daris A Nevil	Modified for use with LAN91C111 device
 .
 ---------------------------------------------------------------------------*/
#ifndef _SMC91111_H_
#define _SMC91111_H_

#include <asm/types.h>
#include <config.h>

/*
 * This function may be called by the board specific initialisation code
 * in order to override the default mac address.
 */

void smc_set_mac_addr (const unsigned char *addr);


/* I want some simple types */

typedef unsigned char			byte;
typedef unsigned short			word;
typedef unsigned long int		dword;

struct smc91111_priv{
	u8 dev_num;
};

/*
 . DEBUGGING LEVELS
 .
 . 0 for normal operation
 . 1 for slightly more details
 . >2 for various levels of increasingly useless information
 .    2 for interrupt tracking, status flags
 .    3 for packet info
 .    4 for complete packet dumps
*/
/*#define SMC_DEBUG 0 */

/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */

#define	SMC_IO_EXTENT	16

#ifdef CONFIG_CPU_PXA25X

#ifdef CONFIG_XSENGINE
#define	SMC_inl(a,r)	(*((volatile dword *)((a)->iobase+((r)<<1))))
#define	SMC_inw(a,r)	(*((volatile word *)((a)->iobase+((r)<<1))))
#define SMC_inb(a,p)  ({ \
	unsigned int __p = (unsigned int)((a)->iobase + ((p)<<1)); \
	unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \
	if (__p & 2) __v >>= 8; \
	else __v &= 0xff; \
	__v; })
#else
#define	SMC_inl(a,r)	(*((volatile dword *)((a)->iobase+(r))))
#define	SMC_inw(a,r)	(*((volatile word *)((a)->iobase+(r))))
#define SMC_inb(a,p)	({ \
	unsigned int __p = (unsigned int)((a)->iobase + (p)); \
	unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \
	if (__p & 1) __v >>= 8; \
	else __v &= 0xff; \
	__v; })
#endif

#ifdef CONFIG_XSENGINE
#define	SMC_outl(a,d,r)	(*((volatile dword *)((a)->iobase+(r<<1))) = d)
#define	SMC_outw(a,d,r)	(*((volatile word *)((a)->iobase+(r<<1))) = d)
#else
#define	SMC_outl(a,d,r)	(*((volatile dword *)((a)->iobase+(r))) = d)
#define	SMC_outw(a,d,r)	(*((volatile word *)((a)->iobase+(r))) = d)
#endif

#define	SMC_outb(a,d,r)	({	word __d = (byte)(d);  \
				word __w = SMC_inw((a),(r)&~1);  \
				__w &= ((r)&1) ? 0x00FF : 0xFF00;  \
				__w |= ((r)&1) ? __d<<8 : __d;  \
				SMC_outw((a),__w,(r)&~1);  \
			})

#define SMC_outsl(a,r,b,l)	({	int __i; \
					dword *__b2; \
					__b2 = (dword *) b; \
					for (__i = 0; __i < l; __i++) { \
					    SMC_outl((a), *(__b2 + __i), r); \
					} \
				})

#define SMC_outsw(a,r,b,l)	({	int __i; \
					word *__b2; \
					__b2 = (word *) b; \
					for (__i = 0; __i < l; __i++) { \
					    SMC_outw((a), *(__b2 + __i), r); \
					} \
				})

#define SMC_insl(a,r,b,l)	({	int __i ;  \
					dword *__b2;  \
					__b2 = (dword *) b;  \
					for (__i = 0; __i < l; __i++) {  \
					  *(__b2 + __i) = SMC_inl((a),(r));  \
					  SMC_inl((a),0);  \
					};  \
				})

#define SMC_insw(a,r,b,l)		({	int __i ;  \
					word *__b2;  \
					__b2 = (word *) b;  \
					for (__i = 0; __i < l; __i++) {  \
					  *(__b2 + __i) = SMC_inw((a),(r));  \
					  SMC_inw((a),0);  \
					};  \
				})

#define SMC_insb(a,r,b,l)	({	int __i ;  \
					byte *__b2;  \
					__b2 = (byte *) b;  \
					for (__i = 0; __i < l; __i++) {  \
					  *(__b2 + __i) = SMC_inb((a),(r));  \
					  SMC_inb((a),0);  \
					};  \
				})

#elif defined(CONFIG_LEON)	/* if not CONFIG_CPU_PXA25X */

#define SMC_LEON_SWAP16(_x_) ({ word _x = (_x_); ((_x << 8) | (_x >> 8)); })

#define SMC_LEON_SWAP32(_x_)			\
    ({ dword _x = (_x_);			\
       ((_x << 24) |				\
       ((0x0000FF00UL & _x) <<  8) |		\
       ((0x00FF0000UL & _x) >>  8) |		\
       (_x  >> 24)); })

#define	SMC_inl(a,r)	(SMC_LEON_SWAP32((*(volatile dword *)((a)->iobase+((r)<<0)))))
#define	SMC_inl_nosw(a,r)	((*(volatile dword *)((a)->iobase+((r)<<0))))
#define	SMC_inw(a,r)	(SMC_LEON_SWAP16((*(volatile word *)((a)->iobase+((r)<<0)))))
#define	SMC_inw_nosw(a,r)	((*(volatile word *)((a)->iobase+((r)<<0))))
#define SMC_inb(a,p)	({ \
	word ___v = SMC_inw((a),(p) & ~1); \
	if ((p) & 1) ___v >>= 8; \
	else ___v &= 0xff; \
	___v; })

#define	SMC_outl(a,d,r)	(*(volatile dword *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP32(d))
#define	SMC_outl_nosw(a,d,r)	(*(volatile dword *)((a)->iobase+((r)<<0))=(d))
#define	SMC_outw(a,d,r)	(*(volatile word *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP16(d))
#define	SMC_outw_nosw(a,d,r)	(*(volatile word *)((a)->iobase+((r)<<0))=(d))
#define	SMC_outb(a,d,r)	do{	word __d = (byte)(d);  \
				word __w = SMC_inw((a),(r)&~1);  \
				__w &= ((r)&1) ? 0x00FF : 0xFF00;  \
				__w |= ((r)&1) ? __d<<8 : __d;  \
				SMC_outw((a),__w,(r)&~1);  \
			}while(0)
#define SMC_outsl(a,r,b,l)	do{	int __i; \
					dword *__b2; \
					__b2 = (dword *) b; \
					for (__i = 0; __i < l; __i++) { \
					    SMC_outl_nosw((a), *(__b2 + __i), r); \
					} \
				}while(0)
#define SMC_outsw(a,r,b,l)	do{	int __i; \
					word *__b2; \
					__b2 = (word *) b; \
					for (__i = 0; __i < l; __i++) { \
					    SMC_outw_nosw((a), *(__b2 + __i), r); \
					} \
				}while(0)
#define SMC_insl(a,r,b,l)	do{	int __i ;  \
					dword *__b2;  \
					__b2 = (dword *) b;  \
					for (__i = 0; __i < l; __i++) {  \
					  *(__b2 + __i) = SMC_inl_nosw((a),(r));  \
					};  \
				}while(0)

#define SMC_insw(a,r,b,l)		do{	int __i ;  \
					word *__b2;  \
					__b2 = (word *) b;  \
					for (__i = 0; __i < l; __i++) {  \
					  *(__b2 + __i) = SMC_inw_nosw((a),(r));  \
					};  \
				}while(0)

#define SMC_insb(a,r,b,l)		do{	int __i ;  \
					byte *__b2;  \
					__b2 = (byte *) b;  \
					for (__i = 0; __i < l; __i++) {  \
					  *(__b2 + __i) = SMC_inb((a),(r));  \
					};  \
				}while(0)
#elif defined(CONFIG_MS7206SE)
#define SWAB7206(x) ({ word __x = x; ((__x << 8)|(__x >> 8)); })
#define SMC_inw(a, r) *((volatile word*)((a)->iobase + (r)))
#define SMC_inb(a, r) (*((volatile byte*)((a)->iobase + ((r) ^ 0x01))))
#define SMC_insw(a, r, b, l) \
	do { \
		int __i; \
		word *__b2 = (word *)(b);		  \
		for (__i = 0; __i < (l); __i++) { \
			*__b2++ = SWAB7206(SMC_inw(a, r));	\
		} \
	} while (0)
#define	SMC_outw(a, d, r)	(*((volatile word *)((a)->iobase+(r))) = d)
#define	SMC_outb(a, d, r)	({	word __d = (byte)(d);  \
				word __w = SMC_inw((a), ((r)&(~1)));	\
				if (((r) & 1)) \
					__w = (__w & 0x00ff) | (__d << 8); \
				else \
					__w = (__w & 0xff00) | (__d); \
				SMC_outw((a), __w, ((r)&(~1)));	      \
			})
#define SMC_outsw(a, r, b, l) \
	do { \
		int __i; \
		word *__b2 = (word *)(b);		  \
		for (__i = 0; __i < (l); __i++) { \
			SMC_outw(a, SWAB7206(*__b2), r);	  \
			__b2++; \
		} \
	} while (0)
#else			/* if not CONFIG_CPU_PXA25X and not CONFIG_LEON */

#ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */
/*
 * We have only 16 Bit PCMCIA access on Socket 0
 */

#ifdef CONFIG_ADNPESC1
#define	SMC_inw(a,r)	(*((volatile word *)((a)->iobase+((r)<<1))))
#elif CONFIG_BLACKFIN
#define	SMC_inw(a,r)	({ word __v = (*((volatile word *)((a)->iobase+(r)))); SSYNC(); __v;})
#elif CONFIG_ARM64
#define	SMC_inw(a, r)	(*((volatile word*)((a)->iobase+((dword)(r)))))
#else
#define SMC_inw(a, r)	(*((volatile word*)((a)->iobase+(r))))
#endif
#define  SMC_inb(a,r)	(((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF))

#ifdef CONFIG_ADNPESC1
#define	SMC_outw(a,d,r)	(*((volatile word *)((a)->iobase+((r)<<1))) = d)
#elif CONFIG_BLACKFIN
#define	SMC_outw(a, d, r)	\
			({	(*((volatile word*)((a)->iobase+((r)))) = d); \
				SSYNC(); \
			})
#elif CONFIG_ARM64
#define	SMC_outw(a, d, r)	\
			(*((volatile word*)((a)->iobase+((dword)(r)))) = d)
#else
#define	SMC_outw(a, d, r)	\
			(*((volatile word*)((a)->iobase+(r))) = d)
#endif
#define	SMC_outb(a,d,r)	({	word __d = (byte)(d);  \
				word __w = SMC_inw((a),(r)&~1);  \
				__w &= ((r)&1) ? 0x00FF : 0xFF00;  \
				__w |= ((r)&1) ? __d<<8 : __d;  \
				SMC_outw((a),__w,(r)&~1);  \
			})
#if 0
#define	SMC_outsw(a,r,b,l)	outsw((a)->iobase+(r), (b), (l))
#else
#define SMC_outsw(a,r,b,l)	({	int __i; \
					word *__b2; \
					__b2 = (word *) b; \
					for (__i = 0; __i < l; __i++) { \
					    SMC_outw((a), *(__b2 + __i), r); \
					} \
				})
#endif

#if 0
#define	SMC_insw(a,r,b,l)	insw((a)->iobase+(r), (b), (l))
#else
#define SMC_insw(a,r,b,l)	({	int __i ;  \
					word *__b2;  \
					__b2 = (word *) b;  \
					for (__i = 0; __i < l; __i++) {  \
					  *(__b2 + __i) = SMC_inw((a),(r));  \
					  SMC_inw((a),0);  \
					};  \
				})
#endif

#endif  /* CONFIG_SMC_USE_IOFUNCS */

#if defined(CONFIG_SMC_USE_32_BIT)

#ifdef CONFIG_XSENGINE
#define	SMC_inl(a,r)	(*((volatile dword *)((a)->iobase+(r<<1))))
#else
#define	SMC_inl(a,r)	(*((volatile dword *)((a)->iobase+(r))))
#endif

#define SMC_insl(a,r,b,l)	({	int __i ;  \
					dword *__b2;  \
					__b2 = (dword *) b;  \
					for (__i = 0; __i < l; __i++) {  \
					  *(__b2 + __i) = SMC_inl((a),(r));  \
					  SMC_inl((a),0);  \
					};  \
				})

#ifdef CONFIG_XSENGINE
#define	SMC_outl(a,d,r)	(*((volatile dword *)((a)->iobase+(r<<1))) = d)
#else
#define	SMC_outl(a,d,r)	(*((volatile dword *)((a)->iobase+(r))) = d)
#endif
#define SMC_outsl(a,r,b,l)	({	int __i; \
					dword *__b2; \
					__b2 = (dword *) b; \
					for (__i = 0; __i < l; __i++) { \
					    SMC_outl((a), *(__b2 + __i), r); \
					} \
				})

#endif /* CONFIG_SMC_USE_32_BIT */

#endif

/*---------------------------------------------------------------
 .
 . A description of the SMSC registers is probably in order here,
 . although for details, the SMC datasheet is invaluable.
 .
 . Basically, the chip has 4 banks of registers ( 0 to 3 ), which
 . are accessed by writing a number into the BANK_SELECT register
 . ( I also use a SMC_SELECT_BANK macro for this ).
 .
 . The banks are configured so that for most purposes, bank 2 is all
 . that is needed for simple run time tasks.
 -----------------------------------------------------------------------*/

/*
 . Bank Select Register:
 .
 .		yyyy yyyy 0000 00xx
 .		xx		= bank number
 .		yyyy yyyy	= 0x33, for identification purposes.
*/
#define	BANK_SELECT		14

/* Transmit Control Register */
/* BANK 0  */
#define	TCR_REG		0x0000	/* transmit control register */
#define TCR_ENABLE	0x0001	/* When 1 we can transmit */
#define TCR_LOOP	0x0002	/* Controls output pin LBK */
#define TCR_FORCOL	0x0004	/* When 1 will force a collision */
#define TCR_PAD_EN	0x0080	/* When 1 will pad tx frames < 64 bytes w/0 */
#define TCR_NOCRC	0x0100	/* When 1 will not append CRC to tx frames */
#define TCR_MON_CSN	0x0400	/* When 1 tx monitors carrier */
#define TCR_FDUPLX	0x0800  /* When 1 enables full duplex operation */
#define TCR_STP_SQET	0x1000	/* When 1 stops tx if Signal Quality Error */
#define	TCR_EPH_LOOP	0x2000	/* When 1 enables EPH block loopback */
#define	TCR_SWFDUP	0x8000	/* When 1 enables Switched Full Duplex mode */

#define	TCR_CLEAR	0	/* do NOTHING */
/* the default settings for the TCR register : */
/* QUESTION: do I want to enable padding of short packets ? */
#define	TCR_DEFAULT	TCR_ENABLE


/* EPH Status Register */
/* BANK 0  */
#define EPH_STATUS_REG	0x0002
#define ES_TX_SUC	0x0001	/* Last TX was successful */
#define ES_SNGL_COL	0x0002	/* Single collision detected for last tx */
#define ES_MUL_COL	0x0004	/* Multiple collisions detected for last tx */
#define ES_LTX_MULT	0x0008	/* Last tx was a multicast */
#define ES_16COL	0x0010	/* 16 Collisions Reached */
#define ES_SQET		0x0020	/* Signal Quality Error Test */
#define ES_LTXBRD	0x0040	/* Last tx was a broadcast */
#define ES_TXDEFR	0x0080	/* Transmit Deferred */
#define ES_LATCOL	0x0200	/* Late collision detected on last tx */
#define ES_LOSTCARR	0x0400	/* Lost Carrier Sense */
#define ES_EXC_DEF	0x0800	/* Excessive Deferral */
#define ES_CTR_ROL	0x1000	/* Counter Roll Over indication */
#define ES_LINK_OK	0x4000	/* Driven by inverted value of nLNK pin */
#define ES_TXUNRN	0x8000	/* Tx Underrun */


/* Receive Control Register */
/* BANK 0  */
#define	RCR_REG		0x0004
#define	RCR_RX_ABORT	0x0001	/* Set if a rx frame was aborted */
#define	RCR_PRMS	0x0002	/* Enable promiscuous mode */
#define	RCR_ALMUL	0x0004	/* When set accepts all multicast frames */
#define RCR_RXEN	0x0100	/* IFF this is set, we can receive packets */
#define	RCR_STRIP_CRC	0x0200	/* When set strips CRC from rx packets */
#define	RCR_ABORT_ENB	0x0200	/* When set will abort rx on collision */
#define	RCR_FILT_CAR	0x0400	/* When set filters leading 12 bit s of carrier */
#define RCR_SOFTRST	0x8000	/* resets the chip */

/* the normal settings for the RCR register : */
#define	RCR_DEFAULT	(RCR_STRIP_CRC | RCR_RXEN)
#define RCR_CLEAR	0x0	/* set it to a base state */

/* Counter Register */
/* BANK 0  */
#define	COUNTER_REG	0x0006

/* Memory Information Register */
/* BANK 0  */
#define	MIR_REG		0x0008

/* Receive/Phy Control Register */
/* BANK 0  */
#define	RPC_REG		0x000A
#define	RPC_SPEED	0x2000	/* When 1 PHY is in 100Mbps mode. */
#define	RPC_DPLX	0x1000	/* When 1 PHY is in Full-Duplex Mode */
#define	RPC_ANEG	0x0800	/* When 1 PHY is in Auto-Negotiate Mode */
#define	RPC_LSXA_SHFT	5	/* Bits to shift LS2A,LS1A,LS0A to lsb */
#define	RPC_LSXB_SHFT	2	/* Bits to get LS2B,LS1B,LS0B to lsb */
#define RPC_LED_100_10	(0x00)	/* LED = 100Mbps OR's with 10Mbps link detect */
#define RPC_LED_RES	(0x01)	/* LED = Reserved */
#define RPC_LED_10	(0x02)	/* LED = 10Mbps link detect */
#define RPC_LED_FD	(0x03)	/* LED = Full Duplex Mode */
#define RPC_LED_TX_RX	(0x04)	/* LED = TX or RX packet occurred */
#define RPC_LED_100	(0x05)	/* LED = 100Mbps link dectect */
#define RPC_LED_TX	(0x06)	/* LED = TX packet occurred */
#define RPC_LED_RX	(0x07)	/* LED = RX packet occurred */
#if defined(CONFIG_DK1C20) || defined(CONFIG_DK1S10)
/* buggy schematic: LEDa -> yellow, LEDb --> green */
#define RPC_DEFAULT	( RPC_SPEED | RPC_DPLX | RPC_ANEG	\
			| (RPC_LED_TX_RX << RPC_LSXA_SHFT)	\
			| (RPC_LED_100_10 << RPC_LSXB_SHFT)	)
#elif defined(CONFIG_ADNPESC1)
/* SSV ADNP/ESC1 has only one LED: LEDa -> Rx/Tx indicator */
#define RPC_DEFAULT	( RPC_SPEED | RPC_DPLX | RPC_ANEG	\
			| (RPC_LED_TX_RX << RPC_LSXA_SHFT)	\
			| (RPC_LED_100_10 << RPC_LSXB_SHFT)	)
#else
/* SMSC reference design: LEDa --> green, LEDb --> yellow */
#define RPC_DEFAULT	( RPC_SPEED | RPC_DPLX | RPC_ANEG	\
			| (RPC_LED_100_10 << RPC_LSXA_SHFT)	\
			| (RPC_LED_TX_RX << RPC_LSXB_SHFT)	)
#endif

/* Bank 0 0x000C is reserved */

/* Bank Select Register */
/* All Banks */
#define BSR_REG	0x000E


/* Configuration Reg */
/* BANK 1 */
#define CONFIG_REG	0x0000
#define CONFIG_EXT_PHY	0x0200	/* 1=external MII, 0=internal Phy */
#define CONFIG_GPCNTRL	0x0400	/* Inverse value drives pin nCNTRL */
#define CONFIG_NO_WAIT	0x1000	/* When 1 no extra wait states on ISA bus */
#define CONFIG_EPH_POWER_EN 0x8000 /* When 0 EPH is placed into low power mode. */

/* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */
#define CONFIG_DEFAULT	(CONFIG_EPH_POWER_EN)


/* Base Address Register */
/* BANK 1 */
#define	BASE_REG	0x0002


/* Individual Address Registers */
/* BANK 1 */
#define	ADDR0_REG	0x0004
#define	ADDR1_REG	0x0006
#define	ADDR2_REG	0x0008