summaryrefslogtreecommitdiffstats
path: root/board/esd/pmc405/pmc405.c
blob: c0781dc950ef7b1815764d03660516778ece4f00 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
/*
 * (C) Copyright 2001-2003
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * (C) Copyright 2005
 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <command.h>
#include <malloc.h>

DECLARE_GLOBAL_DATA_PTR;

extern void lxt971_no_sleep(void);

/* fpga configuration data - not compressed, generated by bin2c */
const unsigned char fpgadata[] =
{
#include "fpgadata.c"
};
int filesize = sizeof(fpgadata);


int board_early_init_f (void)
{
	/*
	 * IRQ 0-15  405GP internally generated; active high; level sensitive
	 * IRQ 16    405GP internally generated; active low; level sensitive
	 * IRQ 17-24 RESERVED
	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
	 */
	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
	mtdcr(uicer, 0x00000000);       /* disable all ints */
	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
	mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */

	/*
	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
	 */
	mtebc (epcr, 0xa8400000);

	/*
	 * Setup GPIO pins
	 */

	mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_FPGA_INIT | \
					CONFIG_SYS_FPGA_DONE | \
					CONFIG_SYS_XEREADY | \
					CONFIG_SYS_NONMONARCH | \
					CONFIG_SYS_REV1_2) << 5));

	if (!(in32(GPIO0_IR) & CONFIG_SYS_REV1_2)) {
		/* rev 1.2 boards */
		mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_INTA_FAKE | \
						CONFIG_SYS_SELF_RST) << 5));
	}

	out32(GPIO0_OR, 0);
	out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK | CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY); /* setup for output */

	/* - check if rev1_2 is low, then:
	 * - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST in TCR to assert INTA# or SELFRST#
	 */

	return 0;
}


/* ------------------------------------------------------------------------- */


int misc_init_r (void)
{
	/* adjust flash start and offset */
	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	gd->bd->bi_flashoffset = 0;

	out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_XEREADY); /* deassert EREADY# */
	return (0);
}

ushort pmc405_pci_subsys_deviceid(void)
{
	ulong val;
	val = in32(GPIO0_IR);
	if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
		if (val & CONFIG_SYS_NONMONARCH) { /* monarch# signal */
			return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
		}
		return CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH;
	}
	return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
}

/*
 * Check Board Identity:
 */
int checkboard (void)
{
	ulong val;

	char str[64];
	int i = getenv_r ("serial#", str, sizeof(str));

	puts ("Board: ");

	if (i == -1) {
		puts ("### No HW ID - assuming PMC405");
	} else {
		puts(str);
	}

	val = in32(GPIO0_IR);
	if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
		puts(" rev1.2 (");
		if (val & CONFIG_SYS_NONMONARCH) { /* monarch# signal */
			puts("non-");
		}
		puts("monarch)");
	} else {
		puts(" <=rev1.1");
	}

	putc ('\n');

	return 0;
}

/* ------------------------------------------------------------------------- */
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP

	/*
	 * Disable sleep mode in LXT971
	 */
	lxt971_no_sleep();
#endif
}


int do_cantest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	ulong addr;
	volatile uchar *ptr;
	volatile uchar val;
	int i;

	addr = simple_strtol (argv[1], NULL, 16) + 0x16;

	i = 0;
	for (;;) {
		ptr = (uchar *)addr;
		for (i=0; i<8; i++) {
			*ptr = i;
			val = *ptr;

			if (val != i) {
				printf("ERROR: addr=%p write=0x%02X, read=0x%02X\n", ptr, i, val);
				return 0;
			}

			/* Abort if ctrl-c was pressed */
			if (ctrlc()) {
				puts("\nAbort\n");
				return 0;
			}

			ptr++;
		}
	}

	return 0;
}
U_BOOT_CMD(
	cantest,	3,	1,	do_cantest,
	"cantest - Test CAN controller",
	NULL
	);