// SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2021 Gateworks Corporation */ #include #include #include #include #include #include #include #include #include #include "gsc.h" DECLARE_GLOBAL_DATA_PTR; int board_phys_sdram_size(phys_size_t *size) { int ddr_size = readl(M4_BOOTROM_BASE_ADDR); if (ddr_size == 0x4) { *size = 0x100000000; } else if (ddr_size == 0x3) { *size = 0xc0000000; } else if (ddr_size == 0x2) { *size = 0x80000000; } else if (ddr_size == 0x1) { *size = 0x40000000; } else { printf("Unknown DDR type!!!\n"); *size = 0x40000000; } return 0; } int board_fit_config_name_match(const char *name) { int i = 0; const char *dtb; char buf[32]; do { dtb = gsc_get_dtb_name(i++, buf, sizeof(buf)); if (!strcmp(dtb, name)) return 0; } while (dtb); return -1; } #if (IS_ENABLED(CONFIG_FEC_MXC)) static int setup_fec(void) { struct iomuxc_gpr_base_regs *gpr = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; /* Use 125M anatop REF_CLK1 for ENET1, not from external */ clrsetbits_le32(&gpr->gpr[1], 0x2000, 0); return 0; } int board_phy_config(struct phy_device *phydev) { unsigned short val; switch (phydev->phy_id) { case 0x2000a231: /* TI DP83867 GbE PHY */ puts("DP83867 "); /* LED configuration */ val = 0; val |= 0x5 << 4; /* LED1(Amber;Speed) : 1000BT link */ val |= 0xb << 8; /* LED2(Green;Link/Act): blink for TX/RX act */ phy_write(phydev, MDIO_DEVAD_NONE, 24, val); break; } if (phydev->drv->config) phydev->drv->config(phydev); return 0; } #endif // IS_ENABLED(CONFIG_FEC_MXC) int board_init(void) { gsc_init(1); if (IS_ENABLED(CONFIG_FEC_MXC)) setup_fec(); gsc_hwmon(); return 0; } int board_late_init(void) { const char *ethmac; char env[32]; int ret, i; u8 enetaddr[6]; led_default_state(); /* Set mac addrs */ i = 0; do { if (i) sprintf(env, "eth%daddr", i); else sprintf(env, "ethaddr"); ethmac = env_get(env); if (!ethmac) { ret = gsc_getmac(i, enetaddr); if (!ret) eth_env_set_enetaddr(env, enetaddr); } i++; } while (!ret); return 0; } int board_mmc_get_env_dev(int devno) { return devno; }