From 5dea3a745b88041d677fc03d34df04dd2836265c Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Fri, 16 Jan 2015 12:46:51 +0800 Subject: bfin: enlarge the monitor size for ip04 board to avoid oversize link error Signed-off-by: Sonic Zhang --- include/configs/ip04.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ip04.h b/include/configs/ip04.h index ec510bdac4..2ee215f706 100644 --- a/include/configs/ip04.h +++ b/include/configs/ip04.h @@ -61,7 +61,7 @@ #define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2 #define CONFIG_EBIU_AMBCTL1_VAL 0xffc2ffc2 -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) #define CONFIG_SYS_MALLOC_LEN (128 * 1024) -- cgit From 0d3fd562c4977af4e992f3f73a441081ff8c60d0 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Fri, 16 Jan 2015 12:52:59 +0800 Subject: bfin: make env offset sector aligned for bct-brettl2 and ibf-dsp561 boards Signed-off-by: Sonic Zhang --- include/configs/bct-brettl2.h | 2 +- include/configs/ibf-dsp561.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h index 39982ef72c..2e0e9224cf 100644 --- a/include/configs/bct-brettl2.h +++ b/include/configs/bct-brettl2.h @@ -97,7 +97,7 @@ #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_OFFSET 0x4000 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_SECT_SIZE 0x12000 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) #define ENV_IS_EMBEDDED diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h index ac5ca9af37..2a937c6a22 100644 --- a/include/configs/ibf-dsp561.h +++ b/include/configs/ibf-dsp561.h @@ -82,7 +82,7 @@ #define CONFIG_ENV_OFFSET 0x4000 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ +#define CONFIG_ENV_SECT_SIZE 0x12000 /* Total Size of Environment Sector */ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) #define ENV_IS_EMBEDDED #else -- cgit From 3ca49c425f523d41bcec8a0eac24cce2d6a0da98 Mon Sep 17 00:00:00 2001 From: Po Liu Date: Wed, 26 Nov 2014 09:38:48 +0800 Subject: powerpc/c29xpcie: Add secure boot support Add NOR and SPI flash secure boot target for C29XPCIE board. Signed-off-by: Po Liu Signed-off-by: Mingkai.Hu Reviewed-by: York Sun --- include/configs/C29XPCIE.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index ecb3d7b25f..e24b923368 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -581,4 +581,6 @@ #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND +#include + #endif /* __CONFIG_H */ -- cgit From 37811ec2265bc56965ca0c1d9eb2ffa81aa8d9e9 Mon Sep 17 00:00:00 2001 From: harninder rai Date: Mon, 15 Dec 2014 12:58:45 +0530 Subject: powerpc/913x: Add config flag for bootdelay CONFIG_BOOTDELAY is missing from board header file. Add this macro to enable counting down of auto boot. Signed-off-by: Harninder Rai [York Sun: Add commit message] Reviewed-by: York Sun --- include/configs/BSC9131RDB.h | 1 + include/configs/BSC9132QDS.h | 1 + 2 files changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index eeb0671ddb..6aaaaa43f0 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -433,6 +433,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ #define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 10 /* -1 disable auto-boot */ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index e8a8d299cd..59a8d1b5d1 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -675,6 +675,7 @@ combinations. this should be removed later #define CONFIG_UBOOTPATH "u-boot.bin" #define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 10 /* -1 disable auto-boot */ #ifdef CONFIG_SDCARD #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" -- cgit From f49b8c1b5d9db6d349000b25312c672a1f6627b8 Mon Sep 17 00:00:00 2001 From: tang yuantian Date: Wed, 17 Dec 2014 15:42:54 +0800 Subject: mpc85xx/t102xrdb: convert deep sleep to generic board interface A new deep sleep interface is introduced to support generic board structure. Converts it to use new interface. Besides, added SPI/SD/NAND boot deep sleep support. Signed-off-by: Tang Yuantian Reviewed-by: York Sun --- include/configs/T102xRDB.h | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 82b669ba6e..e6222f3e17 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -36,7 +36,10 @@ /* support deep sleep */ #define CONFIG_DEEP_SLEEP +#if defined(CONFIG_DEEP_SLEEP) #define CONFIG_SILENT_CONSOLE +#define CONFIG_BOARD_EARLY_INIT_F +#endif #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg @@ -51,7 +54,7 @@ #define CONFIG_SPL_I2C_SUPPORT #define CONFIG_SPL_DRIVERS_MISC_SUPPORT #define CONFIG_FSL_LAW /* Use common FSL init code */ -#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SYS_TEXT_BASE 0x30001000 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 #define CONFIG_SPL_PAD_TO 0x40000 #define CONFIG_SPL_MAX_SIZE 0x28000 @@ -67,21 +70,21 @@ #ifdef CONFIG_NAND #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" #define CONFIG_SPL_NAND_BOOT #endif #ifdef CONFIG_SPIFLASH -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_FLASH_MINIMAL #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" #ifndef CONFIG_SPL_BUILD @@ -91,12 +94,12 @@ #endif #ifdef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_MMC_MINIMAL #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" #ifndef CONFIG_SPL_BUILD -- cgit From e26416a3f1631b906776a4e965313b3269faf259 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Wed, 17 Dec 2014 16:51:08 +0800 Subject: powerpc/t1024rdb: Add support for T1024RDB-PB T1024RDB-PB board adds 2.5G SGMII support with AQR105 PHY. rcw_0x095 is used for 10G XFI + 3x PCIex1 rcw_0x135 is used for 2.5G SGMII + 2x PCIex1 Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- include/configs/T102xRDB.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index e6222f3e17..bd40d6ac93 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -762,8 +762,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_FMAN_ENET #define CONFIG_PHYLIB_10G #define CONFIG_PHY_REALTEK +#define CONFIG_PHY_AQUANTIA #define RGMII_PHY1_ADDR 0x2 #define RGMII_PHY2_ADDR 0x6 +#define SGMII_PHY1_ADDR 0x2 #define FM1_10GEC1_PHY_ADDR 0x1 #endif -- cgit From 2c537642e98969e1810c6fdeff3099584f674a66 Mon Sep 17 00:00:00 2001 From: tang yuantian Date: Thu, 18 Dec 2014 09:55:07 +0800 Subject: mpc85xx/t102xqds: convert deep sleep to generic board interface A new deep sleep interface is introduced to support generic board structure. Converts it to use new interface. Signed-off-by: Tang Yuantian Reviewed-by: York Sun --- include/configs/T102xQDS.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index c2bdbb99ed..3f02cede32 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -35,7 +35,10 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_DEEP_SLEEP +#if defined(CONFIG_DEEP_SLEEP) #define CONFIG_SILENT_CONSOLE +#define CONFIG_BOARD_EARLY_INIT_F +#endif #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg -- cgit From 7d0e97a2945c9da47ad4655f2e3de7e36b5cd7ac Mon Sep 17 00:00:00 2001 From: tang yuantian Date: Thu, 18 Dec 2014 10:20:07 +0800 Subject: mpc85xx/t1040qds: convert deep sleep to generic board interface A new deep sleep interface is introduced to support generic board structure. Converts it to use new interface. Signed-off-by: Tang Yuantian Reviewed-by: York Sun --- include/configs/T1040QDS.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index b70bdfe5e7..5ebc8709aa 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -47,7 +47,10 @@ /* support deep sleep */ #define CONFIG_DEEP_SLEEP +#if defined(CONFIG_DEEP_SLEEP) #define CONFIG_SILENT_CONSOLE +#define CONFIG_BOARD_EARLY_INIT_F +#endif #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xeff40000 -- cgit From f7c38cf827a0cf9d5ab4ca60131dffa10a2e4309 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Tue, 30 Dec 2014 18:32:04 +0800 Subject: phylib: add support for aquantia PHYs This patch supports AQ1202, AQ2104, AQR105 PHY. Signed-off-by: Shaohui Xie Acked-by: Joe Hershberger Reviewed-by: York Sun --- include/phy.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/phy.h b/include/phy.h index 1e282e2964..d117fc1634 100644 --- a/include/phy.h +++ b/include/phy.h @@ -225,6 +225,7 @@ int gen10g_startup(struct phy_device *phydev); int gen10g_shutdown(struct phy_device *phydev); int gen10g_discover_mmds(struct phy_device *phydev); +int phy_aquantia_init(void); int phy_atheros_init(void); int phy_broadcom_init(void); int phy_cortina_init(void); -- cgit From 6706b115a632ac46ff13fd457c7b8a507b922d50 Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Mon, 12 Jan 2015 14:08:33 +0200 Subject: net/vsc9953: Add driver for Vitesse VSC9953 L2 Switch IP This patch adds a driver for VSC9953 L2 Switch. This Vitesse IP is integrated in Freescale T1040 and T1020 SoCs. The L2 switch has 10 Ethernet ports: 2 internal fixed-links (ports 8 and 9) at 2.5 Gbps and and 8 external ports at 1 Gbps. The external ports may be connected to PHYs over QSGMII and SGMII. Commands have also been added to enable/disable a port and to check a port's link speed, duplexity and status. The commands are: ethsw port enable|disable - enable/disable an l2 switch port ethsw port show - show an l2 switch port's configuration port_nr=0..9; use "all" for all ports For more detailse please see doc/README.t1040-l2switch Signed-off-by: Codrin Ciubotariu Acked-by: Joe Hershberger Reviewed-by: York Sun --- include/vsc9953.h | 402 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 402 insertions(+) create mode 100644 include/vsc9953.h (limited to 'include') diff --git a/include/vsc9953.h b/include/vsc9953.h new file mode 100644 index 0000000000..3d11b87a1f --- /dev/null +++ b/include/vsc9953.h @@ -0,0 +1,402 @@ +/* + * vsc9953.h + * + * Driver for the Vitesse VSC9953 L2 Switch + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * Copyright 2013 Freescale Semiconductor, Inc. + * + */ + +#ifndef _VSC9953_H_ +#define _VSC9953_H_ + +#include +#include +#include +#include + +#define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000) + +#define VSC9953_SYS_OFFSET 0x010000 +#define VSC9953_DEV_GMII_OFFSET 0x100000 +#define VSC9953_QSYS_OFFSET 0x200000 +#define VSC9953_ANA_OFFSET 0x280000 +#define VSC9953_DEVCPU_GCB 0x070000 +#define VSC9953_ES0 0x040000 +#define VSC9953_IS1 0x050000 +#define VSC9953_IS2 0x060000 + +#define T1040_SWITCH_GMII_DEV_OFFSET 0x010000 +#define VSC9953_PHY_REGS_OFFST 0x0000AC + +#define CONFIG_VSC9953_SOFT_SWC_RST_ENA 0x00000001 +#define CONFIG_VSC9953_CORE_ENABLE 0x80 +#define CONFIG_VSC9953_MEM_ENABLE 0x40 +#define CONFIG_VSC9953_MEM_INIT 0x20 + +#define CONFIG_VSC9953_PORT_ENA 0x00003a00 +#define CONFIG_VSC9953_MAC_ENA_CFG 0x00000011 +#define CONFIG_VSC9953_MAC_MODE_CFG 0x00000011 +#define CONFIG_VSC9953_MAC_IFG_CFG 0x00000515 +#define CONFIG_VSC9953_MAC_HDX_CFG 0x00001043 +#define CONFIG_VSC9953_CLOCK_CFG 0x00000001 +#define CONFIG_VSC9953_CLOCK_CFG_1000M 0x00000001 +#define CONFIG_VSC9953_PFC_FC 0x00000001 +#define CONFIG_VSC9953_PFC_FC_QSGMII 0x00000000 +#define CONFIG_VSC9953_MAC_FC_CFG 0x04700000 +#define CONFIG_VSC9953_MAC_FC_CFG_QSGMII 0x00700000 +#define CONFIG_VSC9953_PAUSE_CFG 0x001ffffe +#define CONFIG_VSC9953_TOT_TAIL_DROP_LVL 0x000003ff +#define CONFIG_VSC9953_FRONT_PORT_MODE 0x00000000 +#define CONFIG_VSC9953_MAC_MAX_LEN 0x000005ee + +#define CONFIG_VSC9953_VCAP_MV_CFG 0x0000ffff +#define CONFIG_VSC9953_VCAP_UPDATE_CTRL 0x01000004 +#define VSC9953_MAX_PORTS 10 +#define VSC9953_PORT_CHECK(port) \ + (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1) +#define VSC9953_INTERNAL_PORT_CHECK(port) ( \ + ( \ + (port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \ + ) ? 0 : 1 \ +) + +#define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0" + +#define MIIMIND_OPR_PEND 0x00000004 + +struct vsc9953_mdio_info { + struct vsc9953_mii_mng *regs; + char *name; +}; + +/* VSC9953 ANA structure for T1040 U-boot*/ + +struct vsc9953_ana_port { + u32 vlan_cfg; + u32 drop_cfg; + u32 qos_cfg; + u32 vcap_cfg; + u32 vcap_s1_key_cfg[3]; + u32 vcap_s2_cfg; + u32 qos_pcp_dei_map_cfg[16]; + u32 cpu_fwd_cfg; + u32 cpu_fwd_bpdu_cfg; + u32 cpu_fwd_garp_cfg; + u32 cpu_fwd_ccm_cfg; + u32 port_cfg; + u32 pol_cfg; + u32 reserved[34]; +}; + +struct vsc9953_ana_pol { + u32 pol_pir_cfg; + u32 pol_cir_cfg; + u32 pol_mode_cfg; + u32 pol_pir_state; + u32 pol_cir_state; + u32 reserved1[3]; +}; + +struct vsc9953_ana_ana_tables { + u32 entry_lim[11]; + u32 an_moved; + u32 mach_data; + u32 macl_data; + u32 mac_access; + u32 mact_indx; + u32 vlan_access; + u32 vlan_tidx; +}; + +struct vsc9953_ana_ana { + u32 adv_learn; + u32 vlan_mask; + u32 anag_efil; + u32 an_events; + u32 storm_limit_burst; + u32 storm_limit_cfg[4]; + u32 isolated_prts; + u32 community_ports; + u32 auto_age; + u32 mac_options; + u32 learn_disc; + u32 agen_ctrl; + u32 mirror_ports; + u32 emirror_ports; + u32 flooding; + u32 flooding_ipmc; + u32 sflow_cfg[11]; + u32 port_mode[12]; +}; + +struct vsc9953_ana_pgid { + u32 port_grp_id[91]; +}; + +struct vsc9953_ana_pfc { + u32 pfc_cfg; + u32 reserved1[15]; +}; + +struct vsc9953_ana_pol_misc { + u32 pol_flowc[10]; + u32 reserved1[17]; + u32 pol_hyst; +}; + +struct vsc9953_ana_common { + u32 aggr_cfg; + u32 cpuq_cfg; + u32 cpuq_8021_cfg; + u32 dscp_cfg; + u32 dscp_rewr_cfg; + u32 vcap_rng_type_cfg; + u32 vcap_rng_val_cfg; + u32 discard_cfg; + u32 fid_cfg; +}; + +struct vsc9953_analyzer { + struct vsc9953_ana_port port[11]; + u32 reserved1[9536]; + struct vsc9953_ana_pol pol[164]; + struct vsc9953_ana_ana_tables ana_tables; + u32 reserved2[14]; + struct vsc9953_ana_ana ana; + u32 reserved3[22]; + struct vsc9953_ana_pgid port_id_tbl; + u32 reserved4[549]; + struct vsc9953_ana_pfc pfc[10]; + struct vsc9953_ana_pol_misc pol_misc; + u32 reserved5[196]; + struct vsc9953_ana_common common; +}; +/* END VSC9953 ANA structure for T1040 U-boot*/ + +/* VSC9953 DEV_GMII structure for T1040 U-boot*/ + +struct vsc9953_dev_gmii_port_mode { + u32 clock_cfg; + u32 port_misc; + u32 reserved1; + u32 eee_cfg; +}; + +struct vsc9953_dev_gmii_mac_cfg_status { + u32 mac_ena_cfg; + u32 mac_mode_cfg; + u32 mac_maxlen_cfg; + u32 mac_tags_cfg; + u32 mac_adv_chk_cfg; + u32 mac_ifg_cfg; + u32 mac_hdx_cfg; + u32 mac_fc_mac_low_cfg; + u32 mac_fc_mac_high_cfg; + u32 mac_sticky; +}; + +struct vsc9953_dev_gmii { + struct vsc9953_dev_gmii_port_mode port_mode; + struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status; +}; + +/* END VSC9953 DEV_GMII structure for T1040 U-boot*/ + +/* VSC9953 QSYS structure for T1040 U-boot*/ + +struct vsc9953_qsys_hsch { + u32 cir_cfg; + u32 reserved1; + u32 se_cfg; + u32 se_dwrr_cfg[8]; + u32 cir_state; + u32 reserved2[20]; +}; + +struct vsc9953_qsys_sys { + u32 port_mode[12]; + u32 switch_port_mode[11]; + u32 stat_cnt_cfg; + u32 eee_cfg[10]; + u32 eee_thrs; + u32 igr_no_sharing; + u32 egr_no_sharing; + u32 sw_status[11]; + u32 ext_cpu_cfg; + u32 cpu_group_map; + u32 reserved1[23]; +}; + +struct vsc9953_qsys_qos_cfg { + u32 red_profile[16]; + u32 res_qos_mode; +}; + +struct vsc9953_qsys_drop_cfg { + u32 egr_drop_mode; +}; + +struct vsc9953_qsys_mmgt { + u32 eq_cntrl; + u32 reserved1; +}; + +struct vsc9953_qsys_hsch_misc { + u32 hsch_misc_cfg; + u32 reserved1[546]; +}; + +struct vsc9953_qsys_res_ctrl { + u32 res_cfg; + u32 res_stat; + +}; + +struct vsc9953_qsys_reg { + struct vsc9953_qsys_hsch hsch[108]; + struct vsc9953_qsys_sys sys; + struct vsc9953_qsys_qos_cfg qos_cfg; + struct vsc9953_qsys_drop_cfg drop_cfg; + struct vsc9953_qsys_mmgt mmgt; + struct vsc9953_qsys_hsch_misc hsch_misc; + struct vsc9953_qsys_res_ctrl res_ctrl[1024]; +}; + +/* END VSC9953 QSYS structure for T1040 U-boot*/ + +/* VSC9953 SYS structure for T1040 U-boot*/ + +struct vsc9953_sys_stat { + u32 rx_cntrs[64]; + u32 tx_cntrs[64]; + u32 drop_cntrs[64]; + u32 reserved1[6]; +}; + +struct vsc9953_sys_sys { + u32 reset_cfg; + u32 reserved1; + u32 vlan_etype_cfg; + u32 port_mode[12]; + u32 front_port_mode[10]; + u32 frame_aging; + u32 stat_cfg; + u32 reserved2[50]; +}; + +struct vsc9953_sys_pause_cfg { + u32 pause_cfg[11]; + u32 pause_tot_cfg; + u32 tail_drop_level[11]; + u32 tot_tail_drop_lvl; + u32 mac_fc_cfg[10]; +}; + +struct vsc9953_sys_mmgt { + u16 free_cnt; +}; + +struct vsc9953_system_reg { + struct vsc9953_sys_stat stat; + struct vsc9953_sys_sys sys; + struct vsc9953_sys_pause_cfg pause_cfg; + struct vsc9953_sys_mmgt mmgt; +}; + +/* END VSC9953 SYS structure for T1040 U-boot*/ + + +/* VSC9953 DEVCPU_GCB structure for T1040 U-boot*/ + +struct vsc9953_chip_regs { + u32 chipd_id; + u32 gpr; + u32 soft_rst; +}; + +struct vsc9953_gpio { + u32 gpio_out_set[10]; + u32 gpio_out_clr[10]; + u32 gpio_out[10]; + u32 gpio_in[10]; +}; + +struct vsc9953_mii_mng { + u32 miimstatus; + u32 reserved1; + u32 miimcmd; + u32 miimdata; + u32 miimcfg; + u32 miimscan_0; + u32 miimscan_1; + u32 miiscan_lst_rslts; + u32 miiscan_lst_rslts_valid; +}; + +struct vsc9953_mii_read_scan { + u32 mii_scan_results_sticky[2]; +}; + +struct vsc9953_devcpu_gcb { + struct vsc9953_chip_regs chip_regs; + struct vsc9953_gpio gpio; + struct vsc9953_mii_mng mii_mng[2]; + struct vsc9953_mii_read_scan mii_read_scan; +}; + +/* END VSC9953 DEVCPU_GCB structure for T1040 U-boot*/ + +/* VSC9953 IS* structure for T1040 U-boot*/ + +struct vsc9953_vcap_core_cfg { + u32 vcap_update_ctrl; + u32 vcap_mv_cfg; +}; + +struct vsc9953_vcap { +struct vsc9953_vcap_core_cfg vcap_core_cfg; +}; + +/* END VSC9953 IS* structure for T1040 U-boot*/ + +#define VSC9953_PORT_INFO_INITIALIZER(idx) \ +{ \ + .enabled = 0, \ + .phyaddr = 0, \ + .index = idx, \ + .phy_regs = NULL, \ + .enet_if = PHY_INTERFACE_MODE_NONE, \ + .bus = NULL, \ + .phydev = NULL, \ +} + +/* Structure to describe a VSC9953 port */ +struct vsc9953_port_info { + u8 enabled; + u8 phyaddr; + int index; + void *phy_regs; + phy_interface_t enet_if; + struct mii_dev *bus; + struct phy_device *phydev; +}; + +/* Structure to describe a VSC9953 switch */ +struct vsc9953_info { + struct vsc9953_port_info port[VSC9953_MAX_PORTS]; +}; + +void vsc9953_init(bd_t *bis); + +void vsc9953_port_info_set_mdio(int port, struct mii_dev *bus); +void vsc9953_port_info_set_phy_address(int port, int address); +void vsc9953_port_enable(int port); +void vsc9953_port_disable(int port); +void vsc9953_port_info_set_phy_int(int port, phy_interface_t phy_int); + +#endif /* _VSC9953_H_ */ -- cgit From 2b7c0f30813d11adeb1ac27bef45688b3dfd9e86 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 23 Dec 2014 12:04:53 -0700 Subject: sunxi: Drop use of lowlevel_init() This does nothing now, so drop it. We have SPL anyway to do our low-level init. Signed-off-by: Simon Glass Acked-by: Ian Campbell --- include/configs/sunxi-common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index e839053e2b..647cac5a93 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -109,6 +109,7 @@ #define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SKIP_LOWLEVEL_INIT /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -- cgit From a1d31077d06d47233d2bd7002cf65d5ee9b5e501 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Tue, 6 Jan 2015 14:27:42 +0100 Subject: config_distro_bootcmd.h: Remove unnecessary magic to avoid repeated USB scans Now that "usb start" will only start usb if not already started, we can simply call "usb start" whenever we (may) need access to usb devices, and it will only actually scan the bus at the first call. Signed-off-by: Hans de Goede --- include/config_distro_bootcmd.h | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index be616e8bfd..becbe3fa7c 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -90,15 +90,8 @@ #endif #ifdef CONFIG_CMD_USB -#define BOOTENV_RUN_USB_INIT "run usb_init; " -#define BOOTENV_SET_USB_NEED_INIT "setenv usb_need_init; " +#define BOOTENV_RUN_USB_INIT "usb start; " #define BOOTENV_SHARED_USB \ - "usb_init=" \ - "if ${usb_need_init}; then " \ - "setenv usb_need_init false; " \ - "usb start 0; " \ - "fi\0" \ - \ "usb_boot=" \ BOOTENV_RUN_USB_INIT \ BOOTENV_SHARED_BLKDEV_BODY(usb) @@ -106,7 +99,6 @@ #define BOOTENV_DEV_NAME_USB BOOTENV_DEV_NAME_BLKDEV #else #define BOOTENV_RUN_USB_INIT -#define BOOTENV_SET_USB_NEED_INIT #define BOOTENV_SHARED_USB #define BOOTENV_DEV_USB \ BOOT_TARGET_DEVICES_references_USB_without_CONFIG_CMD_USB @@ -202,7 +194,7 @@ \ BOOT_TARGET_DEVICES(BOOTENV_DEV) \ \ - "bootcmd=" BOOTENV_SET_USB_NEED_INIT BOOTENV_SET_SCSI_NEED_INIT \ + "bootcmd=" BOOTENV_SET_SCSI_NEED_INIT \ "for target in ${boot_targets}; do " \ "run bootcmd_${target}; " \ "done\0" -- cgit From 8bb6c1d1e0ac3692df1b83eaeee42541c09e09fc Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 11 Jan 2015 20:38:28 +0100 Subject: usb: Add an interval parameter to create_int_queue Currently create_int_queue is only implemented by the ehci code, and that does not honor interrupt intervals, but other drivers which might also want to implement create_int_queue may honor intervals, so add an interval param. Signed-off-by: Hans de Goede --- include/usb.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/usb.h b/include/usb.h index d3c741597c..3d33b2d46a 100644 --- a/include/usb.h +++ b/include/usb.h @@ -169,7 +169,7 @@ int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, #ifdef CONFIG_USB_EHCI /* Only the ehci code has pollable int support */ struct int_queue *create_int_queue(struct usb_device *dev, unsigned long pipe, - int queuesize, int elementsize, void *buffer); + int queuesize, int elementsize, void *buffer, int interval); int destroy_int_queue(struct usb_device *dev, struct int_queue *queue); void *poll_int_queue(struct usb_device *dev, struct int_queue *queue); #endif -- cgit From 28a15ef7fd7d97f0634440866c6b7baa7708b5eb Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 11 Jan 2015 20:34:48 +0100 Subject: musb-new: Add sunxi musb controller support This is based on Jussi Kivilinna's work for the linux-sunxi-3.4 kernel to use the kernels musb driver instead of Allwinners own custom driver. Signed-off-by: Hans de Goede --- include/usb.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/usb.h b/include/usb.h index 3d33b2d46a..b921a7f856 100644 --- a/include/usb.h +++ b/include/usb.h @@ -154,8 +154,8 @@ enum usb_init_type { defined(CONFIG_USB_OMAP3) || defined(CONFIG_USB_DA8XX) || \ defined(CONFIG_USB_BLACKFIN) || defined(CONFIG_USB_AM35X) || \ defined(CONFIG_USB_MUSB_DSPS) || defined(CONFIG_USB_MUSB_AM35X) || \ - defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined(CONFIG_USB_XHCI) || \ - defined(CONFIG_USB_DWC2) + defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined(CONFIG_USB_MUSB_SUNXI) || \ + defined(CONFIG_USB_XHCI) || defined(CONFIG_USB_DWC2) int usb_lowlevel_init(int index, enum usb_init_type init, void **controller); int usb_lowlevel_stop(int index); -- cgit From 90cdc1039d0bf6d85bb497dbb93d317ad234e846 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 11 Jan 2015 20:34:51 +0100 Subject: musb-new: Fix reset sequence when in host mode This commit fixes a number of issues with the reset sequence of musb-new in host mode: 1) Our usb device probe relies on a second device reset being done after the first descriptors read. Factor the musb reset code into a usb_reset_root_port function (and add this as an empty define for other controllers), and call this when a device has no parent. 2) Just like with normal usb controllers there needs to be a delay after reset, for normal usb controllers, this is handled in hub_port_reset, add a delay to usb_reset_root_port. 3) Sync the musb reset sequence with the upstream kernel, clear all bits of power except bits 4-7, and increase the time reset is asserted to 50 ms. With these fixes an usb keyboard I have now always enumerates properly, where as earlier it would only enumerare properly once every 5 tries. Signed-off-by: Hans de Goede --- include/usb.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/usb.h b/include/usb.h index b921a7f856..a083591ba0 100644 --- a/include/usb.h +++ b/include/usb.h @@ -159,6 +159,11 @@ enum usb_init_type { int usb_lowlevel_init(int index, enum usb_init_type init, void **controller); int usb_lowlevel_stop(int index); +#ifdef CONFIG_MUSB_HOST +void usb_reset_root_port(void); +#else +#define usb_reset_root_port() +#endif int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len); -- cgit From 904f2a83a8c620ceb3974cc6b1529b966d7899b1 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 11 Jan 2015 20:34:54 +0100 Subject: musb-new: Add interrupt queue support Add interrupt queue support, so that a usb keyboard can be used without causing huge latencies. Signed-off-by: Hans de Goede --- include/usb.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/usb.h b/include/usb.h index a083591ba0..a8fee0bdb7 100644 --- a/include/usb.h +++ b/include/usb.h @@ -120,6 +120,7 @@ struct usb_device { * Each instance needs its own set of data structures. */ unsigned long status; + unsigned long int_pending; /* 1 bit per ep, used by int_queue */ int act_len; /* transfered bytes */ int maxchild; /* Number of ports if hub */ int portnr; @@ -172,7 +173,7 @@ int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len, int interval); -#ifdef CONFIG_USB_EHCI /* Only the ehci code has pollable int support */ +#if defined CONFIG_USB_EHCI || defined CONFIG_MUSB_HOST struct int_queue *create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize, int elementsize, void *buffer, int interval); int destroy_int_queue(struct usb_device *dev, struct int_queue *queue); -- cgit From 389aee89308daf67c540e80aafd1d2f1a694f0e8 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 18 Nov 2014 09:41:57 +0100 Subject: arm, at91: enable thumb mode for taurus board in SPL Signed-off-by: Heiko Schocher --- include/configs/taurus.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 20194aebb5..06725cddc9 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -26,6 +26,11 @@ #define CONFIG_SYS_GENERIC_BOARD +#if defined(CONFIG_SPL_BUILD) +#define CONFIG_SYS_THUMB_BUILD +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF +#endif /* * Warning: changing CONFIG_SYS_TEXT_BASE requires * adapting the initial boot program. -- cgit From a1655bb2e1e2bf8f30f40b46d1bb7a45810634be Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 18 Nov 2014 09:41:58 +0100 Subject: taurus, spl: erase also spi flash if recovery button is pressed if in SPL mode recovery button is pressed, erase also spi flash from offset 0 to CONFIG_SYS_NAND_U_BOOT_SIZE on the taurus board. Signed-off-by: Heiko Schocher --- include/configs/taurus.h | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 06725cddc9..65468ad165 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -142,6 +142,19 @@ #define TAURUS_SPI_MASK (1 << 4) #define TAURUS_SPI_CS_PIN AT91_PIN_PA3 +#if defined(CONFIG_SPL_BUILD) +/* SPL related */ +#undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */ +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 + +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif + /* load address */ #define CONFIG_SYS_LOAD_ADDR 0x22000000 @@ -176,8 +189,11 @@ /* Defines for SPL */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x0 -#define CONFIG_SPL_MAX_SIZE (11 * 1024) +#define CONFIG_SPL_MAX_SIZE (14 * 1024) #define CONFIG_SPL_STACK (16 * 1024) +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ + CONFIG_SYS_MALLOC_LEN) +#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN #define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE #define CONFIG_SPL_BSS_MAX_SIZE (3 * 1024) -- cgit From a5f8ccaeab6db682ad5ba47255287604d781d552 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 18 Nov 2014 11:53:53 +0100 Subject: arm, at91: corvus board updates - corvus board fix problems with toshiba nand chips on the corvus board problems with toshiba chips Manufacturer ID: 0x98 Chip ID: 0xdc encounterd. Solve this in the following way: - set other nand timings - enable CONFIG_SYS_NAND_READY_PIN - correct the MACH_TYPE setting Signed-off-by: Heiko Schocher --- include/configs/corvus.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 5b50c1d6dd..ace511f765 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -18,6 +18,7 @@ #define MACH_TYPE_CORVUS 2066 +#define CONFIG_MACH_TYPE MACH_TYPE_CORVUS #define CONFIG_SYS_GENERIC_BOARD /* * Warning: changing CONFIG_SYS_TEXT_BASE requires @@ -106,6 +107,7 @@ /* our CLE is AD22 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 #endif /* Ethernet */ @@ -171,7 +173,6 @@ #define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_GPIO_SUPPORT -#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14) #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_BASE @@ -184,7 +185,6 @@ #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_SIZE (256*1024*1024) #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ -- cgit From 05a4d544299b9a34fb96a0178457bf6d9e1fc33c Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Wed, 19 Nov 2014 19:03:00 +0800 Subject: ARM: at91: sama5d3_xplained: spl: enable PMECC header generation As sama5d3 xplained support the PMECC. So add the PMECC header for spl binary. That make ROM loader can use PMECC to avoid error flips in spl code in nandflash. Signed-off-by: Josh Wu Acked-by: Bo Shen --- include/configs/sama5d3_xplained.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index d5588b1241..9458047c06 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -246,6 +246,7 @@ #define CONFIG_SYS_NAND_OOBSIZE 64 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 +#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER #endif -- cgit From d4798a2b52629a63a476f1378d59ae0e8719c23c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 26 Nov 2014 12:30:17 -0700 Subject: arm: at91: snapper9260: Drop invalid CONFIG_SKIP_RELOCATE_UBOOT This config is not valid, so drop it. Signed-off-by: Simon Glass --- include/configs/snapper9260.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h index 942af2e7f6..9fa644f7c2 100644 --- a/include/configs/snapper9260.h +++ b/include/configs/snapper9260.h @@ -34,7 +34,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SKIP_RELOCATE_UBOOT #define CONFIG_DISPLAY_CPUINFO #define CONFIG_FIT -- cgit From cd5ca303c4861932ed2540cc21b0aec55ca56a6d Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Wed, 3 Dec 2014 18:02:21 +0800 Subject: ARM: atmel: sama5d4ek: enable usb ethernet gadget Signed-off-by: Bo Shen --- include/configs/sama5d4ek.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include') diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index cbdb3a2943..09ab4d7f25 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -121,6 +121,14 @@ #define CONFIG_USB_STORAGE #endif +/* USB device */ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_ATMEL_USBA +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_RNDIS +#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D4EK" + #if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION -- cgit From 52305a829cd927aca2eb4a15985c567e98f562b9 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Wed, 3 Dec 2014 18:02:23 +0800 Subject: ARM: atmel: sama5d4_xplained: enable usb ethernet gadget Signed-off-by: Bo Shen --- include/configs/sama5d4_xplained.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include') diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index 104edef102..996973d99b 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -121,6 +121,14 @@ #define CONFIG_USB_STORAGE #endif +/* USB device */ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_ATMEL_USBA +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_RNDIS +#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D4EK" + #if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION -- cgit From c3dbb4f9b7539e39d418fd1f518129fd60c8eca9 Mon Sep 17 00:00:00 2001 From: Diego Santa Cruz Date: Tue, 23 Dec 2014 10:50:17 +0100 Subject: mmc: extend mmcinfo to show enhanced partition attribute This extends the mmcinfo command's output to show which eMMC partitions have the enhanced attribute set. Note that the eMMC spec says that if the enhanced attribute is supported then the boot and RPMB partitions are of the enhanced type. The output of mmcinfo becomes: Device: OMAP SD/MMC Manufacturer ID: fe OEM: 14e Name: MMC16 Tran Speed: 52000000 Rd Block Len: 512 MMC version 4.41 High Capacity: Yes Capacity: 13.8 GiB Bus Width: 4-bit User Capacity: 13.8 GiB ENH Boot Capacity: 16 MiB ENH RPMB Capacity: 128 KiB ENH GP1 Capacity: 64 MiB ENH GP2 Capacity: 64 MiB ENH Signed-off-by: Diego Santa Cruz --- include/mmc.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/mmc.h b/include/mmc.h index 7ec255d882..69c60706df 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -201,6 +201,9 @@ #define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0) +#define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */ +#define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */ + #define R1_ILLEGAL_COMMAND (1 << 22) #define R1_APP_CMD (1 << 5) @@ -224,6 +227,7 @@ #define MMCPART_NOAVAILABLE (0xff) #define PART_ACCESS_MASK (0x7) #define PART_SUPPORT (0x1) +#define ENHNCD_SUPPORT (0x2) #define PART_ENH_ATTRIB (0x1f) /* Maximum block size for MMC */ @@ -302,6 +306,8 @@ struct mmc { uint csd[4]; uint cid[4]; ushort rca; + u8 part_support; + u8 part_attr; char part_config; char part_num; uint tran_speed; -- cgit From a7f852b6885dc7b89741b1e76921e160b9c9877b Mon Sep 17 00:00:00 2001 From: Diego Santa Cruz Date: Tue, 23 Dec 2014 10:50:22 +0100 Subject: mmc: read the size of eMMC enhanced user data area This modification reads the size of the eMMC enhanced user data area upon initialization of an mmc device, it will be used later by mmcinfo. Signed-off-by: Diego Santa Cruz --- include/mmc.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/mmc.h b/include/mmc.h index 69c60706df..18155c9d6c 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -147,6 +147,8 @@ /* * EXT_CSD fields */ +#define EXT_CSD_ENH_START_ADDR 136 /* R/W */ +#define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */ #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ #define EXT_CSD_PARTITION_SETTING 155 /* R/W */ #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */ @@ -319,6 +321,8 @@ struct mmc { u64 capacity_boot; u64 capacity_rpmb; u64 capacity_gp[4]; + u64 enh_user_start; + u64 enh_user_size; block_dev_desc_t block_dev; char op_cond_pending; /* 1 if we are waiting on an op_cond command */ char init_in_progress; /* 1 if we have done mmc_start_init() */ -- cgit From a4ff9f83f5f902717e87c05cf9d2d02b472d4257 Mon Sep 17 00:00:00 2001 From: Diego Santa Cruz Date: Tue, 23 Dec 2014 10:50:24 +0100 Subject: mmc: fix erase_grp_size computation with high-capacity size definition The erase_grp_size in struct mmc is to be a size in 512-byte sectors but the code used to compute it for eMMC when EXT_CSD_ERASE_GROUP_DEF is enabled computed it as bytes, leading to erase sizes and alignment much larger than what is actually required by the mmc device. Signed-off-by: Diego Santa Cruz --- include/mmc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/mmc.h b/include/mmc.h index 18155c9d6c..6c8bbfc952 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -315,7 +315,7 @@ struct mmc { uint tran_speed; uint read_bl_len; uint write_bl_len; - uint erase_grp_size; + uint erase_grp_size; /* in 512-byte sectors */ u64 capacity; u64 capacity_user; u64 capacity_boot; -- cgit From 037dc0ab5dff36984d97735987dff01a7ec73893 Mon Sep 17 00:00:00 2001 From: Diego Santa Cruz Date: Tue, 23 Dec 2014 10:50:25 +0100 Subject: mmc: read the high capacity WP group size for eMMC Read the eMMC high capacity write protect group size at mmc device initialization. This is useful to correctly partition an eMMC device, as partitions need to be aligned to this size. Signed-off-by: Diego Santa Cruz --- include/mmc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/mmc.h b/include/mmc.h index 6c8bbfc952..bcaf9f012f 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -316,6 +316,7 @@ struct mmc { uint read_bl_len; uint write_bl_len; uint erase_grp_size; /* in 512-byte sectors */ + uint hc_wp_grp_size; /* in 512-byte sectors */ u64 capacity; u64 capacity_user; u64 capacity_boot; -- cgit From ac9da0e08c01e3addc55241ffc09db29aa800473 Mon Sep 17 00:00:00 2001 From: Diego Santa Cruz Date: Tue, 23 Dec 2014 10:50:29 +0100 Subject: mmc: add API to do eMMC hardware partitioning This adds an API to do hardware partitioning on eMMC devices. The new mmc_hwpart_config() function does the partitioning in one go. As the different attributes and partitioning options on eMMC may be interdependent validation has to be done based on the complete partitioning configuration. The function accepts three modes: - MMC_HWPART_CONF_CHECK: just validates that the configuration is valid. - MMC_HWPART_CONF_SET: validates and sets all the fields in EXT_CSD but without setting the "partitioning completed" bit, and thus is reversible. - MMC_HWPART_CONF_COMPLETE: does everything and is thus not reversible. Signed-off-by: Diego Santa Cruz --- include/mmc.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'include') diff --git a/include/mmc.h b/include/mmc.h index bcaf9f012f..aacf820191 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -152,6 +152,7 @@ #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ #define EXT_CSD_PARTITION_SETTING 155 /* R/W */ #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */ +#define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */ #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */ #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ #define EXT_CSD_RPMB_MULT 168 /* RO */ @@ -332,6 +333,23 @@ struct mmc { int ddr_mode; }; +struct mmc_hwpart_conf { + struct { + uint enh_start; /* in 512-byte sectors */ + uint enh_size; /* in 512-byte sectors, if 0 no enh area */ + } user; + struct { + uint size; /* in 512-byte sectors */ + int enhanced; + } gp_part[4]; +}; + +enum mmc_hwpart_conf_mode { + MMC_HWPART_CONF_CHECK, + MMC_HWPART_CONF_SET, + MMC_HWPART_CONF_COMPLETE, +}; + int mmc_register(struct mmc *mmc); struct mmc *mmc_create(const struct mmc_config *cfg, void *priv); void mmc_destroy(struct mmc *mmc); @@ -344,6 +362,8 @@ int mmc_set_dev(int dev_num); void print_mmc_devices(char separator); int get_mmc_num(void); int mmc_switch_part(int dev_num, unsigned int part_num); +int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf, + enum mmc_hwpart_conf_mode mode); int mmc_getcd(struct mmc *mmc); int board_mmc_getcd(struct mmc *mmc); int mmc_getwp(struct mmc *mmc); -- cgit From 8dda5b0e60b84f2679bd51ae4bcdbe527fa438d4 Mon Sep 17 00:00:00 2001 From: Diego Santa Cruz Date: Tue, 23 Dec 2014 10:50:31 +0100 Subject: mmc: extend the mmc hardware partitioning API with write reliability The eMMC partition write reliability settings are to be set while partitioning a device, as per the eMMC spec, so changes to these attributes needs to be done in the hardware partitioning API. This commit adds such support. Signed-off-by: Diego Santa Cruz --- include/mmc.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/mmc.h b/include/mmc.h index aacf820191..8d41234e20 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -155,6 +155,8 @@ #define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */ #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */ #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ +#define EXT_CSD_WR_REL_PARAM 166 /* R */ +#define EXT_CSD_WR_REL_SET 167 /* R/W */ #define EXT_CSD_RPMB_MULT 168 /* RO */ #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ #define EXT_CSD_BOOT_BUS_WIDTH 177 @@ -207,6 +209,11 @@ #define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */ #define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */ +#define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */ + +#define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */ +#define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */ + #define R1_ILLEGAL_COMMAND (1 << 22) #define R1_APP_CMD (1 << 5) @@ -337,10 +344,14 @@ struct mmc_hwpart_conf { struct { uint enh_start; /* in 512-byte sectors */ uint enh_size; /* in 512-byte sectors, if 0 no enh area */ + unsigned wr_rel_change : 1; + unsigned wr_rel_set : 1; } user; struct { uint size; /* in 512-byte sectors */ - int enhanced; + unsigned enhanced : 1; + unsigned wr_rel_change : 1; + unsigned wr_rel_set : 1; } gp_part[4]; }; -- cgit From 9e41a00b572f415bbcc3d8f6fb1c6c541293655b Mon Sep 17 00:00:00 2001 From: Diego Santa Cruz Date: Tue, 23 Dec 2014 10:50:33 +0100 Subject: mmc: extend mmcinfo output to show partition write reliability settings This extends the mmcinfo hardware partition info output to show partitions with write reliability enabled with the "WRREL" string. If the partition does not have write reliability enabled the "WRREL" string is omitted; this is analogous to the ehhanced attribute. Example output: Device: OMAP SD/MMC Manufacturer ID: fe OEM: 14e Name: MMC16 Tran Speed: 52000000 Rd Block Len: 512 MMC version 4.41 High Capacity: Yes Capacity: 13.8 GiB Bus Width: 4-bit Erase Group Size: 8 MiB HC WP Group Size: 16 MiB User Capacity: 13.8 GiB ENH WRREL User Enhanced Start: 0 Bytes User Enhanced Size: 512 MiB Boot Capacity: 16 MiB ENH RPMB Capacity: 128 KiB ENH GP1 Capacity: 64 MiB ENH WRREL GP2 Capacity: 64 MiB ENH WRREL Signed-off-by: Diego Santa Cruz --- include/mmc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/mmc.h b/include/mmc.h index 8d41234e20..09101e2c87 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -318,6 +318,7 @@ struct mmc { ushort rca; u8 part_support; u8 part_attr; + u8 wr_rel_set; char part_config; char part_num; uint tran_speed; -- cgit From 77d52ed278516c4418af08a0398dff4a97772648 Mon Sep 17 00:00:00 2001 From: Sinan Akman Date: Sat, 17 Jan 2015 02:09:13 -0500 Subject: Use generic board architecture for MPC837xERDB Signed-off-by: Sinan Akman Cc: kim.phillips@freescale.com --- include/configs/MPC837XERDB.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 8ed0f7c21a..19e0e30eef 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -15,6 +15,8 @@ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ #define CONFIG_MPC837XERDB 1 +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_TEXT_BASE 0xFE000000 -- cgit From 6583505c23207e25a1b736aeaf207122d468d671 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 14 Jan 2015 09:59:00 +0100 Subject: fpga: Remove extern prototypes from .h This problem is reported by checkpatch.pl Warnings: CHECK: extern prototypes should be avoided in .h files Signed-off-by: Michal Simek --- include/fpga.h | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/include/fpga.h b/include/fpga.h index 914024c17c..ef044e9362 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -49,18 +49,18 @@ typedef enum { } bitstream_type; /* root function definitions */ -extern void fpga_init(void); -extern int fpga_add(fpga_type devtype, void *desc); -extern int fpga_count(void); -extern int fpga_load(int devnum, const void *buf, size_t bsize, - bitstream_type bstype); -extern int fpga_fsload(int devnum, const void *buf, size_t size, - fpga_fs_info *fpga_fsinfo); -extern int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, - bitstream_type bstype); -extern int fpga_dump(int devnum, const void *buf, size_t bsize); -extern int fpga_info(int devnum); -extern const fpga_desc *const fpga_validate(int devnum, const void *buf, - size_t bsize, char *fn); +void fpga_init(void); +int fpga_add(fpga_type devtype, void *desc); +int fpga_count(void); +int fpga_load(int devnum, const void *buf, size_t bsize, + bitstream_type bstype); +int fpga_fsload(int devnum, const void *buf, size_t size, + fpga_fs_info *fpga_fsinfo); +int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, + bitstream_type bstype); +int fpga_dump(int devnum, const void *buf, size_t bsize); +int fpga_info(int devnum); +const fpga_desc *const fpga_validate(int devnum, const void *buf, + size_t bsize, char *fn); #endif /* _FPGA_H_ */ -- cgit From ebd322de43d7d43dd59955aa58952bafa95cfd4a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 13 Jan 2015 16:09:53 +0100 Subject: fpga: Export fpga_get_desc for SPL SPL needs to detect FPGA device which will be used for loading bitstream. Signed-off-by: Michal Simek --- include/fpga.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/fpga.h b/include/fpga.h index ef044e9362..e0d12981b2 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -52,6 +52,7 @@ typedef enum { void fpga_init(void); int fpga_add(fpga_type devtype, void *desc); int fpga_count(void); +const fpga_desc *const fpga_get_desc(int devnum); int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype); int fpga_fsload(int devnum, const void *buf, size_t size, -- cgit From 4e9acc16fc026ae0991b32e52c15c0e9a36a53a7 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 16 Jul 2014 10:43:47 +0200 Subject: fpga: xilinx: spartan2: Setup NULL fpga_op without driver Set fpga operations to NULL for cases where FPGA is setup in board file but driver is not added. Signed-off-by: Michal Simek --- include/spartan2.h | 38 +++++++++++++++++++++++++++----------- 1 file changed, 27 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/include/spartan2.h b/include/spartan2.h index 2aca954e73..14606c3031 100644 --- a/include/spartan2.h +++ b/include/spartan2.h @@ -38,7 +38,12 @@ typedef struct { xilinx_post_fn post; } xilinx_spartan2_slave_serial_fns; +#if defined(CONFIG_FPGA_SPARTAN2) extern struct xilinx_fpga_op spartan2_op; +# define FPGA_SPARTAN2_OPS &spartan2_op +#else +# define FPGA_SPARTAN2_OPS NULL +#endif /* Device Image Sizes *********************************************************************/ @@ -61,36 +66,47 @@ extern struct xilinx_fpga_op spartan2_op; *********************************************************************/ /* Spartan-II devices */ #define XILINX_XC2S15_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, &spartan2_op } +{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, \ + FPGA_SPARTAN2_OPS } #define XILINX_XC2S30_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, &spartan2_op } +{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, \ + FPGA_SPARTAN2_OPS } #define XILINX_XC2S50_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, &spartan2_op } +{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, \ + FPGA_SPARTAN2_OPS } #define XILINX_XC2S100_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, &spartan2_op } +{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, \ + FPGA_SPARTAN2_OPS } #define XILINX_XC2S150_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, &spartan2_op } +{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, \ + FPGA_SPARTAN2_OPS } #define XILINX_XC2S200_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, &spartan2_op } +{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, \ + FPGA_SPARTAN2_OPS } #define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, &spartan2_op } +{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, \ + FPGA_SPARTAN2_OPS } #define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, &spartan2_op } +{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, \ + FPGA_SPARTAN2_OPS } #define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, &spartan2_op } +{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, \ + FPGA_SPARTAN2_OPS } #define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, &spartan2_op } +{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, \ + FPGA_SPARTAN2_OPS } #define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, &spartan2_op } +{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, \ + FPGA_SPARTAN2_OPS } #endif /* _SPARTAN2_H_ */ -- cgit From a99a06cbbd89d7c116b0ed61325ac359f26ed64e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 16 Jul 2014 10:46:35 +0200 Subject: fpga: xilinx: spartan3: Setup NULL fpga_op without driver Set fpga operations to NULL for cases where FPGA is setup in board file but driver is not added. Signed-off-by: Michal Simek --- include/spartan3.h | 45 +++++++++++++++++++++++++++++++-------------- 1 file changed, 31 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/include/spartan3.h b/include/spartan3.h index d6d67a6e56..fcb27b01e4 100644 --- a/include/spartan3.h +++ b/include/spartan3.h @@ -40,7 +40,12 @@ typedef struct { xilinx_abort_fn abort; } xilinx_spartan3_slave_serial_fns; +#if defined(CONFIG_FPGA_SPARTAN3) extern struct xilinx_fpga_op spartan3_op; +# define FPGA_SPARTAN3_OPS &spartan3_op +#else +# define FPGA_SPARTAN3_OPS NULL +#endif /* Device Image Sizes *********************************************************************/ @@ -71,48 +76,60 @@ extern struct xilinx_fpga_op spartan3_op; *********************************************************************/ /* Spartan-III devices */ #define XILINX_XC3S50_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, &spartan3_op } +{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, \ + FPGA_SPARTAN3_OPS } #define XILINX_XC3S200_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, &spartan3_op } +{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, \ + FPGA_SPARTAN3_OPS } #define XILINX_XC3S400_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, &spartan3_op } +{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, \ + FPGA_SPARTAN3_OPS } #define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, &spartan3_op } +{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, \ + FPGA_SPARTAN3_OPS } #define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, &spartan3_op } +{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, \ + FPGA_SPARTAN3_OPS } #define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, &spartan3_op } +{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, \ + FPGA_SPARTAN3_OPS } #define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, &spartan3_op } +{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, \ + FPGA_SPARTAN3_OPS } #define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, &spartan3_op } +{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, \ + FPGA_SPARTAN3_OPS } /* Spartan-3E devices */ #define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, &spartan3_op } +{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, \ + FPGA_SPARTAN3_OPS } #define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, &spartan3_op } +{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, \ + FPGA_SPARTAN3_OPS } #define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, &spartan3_op } +{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, \ + FPGA_SPARTAN3_OPS } #define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \ { xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie, \ - &spartan3_op } + FPGA_SPARTAN3_OPS } #define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \ { xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie, \ - &spartan3_op } + FPGA_SPARTAN3_OPS } #define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, &spartan3_op } +{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, \ + FPGA_SPARTAN3_OPS } #endif /* _SPARTAN3_H_ */ -- cgit From 6a6acd12ad835232c917a50d4a4d9b79cf59c318 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 16 Jul 2014 10:48:08 +0200 Subject: fpga: xilinx: virtex2: Setup NULL fpga_op without driver Set fpga operations to NULL for cases where FPGA is setup in board file but driver is not added Signed-off-by: Michal Simek --- include/virtex2.h | 45 +++++++++++++++++++++++++++++++-------------- 1 file changed, 31 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/include/virtex2.h b/include/virtex2.h index 7b7825f513..5944bbcb61 100644 --- a/include/virtex2.h +++ b/include/virtex2.h @@ -11,8 +11,6 @@ #include -extern struct xilinx_fpga_op virtex2_op; - /* * Slave SelectMap Implementation function table. */ @@ -40,6 +38,13 @@ typedef struct { xilinx_wdata_fn wdata; } xilinx_virtex2_slave_serial_fns; +#if defined(CONFIG_FPGA_VIRTEX2) +extern struct xilinx_fpga_op virtex2_op; +# define FPGA_VIRTEX2_OPS &virtex2_op +#else +# define FPGA_VIRTEX2_OPS NULL +#endif + /* Device Image Sizes (in bytes) *********************************************************************/ #define XILINX_XC2V40_SIZE (338208 / 8) @@ -58,39 +63,51 @@ typedef struct { /* Descriptor Macros *********************************************************************/ #define XILINX_XC2V40_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, &virtex2_op } +{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, \ + FPGA_VIRTEX2_OPS } #define XILINX_XC2V80_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, &virtex2_op } +{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, \ + FPGA_VIRTEX2_OPS } #define XILINX_XC2V250_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, &virtex2_op } +{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, \ + FPGA_VIRTEX2_OPS } #define XILINX_XC2V500_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, &virtex2_op } +{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, \ + FPGA_VIRTEX2_OPS } #define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, &virtex2_op } +{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, \ + FPGA_VIRTEX2_OPS } #define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, &virtex2_op } +{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, \ + FPGA_VIRTEX2_OPS } #define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, &virtex2_op } +{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, \ + FPGA_VIRTEX2_OPS } #define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, &virtex2_op } +{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, \ + FPGA_VIRTEX2_OPS } #define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, &virtex2_op } +{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, \ + FPGA_VIRTEX2_OPS } #define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, &virtex2_op } +{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, \ + FPGA_VIRTEX2_OPS } #define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, &virtex2_op } +{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, \ + FPGA_VIRTEX2_OPS } #define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, &virtex2_op } +{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, \ + FPGA_VIRTEX2_OPS } #endif /* _VIRTEX2_H_ */ -- cgit From a3607365f78ce79f8592e3acb4a04ab4d4ac8f36 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 16 Jul 2014 10:47:43 +0200 Subject: fpga: xilinx: virtex2: Fix macro indentation No functional changes. Signed-off-by: Michal Simek --- include/virtex2.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/virtex2.h b/include/virtex2.h index 5944bbcb61..503df9abae 100644 --- a/include/virtex2.h +++ b/include/virtex2.h @@ -47,10 +47,10 @@ extern struct xilinx_fpga_op virtex2_op; /* Device Image Sizes (in bytes) *********************************************************************/ -#define XILINX_XC2V40_SIZE (338208 / 8) -#define XILINX_XC2V80_SIZE (597408 / 8) -#define XILINX_XC2V250_SIZE (1591584 / 8) -#define XILINX_XC2V500_SIZE (2557857 / 8) +#define XILINX_XC2V40_SIZE (338208 / 8) +#define XILINX_XC2V80_SIZE (597408 / 8) +#define XILINX_XC2V250_SIZE (1591584 / 8) +#define XILINX_XC2V500_SIZE (2557857 / 8) #define XILINX_XC2V1000_SIZE (3749408 / 8) #define XILINX_XC2V1500_SIZE (5166240 / 8) #define XILINX_XC2V2000_SIZE (6808352 / 8) -- cgit From 345f9e195675207372efbb492f29dcfdcb938fd7 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 16 Jul 2014 10:47:13 +0200 Subject: fpga: xilinx: zynqpl: Setup NULL fpga_op without driver Set fpga operations to NULL for cases where FPGA is setup in board file but driver is not added Signed-off-by: Michal Simek --- include/zynqpl.h | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/zynqpl.h b/include/zynqpl.h index 8a9ec3297f..d0ff0d9a8b 100644 --- a/include/zynqpl.h +++ b/include/zynqpl.h @@ -12,7 +12,12 @@ #include +#if defined(CONFIG_FPGA_ZYNQPL) extern struct xilinx_fpga_op zynq_op; +# define FPGA_ZYNQPL_OPS &zynq_op +#else +# define FPGA_ZYNQPL_OPS NULL +#endif #define XILINX_ZYNQ_7010 0x2 #define XILINX_ZYNQ_7015 0x1b @@ -31,21 +36,27 @@ extern struct xilinx_fpga_op zynq_op; /* Descriptor Macros */ #define XILINX_XC7Z010_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, &zynq_op, "7z010" } +{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z010" } #define XILINX_XC7Z015_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, &zynq_op, "7z015" } +{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z015" } #define XILINX_XC7Z020_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, &zynq_op, "7z020" } +{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z020" } #define XILINX_XC7Z030_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, &zynq_op, "7z030" } +{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z030" } #define XILINX_XC7Z045_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, &zynq_op, "7z045" } +{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z045" } #define XILINX_XC7Z100_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, &zynq_op, "7z100" } +{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z100" } #endif /* _ZYNQPL_H_ */ -- cgit From b9103809eb9052f40479d2d741e980832b75ebba Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 25 Nov 2014 15:29:54 +0530 Subject: fpga: zynqpl: Add support for zc7035 Added support for zc7035 Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- include/zynqpl.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/zynqpl.h b/include/zynqpl.h index d0ff0d9a8b..1d37a51a04 100644 --- a/include/zynqpl.h +++ b/include/zynqpl.h @@ -23,6 +23,7 @@ extern struct xilinx_fpga_op zynq_op; #define XILINX_ZYNQ_7015 0x1b #define XILINX_ZYNQ_7020 0x7 #define XILINX_ZYNQ_7030 0xc +#define XILINX_ZYNQ_7035 0x12 #define XILINX_ZYNQ_7045 0x11 #define XILINX_ZYNQ_7100 0x16 @@ -31,6 +32,7 @@ extern struct xilinx_fpga_op zynq_op; #define XILINX_XC7Z015_SIZE 28085344/8 #define XILINX_XC7Z020_SIZE 32364512/8 #define XILINX_XC7Z030_SIZE 47839328/8 +#define XILINX_XC7Z035_SIZE 106571232/8 #define XILINX_XC7Z045_SIZE 106571232/8 #define XILINX_XC7Z100_SIZE 139330784/8 @@ -51,6 +53,10 @@ extern struct xilinx_fpga_op zynq_op; { xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ "7z030" } +#define XILINX_XC7Z035_DESC(cookie) \ +{ xilinx_zynq, devcfg, XILINX_XC7Z035_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z035" } + #define XILINX_XC7Z045_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ "7z045" } -- cgit From 5840537879d93814f681d45ccf26d8b171f80acf Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 14 Jan 2015 15:44:21 +0100 Subject: net: gem: Use phys_addr_t instead of int for addresses Use phys_addr_t for physical address declaration. It is also unsigned type instead of sign. Signed-off-by: Michal Simek --- include/netdev.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/netdev.h b/include/netdev.h index 34651ab377..daffc1222d 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -93,7 +93,8 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags, unsigned long ctrl_addr); int zynq_gem_of_init(const void *blob); -int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio); +int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr, + int phy_addr, u32 emio); /* * As long as the Xilinx xps_ll_temac ethernet driver has not its own interface * exported by a public hader file, we need a global definition at this point. -- cgit From 9d638eeab71c506cdb7b085fa1932dad13885c02 Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Sun, 18 Jan 2015 22:00:18 +0100 Subject: MIPS: add Kconfig option for CONFIG_SWAP_IO_SPACE Signed-off-by: Daniel Schwierzeck --- include/configs/malta.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/configs/malta.h b/include/configs/malta.h index a29b86b4f6..684d249590 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -38,8 +38,6 @@ #define CONFIG_SYS_MHZ 250 /* arbitrary value */ #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) -#define CONFIG_SWAP_IO_SPACE - /* * Memory map */ -- cgit From a83fccc2c979263ba88a6801130258124caca51a Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Wed, 21 Jan 2015 11:54:11 +0200 Subject: board/T1040qds: Add VSC9953 support for T1040qds board This patch configures and initializes the L2 switch on T1040QDS board. The L2 switch ports must be initialized according to the SerDes protocols. Signed-off-by: Codrin Ciubotariu --- include/configs/T1040QDS.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 5ebc8709aa..92f5f56718 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -692,6 +692,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #endif +/* Enable VSC9953 L2 Switch driver */ +#define CONFIG_VSC9953 +#define CONFIG_VSC9953_CMD +#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 +#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 + /* * Dynamic MTD Partition support with mtdparts */ -- cgit From db4a1767c09a4696792204d1cac33631cb38424e Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Wed, 21 Jan 2015 11:54:12 +0200 Subject: board/T1040rdb: Add VSC9953 support for T1040rdb board This patch configures and initializes the L2 switch on T1040rdb board. The external L2 switch ports may be connected to PHYs only over QSGMII, for T1040rdb. Signed-off-by: Codrin Ciubotariu --- include/configs/T104xRDB.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include') diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 57cdf7213c..d47f1be685 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -726,6 +726,14 @@ #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 +/* Enable VSC9953 L2 Switch driver on T1040 SoC */ +#ifdef CONFIG_T1040RDB +#define CONFIG_VSC9953 +#define CONFIG_VSC9953_CMD +#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 +#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 +#endif + #define CONFIG_MII /* MII PHY management */ #define CONFIG_ETHPRIME "FM1@DTSEC4" #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ -- cgit From b56f6e2b4e0291efbe1b50f082dec73272ad7ab3 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 21 Jan 2015 16:24:05 +0100 Subject: sunxi: Restore lowlevel_init usage 2 recent sunxi changes have removed the usage of lowlevel_init by moving some code around and then setting CONFIG_SKIP_LOWLEVEL_INIT. This is problematic for 2 reasons: 1) It does not just stop s_init from being called, it also stops cpu_init_cp15 from getting called, which is undesirable. 2) We want u-boot.bin to be usable standalone, without SPL, some people e.g. use an upstream u-boot.bin together with Allwinner's boot0 loader. So u-boot.bin must (re)initialize the gpios, timer, etc. This commit restores the lowlevel_init / s_init usage, while keeping the changes to no longer use the global-data (gd) struct in the SPL. Signed-off-by: Hans de Goede --- include/configs/sunxi-common.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 647cac5a93..e839053e2b 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -109,7 +109,6 @@ #define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_SKIP_LOWLEVEL_INIT /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -- cgit From 6906df1ab8d64a4e21d38ea538d6cd383a089e1d Mon Sep 17 00:00:00 2001 From: Siarhei Siamashka Date: Mon, 19 Jan 2015 05:23:30 +0200 Subject: sunxi: axp221: Add ELDO[1-3] support And also add Kconfig option for selecting ELDO3 voltage. The reason for having this option is that the Android kernel sets ELDO3 to 1.2V when powering up LCD in the case if 'lcd_if' configuration variable is set to 6 (LCD_IF_EXT_DSI) in the FEX file. Most likely to supply power for a SSD2828 chip. However on the MSI Primo81 tablet, which is using this particular 'lcd_if = 6' setup for LCD, setting the ELDO3 voltage appears to be unnecessary and it works regardless. Having no schematics of this tablet, I can only guess that 1.2V is supplied to SSD2828 in some other way. Signed-off-by: Siarhei Siamashka Acked-by: Hans de Goede Signed-off-by: Hans de Goede --- include/axp221.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include') diff --git a/include/axp221.h b/include/axp221.h index e6639f1ffe..6f24a617b6 100644 --- a/include/axp221.h +++ b/include/axp221.h @@ -26,6 +26,9 @@ #define AXP221_OUTPUT_CTRL1_ALDO1_EN (1 << 6) #define AXP221_OUTPUT_CTRL1_ALDO2_EN (1 << 7) #define AXP221_OUTPUT_CTRL2 0x12 +#define AXP221_OUTPUT_CTRL2_ELDO1_EN (1 << 0) +#define AXP221_OUTPUT_CTRL2_ELDO2_EN (1 << 1) +#define AXP221_OUTPUT_CTRL2_ELDO3_EN (1 << 2) #define AXP221_OUTPUT_CTRL2_DLDO1_EN (1 << 3) #define AXP221_OUTPUT_CTRL2_DLDO2_EN (1 << 4) #define AXP221_OUTPUT_CTRL2_DLDO3_EN (1 << 5) @@ -37,6 +40,9 @@ #define AXP221_DLDO2_CTRL 0x16 #define AXP221_DLDO3_CTRL 0x17 #define AXP221_DLDO4_CTRL 0x18 +#define AXP221_ELDO1_CTRL 0x19 +#define AXP221_ELDO2_CTRL 0x1a +#define AXP221_ELDO3_CTRL 0x1b #define AXP221_DCDC1_CTRL 0x21 #define AXP221_DCDC2_CTRL 0x22 #define AXP221_DCDC3_CTRL 0x23 @@ -69,6 +75,7 @@ int axp221_set_dldo4(unsigned int mvolt); int axp221_set_aldo1(unsigned int mvolt); int axp221_set_aldo2(unsigned int mvolt); int axp221_set_aldo3(unsigned int mvolt); +int axp221_set_eldo(int eldo_num, unsigned int mvolt); int axp221_init(void); int axp221_get_sid(unsigned int *sid); int axp_drivebus_enable(void); -- cgit From ebe079bc51e0ad1d49424cc3da8bf199511a81ac Mon Sep 17 00:00:00 2001 From: Siarhei Siamashka Date: Mon, 19 Jan 2015 05:23:31 +0200 Subject: include: Add header file with MIPI DSI constants from linux 3.18 The file, originally named "include/video/mipi_display.h", is taken from linux 3.18 (commit b2776bf7149bddd1f4161f14f79520f17fc1d71d). It provides MIPI DSI constants for DCS commands, which are needed to implement support for SSD2828 in u-boot. Signed-off-by: Siarhei Siamashka Acked-by: Hans de Goede Signed-off-by: Hans de Goede --- include/mipi_display.h | 130 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 130 insertions(+) create mode 100644 include/mipi_display.h (limited to 'include') diff --git a/include/mipi_display.h b/include/mipi_display.h new file mode 100644 index 0000000000..ddcc8ca731 --- /dev/null +++ b/include/mipi_display.h @@ -0,0 +1,130 @@ +/* + * Defines for Mobile Industry Processor Interface (MIPI(R)) + * Display Working Group standards: DSI, DCS, DBI, DPI + * + * Copyright (C) 2010 Guennadi Liakhovetski + * Copyright (C) 2006 Nokia Corporation + * Author: Imre Deak + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef MIPI_DISPLAY_H +#define MIPI_DISPLAY_H + +/* MIPI DSI Processor-to-Peripheral transaction types */ +enum { + MIPI_DSI_V_SYNC_START = 0x01, + MIPI_DSI_V_SYNC_END = 0x11, + MIPI_DSI_H_SYNC_START = 0x21, + MIPI_DSI_H_SYNC_END = 0x31, + + MIPI_DSI_COLOR_MODE_OFF = 0x02, + MIPI_DSI_COLOR_MODE_ON = 0x12, + MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22, + MIPI_DSI_TURN_ON_PERIPHERAL = 0x32, + + MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03, + MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13, + MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23, + + MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04, + MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14, + MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24, + + MIPI_DSI_DCS_SHORT_WRITE = 0x05, + MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15, + + MIPI_DSI_DCS_READ = 0x06, + + MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, + + MIPI_DSI_END_OF_TRANSMISSION = 0x08, + + MIPI_DSI_NULL_PACKET = 0x09, + MIPI_DSI_BLANKING_PACKET = 0x19, + MIPI_DSI_GENERIC_LONG_WRITE = 0x29, + MIPI_DSI_DCS_LONG_WRITE = 0x39, + + MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c, + + MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d, + MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d, + + MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e, + MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e, + MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e, + MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e, +}; + +/* MIPI DSI Peripheral-to-Processor transaction types */ +enum { + MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02, + MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08, + MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11, + MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12, + MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a, + MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c, + MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21, + MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22, +}; + +/* MIPI DCS commands */ +enum { + MIPI_DCS_NOP = 0x00, + MIPI_DCS_SOFT_RESET = 0x01, + MIPI_DCS_GET_DISPLAY_ID = 0x04, + MIPI_DCS_GET_RED_CHANNEL = 0x06, + MIPI_DCS_GET_GREEN_CHANNEL = 0x07, + MIPI_DCS_GET_BLUE_CHANNEL = 0x08, + MIPI_DCS_GET_DISPLAY_STATUS = 0x09, + MIPI_DCS_GET_POWER_MODE = 0x0A, + MIPI_DCS_GET_ADDRESS_MODE = 0x0B, + MIPI_DCS_GET_PIXEL_FORMAT = 0x0C, + MIPI_DCS_GET_DISPLAY_MODE = 0x0D, + MIPI_DCS_GET_SIGNAL_MODE = 0x0E, + MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F, + MIPI_DCS_ENTER_SLEEP_MODE = 0x10, + MIPI_DCS_EXIT_SLEEP_MODE = 0x11, + MIPI_DCS_ENTER_PARTIAL_MODE = 0x12, + MIPI_DCS_ENTER_NORMAL_MODE = 0x13, + MIPI_DCS_EXIT_INVERT_MODE = 0x20, + MIPI_DCS_ENTER_INVERT_MODE = 0x21, + MIPI_DCS_SET_GAMMA_CURVE = 0x26, + MIPI_DCS_SET_DISPLAY_OFF = 0x28, + MIPI_DCS_SET_DISPLAY_ON = 0x29, + MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A, + MIPI_DCS_SET_PAGE_ADDRESS = 0x2B, + MIPI_DCS_WRITE_MEMORY_START = 0x2C, + MIPI_DCS_WRITE_LUT = 0x2D, + MIPI_DCS_READ_MEMORY_START = 0x2E, + MIPI_DCS_SET_PARTIAL_AREA = 0x30, + MIPI_DCS_SET_SCROLL_AREA = 0x33, + MIPI_DCS_SET_TEAR_OFF = 0x34, + MIPI_DCS_SET_TEAR_ON = 0x35, + MIPI_DCS_SET_ADDRESS_MODE = 0x36, + MIPI_DCS_SET_SCROLL_START = 0x37, + MIPI_DCS_EXIT_IDLE_MODE = 0x38, + MIPI_DCS_ENTER_IDLE_MODE = 0x39, + MIPI_DCS_SET_PIXEL_FORMAT = 0x3A, + MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C, + MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E, + MIPI_DCS_SET_TEAR_SCANLINE = 0x44, + MIPI_DCS_GET_SCANLINE = 0x45, + MIPI_DCS_READ_DDB_START = 0xA1, + MIPI_DCS_READ_DDB_CONTINUE = 0xA8, +}; + +/* MIPI DCS pixel formats */ +#define MIPI_DCS_PIXEL_FMT_24BIT 7 +#define MIPI_DCS_PIXEL_FMT_18BIT 6 +#define MIPI_DCS_PIXEL_FMT_16BIT 5 +#define MIPI_DCS_PIXEL_FMT_12BIT 3 +#define MIPI_DCS_PIXEL_FMT_8BIT 2 +#define MIPI_DCS_PIXEL_FMT_3BIT 1 + +#endif -- cgit From 1a800f7af3ef5f42ff703fd4b313b79e471f6ced Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 11 Jan 2015 17:17:00 +0100 Subject: sunxi: Hookup OTG USB controller support Hookup OTG USB controller support and enable the otg controller + USB-keyb on various tablets. This allows tablet owners to interact with u-boot without needing to solder a serial console onto their tablet PCB. Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- include/configs/sunxi-common.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index e839053e2b..7a66a4dca6 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -247,8 +247,16 @@ #endif #ifdef CONFIG_USB_EHCI -#define CONFIG_CMD_USB #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 +#endif + +#ifdef CONFIG_USB_MUSB_SUNXI +#define CONFIG_MUSB_HOST +#define CONFIG_MUSB_PIO_ONLY +#endif + +#if defined CONFIG_USB_EHCI || defined CONFIG_USB_MUSB_SUNXI +#define CONFIG_CMD_USB #define CONFIG_USB_STORAGE #endif -- cgit From 4e7c892d15e2aa98086aaacdb979821d011b7db2 Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Fri, 23 Jan 2015 10:17:35 +0000 Subject: sunxi: Use a common CONFIG_SYS_PROMPT The CPU info is already logged during boot e.g. CPU: Allwinner A20 (SUN7I) so the prompt is just one more thing to change for each new SoC, just makes it "sunxi#" instead. Signed-off-by: Ian Campbell Acked-by: Hans de Goede Signed-off-by: Hans de Goede --- include/configs/sun4i.h | 1 - include/configs/sun5i.h | 1 - include/configs/sun6i.h | 2 -- include/configs/sun7i.h | 1 - include/configs/sun8i.h | 2 -- include/configs/sunxi-common.h | 2 ++ 6 files changed, 2 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h index 7b857405e9..87d269b041 100644 --- a/include/configs/sun4i.h +++ b/include/configs/sun4i.h @@ -13,7 +13,6 @@ */ #define CONFIG_CLK_FULL_SPEED 1008000000 -#define CONFIG_SYS_PROMPT "sun4i# " #define CONFIG_MACH_TYPE 4104 #ifdef CONFIG_USB_EHCI diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h index 09f7533575..52e3a6ff01 100644 --- a/include/configs/sun5i.h +++ b/include/configs/sun5i.h @@ -13,7 +13,6 @@ */ #define CONFIG_CLK_FULL_SPEED 1008000000 -#define CONFIG_SYS_PROMPT "sun5i# " #define CONFIG_MACH_TYPE 4138 #ifdef CONFIG_USB_EHCI diff --git a/include/configs/sun6i.h b/include/configs/sun6i.h index 1b73852799..f5e11ddb69 100644 --- a/include/configs/sun6i.h +++ b/include/configs/sun6i.h @@ -16,8 +16,6 @@ */ #define CONFIG_CLK_FULL_SPEED 1008000000 -#define CONFIG_SYS_PROMPT "sun6i# " - #ifdef CONFIG_USB_EHCI #define CONFIG_USB_EHCI_SUNXI #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h index ccec50c328..7cd7890341 100644 --- a/include/configs/sun7i.h +++ b/include/configs/sun7i.h @@ -14,7 +14,6 @@ */ #define CONFIG_CLK_FULL_SPEED 912000000 -#define CONFIG_SYS_PROMPT "sun7i# " #define CONFIG_MACH_TYPE 4283 #ifdef CONFIG_USB_EHCI diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h index f16e60b576..3bdedb390c 100644 --- a/include/configs/sun8i.h +++ b/include/configs/sun8i.h @@ -14,8 +14,6 @@ */ #define CONFIG_CLK_FULL_SPEED 1008000000 -#define CONFIG_SYS_PROMPT "sun8i# " - #ifdef CONFIG_USB_EHCI #define CONFIG_USB_EHCI_SUNXI #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 7a66a4dca6..4a5cab25d4 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -40,6 +40,8 @@ */ #define CONFIG_DISPLAY_CPUINFO +#define CONFIG_SYS_PROMPT "sunxi# " + /* Serial & console */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL -- cgit From 8d1e3cb14009d3fb4752489e02ae1a88d75e6b0b Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 23 Jan 2015 00:24:15 +0900 Subject: powerpc: mpc83xx: remove MPC8360ERDK, EMPC8360EMDS support These boards are still non-generic boards. Signed-off-by: Masahiro Yamada Cc: Dave Liu Cc: Anton Vorontsov --- include/configs/MPC8360EMDS.h | 735 ------------------------------------------ include/configs/MPC8360ERDK.h | 620 ----------------------------------- 2 files changed, 1355 deletions(-) delete mode 100644 include/configs/MPC8360EMDS.h delete mode 100644 include/configs/MPC8360ERDK.h (limited to 'include') diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h deleted file mode 100644 index aefde74fc5..0000000000 --- a/include/configs/MPC8360EMDS.h +++ /dev/null @@ -1,735 +0,0 @@ -/* - * Copyright (C) 2006,2011 Freescale Semiconductor, Inc. - * - * Dave Liu - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ -#define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ -#define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */ - -#define CONFIG_SYS_TEXT_BASE 0xFE000000 - -#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */ -#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */ - -/* - * System Clock Setup - */ -#ifdef CONFIG_CLKIN_33MHZ -#ifdef CONFIG_PCISLAVE -#define CONFIG_83XX_PCICLK 33330000 /* in HZ */ -#else -#define CONFIG_83XX_CLKIN 33330000 /* in Hz */ -#endif - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 33330000 -#endif - -#elif defined(CONFIG_CLKIN_66MHZ) -#ifdef CONFIG_PCISLAVE -#define CONFIG_83XX_PCICLK 66000000 /* in HZ */ -#else -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ -#endif - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 66000000 -#endif -#else -#error Unknown oscillator frequency. -#endif - -/* - * Hardware Reset Configuration Word - */ -#ifdef CONFIG_CLKIN_33MHZ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN_8X1 |\ - HRCWL_VCO_1X2 |\ - HRCWL_CE_PLL_VCO_DIV_4 |\ - HRCWL_CE_PLL_DIV_1X1 |\ - HRCWL_CE_TO_PLL_1X15 |\ - HRCWL_CORE_TO_CSB_2X1) -#elif defined(CONFIG_CLKIN_66MHZ) -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ - HRCWL_VCO_1X2 |\ - HRCWL_CE_PLL_VCO_DIV_4 |\ - HRCWL_CE_PLL_DIV_1X1 |\ - HRCWL_CE_TO_PLL_1X6 |\ - HRCWL_CORE_TO_CSB_2X1) -#endif - -#ifdef CONFIG_PCISLAVE -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT |\ - HRCWH_PCI1_ARBITER_DISABLE |\ - HRCWH_PCICKDRV_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCICKDRV_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT) -#endif - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRH 0x00000000 -#define CONFIG_SYS_SICRL 0x40000000 - -#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ -#define CONFIG_BOARD_EARLY_INIT_R - -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE - /* + 256M */ -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ - | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CONFIG_SYS_83XX_DDR_USES_CS0 - -#define CONFIG_DDR_ECC /* support DDR ECC function */ -#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ - -/* - * DDRCDR - DDR Control Driver Register - */ -#define CONFIG_SYS_DDRCDR_VALUE 0x80080001 - -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#if defined(CONFIG_SPD_EEPROM) -/* - * Determine DDR configuration from I2C interface. - */ -#define SPD_EEPROM_ADDRESS 0x52 /* DDR SODIMM */ -#else -/* - * Manually set up DDR parameters - */ -#define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#if defined(CONFIG_DDR_II) -#define CONFIG_SYS_DDRCDR 0x80080001 -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80330102 -#define CONFIG_SYS_DDR_TIMING_0 0x00220802 -#define CONFIG_SYS_DDR_TIMING_1 0x38357322 -#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 -#define CONFIG_SYS_DDR_MODE 0x47d00432 -#define CONFIG_SYS_DDR_MODE2 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 -#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#else -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ROW_BIT_13 \ - | CSCONFIG_COL_BIT_9) -#define CONFIG_SYS_DDR_CS1_CONFIG CONFIG_SYS_DDR_CS0_CONFIG -#define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */ -#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */ -#define CONFIG_SYS_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */ -#define CONFIG_SYS_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */ -#define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* page mode */ -#endif -#endif - -/* - * Memory test - */ -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00100000 - -/* - * The reserved memory - */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 -#define CONFIG_SYS_LBC_LBCR 0x00000000 - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - - /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM - -/* - * BCSR on the Local Bus - */ -#define CONFIG_SYS_BCSR 0xF8000000 - /* Access window base at BCSR base */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) - -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ - | BR_PS_8 \ - | BR_MS_GPCM \ - | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xFFFFE9F7 */ - -/* - * SDRAM on the Local Bus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -#define CONFIG_SYS_LB_SDRAM /* if board has SRDAM on local bus */ - -#ifdef CONFIG_SYS_LB_SDRAM -#define CONFIG_SYS_LBLAWBAR2 0 -#define CONFIG_SYS_LBLAWAR2 (LBLAWAR_EN | LBLAWAR_64MB) - -/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * - * For BR2, need: - * Base address = BR[0:16] = dynamic - * port size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * xxxx xxxx xxxx xxxx x001 1000 0110 0001 = 00001861 - */ - -/* Port size=32bit, MSEL=DRAM */ -#define CONFIG_SYS_BR2 (BR_PS_32 | BR_MS_SDRAM | BR_V) /* 0xF0001861 */ - -/* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 - */ - -#define CONFIG_SYS_OR2 (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \ - | OR_SDRAM_XAM \ - | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ - | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ - | OR_SDRAM_EAD) - /* 0xFC006901 */ - - /* LB sdram refresh timer, about 6us */ -#define CONFIG_SYS_LBC_LSRT 0x32000000 - /* LB refresh timer prescal, 266MHz/32 */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 - -#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723 - -/* - * SDRAM Controller configuration sequence. - */ -#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) -#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) -#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) - -#endif - -/* - * Windows to access Platform I/O Boards (PIB) via local bus - */ -#define CONFIG_SYS_PIB_BASE 0xF8008000 -#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024) - -/* [RFC] This LBLAW only covers the 2nd window (CS5) */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM \ - CONFIG_SYS_PIB_BASE + CONFIG_SYS_PIB_WINDOW_SIZE -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - -/* - * CS4 on Local Bus, to PIB - */ - /* CS4 base address at 0xf8008000 */ -#define CONFIG_SYS_BR4_PRELIM (CONFIG_SYS_PIB_BASE \ - | BR_PS_8 \ - | BR_MS_GPCM \ - | BR_V) - /* 0xF8008801 */ -#define CONFIG_SYS_OR4_PRELIM (OR_AM_32KB \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xffffe9f7 */ - -/* - * CS5 on Local Bus, to PIB - */ - /* CS5 base address at 0xf8010000 */ -#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_PIB_BASE + \ - CONFIG_SYS_PIB_WINDOW_SIZE) \ - | BR_PS_8 \ - | BR_MS_GPCM \ - | BR_V) - /* 0xF8010801 */ -#define CONFIG_SYS_OR5_PRELIM (CONFIG_SYS_PIB_BASE \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xffffe9f7 */ - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} } - -/* - * Config on-board RTC - */ -#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ - -#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 -#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 - - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE - -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_83XX_PCI_STREAMING - -#undef CONFIG_EEPRO100 -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ - -#endif /* CONFIG_PCI */ - - -#define CONFIG_HWCONFIG 1 - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" -#define CONFIG_PHY_MODE_NEED_CHANGE - -#define CONFIG_UEC_ETH1 /* GETH1 */ - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 -#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 -#endif - -#define CONFIG_UEC_ETH2 /* GETH2 */ - -#ifdef CONFIG_UEC_ETH2 -#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ -#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE -#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4 -#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH -#define CONFIG_SYS_UEC2_PHY_ADDR 1 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID -#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT - #define CONFIG_ENV_IS_IN_FLASH 1 - #define CONFIG_ENV_ADDR \ - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - #define CONFIG_ENV_SECT_SIZE 0x20000 - #define CONFIG_ENV_SIZE 0x2000 -#else - #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ - #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_SDRAM - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - -#if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_SAVEENV - #undef CONFIG_CMD_LOADS -#endif - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -#if defined(CONFIG_CMD_KGDB) - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - - /* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ - /* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ - -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - -/* - * MMU Setup - */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ -#define CONFIG_BAT_RW - -/* DDR/LBC SDRAM: cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ - | BATU_BL_4M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* BCSR: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \ - | BATU_BL_128K \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \ - | BATU_BL_32M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* DDR/LBC SDRAM next 256M: cacheable */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM_BASE2 \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM_BASE2 \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ - | BATU_BL_128K \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -#ifdef CONFIG_PCI -/* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -/* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U -#else -#define CONFIG_SYS_IBAT6L (0) -#define CONFIG_SYS_IBAT6U (0) -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=1000000\0" \ - "ramdiskfile=ramfs.83xx\0" \ - "fdtaddr=780000\0" \ - "fdtfile=mpc836x_mds.dtb\0" \ - "" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ - "$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h deleted file mode 100644 index 1b8bad179b..0000000000 --- a/include/configs/MPC8360ERDK.h +++ /dev/null @@ -1,620 +0,0 @@ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * Dave Liu - * - * Copyright (C) 2007 Logic Product Development, Inc. - * Peter Barada - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ -#define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ -#define CONFIG_MPC8360ERDK 1 /* MPC8360ERDK board specific */ - -#define CONFIG_SYS_TEXT_BASE 0xFF800000 - -/* - * System Clock Setup - */ -#ifdef CONFIG_CLKIN_33MHZ -#define CONFIG_83XX_CLKIN 33333333 -#define CONFIG_SYS_CLK_FREQ 33333333 -#define CONFIG_PCI_33M 1 -#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_10X1 -#else -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_PCI_66M 1 -#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_5X1 -#endif /* CONFIG_CLKIN_33MHZ */ - -/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN_MPC8360ERDK |\ - HRCWL_CORE_TO_CSB_2X1 |\ - HRCWL_CE_TO_PLL_1X15) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCICKDRV_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_SECONDARY_DDR_DISABLE |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LALE_EARLY) - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRH 0x00000000 -#define CONFIG_SYS_SICRL 0x40000000 - -#define CONFIG_BOARD_EARLY_INIT_R - -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ - | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CONFIG_SYS_83XX_DDR_USES_CS0 - -#define CONFIG_DDR_ECC /* support DDR ECC function */ -#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ - -/* - * DDRCDR - DDR Control Driver Register - */ -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ - | DDRCDR_ODT \ - | DDRCDR_Q_DRN) - /* 0x80080001 */ - -#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */ - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ROW_BIT_13 \ - | CSCONFIG_COL_BIT_10 \ - | CSCONFIG_ODT_WR_ONLY_CURRENT) -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_ECC_EN) -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) \ - | (1115 << SDRAM_INTERVAL_REFINT_SHIFT)) -#define CONFIG_SYS_DDR_MODE 0x47800432 -#define CONFIG_SYS_DDR_MODE2 0x8000c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_30) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (10 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (0 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -/* - * Memory test - */ -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00100000 - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* FLASH base address */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 -#define CONFIG_SYS_LBC_LBCR 0x00000000 - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ -#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use intel Flash protection. */ - - /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM - -/* - * NAND flash on the local bus - */ -#define CONFIG_SYS_NAND_BASE 0x60000000 -#define CONFIG_CMD_NAND 1 -#define CONFIG_NAND_FSL_UPM 1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE - -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -/* - * [RFC] Comment said 4KB window; code said 256MB window; OR1 says 64MB - * ... What's correct? - */ -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - -/* Port size 8 bit, UPMA */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ - | BR_PS_8 \ - | BR_MS_UPMA \ - | BR_V) - /* 0x60000881 */ -#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_UPM_EAD) - /* 0xFC000001 */ - -/* - * Fujitsu MB86277 (MINT) graphics controller - */ -#define CONFIG_SYS_VIDEO_BASE 0x70000000 - -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VIDEO_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) - -/* Port size 32 bit, UPMB */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VIDEO_BASE \ - | BR_PS_32 \ - | BR_MS_UPMB \ - | BR_V) - /* 0x000018a1 */ -#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB | OR_UPM_EAD) - /* 0xFC000001 */ - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER - -/* Pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} } - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_PCI - -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0xE0300000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE - -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ - -#endif /* CONFIG_PCI */ - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#define CONFIG_UEC_ETH1 /* GETH1 */ - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 -#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 2 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 -#endif - -#define CONFIG_UEC_ETH2 /* GETH2 */ - -#ifdef CONFIG_UEC_ETH2 -#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ -#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE -#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4 -#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH -#define CONFIG_SYS_UEC2_PHY_ADDR 4 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID -#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 -#endif - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#define CONFIG_ENV_SIZE 0x20000 -#else /* CONFIG_SYS_RAMBOOT */ -#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ -#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CONFIG_SYS_RAMBOOT */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_PCI -#endif - -#if defined(CONFIG_SYS_RAMBOOT) -#undef CONFIG_CMD_SAVEENV -#undef CONFIG_CMD_LOADS -#endif - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -#if defined(CONFIG_CMD_KGDB) - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - - /* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ - /* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ - -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - -/* - * MMU Setup - */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ - | BATU_BL_4M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_NAND_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_NAND_BASE \ - | BATU_BL_64M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \ - | BATU_BL_32M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR \ - | BATL_PP_RW) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \ - | BATU_BL_128K \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_VIDEO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_VIDEO_BASE \ - | BATU_BL_64M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -#ifdef CONFIG_PCI -/* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -/* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U -#else /* CONFIG_PCI */ -#define CONFIG_SYS_IBAT6L (0) -#define CONFIG_SYS_IBAT6U (0) -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADADDR a00000 -#define CONFIG_HOSTNAME mpc8360erdk -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_ROOTPATH "/nfsroot/" - -#define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "loadaddr=a00000\0" \ - "fdtaddr=900000\0" \ - "fdtfile=mpc836x_rdk.dtb\0" \ - "fsfile=fs\0" \ - "ubootfile=u-boot.bin\0" \ - "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),"\ - "-(rootfs)\0" \ - "setbootargs=setenv bootargs console=$consoledev,$baudrate " \ - "$mtdparts panic=1\0" \ - "adddhcpargs=setenv bootargs $bootargs ip=on\0" \ - "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:" \ - "$gatewayip:$netmask:$hostname:$netdev:off " \ - "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \ - "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 " \ - "rootfstype=jffs2 rw\0" \ - "tftp_get_uboot=tftp 100000 $ubootfile\0" \ - "tftp_get_kernel=tftp $loadaddr $bootfile\0" \ - "tftp_get_dtb=tftp $fdtaddr $fdtfile\0" \ - "tftp_get_fs=tftp c00000 $fsfile\0" \ - "nand_erase_kernel=nand erase 0 400000\0" \ - "nand_erase_dtb=nand erase 400000 20000\0" \ - "nand_erase_fs=nand erase 420000 3be0000\0" \ - "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0" \ - "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0" \ - "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0" \ - "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0" \ - "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0" \ - "nor_reflash=protect off ff800000 ff87ffff ; " \ - "erase ff800000 ff87ffff ; " \ - "cp.b 100000 ff800000 $filesize\0" \ - "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel " \ - "nand_write_kernel\0" \ - "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\ - "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0" \ - "nand_reflash=run nand_reflash_kernel nand_reflash_dtb " \ - "nand_reflash_fs\0" \ - "boot_m=bootm $loadaddr - $fdtaddr\0" \ - "dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\ - "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\ - "boot_m\0" \ - "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\ - "boot_m\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run dhcpboot" - -#endif /* __CONFIG_H */ -- cgit From 743d48151d2df4215b90310dc422db84d45e8002 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 23 Jan 2015 00:24:16 +0900 Subject: powerpc: mpc85xx: remove P1_P2_RDB boards These boards are still non-generic boards: P1011RDB, P1022RDB, P2010RDB, P2020RDB Signed-off-by: Masahiro Yamada Cc: Poonam Aggrwal --- include/configs/P1_P2_RDB.h | 808 -------------------------------------------- 1 file changed, 808 deletions(-) delete mode 100644 include/configs/P1_P2_RDB.h (limited to 'include') diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h deleted file mode 100644 index c75638abda..0000000000 --- a/include/configs/P1_P2_RDB.h +++ /dev/null @@ -1,808 +0,0 @@ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * P1 P2 RDB board configuration file - * This file is intended to address a set of Low End and Ultra Low End - * Freescale SOCs of QorIQ series(RDB platforms). - * Currently only P2020RDB - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifdef CONFIG_36BIT -#define CONFIG_PHYS_64BIT -#endif - -#ifdef CONFIG_P1011RDB -#define CONFIG_P1011 -#define CONFIG_SYS_L2_SIZE (256 << 10) -#endif -#ifdef CONFIG_P1020RDB -#define CONFIG_P1020 -#define CONFIG_SYS_L2_SIZE (256 << 10) -#endif -#ifdef CONFIG_P2010RDB -#define CONFIG_P2010 -#define CONFIG_SYS_L2_SIZE (512 << 10) -#endif -#ifdef CONFIG_P2020RDB -#define CONFIG_P2020 -#define CONFIG_SYS_L2_SIZE (512 << 10) -#endif - -#ifdef CONFIG_SDCARD -#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT -#define CONFIG_SPL_ENV_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_MMC_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SYS_TEXT_BASE 0x11001000 -#define CONFIG_SPL_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_SPL_MAX_SIZE (128 * 1024) -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (129 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" -#define CONFIG_SPL_MMC_BOOT -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_COMMON_INIT_DDR -#endif -#endif - -#ifdef CONFIG_SPIFLASH -#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT -#define CONFIG_SPL_ENV_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_SPI_SUPPORT -#define CONFIG_SPL_SPI_FLASH_SUPPORT -#define CONFIG_SPL_SPI_FLASH_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SYS_TEXT_BASE 0x11001000 -#define CONFIG_SPL_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_SPL_MAX_SIZE (128 * 1024) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" -#define CONFIG_SPL_SPI_BOOT -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_COMMON_INIT_DDR -#endif -#endif - -#ifdef CONFIG_NAND -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SPL_NAND_BOOT -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_ENV_SUPPORT -#define CONFIG_SPL_NAND_INIT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SPL_MAX_SIZE (128 << 10) -#define CONFIG_SPL_TEXT_BASE 0xf8f81000 -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) -#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) -#elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_TEXT_BASE 0xff800000 -#define CONFIG_SPL_MAX_SIZE 4096 -#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 -#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) -#endif /* not CONFIG_TPL_BUILD */ - -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_TPL_PAD_TO 0x20000 -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SYS_TEXT_BASE 0x11001000 -#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" -#endif - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff40000 -#endif - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#ifndef CONFIG_SYS_MONITOR_BASE -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif -#endif - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */ - -#define CONFIG_PCI 1 /* Enable PCI/PCIE */ -#if defined(CONFIG_PCI) -#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ -#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#endif /* #if defined(CONFIG_PCI) */ -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_PCI) -#define CONFIG_E1000 1 /* E1000 pci Ethernet card*/ -#endif - -#ifndef __ASSEMBLY__ -extern unsigned long get_board_sys_clk(unsigned long dummy); -#endif -#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1_P2 RDB */ -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for P1_P2 RDB */ - -#if defined(CONFIG_P2020) || defined(CONFIG_P1020) -#define CONFIG_MP -#endif - -#define CONFIG_HWCONFIG - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CONFIG_ENABLE_36BIT_PHYS 1 - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x1fffffff -#define CONFIG_PANIC_HANG /* do not reset board on panic */ - -/* - * Config the L2 Cache as L2 SRAM -*/ -#if defined(CONFIG_SPL_BUILD) -#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) -#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) -#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) -#if defined(CONFIG_P2020RDB) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) -#else -#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) -#endif -#elif defined(CONFIG_NAND) -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) -#else -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) -#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) -#endif /* CONFIG_TPL_BUILD */ -#endif -#endif - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR2 -#undef CONFIG_FSL_DDR_INTERACTIVE -#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#if defined(CONFIG_P1011RDB) || defined(CONFIG_P1020RDB) -/* - * P1020 and it's derivatives support max 32bit DDR width - * So Reduce available DDR size -*/ -#define CONFIG_SYS_SDRAM_SIZE 512 -#else -#define CONFIG_SYS_SDRAM_SIZE 1024 -#endif -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 - -#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d -#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 -#define CONFIG_SYS_DDR_SBE 0x00FF0000 - -/* - * Memory map - * - * 0x0000_0000 0x3fff_ffff DDR 1G cacheablen - * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable - * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable - * - * Localbus cacheable (TBD) - * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable - * - * Localbus non-cacheable - * 0xef00_0000 0xefff_ffff FLASH 16M non-cacheable - * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable - * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 - * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - */ - -/* - * Local Bus Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */ - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfef000000ull -#else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif - -#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - BR_PS_16 | BR_V) -#define CONFIG_FLASH_OR_PRELIM 0xff000ff7 - -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 - -#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ -#define CONFIG_MISC_INIT_R -#define CONFIG_HWCONFIG - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR -/* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS -#endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ - - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ - -#define CONFIG_SYS_NAND_BASE 0xff800000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif - -#define CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_NAND_FSL_ELBC 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) - -/* NAND flash config */ -#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | (2< - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_SETEXPR -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_NET -#define CONFIG_CMD_PCI -#endif - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_MMC 1 - -#ifdef CONFIG_MMC -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_CMD_MMC -#define CONFIG_DOS_PARTITION -#define CONFIG_FSL_ESDHC -#define CONFIG_GENERIC_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#ifdef CONFIG_P2020 -#define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/ -#endif -#endif - -#define CONFIG_HAS_FSL_DR_USB - -#if defined(CONFIG_HAS_FSL_DR_USB) -#define CONFIG_USB_EHCI - -#ifdef CONFIG_USB_EHCI -#define CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_EHCI_FSL -#define CONFIG_USB_STORAGE -#endif -#endif - -#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) - /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20)/* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#endif - -#define CONFIG_HOSTNAME P2020RDB -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "loadaddr=1000000\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=c00000\0" \ - "fdtfile=p2020rdb.dtb\0" \ - "bdev=sda1\0" \ - "jffs2nor=mtdblock3\0" \ - "norbootaddr=ef080000\0" \ - "norfdtaddr=ef040000\0" \ - "jffs2nand=mtdblock9\0" \ - "nandbootaddr=100000\0" \ - "nandfdtaddr=80000\0" \ - "nandimgsize=400000\0" \ - "nandfdtsize=80000\0" \ - "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ - "vscfw_addr=ef000000\0" \ - "othbootargs=ramdisk_size=600000\0" \ - "usbfatboot=setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "usb start;" \ - "fatload usb 0:2 $loadaddr $bootfile;" \ - "fatload usb 0:2 $fdtaddr $fdtfile;" \ - "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ - "usbext2boot=setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "usb start;" \ - "ext2load usb 0:4 $loadaddr $bootfile;" \ - "ext2load usb 0:4 $fdtaddr $fdtfile;" \ - "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ - "norboot=setenv bootargs root=/dev/$jffs2nor rw " \ - "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ - "bootm $norbootaddr - $norfdtaddr\0" \ - "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "nand read 2000000 $nandbootaddr $nandimgsize;" \ - "nand read 3000000 $nandfdtaddr $nandfdtsize;" \ - "bootm 2000000 - 3000000;\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "usb start;" \ - "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ - "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT - -#endif /* __CONFIG_H */ -- cgit From 891235366d9949b4b21653e93b97dd8931314153 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 23 Jan 2015 00:24:17 +0900 Subject: powerpc: mpc85xx: remove P2020COME board support This board is still a non-generic board. Signed-off-by: Masahiro Yamada Cc: Ira W. Snyder --- include/configs/P2020COME.h | 547 -------------------------------------------- 1 file changed, 547 deletions(-) delete mode 100644 include/configs/P2020COME.h (limited to 'include') diff --git a/include/configs/P2020COME.h b/include/configs/P2020COME.h deleted file mode 100644 index d414b84dd2..0000000000 --- a/include/configs/P2020COME.h +++ /dev/null @@ -1,547 +0,0 @@ -/* - * Copyright 2009-2010,2012 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* The P2020COME board is only booted via the Freescale On-Chip ROM */ -#define CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_EXTRA_ENV_RELOC - -#define CONFIG_SYS_TEXT_BASE 0xf8f80000 -#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc - -#ifdef CONFIG_SDCARD -#define CONFIG_RAMBOOT_SDCARD 1 -#endif - -#ifdef CONFIG_SPIFLASH -#define CONFIG_RAMBOOT_SPIFLASH 1 -#endif - -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_P2020 1 -#define CONFIG_P2020COME 1 -#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */ -#define CONFIG_MP - -#define CONFIG_PCI 1 /* Enable PCI/PCIE */ -#if defined(CONFIG_PCI) -#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ -#define CONFIG_PCIE3 1 /* PCIE controller 3 (slot 3) */ - -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#endif /* #if defined(CONFIG_PCI) */ -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_PCI) -#define CONFIG_E1000 1 /* E1000 pci Ethernet card */ -#endif - -#ifndef __ASSEMBLY__ -extern unsigned long get_board_ddr_clk(unsigned long dummy); -extern unsigned long get_board_sys_clk(unsigned long dummy); -#endif - -/* - * For P2020COME DDRCLK and SYSCLK are from the same oscillator - * For DA phase the SYSCLK is 66MHz - * For EA phase the SYSCLK is 100MHz - */ -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) - -#define CONFIG_HWCONFIG - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch prediction */ - -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CONFIG_ENABLE_36BIT_PHYS 1 - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x1fffffff -#define CONFIG_PANIC_HANG /* do not reset board on panic */ - - /* - * Config the L2 Cache as L2 SRAM - */ -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull -#else -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#endif -#define CONFIG_SYS_L2_SIZE (512 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR \ - + CONFIG_SYS_L2_SIZE) - -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR3 -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#define CONFIG_DDR_SPD - -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef - -#define CONFIG_SYS_SDRAM_SIZE 2048ULL /* DDR size on P2020COME */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 - -#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d -#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 -#define CONFIG_SYS_DDR_SBE 0x00ff0000 - -#define CONFIG_SYS_SPD_BUS_NUM 1 -#define SPD_EEPROM_ADDRESS 0x53 - -/* - * Memory map - * - * 0x0000_0000 0x7fff_ffff DDR3 2G Cacheable - * 0x8000_0000 0x9fff_ffff PCI Express 3 Mem 1G non-cacheable - * 0xa000_0000 0xbfff_ffff PCI Express 2 Mem 1G non-cacheable - * 0xc000_0000 0xdfff_ffff PCI Express 1 Mem 1G non-cacheable - * 0xffc1_0000 0xffc1_ffff PCI Express 3 IO 64K non-cacheable - * 0xffc2_0000 0xffc2_ffff PCI Express 2 IO 64K non-cacheable - * 0xffc3_0000 0xffc3_ffff PCI Express 1 IO 64K non-cacheable - * - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 - * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - */ - -/* - * Local Bus Definitions - */ - -/* There is no NOR Flash on P2020COME */ -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ -#define CONFIG_HWCONFIG - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR -/* the assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS -#endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ - - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) - -/* Serial Port - controlled on board with jumper J8 - * open - index 2 - * shorted - index 1 - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER - -/* - * Pass open firmware flat tree - */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -/* new uImage format support */ -#define CONFIG_FIT 1 -#define CONFIG_FIT_VERBOSE 1 - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } - -/* - * I2C2 EEPROM - */ -#define CONFIG_ID_EEPROM -#ifdef CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#endif -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR2 0x18 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * eSPI - Enhanced SPI - */ -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_CMD_SF -#define CONFIG_SF_DEFAULT_SPEED 10000000 -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#if defined(CONFIG_PCI) - -/* controller 3, Slot 3, tgtid 3, Base address 8000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc10000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc10000 -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ - -/* controller 2, Slot 2, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ - -/* controller 1, Slot 1, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP -#undef CONFIG_RTL8139 - -#ifdef CONFIG_RTL8139 -/* This macro is used by RTL8139 but not defined in PPC architecture */ -#define KSEG1ADDR(x) (x) -#define _IO_BASE 0x00000000 -#endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_DOS_PARTITION - -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC3" - -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 2 -#define TSEC3_PHY_ADDR 1 - -#undef CONFIG_VSC7385_ENET - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC1" - -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#if defined(CONFIG_RAMBOOT_SDCARD) - #define CONFIG_ENV_IS_IN_MMC 1 - #define CONFIG_FSL_FIXED_MMC_LOCATION - #define CONFIG_ENV_SIZE 0x2000 - #define CONFIG_SYS_MMC_ENV_DEV 0 -#elif defined(CONFIG_RAMBOOT_SPIFLASH) - #define CONFIG_ENV_IS_IN_SPI_FLASH - #define CONFIG_ENV_SPI_BUS 0 - #define CONFIG_ENV_SPI_CS 0 - #define CONFIG_ENV_SPI_MAX_HZ 10000000 - #define CONFIG_ENV_SPI_MODE 0 - #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ - #define CONFIG_ENV_SECT_SIZE 0x10000 - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_SETEXPR -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_NET -#define CONFIG_CMD_PCI -#endif - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_MMC 1 - -#ifdef CONFIG_MMC -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_CMD_MMC -#define CONFIG_DOS_PARTITION -#define CONFIG_FSL_ESDHC -#define CONFIG_GENERIC_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT -#endif /* CONFIG_MMC */ - -#define CONFIG_HAS_FSL_DR_USB -#ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI - -#ifdef CONFIG_USB_EHCI -#define CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_EHCI_FSL -#define CONFIG_USB_STORAGE -#endif -#endif - -#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION -#endif - -/* Misc Extra Settings */ -#define CONFIG_CMD_DHCP 1 - -#define CONFIG_CMD_DATE 1 -#define CONFIG_RTC_M41T62 1 -#define CONFIG_SYS_RTC_BUS_NUM 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) - /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) -#define CONFIG_SYS_BOOTM_LEN (64 << 20) - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#endif - -#define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ecc=on\0" \ - "bootcmd=run sdboot\0" \ - "sdboot=setenv bootargs root=/dev/mmcblk0p2 rw " \ - "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\ - "$othbootargs; mmcinfo; " \ - "ext2load mmc 0:2 $loadaddr /boot/$bootfile; " \ - "ext2load mmc 0:2 $fdtaddr /boot/$fdtfile; " \ - "bootm $loadaddr - $fdtaddr\0" \ - "sdfatboot=setenv bootargs root=/dev/ram rw " \ - "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\ - "$othbootargs; mmcinfo; " \ - "fatload mmc 0:1 $loadaddr $bootfile; " \ - "fatload mmc 0:1 $fdtaddr $fdtfile; " \ - "fatload mmc 0:1 $ramdiskaddr $ramdiskfile; " \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ - "usbboot=setenv bootargs root=/dev/sda1 rw " \ - "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\ - "$othbootargs; " \ - "usb start; " \ - "ext2load usb 0:1 $loadaddr /boot/$bootfile; " \ - "ext2load usb 0:1 $fdtaddr /boot/$fdtfile; " \ - "bootm $loadaddr - $fdtaddr\0" \ - "usbfatboot=setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "usb start; " \ - "fatload usb 0:2 $loadaddr $bootfile; " \ - "fatload usb 0:2 $fdtaddr $fdtfile; " \ - "fatload usb 0:2 $ramdiskaddr $ramdiskfile; " \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ - "usbext2boot=setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "usb start; " \ - "ext2load usb 0:4 $loadaddr $bootfile; " \ - "ext2load usb 0:4 $fdtaddr $fdtfile; " \ - "ext2load usb 0:4 $ramdiskaddr $ramdiskfile; " \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ - "upgradespi=sf probe 0; " \ - "setenv startaddr 0; " \ - "setenv erasesize a0000; " \ - "tftp 1000000 $tftppath/$uboot_spi; " \ - "sf erase $startaddr $erasesize; " \ - "sf write 1000000 $startaddr $filesize; " \ - "sf erase 100000 120000\0" \ - "clearspienv=sf probe 0;sf erase 100000 20000\0" \ - "othbootargs=ramdisk_size=700000 cache-sram-size=0x10000\0" \ - "netdev=eth0\0" \ - "rootdelaysecond=15\0" \ - "uboot_nor=u-boot-nor.bin\0" \ - "uboot_spi=u-boot-p2020.spi\0" \ - "uboot_sd=u-boot-p2020.bin\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=rootfs-dev.ext2.img\0" \ - "fdtaddr=c00000\0" \ - "fdtfile=uImage-2.6.32-p2020.dtb\0" \ - "tftppath=p2020\0" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "usb start;" \ - "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ - "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $tftppath/$bootfile;" \ - "tftp $fdtaddr $tftppath/$fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $tftppath/$ramdiskfile;" \ - "tftp $loadaddr $tftppath/$bootfile;" \ - "tftp $fdtaddr $tftppath/$fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT - -#endif /* __CONFIG_H */ -- cgit From 168dcc6cef7a0e13bc52fc8fa8de2866cf4033dc Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 23 Jan 2015 00:24:18 +0900 Subject: powerpc: mpc85xx: remove P2020DS board support This board is still a non-generic board. Signed-off-by: Masahiro Yamada --- include/configs/P2020DS.h | 751 ---------------------------------------------- 1 file changed, 751 deletions(-) delete mode 100644 include/configs/P2020DS.h (limited to 'include') diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h deleted file mode 100644 index 820b6332a6..0000000000 --- a/include/configs/P2020DS.h +++ /dev/null @@ -1,751 +0,0 @@ -/* - * Copyright 2007-2012 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * p2020ds board configuration file - * - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "../board/freescale/common/ics307_clk.h" - -#ifdef CONFIG_36BIT -#define CONFIG_PHYS_64BIT -#endif - -#ifdef CONFIG_SDCARD -#define CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_SYS_TEXT_BASE 0xf8f40000 -#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc -#endif - -#ifdef CONFIG_SPIFLASH -#define CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_SYS_TEXT_BASE 0xf8f40000 -#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc -#endif - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_P2020 1 -#define CONFIG_P2020DS 1 -#define CONFIG_MP 1 /* support multiple processors */ - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff40000 -#endif - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ - -#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ -#define CONFIG_PCI 1 /* Enable PCI/PCIE */ -#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ -#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ -#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ - -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ - -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ -#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ - -#define CONFIG_ENABLE_36BIT_PHYS 1 - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - -#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 -#define CONFIG_PANIC_HANG /* do not reset board on panic */ - -/* - * Config the L2 Cache - */ -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull -#else -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#endif -#define CONFIG_SYS_L2_SIZE (512 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) - -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ -#define CONFIG_VERY_BIG_RAM -#ifdef CONFIG_DDR2 -#define CONFIG_SYS_FSL_DDR2 -#else -#define CONFIG_SYS_FSL_DDR3 1 -#endif - -/* ECC will be enabled based on perf_mode environment variable */ -/* #define CONFIG_DDR_ECC */ - -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 - -/* I2C addresses of SPD EEPROMs */ -#define CONFIG_DDR_SPD -#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */ -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ - -/* These are used when DDR doesn't use SPD. */ -#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */ - -/* Default settings for "stable" mode */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F -#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 -#define CONFIG_SYS_DDR_TIMING_3 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0 0x00330804 -#define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846 -#define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4 -#define CONFIG_SYS_DDR_MODE_1 0x00421422 -#define CONFIG_SYS_DDR_MODE_2 0x00000000 -#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL 0x61800100 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_CLK_CTRL 0x02000000 -#define CONFIG_SYS_DDR_TIMING_4 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5 0x03402400 -#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608 -#define CONFIG_SYS_DDR_CONTROL 0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */ -#define CONFIG_SYS_DDR_CONTROL2 0x24400011 -#define CONFIG_SYS_DDR_CDR1 0x00040000 -#define CONFIG_SYS_DDR_CDR2 0x00000000 - -#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d -#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 -#define CONFIG_SYS_DDR_SBE 0x00010000 - -/* Settings that differ for "performance" mode */ -#define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */ -#define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */ -#define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202 -#define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543 -#define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce -#define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */ - -/* - * The following set of values were tested for DDR2 - * with a DDR3 to DDR2 interposer - * -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1 0x3935d322 -#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 -#define CONFIG_SYS_DDR_MODE_1 0x00480432 -#define CONFIG_SYS_DDR_MODE_2 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL 0x06180100 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 -#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 -#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xC3008000 -#define CONFIG_SYS_DDR_CONTROL2 0x04400010 - * - */ - -/* - * Memory map - * - * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable - * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable - * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable - * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable - * - * Localbus cacheable (TBD) - * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable - * - * Localbus non-cacheable - * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable - * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable - * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable - * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 - * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - */ - -/* - * Local Bus Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull -#else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif - -#define CONFIG_FLASH_BR_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) -#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 - -#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 - -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 - -#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ - -#define CONFIG_HWCONFIG /* enable hwconfig */ -#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ - -#ifdef CONFIG_FSL_NGPIXIS -#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ -#ifdef CONFIG_PHYS_64BIT -#define PIXIS_BASE_PHYS 0xfffdf0000ull -#else -#define PIXIS_BASE_PHYS PIXIS_BASE -#endif - -#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ - -#define PIXIS_LBMAP_SWITCH 7 -#define PIXIS_LBMAP_MASK 0xf0 -#define PIXIS_LBMAP_SHIFT 4 -#define PIXIS_LBMAP_ALTBANK 0x20 -#endif - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR -/* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS -#endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ - -#define CONFIG_SYS_NAND_BASE 0xffa00000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ - CONFIG_SYS_NAND_BASE + 0x40000, \ - CONFIG_SYS_NAND_BASE + 0x80000,\ - CONFIG_SYS_NAND_BASE + 0xC0000} -#define CONFIG_SYS_MAX_NAND_DEVICE 4 -#define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_CMD_NAND 1 -#define CONFIG_NAND_FSL_ELBC 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -/* NAND flash config */ -#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | (2< - -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_SETEXPR -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_PCI -#define CONFIG_CMD_NET -#define CONFIG_CMD_SCSI -#define CONFIG_CMD_EXT2 -#endif - -/* - * USB - */ -#define CONFIG_HAS_FSL_DR_USB -#ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI - -#ifdef CONFIG_USB_EHCI -#define CONFIG_CMD_USB -#define CONFIG_USB_STORAGE -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif -#endif - -/* - * SDHC/MMC - */ -#define CONFIG_MMC - -#ifdef CONFIG_MMC -#define CONFIG_FSL_ESDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_CMD_MMC -#define CONFIG_GENERIC_MMC -#endif - -#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#endif - -#define CONFIG_IPADDR 192.168.1.254 - -#define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"perf_mode=performance\0" \ - "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \ - "usb1:dr_mode=host,phy_type=ulpi\0" \ -"netdev=eth0\0" \ -"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ -"tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ -"satabootcmd=setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" \ -"consoledev=ttyS0\0" \ -"ramdiskaddr=2000000\0" \ -"ramdiskfile=p2020ds/ramdisk.uboot\0" \ -"fdtaddr=c00000\0" \ -"othbootargs=cache-sram-size=0x10000\0" \ -"fdtfile=p2020ds/p2020ds.dtb\0" \ -"bdev=sda3\0" \ -"partition=scsi 0:0\0" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "ext2load $partition $loadaddr $bootfile;" \ - "ext2load $partition $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT - -#endif /* __CONFIG_H */ -- cgit From 5344cc1a82fcc2817d4671696b3939b0dfa4323e Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 23 Jan 2015 00:24:19 +0900 Subject: powerpc: ppc4xx: remove PPChameleonEVB, CATcenter boards These boards are still non-generic boards. It is a good thing that we can drop board-specific hack code from drivers/mtd/nand/nand_base.c Signed-off-by: Masahiro Yamada Acked-by: Stefan Roese Cc: Andrea "llandre" Marson --- include/configs/CATcenter.h | 750 ------------------------------------- include/configs/PPChameleonEVB.h | 777 --------------------------------------- 2 files changed, 1527 deletions(-) delete mode 100644 include/configs/CATcenter.h delete mode 100644 include/configs/PPChameleonEVB.h (limited to 'include') diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h deleted file mode 100644 index 27539d27d7..0000000000 --- a/include/configs/CATcenter.h +++ /dev/null @@ -1,750 +0,0 @@ -/* - * ueberarbeitet durch Christoph Seyfert - * - * (C) Copyright 2004-2005 DENX Software Engineering, - * Wolfgang Grandegger - * (C) Copyright 2003 - * DAVE Srl - * - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * Credits: Stefan Roese, Wolfgang Denk - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */ -#define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */ -#define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */ -#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL -#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA -#endif - -/* Only one of the following two symbols must be defined (default is 25 MHz) - * CONFIG_PPCHAMELEON_CLK_25 - * CONFIG_PPCHAMELEON_CLK_33 - */ -#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33)) -#define CONFIG_PPCHAMELEON_CLK_25 -#endif - -#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33)) -#error "* Two external frequencies (SysClk) are defined! *" -#endif - -#undef CONFIG_PPCHAMELEON_SMI712 - -/* - * Debug stuff - */ -#undef __DEBUG_START_FROM_SRAM__ -#define __DISABLE_MACHINE_EXCEPTION__ - -#ifdef __DEBUG_START_FROM_SRAM__ -#define CONFIG_SYS_DUMMY_FLASH_SIZE 1024*1024*4 -#endif - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFB0000 /* Reserve 320 kB for Monitor */ -#define CONFIG_SYS_LDSCRIPT "board/dave/PPChameleonEVB/u-boot.lds" - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#ifdef CONFIG_PPCHAMELEON_CLK_25 -# define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ -#elif (defined (CONFIG_PPCHAMELEON_CLK_33)) -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ -#else -# error "* External frequency (SysClk) not defined! *" -#endif - -#define CONFIG_CONS_INDEX 2 /* Use UART1 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_VERSION_VARIABLE 1 /* add version variable */ -#define CONFIG_IDENT_STRING "1" - -#undef CONFIG_BOOTARGS - -/* Ethernet stuff */ -#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */ -#define CONFIG_ETHADDR 00:50:C2:1E:AF:FE -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - - -#define CONFIG_PPC4xx_EMAC -#undef CONFIG_EXT_PHY - -#define CONFIG_MII 1 /* MII PHY management */ -#ifndef CONFIG_EXT_PHY -#define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */ -#define CONFIG_PHY1_ADDR 16 /* EMAC1 PHY address */ -#else -#define CONFIG_PHY_ADDR 2 /* PHY address */ -#endif -#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_NAND -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ -#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_NAND0_BASE 0xFF400000 -#define CONFIG_SYS_NAND1_BASE 0xFF000000 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE } -#define NAND_BIG_DELAY_US 25 - -/* For CATcenter there is only NAND on the module */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_NO_RB - -#define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define CONFIG_SYS_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */ -#define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */ -#define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */ -#define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */ - - -#define MACRO_NAND_DISABLE_CE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CONFIG_SYS_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \ - break; \ - case CONFIG_SYS_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \ - break; \ - } \ -} while(0) - -#define MACRO_NAND_ENABLE_CE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CONFIG_SYS_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \ - break; \ - case CONFIG_SYS_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \ - break; \ - } \ -} while(0) - -#define MACRO_NAND_CTL_CLRALE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CONFIG_SYS_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \ - break; \ - case CONFIG_SYS_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \ - break; \ - } \ -} while(0) - -#define MACRO_NAND_CTL_SETALE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CONFIG_SYS_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \ - break; \ - case CONFIG_SYS_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \ - break; \ - } \ -} while(0) - -#define MACRO_NAND_CTL_CLRCLE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CONFIG_SYS_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \ - break; \ - case CONFIG_SYS_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \ - break; \ - } \ -} while(0) - -#define MACRO_NAND_CTL_SETCLE(nandptr) do { \ - switch((unsigned long)nandptr) { \ - case CONFIG_SYS_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \ - break; \ - case CONFIG_SYS_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \ - break; \ - } \ -} while(0) - -#ifdef NAND_NO_RB -/* constant delay (see also tR in the datasheet) */ -#define NAND_WAIT_READY(nand) do { \ - udelay(12); \ -} while (0) -#else -/* use the R/B pin */ -/* TBD */ -#endif - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#if 0 /* No PCI on CATcenter */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#undef CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ - -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ -#endif /* No PCI */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CONFIG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */ -#define CONFIG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/ -#define CONFIG_ENV_ADDR_REDUND 0xFFFFA000 -#define CONFIG_ENV_SIZE_REDUND 0x2000 - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07*/ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (External SRAM) initialization */ -/* Since this must replace NOR Flash, we use the same settings for CS0 */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x92015480 -#define CONFIG_SYS_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x92015480 -#define CONFIG_SYS_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */ - -#ifdef CONFIG_PPCHAMELEON_SMI712 -/* - * Video console (graphic: SMI LynxEM) - */ -#define CONFIG_VIDEO -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_SMI_LYNXEM -#define CONFIG_VIDEO_LOGO -/*#define CONFIG_VIDEO_BMP_LOGO*/ -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VGA_AS_SINGLE_DEVICE -/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */ -#define CONFIG_SYS_ISA_IO 0xE8000000 -/* see also drivers/video/videomodes.c */ -#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303 -#endif - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -/* FPGA internal regs */ -#define CONFIG_SYS_FPGA_MODE 0x00 -#define CONFIG_SYS_FPGA_STATUS 0x02 -#define CONFIG_SYS_FPGA_TS 0x04 -#define CONFIG_SYS_FPGA_TS_LOW 0x06 -#define CONFIG_SYS_FPGA_TS_CAP0 0x10 -#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12 -#define CONFIG_SYS_FPGA_TS_CAP1 0x14 -#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16 -#define CONFIG_SYS_FPGA_TS_CAP2 0x18 -#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a -#define CONFIG_SYS_FPGA_TS_CAP3 0x1c -#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e - -/* FPGA Mode Reg */ -#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001 -#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100 -#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000 -#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000 - -/* FPGA Status Reg */ -#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001 -#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002 -#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004 -#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008 -#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000 - -#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ - -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs -> GPIO - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30] - EMAC0 input - * GPIO0[31] - EMAC1 reject packet as output - */ -#define CONFIG_SYS_GPIO0_OSRL 0x40000550 -#define CONFIG_SYS_GPIO0_OSRH 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 -/*#define CONFIG_SYS_GPIO0_ISR1H 0x15555445*/ -#define CONFIG_SYS_GPIO0_ISR1H 0x15555444 -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 -#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014 - -#define CONFIG_NO_SERIAL_EEPROM - -/*--------------------------------------------------------------------*/ - -#ifdef CONFIG_NO_SERIAL_EEPROM - -/* -!----------------------------------------------------------------------- -! Defines for entry options. -! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that -! are plugged in the board will be utilized as non-ECC DIMMs. -!----------------------------------------------------------------------- -*/ -#undef AUTO_MEMORY_CONFIG -#define DIMM_READ_ADDR 0xAB -#define DIMM_WRITE_ADDR 0xAA - -/* Defines for CPC0_PLLMR1 Register fields */ -#define PLL_ACTIVE 0x80000000 -#define CPC0_PLLMR1_SSCS 0x80000000 -#define PLL_RESET 0x40000000 -#define CPC0_PLLMR1_PLLR 0x40000000 - /* Feedback multiplier */ -#define PLL_FBKDIV 0x00F00000 -#define CPC0_PLLMR1_FBDV 0x00F00000 -#define PLL_FBKDIV_16 0x00000000 -#define PLL_FBKDIV_1 0x00100000 -#define PLL_FBKDIV_2 0x00200000 -#define PLL_FBKDIV_3 0x00300000 -#define PLL_FBKDIV_4 0x00400000 -#define PLL_FBKDIV_5 0x00500000 -#define PLL_FBKDIV_6 0x00600000 -#define PLL_FBKDIV_7 0x00700000 -#define PLL_FBKDIV_8 0x00800000 -#define PLL_FBKDIV_9 0x00900000 -#define PLL_FBKDIV_10 0x00A00000 -#define PLL_FBKDIV_11 0x00B00000 -#define PLL_FBKDIV_12 0x00C00000 -#define PLL_FBKDIV_13 0x00D00000 -#define PLL_FBKDIV_14 0x00E00000 -#define PLL_FBKDIV_15 0x00F00000 - /* Forward A divisor */ -#define PLL_FWDDIVA 0x00070000 -#define CPC0_PLLMR1_FWDVA 0x00070000 -#define PLL_FWDDIVA_8 0x00000000 -#define PLL_FWDDIVA_7 0x00010000 -#define PLL_FWDDIVA_6 0x00020000 -#define PLL_FWDDIVA_5 0x00030000 -#define PLL_FWDDIVA_4 0x00040000 -#define PLL_FWDDIVA_3 0x00050000 -#define PLL_FWDDIVA_2 0x00060000 -#define PLL_FWDDIVA_1 0x00070000 - /* Forward B divisor */ -#define PLL_FWDDIVB 0x00007000 -#define CPC0_PLLMR1_FWDVB 0x00007000 -#define PLL_FWDDIVB_8 0x00000000 -#define PLL_FWDDIVB_7 0x00001000 -#define PLL_FWDDIVB_6 0x00002000 -#define PLL_FWDDIVB_5 0x00003000 -#define PLL_FWDDIVB_4 0x00004000 -#define PLL_FWDDIVB_3 0x00005000 -#define PLL_FWDDIVB_2 0x00006000 -#define PLL_FWDDIVB_1 0x00007000 - /* PLL tune bits */ -#define PLL_TUNE_MASK 0x000003FF -#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ -#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ -#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ -#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ -#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ -#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ -#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ - -/* Defines for CPC0_PLLMR0 Register fields */ - /* CPU divisor */ -#define PLL_CPUDIV 0x00300000 -#define CPC0_PLLMR0_CCDV 0x00300000 -#define PLL_CPUDIV_1 0x00000000 -#define PLL_CPUDIV_2 0x00100000 -#define PLL_CPUDIV_3 0x00200000 -#define PLL_CPUDIV_4 0x00300000 - /* PLB divisor */ -#define PLL_PLBDIV 0x00030000 -#define CPC0_PLLMR0_CBDV 0x00030000 -#define PLL_PLBDIV_1 0x00000000 -#define PLL_PLBDIV_2 0x00010000 -#define PLL_PLBDIV_3 0x00020000 -#define PLL_PLBDIV_4 0x00030000 - /* OPB divisor */ -#define PLL_OPBDIV 0x00003000 -#define CPC0_PLLMR0_OPDV 0x00003000 -#define PLL_OPBDIV_1 0x00000000 -#define PLL_OPBDIV_2 0x00001000 -#define PLL_OPBDIV_3 0x00002000 -#define PLL_OPBDIV_4 0x00003000 - /* EBC divisor */ -#define PLL_EXTBUSDIV 0x00000300 -#define CPC0_PLLMR0_EPDV 0x00000300 -#define PLL_EXTBUSDIV_2 0x00000000 -#define PLL_EXTBUSDIV_3 0x00000100 -#define PLL_EXTBUSDIV_4 0x00000200 -#define PLL_EXTBUSDIV_5 0x00000300 - /* MAL divisor */ -#define PLL_MALDIV 0x00000030 -#define CPC0_PLLMR0_MPDV 0x00000030 -#define PLL_MALDIV_1 0x00000000 -#define PLL_MALDIV_2 0x00000010 -#define PLL_MALDIV_3 0x00000020 -#define PLL_MALDIV_4 0x00000030 - /* PCI divisor */ -#define PLL_PCIDIV 0x00000003 -#define CPC0_PLLMR0_PPFD 0x00000003 -#define PLL_PCIDIV_1 0x00000000 -#define PLL_PCIDIV_2 0x00000001 -#define PLL_PCIDIV_3 0x00000002 -#define PLL_PCIDIV_4 0x00000003 - -#ifdef CONFIG_PPCHAMELEON_CLK_25 -/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */ -#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_2) -#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) - -#elif (defined (CONFIG_PPCHAMELEON_CLK_33)) - -/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */ -#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \ - PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ - PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_2) -#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) - -#else -#error "* External frequency (SysClk) not defined! *" -#endif - -#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI) -/* Model HI */ -#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55 -#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55 -#define CONFIG_SYS_OPB_FREQ 55555555 -/* Model ME */ -#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) -#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33 -#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33 -#define CONFIG_SYS_OPB_FREQ 66666666 -#else -/* Model BA (default) */ -#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33 -#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33 -#define CONFIG_SYS_OPB_FREQ 66666666 -#endif - -#endif /* CONFIG_NO_SERIAL_EEPROM */ - -#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ -#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */ - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nand" -#define CONFIG_JFFS2_PART_SIZE 0x00200000 -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support - * - * Note: fake mtd_id used, no linux mtd map file - */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nand0=catcenter" -#define MTDPARTS_DEFAULT "mtdparts=catcenter:2m(nand)" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h deleted file mode 100644 index e277d0d933..0000000000 --- a/include/configs/PPChameleonEVB.h +++ /dev/null @@ -1,777 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, - * - * (C) Copyright 2003 - * DAVE Srl - * - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * Credits: Stefan Roese, Wolfgang Denk - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */ -#define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */ -#define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */ -#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL -#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA -#endif - - -/* Only one of the following two symbols must be defined (default is 25 MHz) - * CONFIG_PPCHAMELEON_CLK_25 - * CONFIG_PPCHAMELEON_CLK_33 - */ -#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33)) -#define CONFIG_PPCHAMELEON_CLK_25 -#endif - -#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33)) -#error "* Two external frequencies (SysClk) are defined! *" -#endif - -#undef CONFIG_PPCHAMELEON_SMI712 - -/* - * Debug stuff - */ -#undef __DEBUG_START_FROM_SRAM__ -#define __DISABLE_MACHINE_EXCEPTION__ - -#ifdef __DEBUG_START_FROM_SRAM__ -#define CONFIG_SYS_DUMMY_FLASH_SIZE 1024*1024*4 -#endif - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFB0000 /* Reserve 320 kB for Monitor */ -#define CONFIG_SYS_LDSCRIPT "board/dave/PPChameleonEVB/u-boot.lds" - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - - -#ifdef CONFIG_PPCHAMELEON_CLK_25 -# define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ -#elif (defined (CONFIG_PPCHAMELEON_CLK_33)) -# define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ -#else -# error "* External frequency (SysClk) not defined! *" -#endif - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#undef CONFIG_BOOTARGS - -/* Ethernet stuff */ -#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */ -#define CONFIG_ETHADDR 00:50:c2:1e:af:fe -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#undef CONFIG_EXT_PHY - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#ifndef CONFIG_EXT_PHY -#define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */ -#define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */ -#else -#define CONFIG_PHY_ADDR 2 /* PHY address */ -#endif -#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_NAND -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SNTP - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_M41T11 1 /* uses a M41T00 RTC */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_M41T11_BASE_YEAR 1900 - -/* - * SDRAM configuration (please see cpu/ppc/sdram.[ch]) - */ -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* SDRAM timings used in datasheet */ -#define CONFIG_SYS_SDRAM_CL 2 -#define CONFIG_SYS_SDRAM_tRP 20 -#define CONFIG_SYS_SDRAM_tRC 65 -#define CONFIG_SYS_SDRAM_tRCD 20 -#undef CONFIG_SYS_SDRAM_tRFC - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ - -/* - * nand device 1 on dave (PPChameleonEVB) needs more time, - * so we just introduce additional wait in nand_wait(), - * effectively for both devices. - */ -#define PPCHAMELON_NAND_TIMER_HACK - -#define CONFIG_SYS_NAND0_BASE 0xFF400000 -#define CONFIG_SYS_NAND1_BASE 0xFF000000 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, CONFIG_SYS_NAND1_BASE } -#define NAND_BIG_DELAY_US 25 -#define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ - -#define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ -#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ - -#define CONFIG_SYS_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */ -#define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */ -#define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */ -#define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */ - -#define MACRO_NAND_DISABLE_CE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CONFIG_SYS_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \ - break; \ - case CONFIG_SYS_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \ - break; \ - } \ -} while(0) - -#define MACRO_NAND_ENABLE_CE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CONFIG_SYS_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \ - break; \ - case CONFIG_SYS_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \ - break; \ - } \ -} while(0) - -#define MACRO_NAND_CTL_CLRALE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CONFIG_SYS_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \ - break; \ - case CONFIG_SYS_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \ - break; \ - } \ -} while(0) - -#define MACRO_NAND_CTL_SETALE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CONFIG_SYS_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \ - break; \ - case CONFIG_SYS_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \ - break; \ - } \ -} while(0) - -#define MACRO_NAND_CTL_CLRCLE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CONFIG_SYS_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \ - break; \ - case CONFIG_SYS_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \ - break; \ - } \ -} while(0) - -#define MACRO_NAND_CTL_SETCLE(nandptr) do { \ - switch((unsigned long)nandptr) { \ - case CONFIG_SYS_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \ - break; \ - case CONFIG_SYS_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \ - break; \ - } \ -} while(0) - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#undef CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ - -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* Reserve 256 kB for Monitor */ -/* -#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -*/ - -/* Reserve 320 kB for Monitor */ -#define CONFIG_SYS_FLASH_BASE 0xFFFB0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (320 * 1024) - -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#ifdef ENVIRONMENT_IN_EEPROM - -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x700 /* 2048-256 bytes may be used for env vars (total size of a CAT24WC16 is 2048 bytes)*/ - -#else /* DEFAULT: environment in flash, using redundand flash sectors */ - -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CONFIG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */ -#define CONFIG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/ -#define CONFIG_ENV_ADDR_REDUND 0xFFFFA000 -#define CONFIG_ENV_SIZE_REDUND 0x2000 - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#endif /* ENVIRONMENT_IN_EEPROM */ - - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07*/ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (External SRAM) initialization */ -/* Since this must replace NOR Flash, we use the same settings for CS0 */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x92015480 -#define CONFIG_SYS_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x92015480 -#define CONFIG_SYS_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */ - -#ifdef CONFIG_PPCHAMELEON_SMI712 -/* - * Video console (graphic: SMI LynxEM) - */ -#define CONFIG_VIDEO -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_SMI_LYNXEM -#define CONFIG_VIDEO_LOGO -/*#define CONFIG_VIDEO_BMP_LOGO*/ -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VGA_AS_SINGLE_DEVICE -/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */ -#define CONFIG_SYS_ISA_IO 0xE8000000 -/* see also drivers/video/videomodes.c */ -#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303 -#endif - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -/* FPGA internal regs */ -#define CONFIG_SYS_FPGA_MODE 0x00 -#define CONFIG_SYS_FPGA_STATUS 0x02 -#define CONFIG_SYS_FPGA_TS 0x04 -#define CONFIG_SYS_FPGA_TS_LOW 0x06 -#define CONFIG_SYS_FPGA_TS_CAP0 0x10 -#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12 -#define CONFIG_SYS_FPGA_TS_CAP1 0x14 -#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16 -#define CONFIG_SYS_FPGA_TS_CAP2 0x18 -#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a -#define CONFIG_SYS_FPGA_TS_CAP3 0x1c -#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e - -/* FPGA Mode Reg */ -#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001 -#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100 -#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000 -#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000 - -/* FPGA Status Reg */ -#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001 -#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002 -#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004 -#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008 -#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000 - -#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ - -/* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs -> GPIO - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30] - EMAC0 input - * GPIO0[31] - EMAC1 reject packet as output - */ -#define CONFIG_SYS_GPIO0_OSRL 0x40000550 -#define CONFIG_SYS_GPIO0_OSRH 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 -/*#define CONFIG_SYS_GPIO0_ISR1H 0x15555445*/ -#define CONFIG_SYS_GPIO0_ISR1H 0x15555444 -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 -#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014 - -#define CONFIG_NO_SERIAL_EEPROM - -/*--------------------------------------------------------------------*/ - -#ifdef CONFIG_NO_SERIAL_EEPROM - -/* -!----------------------------------------------------------------------- -! Defines for entry options. -! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that -! are plugged in the board will be utilized as non-ECC DIMMs. -!----------------------------------------------------------------------- -*/ -#undef AUTO_MEMORY_CONFIG -#define DIMM_READ_ADDR 0xAB -#define DIMM_WRITE_ADDR 0xAA - -/* Defines for CPC0_PLLMR1 Register fields */ -#define PLL_ACTIVE 0x80000000 -#define CPC0_PLLMR1_SSCS 0x80000000 -#define PLL_RESET 0x40000000 -#define CPC0_PLLMR1_PLLR 0x40000000 - /* Feedback multiplier */ -#define PLL_FBKDIV 0x00F00000 -#define CPC0_PLLMR1_FBDV 0x00F00000 -#define PLL_FBKDIV_16 0x00000000 -#define PLL_FBKDIV_1 0x00100000 -#define PLL_FBKDIV_2 0x00200000 -#define PLL_FBKDIV_3 0x00300000 -#define PLL_FBKDIV_4 0x00400000 -#define PLL_FBKDIV_5 0x00500000 -#define PLL_FBKDIV_6 0x00600000 -#define PLL_FBKDIV_7 0x00700000 -#define PLL_FBKDIV_8 0x00800000 -#define PLL_FBKDIV_9 0x00900000 -#define PLL_FBKDIV_10 0x00A00000 -#define PLL_FBKDIV_11 0x00B00000 -#define PLL_FBKDIV_12 0x00C00000 -#define PLL_FBKDIV_13 0x00D00000 -#define PLL_FBKDIV_14 0x00E00000 -#define PLL_FBKDIV_15 0x00F00000 - /* Forward A divisor */ -#define PLL_FWDDIVA 0x00070000 -#define CPC0_PLLMR1_FWDVA 0x00070000 -#define PLL_FWDDIVA_8 0x00000000 -#define PLL_FWDDIVA_7 0x00010000 -#define PLL_FWDDIVA_6 0x00020000 -#define PLL_FWDDIVA_5 0x00030000 -#define PLL_FWDDIVA_4 0x00040000 -#define PLL_FWDDIVA_3 0x00050000 -#define PLL_FWDDIVA_2 0x00060000 -#define PLL_FWDDIVA_1 0x00070000 - /* Forward B divisor */ -#define PLL_FWDDIVB 0x00007000 -#define CPC0_PLLMR1_FWDVB 0x00007000 -#define PLL_FWDDIVB_8 0x00000000 -#define PLL_FWDDIVB_7 0x00001000 -#define PLL_FWDDIVB_6 0x00002000 -#define PLL_FWDDIVB_5 0x00003000 -#define PLL_FWDDIVB_4 0x00004000 -#define PLL_FWDDIVB_3 0x00005000 -#define PLL_FWDDIVB_2 0x00006000 -#define PLL_FWDDIVB_1 0x00007000 - /* PLL tune bits */ -#define PLL_TUNE_MASK 0x000003FF -#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ -#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ -#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ -#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ -#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ -#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ -#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ - -/* Defines for CPC0_PLLMR0 Register fields */ - /* CPU divisor */ -#define PLL_CPUDIV 0x00300000 -#define CPC0_PLLMR0_CCDV 0x00300000 -#define PLL_CPUDIV_1 0x00000000 -#define PLL_CPUDIV_2 0x00100000 -#define PLL_CPUDIV_3 0x00200000 -#define PLL_CPUDIV_4 0x00300000 - /* PLB divisor */ -#define PLL_PLBDIV 0x00030000 -#define CPC0_PLLMR0_CBDV 0x00030000 -#define PLL_PLBDIV_1 0x00000000 -#define PLL_PLBDIV_2 0x00010000 -#define PLL_PLBDIV_3 0x00020000 -#define PLL_PLBDIV_4 0x00030000 - /* OPB divisor */ -#define PLL_OPBDIV 0x00003000 -#define CPC0_PLLMR0_OPDV 0x00003000 -#define PLL_OPBDIV_1 0x00000000 -#define PLL_OPBDIV_2 0x00001000 -#define PLL_OPBDIV_3 0x00002000 -#define PLL_OPBDIV_4 0x00003000 - /* EBC divisor */ -#define PLL_EXTBUSDIV 0x00000300 -#define CPC0_PLLMR0_EPDV 0x00000300 -#define PLL_EXTBUSDIV_2 0x00000000 -#define PLL_EXTBUSDIV_3 0x00000100 -#define PLL_EXTBUSDIV_4 0x00000200 -#define PLL_EXTBUSDIV_5 0x00000300 - /* MAL divisor */ -#define PLL_MALDIV 0x00000030 -#define CPC0_PLLMR0_MPDV 0x00000030 -#define PLL_MALDIV_1 0x00000000 -#define PLL_MALDIV_2 0x00000010 -#define PLL_MALDIV_3 0x00000020 -#define PLL_MALDIV_4 0x00000030 - /* PCI divisor */ -#define PLL_PCIDIV 0x00000003 -#define CPC0_PLLMR0_PPFD 0x00000003 -#define PLL_PCIDIV_1 0x00000000 -#define PLL_PCIDIV_2 0x00000001 -#define PLL_PCIDIV_3 0x00000002 -#define PLL_PCIDIV_4 0x00000003 - -#ifdef CONFIG_PPCHAMELEON_CLK_25 -/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */ -#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_2) -#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) - -#elif (defined (CONFIG_PPCHAMELEON_CLK_33)) - -/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */ -#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \ - PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ - PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_2) -#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) - -#else -#error "* External frequency (SysClk) not defined! *" -#endif - -#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI) -/* Model HI */ -#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55 -#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55 -#define CONFIG_SYS_OPB_FREQ 55555555 -/* Model ME */ -#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) -#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33 -#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33 -#define CONFIG_SYS_OPB_FREQ 66666666 -#else -/* Model BA (default) */ -#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33 -#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33 -#define CONFIG_SYS_OPB_FREQ 66666666 -#endif - -#endif /* CONFIG_NO_SERIAL_EEPROM */ - -#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ -#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */ - -/* - * JFFS2 partitions - */ - -/* No command line, one static partition */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nand0" -#define CONFIG_JFFS2_PART_SIZE 0x00400000 -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor0=PPChameleon-0,nand0=ppchameleonevb-nand" -*/ - -/* 256 kB U-boot image */ -/* -#define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \ - "1792k(user),256k(u-boot);" \ - "ppchameleonevb-nand:-(nand)" -*/ - -/* 320 kB U-boot image */ -/* -#define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \ - "1728k(user),320k(u-boot);" \ - "ppchameleonevb-nand:-(nand)" -*/ - -#endif /* __CONFIG_H */ -- cgit From ad734f7dc2238aa9c6a99ff30e40aedbc01fb4fd Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 23 Jan 2015 00:24:20 +0900 Subject: powerpc: mpc5xxx: remove Total5200 board support This board is still a non-generic board. Signed-off-by: Masahiro Yamada --- include/configs/Total5200.h | 386 -------------------------------------------- 1 file changed, 386 deletions(-) delete mode 100644 include/configs/Total5200.h (limited to 'include') diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h deleted file mode 100644 index a58eecab84..0000000000 --- a/include/configs/Total5200.h +++ /dev/null @@ -1,386 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Check valid setting of revision define. - * Total5100 and Total5200 Rev.1 are identical except for the processor. - */ -#if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2) -#error CONFIG_TOTAL5200_REV must be 1 or 2 -#endif - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ -#define CONFIG_TOTAL5200 1 /* ... on Total5200 board */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFFF00000 boot high (standard configuration) - * 0xFE000000 boot low - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Video console - */ -#define CONFIG_VIDEO -#define CONFIG_VIDEO_SED13806 -#define CONFIG_VIDEO_SED13806_16BPP - -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -/* #define CONFIG_VIDEO_BMP_LOGO */ -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_SPLASH_SCREEN - - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -#define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_MII 1 -#define CONFIG_EEPRO100 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* USB */ -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI - -#define CONFIG_CMD_BMP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_PING -#define CONFIG_CMD_USB - - -#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low */ -# define CONFIG_SYS_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT \ - "setenv stdout serial;setenv stderr serial;" \ - "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/MPC5200/uImage\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* - * IPB Bus clocking configuration. - */ -#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */ - -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#if CONFIG_TOTAL5200_REV==2 -# define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */ -# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS5_START, CONFIG_SYS_CS4_START, CONFIG_SYS_BOOTCS_START } -#else -# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START } -#endif -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#if CONFIG_TOTAL5200_REV==1 -# define CONFIG_SYS_FLASH_BASE 0xFE000000 -# define CONFIG_SYS_FLASH_SIZE 0x02000000 -#elif CONFIG_TOTAL5200_REV==2 -# define CONFIG_SYS_FLASH_BASE 0xFA000000 -# define CONFIG_SYS_FLASH_SIZE 0x06000000 -#endif /* CONFIG_TOTAL5200_REV */ - -#if defined(CONFIG_SYS_LOWBOOT) -# define CONFIG_ENV_ADDR 0xFE040000 -#else /* CONFIG_SYS_LOWBOOT */ -# define CONFIG_ENV_ADDR 0xFFF40000 -#endif /* CONFIG_SYS_LOWBOOT */ - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x40000 -#define CONFIG_ENV_SECT_SIZE 0x40000 -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Memory map - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 -#define CONFIG_SYS_MBAR 0xF0000000 /* 64 kB */ -#define CONFIG_SYS_FPGA_BASE 0xF0010000 /* 64 kB */ -#define CONFIG_SYS_CPLD_BASE 0xF0020000 /* 64 kB */ -#define CONFIG_SYS_LCD_BASE 0xF1000000 /* 4096 kB */ - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_SEVENWIRE -/* dummy, 7-wire FEC does not have phy address */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - * - * CS1: SDRAM CS1 disabled, gpio_wkup_6 enabled 0 - * Reserved 0 - * ALTs: CAN1/2 on PSC2, SPI on PSC3 00 - * CS7: Interrupt GPIO on PSC3_5 0 - * CS8: Interrupt GPIO on PSC3_4 0 - * ATA: reset default, changed in ATA driver 00 - * IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO 0 - * IRDA: reset default, changed in IrDA driver 000 - * ETHER: reset default, changed in Ethernet driver 0000 - * PCI_DIS: reset default, changed in PCI driver 0 - * USB_SE: reset default, changed in USB driver 0 - * USB: reset default, changed in USB driver 00 - * PSC3: SPI and UART functionality without CD 1100 - * Reserved 0 - * PSC2: CAN1/2 001 - * Reserved 0 - * PSC1: reset default, changed in AC'97 driver 000 - * - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x00000C10 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#if CONFIG_TOTAL5200_REV==1 -# define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -# define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */ -# define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ -# define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -# define CONFIG_SYS_CS0_SIZE 0x02000000 /* 32 MB */ -#else -# define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS4_START + CONFIG_SYS_CS4_SIZE) -# define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */ -# define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ -# define CONFIG_SYS_CS4_START (CONFIG_SYS_CS5_START + CONFIG_SYS_CS5_SIZE) -# define CONFIG_SYS_CS4_SIZE 0x02000000 /* 32 MB */ -# define CONFIG_SYS_CS4_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ -# define CONFIG_SYS_CS5_START CONFIG_SYS_FLASH_BASE -# define CONFIG_SYS_CS5_SIZE 0x02000000 /* 32 MB */ -# define CONFIG_SYS_CS5_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ -#endif - -#define CONFIG_SYS_CS1_START CONFIG_SYS_FPGA_BASE -#define CONFIG_SYS_CS1_SIZE 0x00010000 /* 64 kB */ -#define CONFIG_SYS_CS1_CFG 0x0019FF00 /* 25WS, MX, AL, AA, CE, AS_25, DS_32 */ - -#define CONFIG_SYS_CS2_START CONFIG_SYS_LCD_BASE -#define CONFIG_SYS_CS2_SIZE 0x00400000 /* 4096 kB */ -#define CONFIG_SYS_CS2_CFG 0x0032FD0C /* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */ - -#if CONFIG_TOTAL5200_REV==1 -# define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE -# define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */ -# define CONFIG_SYS_CS3_CFG 0x000ADF00 /* 10WS, MX, AL, CE, AS_25, DS_32 */ -#else -# define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE -# define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */ -# define CONFIG_SYS_CS3_CFG 0x000AD800 /* 10WS, MX, AL, CE, AS_24, DS_8 */ -#endif - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_ATA_CS_ON_I2C2 -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#endif /* __CONFIG_H */ -- cgit From a258e732a7e2608695c9244eb10998af8f968f5b Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 23 Jan 2015 00:24:21 +0900 Subject: powerpc: mpc5xxx: PM520 board support This board is still a non-generic board. Signed-off-by: Masahiro Yamada Cc: Josef Wagner --- include/configs/PM520.h | 342 ------------------------------------------------ 1 file changed, 342 deletions(-) delete mode 100644 include/configs/PM520.h (limited to 'include') diff --git a/include/configs/PM520.h b/include/configs/PM520.h deleted file mode 100644 index de46216422..0000000000 --- a/include/configs/PM520.h +++ /dev/null @@ -1,342 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 -#define CONFIG_PM520 1 /* PM520 board */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -#define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_MII 1 -#define CONFIG_EEPRO100 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#undef CONFIG_NS8382X - - -/* Partitions */ -#define CONFIG_DOS_PARTITION - -/* USB */ -#if 1 -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_USB - -#define CONFIG_CMD_PCI - - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=pm520\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk30/ppc_82xx\0" \ - "bootfile=/tftpboot/PM520/uImage\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* - * IPB Bus clocking configuration. - */ -#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* - * RTC configuration - */ -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -#define CONFIG_SYS_DOC_BASE 0xE0000000 -#define CONFIG_SYS_DOC_SIZE 0x00100000 - -#if defined(CONFIG_BOOT_ROM) -/* - * Flash configuration (8,16 or 32 MB) - * TEXT base always at 0xFFF00000 - * ENV_ADDR always at 0xFFF40000 - * FLASH_BASE at 0xFA000000 for 64 MB - * 0xFC000000 for 32 MB - * 0xFD000000 for 16 MB - * 0xFD800000 for 8 MB - */ -#define CONFIG_SYS_FLASH_BASE 0xFA000000 -#define CONFIG_SYS_FLASH_SIZE 0x04000000 -#define CONFIG_SYS_BOOTROM_BASE 0xFFF00000 -#define CONFIG_SYS_BOOTROM_SIZE 0x00080000 -#define CONFIG_ENV_ADDR (0xFDF00000 + 0x40000) -#else -/* - * Flash configuration (8,16 or 32 MB) - * TEXT base always at 0xFFF00000 - * ENV_ADDR always at 0xFFF40000 - * FLASH_BASE at 0xFC000000 for 64 MB - * 0xFE000000 for 32 MB - * 0xFF000000 for 16 MB - * 0xFF800000 for 8 MB - */ -#define CONFIG_SYS_FLASH_BASE 0xFC000000 -#define CONFIG_SYS_FLASH_SIZE 0x04000000 -#define CONFIG_ENV_ADDR (0xFFF00000 + 0x40000) -#endif -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ - -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ -#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ -#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ -#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ - -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ - -#undef CONFIG_FLASH_16BIT /* Flash is 32-bit */ - - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x40000 -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xf0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ - - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -/* - * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb - */ -/* #define CONFIG_MPC5xxx_FEC_MII10 */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#if defined(CONFIG_BOOT_ROM) -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_BOOTROM_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_BOOTROM_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00047800 -#define CONFIG_SYS_CS0_START CONFIG_SYS_BOOTROM_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_BOOTROM_SIZE -#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_CS1_CFG 0x0004FF00 -#else -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x0004FF00 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_CS1_START CONFIG_SYS_DOC_BASE -#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_DOC_SIZE -#define CONFIG_SYS_CS1_CFG 0x00047800 -#endif - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00005000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#undef CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#endif /* __CONFIG_H */ -- cgit From 37b608a52dcb13312a4f7ccea199cd6bac76d298 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 23 Jan 2015 00:24:22 +0900 Subject: powerpc: remove icecube_5200, Lite5200, cpci5200, mecp5200, pf5200 These boards are still non-generic boards. Signed-off-by: Masahiro Yamada Cc: Wolfgang Denk Cc: Reinhard Arlt --- include/configs/IceCube.h | 403 --------------------------------------------- include/configs/cpci5200.h | 390 ------------------------------------------- include/configs/mecp5200.h | 319 ----------------------------------- include/configs/pf5200.h | 372 ----------------------------------------- 4 files changed, 1484 deletions(-) delete mode 100644 include/configs/IceCube.h delete mode 100644 include/configs/cpci5200.h delete mode 100644 include/configs/mecp5200.h delete mode 100644 include/configs/pf5200.h (limited to 'include') diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h deleted file mode 100644 index 1861aa86d9..0000000000 --- a/include/configs/IceCube.h +++ /dev/null @@ -1,403 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ -#define CONFIG_ICECUBE 1 /* ... on IceCube board */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFFF00000 boot high (standard configuration) - * 0xFF000000 boot low for 16 MiB boards - * 0xFF800000 boot low for 8 MiB boards - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#define CONFIG_PCI - -#if defined(CONFIG_PCI) -#define CONFIG_PCI_PNP 1 -#define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 -#endif - -#define CONFIG_SYS_XLB_PIPELINING 1 - -#define CONFIG_MII 1 -#define CONFIG_EEPRO100 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -/* USB */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_USB_STORAGE -#define CONFIG_SYS_OHCI_BE_CONTROLLER -#undef CONFIG_SYS_USB_OHCI_BOARD_INIT -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 -#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_USB - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_PCI -#endif - - -#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ -# define CONFIG_SYS_LOWBOOT 1 -# define CONFIG_SYS_LOWBOOT16 1 -#endif -#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ -#if defined(CONFIG_LITE5200B) -# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B -#else -# define CONFIG_SYS_LOWBOOT 1 -# define CONFIG_SYS_LOWBOOT08 1 -#endif -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/MPC5200/uImage\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* - * IPB Bus clocking configuration. - */ -#if defined(CONFIG_LITE5200B) -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#else -#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 - -/* - * Flash configuration - */ -#if defined(CONFIG_LITE5200B) -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_SIZE 0x01000000 -#if !defined(CONFIG_SYS_LOWBOOT) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01760000 + 0x00800000) -#else /* CONFIG_SYS_LOWBOOT */ -#if defined(CONFIG_SYS_LOWBOOT08) -# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B -#endif -#if defined(CONFIG_SYS_LOWBOOT16) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01060000) -#endif -#endif /* CONFIG_SYS_LOWBOOT */ -#else /* !CONFIG_LITE5200B (IceCube)*/ -#define CONFIG_SYS_FLASH_BASE 0xFF000000 -#define CONFIG_SYS_FLASH_SIZE 0x01000000 -#if !defined(CONFIG_SYS_LOWBOOT) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00740000 + 0x00800000) -#else /* CONFIG_SYS_LOWBOOT */ -#if defined(CONFIG_SYS_LOWBOOT08) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000 + 0x00800000) -#endif -#if defined(CONFIG_SYS_LOWBOOT16) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) -#endif -#endif /* CONFIG_SYS_LOWBOOT */ -#endif /* CONFIG_LITE5200B */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */ - -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */ - -#if defined(CONFIG_LITE5200B) -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS1_START,CONFIG_SYS_CS0_START} -#endif - - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 -#if defined(CONFIG_LITE5200B) -#define CONFIG_ENV_SECT_SIZE 0x20000 -#else -#define CONFIG_ENV_SECT_SIZE 0x10000 -#endif -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ - - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -/* - * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb - */ -/* #define CONFIG_MPC5xxx_FEC_MII10 */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - */ -#ifdef CONFIG_MPC5200_DDR -#define CONFIG_SYS_GPS_PORT_CONFIG 0x90000004 -#else -#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004 -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#if defined(CONFIG_LITE5200B) -#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_CS1_CFG 0x00047800 -#define CONFIG_SYS_CS0_START (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE) -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_CS0_START -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00047800 -#else /* IceCube aka Lite5200 */ -#ifdef CONFIG_MPC5200_DDR - -#define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS1_START + CONFIG_SYS_CS1_SIZE) -#define CONFIG_SYS_BOOTCS_SIZE 0x00800000 -#define CONFIG_SYS_BOOTCS_CFG 0x00047801 -#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS1_SIZE 0x00800000 -#define CONFIG_SYS_CS1_CFG 0x00047800 - -#else /* !CONFIG_MPC5200_DDR */ - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00047801 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#endif /* CONFIG_MPC5200_DDR */ -#endif /*CONFIG_LITE5200B */ - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#define CONFIG_ATAPI 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h deleted file mode 100644 index ec926fd22d..0000000000 --- a/include/configs/cpci5200.h +++ /dev/null @@ -1,390 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - - */ - -/************************************************************************* - * (c) 2005 esd gmbh Hannover - * - * - * from IceCube.h file - * by Reinhard Arlt reinhard.arlt@esd-electronics.com - * - *************************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_ICECUBE 1 /* ... on IceCube board */ -#define CONFIG_CPCI5200 1 /* ... on CPCI5200 board */ -#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */ -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#if 1 -#define CONFIG_PCI 1 -#if 1 -#define CONFIG_PCI_PNP 1 -#endif -#define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 -#endif - -#define CONFIG_MII -#if 0 /* test-only !!! */ -#define CONFIG_EEPRO100 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 -#endif - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* USB */ -#if 0 -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_PCI -#endif - -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_FAT -#define CONFIG_CMD_IDE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_BSP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_DATE - -#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ -# define CONFIG_SYS_LOWBOOT 1 -# define CONFIG_SYS_LOWBOOT16 1 -#endif -#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ -# define CONFIG_SYS_LOWBOOT 1 -# define CONFIG_SYS_LOWBOOT08 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Welcome to esd CPU CPCI/5200;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \ - "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \ - "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \ - "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \ - "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \ - "loadaddr=01000000\0" \ - "serverip=192.168.2.99\0" \ - "gatewayip=10.0.0.79\0" \ - "user=mu\0" \ - "target=cpci5200.esd\0" \ - "script=cpci5200.bat\0" \ - "image=/tftpboot/vxWorks_cpci5200\0" \ - "ipaddr=10.0.13.196\0" \ - "netmask=255.255.0.0\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_vxworks0" - -#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfd010000 -#define CONFIG_SYS_NVRAM_SIZE 32*1024 - -/* - * IPB Bus clocking configuration. - */ -#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */ - -#define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 -/* - * Flash configuration - */ - -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_SIZE 0x02000000 -#define CONFIG_SYS_FLASH_INCREMENT 0x01000000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000) -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 - -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/* - * Environment settings - */ -#if 1 /* test-only */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OVERWRITE 1 -#else -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */ - /* total size of a CAT24WC32 is 8192 bytes */ -#define CONFIG_ENV_OVERWRITE 1 -#endif - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -/* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb - */ -/* #define CONFIG_FEC_10MBIT 1 */ -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_UDP_CHECKSUM 1 - -/* - * GPIO configuration - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x0004DD00 - -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_SYS_CS1_START 0xfd000000 -#define CONFIG_SYS_CS1_SIZE 0x00010000 -#define CONFIG_SYS_CS1_CFG 0x10101410 - -#define CONFIG_SYS_CS3_START 0xfd010000 -#define CONFIG_SYS_CS3_SIZE 0x00010000 -#define CONFIG_SYS_CS3_CFG 0x10109410 - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -/*----------------------------------------------------------------------- - * CPLD stuff - */ -#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ -#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ - -/* CPLD program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */ -#define CONFIG_SYS_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */ - -#define JTAG_GPIO_ADDR_TMS (CONFIG_SYS_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */ -#define JTAG_GPIO_ADDR_TCK (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */ -#define JTAG_GPIO_ADDR_TDI (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */ -#define JTAG_GPIO_ADDR_TDO (CONFIG_SYS_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */ - -#define JTAG_GPIO_ADDR_CFG (CONFIG_SYS_MBAR + 0xB00) -#define JTAG_GPIO_CFG_SET 0x00000000 -#define JTAG_GPIO_CFG_RESET 0x00F00000 - -#define JTAG_GPIO_ADDR_EN_TMS (CONFIG_SYS_MBAR + 0xB04) -#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */ -#define JTAG_GPIO_TMS_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TMS (CONFIG_SYS_MBAR + 0xB0C) -#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */ -#define JTAG_GPIO_TMS_DDR_RESET 0x00000000 - -#define JTAG_GPIO_ADDR_EN_TCK (CONFIG_SYS_MBAR + 0xC00) -#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */ -#define JTAG_GPIO_TCK_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TCK (CONFIG_SYS_MBAR + 0xC08) -#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */ -#define JTAG_GPIO_TCK_DDR_RESET 0x00000000 - -#define JTAG_GPIO_ADDR_EN_TDI (CONFIG_SYS_MBAR + 0xC00) -#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */ -#define JTAG_GPIO_TDI_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TDI (CONFIG_SYS_MBAR + 0xC08) -#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */ -#define JTAG_GPIO_TDI_DDR_RESET 0x00000000 - -#define JTAG_GPIO_ADDR_EN_TDO (CONFIG_SYS_MBAR + 0xB04) -#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */ -#define JTAG_GPIO_TDO_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TDO (CONFIG_SYS_MBAR + 0xB0C) -#define JTAG_GPIO_TDO_DDR_SET 0x00000000 -#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h deleted file mode 100644 index b270429dd8..0000000000 --- a/include/configs/mecp5200.h +++ /dev/null @@ -1,319 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -/************************************************************************* - * (c) 2005 esd gmbh Hannover - * - * - * from IceCube.h file - * by Reinhard Arlt reinhard.arlt@esd-electronics.com - * - *************************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_ICECUBE 1 /* ... on IceCube board */ -#define CONFIG_MECP5200 1 /* ... on MECP5200 board */ -#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#if 0 /* test-only */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#else -#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */ -#endif -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_MII -#if 0 /* test-only !!! */ -#define CONFIG_EEPRO100 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 -#endif - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* USB */ -#if 0 -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE -#endif - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_BSP -#define CONFIG_CMD_ELF - - -#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ -# define CONFIG_SYS_LOWBOOT 1 -# define CONFIG_SYS_LOWBOOT16 1 -#endif -#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ -# define CONFIG_SYS_LOWBOOT 1 -# define CONFIG_SYS_LOWBOOT08 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Welcome to CBX-CPU5200 (mecp5200);" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \ - "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \ - "net_vxworks=tftp $(loadaddr) $(image);run vxworks_args;bootvx\0" \ - "vxworks_args=setenv bootargs fec(0,0)$(host):$(image) h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script)\0" \ - "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script) o=fec0 \0" \ - "loadaddr=01000000\0" \ - "serverip=192.168.2.99\0" \ - "gatewayip=10.0.0.79\0" \ - "user=mu\0" \ - "target=mecp5200.esd\0" \ - "script=mecp5200.bat\0" \ - "image=/tftpboot/vxWorks_mecp5200\0" \ - "ipaddr=10.0.13.196\0" \ - "netmask=255.255.0.0\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_vxworks0" - -/* - * IPB Bus clocking configuration. - */ -#undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */ -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_BASE 0xFFC00000 -#define CONFIG_SYS_FLASH_SIZE 0x00400000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x003E0000) -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/* - * Environment settings - */ -#if 1 /* test-only */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_OVERWRITE 1 -#else -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars*/ - /* total size of a CAT24WC32 is 8192 bytes */ -#define CONFIG_ENV_OVERWRITE 1 -#endif - -#define CONFIG_FLASH_CFI_DRIVER 1 /* Flash is CFI conformant */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ -#if 0 -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#endif -#define CONFIG_SYS_FLASH_INCREMENT 0x00400000 /* size of flash bank */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* show if bank is empty */ - - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ - - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -/* - * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb - */ -/* #define CONFIG_MPC5xxx_FEC_MII10 */ -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_UDP_CHECKSUM 1 - - -/* - * GPIO configuration - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00085d00 - -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_SYS_CS1_START 0xfd000000 -#define CONFIG_SYS_CS1_SIZE 0x00010000 -#define CONFIG_SYS_CS1_CFG 0x10101410 - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#endif /* __CONFIG_H */ diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h deleted file mode 100644 index be76478c30..0000000000 --- a/include/configs/pf5200.h +++ /dev/null @@ -1,372 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * (c) 2005 esd gmbh Hannover - * - * - * from IceCube.h file - * by Reinhard Arlt reinhard.arlt@esd-electronics.com - * - *************************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_ICECUBE 1 /* ... on IceCube board */ -#define CONFIG_PF5200 1 /* ... on PF5200 board */ -#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#if 0 /* test-only */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#else -#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */ -#endif -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -#define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_MII 1 -#if 0 /* test-only !!! */ -#define CONFIG_EEPRO100 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 -#endif - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* USB */ -#if 0 -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE -#endif - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BSP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE - -#define CONFIG_CMD_PCI - - -#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ -# define CONFIG_SYS_LOWBOOT 1 -# define CONFIG_SYS_LOWBOOT16 1 -#endif -#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ -# define CONFIG_SYS_LOWBOOT 1 -# define CONFIG_SYS_LOWBOOT08 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Welcome to ParaFinder pf5200;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \ - "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \ - "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \ - "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \ - "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \ - "loadaddr=01000000\0" \ - "serverip=192.168.2.99\0" \ - "gatewayip=10.0.0.79\0" \ - "user=mu\0" \ - "target=pf5200.esd\0" \ - "script=pf5200.bat\0" \ - "image=/tftpboot/vxWorks_pf5200\0" \ - "ipaddr=10.0.13.196\0" \ - "netmask=255.255.0.0\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_vxworks0" - -/* - * IPB Bus clocking configuration. - */ -#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_SIZE 0x02000000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000) -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/* - * Environment settings - */ -#if 1 /* test-only */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_OVERWRITE 1 -#else -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */ - /* total size of a CAT24WC32 is 8192 bytes */ -#define CONFIG_ENV_OVERWRITE 1 -#endif - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -/* - * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb - */ -/* #define CONFIG_MPC5xxx_FEC_MII10 */ -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_UDP_CHECKSUM 1 - -/* - * GPIO configuration - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x0004DD00 - -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_SYS_CS1_START 0xfd000000 -#define CONFIG_SYS_CS1_SIZE 0x00010000 -#define CONFIG_SYS_CS1_CFG 0x10101410 - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -/*----------------------------------------------------------------------- - * CPLD stuff - */ -#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ -#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ - -/* CPLD program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */ -#define CONFIG_SYS_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */ - -#define JTAG_GPIO_ADDR_TMS (CONFIG_SYS_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */ -#define JTAG_GPIO_ADDR_TCK (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */ -#define JTAG_GPIO_ADDR_TDI (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */ -#define JTAG_GPIO_ADDR_TDO (CONFIG_SYS_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */ - -#define JTAG_GPIO_ADDR_CFG (CONFIG_SYS_MBAR + 0xB00) -#define JTAG_GPIO_CFG_SET 0x00000000 -#define JTAG_GPIO_CFG_RESET 0x00F00000 - -#define JTAG_GPIO_ADDR_EN_TMS (CONFIG_SYS_MBAR + 0xB04) -#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */ -#define JTAG_GPIO_TMS_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TMS (CONFIG_SYS_MBAR + 0xB0C) -#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */ -#define JTAG_GPIO_TMS_DDR_RESET 0x00000000 - -#define JTAG_GPIO_ADDR_EN_TCK (CONFIG_SYS_MBAR + 0xC00) -#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */ -#define JTAG_GPIO_TCK_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TCK (CONFIG_SYS_MBAR + 0xC08) -#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */ -#define JTAG_GPIO_TCK_DDR_RESET 0x00000000 - -#define JTAG_GPIO_ADDR_EN_TDI (CONFIG_SYS_MBAR + 0xC00) -#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */ -#define JTAG_GPIO_TDI_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TDI (CONFIG_SYS_MBAR + 0xC08) -#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */ -#define JTAG_GPIO_TDI_DDR_RESET 0x00000000 - -#define JTAG_GPIO_ADDR_EN_TDO (CONFIG_SYS_MBAR + 0xB04) -#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */ -#define JTAG_GPIO_TDO_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TDO (CONFIG_SYS_MBAR + 0xB0C) -#define JTAG_GPIO_TDO_DDR_SET 0x00000000 -#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */ - -#endif /* __CONFIG_H */ -- cgit From bdc88d4eb31e2bc84afb427c216c79e87a4233ef Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 29 Dec 2014 19:32:24 -0700 Subject: x86: Support ROMs on other archs We shouldn't assume that the VGA ROM can always be loaded at c0000. This is only true on x86 machines. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- include/pci_rom.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/pci_rom.h b/include/pci_rom.h index 8b2674cf87..4ba36eb1b7 100644 --- a/include/pci_rom.h +++ b/include/pci_rom.h @@ -8,7 +8,6 @@ #define _PCI_ROM_H #define PCI_ROM_HDR 0xaa55 -#define PCI_VGA_RAM_IMAGE_START 0xc0000 struct pci_rom_header { uint16_t signature; -- cgit From 222f25f85503f19acb9cb7ff138d3fe5215c3ad9 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 29 Dec 2014 19:32:26 -0700 Subject: bios_emulator: Add some VESA interface debugging Allow the supported modes to be listed when in debug mode. Signed-off-by: Simon Glass --- include/vbe.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/vbe.h b/include/vbe.h index d4056914c4..c5deee9eca 100644 --- a/include/vbe.h +++ b/include/vbe.h @@ -35,10 +35,14 @@ struct __packed screen_info_input { struct __packed vbe_info { char signature[4]; u16 version; - u8 *oem_string_ptr; + u32 oem_string_ptr; u32 capabilities; - u16 video_mode_list[256]; + u32 modes_ptr; u16 total_memory; + u16 oem_version; + u32 vendor_name_ptr; + u32 product_name_ptr; + u32 product_rev_ptr; }; struct __packed vesa_mode_info { @@ -96,6 +100,7 @@ struct vbe_ddc_info { #define VESA_GET_INFO 0x4f00 #define VESA_GET_MODE_INFO 0x4f01 #define VESA_SET_MODE 0x4f02 +#define VESA_GET_CUR_MODE 0x4f03 struct graphic_device; int vbe_get_video_info(struct graphic_device *gdev); -- cgit From 4a2708a097eacd7aa3d10ccf26a70a467fa69217 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 14 Jan 2015 21:37:04 -0700 Subject: x86: Access the VGA ROM when needed Add code to the generic pci_rom file to access the VGA ROM in PCI space when needed. Signed-off-by: Simon Glass --- include/pci.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include') diff --git a/include/pci.h b/include/pci.h index 7f67ca6542..4fbb8f6729 100644 --- a/include/pci.h +++ b/include/pci.h @@ -697,5 +697,14 @@ void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum, * */ u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum); +/** + * pciauto_setup_rom() - Set up access to a device ROM + * + * @hose: PCI hose to use + * @dev: PCI device to adjust + * @return 0 if done, -ve on error + */ +int pciauto_setup_rom(struct pci_controller *hose, pci_dev_t dev); + #endif /* __ASSEMBLY__ */ #endif /* _PCI_H */ -- cgit From d1a5d3c133a07d6035b9f97a6315afed7d73514a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 1 Jan 2015 16:17:58 -0700 Subject: x86: config: Always scroll the display by 5 lines, for speed Scrolling a line at a time is very slow for reasons that I don't understand. It seems to take about 100ms to copy 4MB of RAM in the frame buffer. To cope with this, scroll 5 lines each time. Signed-off-by: Simon Glass --- include/configs/x86-common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index f16ae32913..4f0a3c5928 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -179,6 +179,7 @@ #define VIDEO_FB_16BPP_WORD_SWAP #define CONFIG_I8042_KBD #define CONFIG_CFB_CONSOLE +#define CONFIG_CONSOLE_SCROLL_LINES 5 /*----------------------------------------------------------------------- * CPU Features -- cgit From dda3b610eee9dcd433627202584ded417327dd51 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Dec 2014 15:30:55 -0800 Subject: arm/ls1021a: Add workaround for DDR erratum A008378 Internal memory controller counters can reach a bad state after training in DDR4 mode if accumulated ECC or DBI mode is eanbled. Signed-off-by: York Sun --- include/fsl_ddr.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index 675557ad1f..3286c95907 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -23,9 +23,15 @@ #ifdef CONFIG_SYS_FSL_DDR_LE #define ddr_in32(a) in_le32(a) #define ddr_out32(a, v) out_le32(a, v) +#define ddr_setbits32(a, v) setbits_le32(a, v) +#define ddr_clrbits32(a, v) clrbits_le32(a, v) +#define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set) #else #define ddr_in32(a) in_be32(a) #define ddr_out32(a, v) out_be32(a, v) +#define ddr_setbits32(a, v) setbits_be32(a, v) +#define ddr_clrbits32(a, v) clrbits_be32(a, v) +#define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set) #endif #define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR -- cgit From dd04832d522918cad1d3ae894f94c5e59c04d567 Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Tue, 16 Dec 2014 14:50:33 +0800 Subject: ls102xa: dcu: Add platform support for DCU on LS1021AQDS board This patch adds the CH7301 HDMI options and the common configuration for DCU on LS1021AQDS board. Signed-off-by: Xiubo Li Signed-off-by: Alison Wang Cc: Jason Jin Reviewed-by: York Sun --- include/configs/ls1021aqds.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'include') diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 8dc04f2e57..8b757daef0 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -385,6 +385,7 @@ unsigned long get_board_ddr_clk(void); */ #define I2C_MUX_PCA_ADDR_PRI 0x77 #define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH_CH7301 0xC /* * MMC @@ -426,6 +427,25 @@ unsigned long get_board_ddr_clk(void); #endif #endif +/* + * Video + */ +#define CONFIG_FSL_DCU_FB + +#ifdef CONFIG_FSL_DCU_FB +#define CONFIG_VIDEO +#define CONFIG_CMD_BMP +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO + +#define CONFIG_FSL_DIU_CH7301 +#define CONFIG_SYS_I2C_DVI_BUS_NUM 0 +#define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 +#define CONFIG_SYS_I2C_DVI_ADDR 0x75 +#endif + /* * eTSEC */ -- cgit From 8fc2121a10e92bfd7cb1db50fb110d3ca9acfbda Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Sun, 4 Jan 2015 15:30:58 +0800 Subject: arm: ls102xa: Add LPUART support for LS1021AQDS board This patch adds LPUART support for LS1021AQDS board. For ls1021aqds_nor_lpuart_defconfig, LPUART is used as the console. Signed-off-by: Alison Wang Reviewed-by: York Sun --- include/configs/ls1021aqds.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'include') diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 8b757daef0..296ded9f5e 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -365,11 +365,16 @@ unsigned long get_board_ddr_clk(void); /* * Serial Port */ +#ifdef CONFIG_LPUART +#define CONFIG_FSL_LPUART +#define CONFIG_LPUART_32B_REG +#else #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() +#endif #define CONFIG_BAUDRATE 115200 @@ -528,11 +533,19 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_QE_FW_ADDR 0x67f40000 +#ifdef CONFIG_LPUART +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ + "fdt_high=0xcfffffff\0" \ + "initrd_high=0xcfffffff\0" \ + "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" +#else #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ "fdt_high=0xcfffffff\0" \ "initrd_high=0xcfffffff\0" \ "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" +#endif /* * Miscellaneous configurable options -- cgit From 55d53ab45e3be3442c7b8555ff059df1d28f2838 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Sun, 4 Jan 2015 15:30:59 +0800 Subject: arm: ls102xa: Add LPUART support for LS1021ATWR board This patch adds LPUART support for LS1021ATWR board. For ls1021atwr_nor_lpuart_defconfig, LPUART is used as the console. Signed-off-by: Alison Wang Reviewed-by: York Sun --- include/configs/ls1021atwr.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'include') diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 66954d0a40..0a0bb5f109 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -186,11 +186,16 @@ /* * Serial Port */ +#ifdef CONFIG_LPUART +#define CONFIG_FSL_LPUART +#define CONFIG_LPUART_32B_REG +#else #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() +#endif #define CONFIG_BAUDRATE 115200 @@ -325,10 +330,17 @@ #define CONFIG_BOOTDELAY 3 +#ifdef CONFIG_LPUART +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ + "initrd_high=0xcfffffff\0" \ + "fdt_high=0xcfffffff\0" +#else #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ "initrd_high=0xcfffffff\0" \ "fdt_high=0xcfffffff\0" +#endif /* * Miscellaneous configurable options -- cgit From 5da38086bd6c39efd09e57900702b99541844339 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 19 Jan 2015 22:16:06 -0700 Subject: x86: dts: Add compatible string for Intel ICH9 SPI controller Add this to the enum so that we can use the various fdtdec functions. A later commit will move this driver to driver model. Signed-off-by: Simon Glass --- include/fdtdec.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/fdtdec.h b/include/fdtdec.h index 75af750ee5..8c2bd21b2d 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -173,6 +173,7 @@ enum fdt_compat_id { COMPAT_INTEL_MODEL_206AX, /* Intel Model 206AX CPU */ COMPAT_INTEL_GMA, /* Intel Graphics Media Accelerator */ COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */ + COMPAT_INTEL_ICH_SPI, /* Intel ICH7/9 SPI controller */ COMPAT_COUNT, }; -- cgit From 9b0e35cb4889eb04a7ea5dd648d73df0bf37cc68 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 19 Jan 2015 22:16:07 -0700 Subject: net: Add a separate file for IP checksumming Move the checksum code out into its own file so it can be used elsewhere. Also use a new version which supports a length which is not a multiple of 2 and add a new function to add two checksums. Signed-off-by: Simon Glass --- include/net.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'include') diff --git a/include/net.h b/include/net.h index 3da35fe981..73ea88b42d 100644 --- a/include/net.h +++ b/include/net.h @@ -482,6 +482,36 @@ extern void net_set_ip_header(uchar *pkt, IPaddr_t dest, IPaddr_t source); extern void net_set_udp_header(uchar *pkt, IPaddr_t dest, int dport, int sport, int len); +/** + * compute_ip_checksum() - Compute IP checksum + * + * @addr: Address to check (must be 16-bit aligned) + * @nbytes: Number of bytes to check (normally a multiple of 2) + * @return 16-bit IP checksum + */ +unsigned compute_ip_checksum(const void *addr, unsigned nbytes); + +/** + * add_ip_checksums() - add two IP checksums + * + * @offset: Offset of first sum (if odd we do a byte-swap) + * @sum: First checksum + * @new_sum: New checksum to add + * @return updated 16-bit IP checksum + */ +unsigned add_ip_checksums(unsigned offset, unsigned sum, unsigned new_sum); + +/** + * ip_checksum_ok() - check if a checksum is correct + * + * This works by making sure the checksum sums to 0 + * + * @addr: Address to check (must be 16-bit aligned) + * @nbytes: Number of bytes to check (normally a multiple of 2) + * @return true if the checksum matches, false if not + */ +int ip_checksum_ok(const void *addr, unsigned nbytes); + /* Checksum */ extern int NetCksumOk(uchar *, int); /* Return true if cksum OK */ extern uint NetCksum(uchar *, int); /* Calculate the checksum */ -- cgit From fc4860c089a6b6603e1ae4f9c1f8bd1b3aadfc8b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 19 Jan 2015 22:16:10 -0700 Subject: x86: rtc: mc146818: Add helpers to read/write CMOS RAM On x86 we use CMOS RAM to read and write some settings. Add basic support for this, including access to registers 128-255. Signed-off-by: Simon Glass --- include/rtc.h | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'include') diff --git a/include/rtc.h b/include/rtc.h index d11aa8baf9..54e361ea5e 100644 --- a/include/rtc.h +++ b/include/rtc.h @@ -50,6 +50,38 @@ void to_tm (int, struct rtc_time *); unsigned long mktime (unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int); +/** + * rtc_read8() - Read an 8-bit register + * + * @reg: Register to read + * @return value read + */ +int rtc_read8(int reg); + +/** + * rtc_write8() - Write an 8-bit register + * + * @reg: Register to write + * @value: Value to write + */ +void rtc_write8(int reg, uchar val); + +/** + * rtc_read32() - Read a 32-bit value from the RTC + * + * @reg: Offset to start reading from + * @return value read + */ +u32 rtc_read32(int reg); + +/** + * rtc_write32() - Write a 32-bit value to the RTC + * + * @reg: Register to start writing to + * @value: Value to write + */ +void rtc_write32(int reg, u32 value); + /** * rtc_init() - Set up the real time clock ready for use */ -- cgit From 8e899af0597a43d70752654b227f308dd0d0039c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 19 Jan 2015 22:16:11 -0700 Subject: x86: spi: Add device tree support As a temporary measure before the ICH driver moves over to driver model, add device tree support to the driver. Signed-off-by: Simon Glass --- include/configs/x86-common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 4f0a3c5928..ecedfc3ab1 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -211,6 +211,7 @@ #define CONFIG_CMD_SF_TEST #define CONFIG_CMD_SPI #define CONFIG_SPI +#define CONFIG_OF_SPI_FLASH /*----------------------------------------------------------------------- * Environment configuration -- cgit From 069f5481ba19b819ef11ba23181a264fc566b180 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 19 Jan 2015 22:16:15 -0700 Subject: x86: config: Enable hook for saving MRC configuration Add a hook to ensure that this information is saved. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- include/configs/chromebook_link.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h index 7e6d239d13..6e8b9efb45 100644 --- a/include/configs/chromebook_link.h +++ b/include/configs/chromebook_link.h @@ -20,6 +20,7 @@ #define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000 #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R #define CONFIG_NR_DRAM_BANKS 8 #define CONFIG_X86_MRC_ADDR 0xfffa0000 -- cgit From e43ade3749ff10bc313f33bf23705465e4163896 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 19 Jan 2015 22:16:17 -0700 Subject: x86: config: chromebook_link: Enable environment Enable an environment area. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- include/configs/chromebook_link.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include') diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h index 6e8b9efb45..7b460e83c4 100644 --- a/include/configs/chromebook_link.h +++ b/include/configs/chromebook_link.h @@ -64,6 +64,13 @@ #define CONFIG_CMD_CROS_EC #define CONFIG_ARCH_EARLY_INIT_R +#undef CONFIG_ENV_IS_NOWHERE +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x003f8000 + #define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ "stdout=vga,serial\0" \ "stderr=vga,serial\0" -- cgit From 41ba57d0c7968506ddcc71604bd39131acf6ee23 Mon Sep 17 00:00:00 2001 From: tang yuantian Date: Wed, 17 Dec 2014 12:58:05 +0800 Subject: fsl/ls1021qds: Add deep sleep support Add deep sleep support on Freescale LS1021QDS platform. Signed-off-by: Tang Yuantian [York Sun: Fix conflict in fdt.c] Reviewed-by: York Sun --- include/configs/ls1021aqds.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 296ded9f5e..2874ccc6fa 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -19,6 +19,11 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DEEP_SLEEP +#if defined(CONFIG_DEEP_SLEEP) +#define CONFIG_SILENT_CONSOLE +#endif + /* * Size of malloc() pool */ @@ -72,7 +77,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SPL_PAD_TO 0x1c000 #define CONFIG_SYS_TEXT_BASE 0x82000000 -#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ + CONFIG_SYS_MONITOR_LEN) #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -- cgit From c147ff9df18ba132ecc93092d75955113a8238f7 Mon Sep 17 00:00:00 2001 From: Luka Perkov Date: Wed, 2 Jul 2014 01:47:23 +0200 Subject: kirkwood: ib62x0: add CONFIG_SYS_GENERIC_BOARD define Signed-off-by: Luka Perkov Acked-by: Stefan Roese CC: Prafulla Wadaskar --- include/configs/ib62x0.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h index f4c748a91d..f1ddf21580 100644 --- a/include/configs/ib62x0.h +++ b/include/configs/ib62x0.h @@ -9,6 +9,8 @@ #ifndef _CONFIG_IB62x0_H #define _CONFIG_IB62x0_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Version number information */ -- cgit From 6054b153a531604d4da2d426b7b54a77a1e755f7 Mon Sep 17 00:00:00 2001 From: Luka Perkov Date: Sun, 30 Nov 2014 02:40:37 +0100 Subject: kirkwood: dockstar: add CONFIG_SYS_GENERIC_BOARD define Signed-off-by: Luka Perkov Acked-by: Stefan Roese CC: Prafulla Wadaskar --- include/configs/dockstar.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/dockstar.h b/include/configs/dockstar.h index 46a42b3087..ec7f721ff3 100644 --- a/include/configs/dockstar.h +++ b/include/configs/dockstar.h @@ -12,6 +12,8 @@ #ifndef _CONFIG_DOCKSTAR_H #define _CONFIG_DOCKSTAR_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Version number information */ -- cgit From 15155b49adcbd5f00c2d2cdd8235f843ab55a7e0 Mon Sep 17 00:00:00 2001 From: Luka Perkov Date: Sun, 30 Nov 2014 02:40:51 +0100 Subject: kirkwood: goflexhome: add CONFIG_SYS_GENERIC_BOARD define Signed-off-by: Luka Perkov Acked-by: Stefan Roese CC: Prafulla Wadaskar --- include/configs/goflexhome.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h index 5ed949791f..836515d178 100644 --- a/include/configs/goflexhome.h +++ b/include/configs/goflexhome.h @@ -15,6 +15,8 @@ #ifndef _CONFIG_GOFLEXHOME_H #define _CONFIG_GOFLEXHOME_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Version number information */ -- cgit From 92ca8bda4103e676c5e342df455ab391d1b8e885 Mon Sep 17 00:00:00 2001 From: Luka Perkov Date: Sun, 30 Nov 2014 02:41:04 +0100 Subject: kirkwood: iconnect: add CONFIG_SYS_GENERIC_BOARD define Signed-off-by: Luka Perkov Acked-by: Stefan Roese CC: Prafulla Wadaskar --- include/configs/iconnect.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/iconnect.h b/include/configs/iconnect.h index 9f4a4b83a3..2baf50cc4e 100644 --- a/include/configs/iconnect.h +++ b/include/configs/iconnect.h @@ -9,6 +9,8 @@ #ifndef _CONFIG_ICONNECT_H #define _CONFIG_ICONNECT_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Version number information */ -- cgit From 604a0dd64ef9ccf5fb2c017a54776244f8f3a65e Mon Sep 17 00:00:00 2001 From: Luka Perkov Date: Sun, 30 Nov 2014 02:41:19 +0100 Subject: kirkwood: pogo_e02: add CONFIG_SYS_GENERIC_BOARD define Signed-off-by: Luka Perkov Acked-by: Stefan Roese CC: Prafulla Wadaskar --- include/configs/pogo_e02.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/pogo_e02.h b/include/configs/pogo_e02.h index 7594bdb412..89560ad1c5 100644 --- a/include/configs/pogo_e02.h +++ b/include/configs/pogo_e02.h @@ -13,6 +13,8 @@ #ifndef _CONFIG_POGO_E02_H #define _CONFIG_POGO_E02_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Machine type definition and ID */ -- cgit From d4d8f1b7269d531945d7a48c36f51b398d761d48 Mon Sep 17 00:00:00 2001 From: Luka Perkov Date: Sun, 30 Nov 2014 02:41:49 +0100 Subject: kirkwood: sheevaplug: add CONFIG_SYS_GENERIC_BOARD define Signed-off-by: Luka Perkov Acked-by: Stefan Roese CC: Prafulla Wadaskar --- include/configs/sheevaplug.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index 71be823899..21c8bda9f3 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -10,6 +10,8 @@ #ifndef _CONFIG_SHEEVAPLUG_H #define _CONFIG_SHEEVAPLUG_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Version number information */ -- cgit From 361b3d8613f57e137a9048ef69e58e9bcaf51b78 Mon Sep 17 00:00:00 2001 From: Gerald Kerma Date: Fri, 19 Dec 2014 08:13:09 +0100 Subject: marvell: kirkwood: guruplug refresh for newer kernel Refresh for newer kernel. Prepare ENV settings for sheevaplugs to be OpenWRT ready. +----------+ | UBOOT | >> 896 Kb (7x128) = uboot +----------+ | ENV | >> 128 Kb = uboot_env +----------+ | ROOT(FS) | >> 511 Mb @ 1 Mb = root -> rootfs (ubifs) +----------+ With (CC) TRUNK OpenWRT build (QUICK HOWTO) : Marvell>> nand erase.part root Marvell>> ubi part root Marvell>> ubi remove rootfs Marvell>> ubi create rootfs Marvell>> usb reset Marvell>> fatload usb 2:1 0x800000 guruplug/openwrt/openwrt-kirkwood-guruplug-rootfs.ubifs Marvell>> ubi write 0x800000 rootfs ${filesize} Marvell>> reset Changes in v1: - ADD generic board define - ADD FDT support - ADD HUSH interpreter - Define new NAND partition mapping Signed-off-by: Gerald Kerma --- include/configs/guruplug.h | 84 ++++++++++++++++++++++++++++++++++++---------- 1 file changed, 67 insertions(+), 17 deletions(-) (limited to 'include') diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h index a56a4cb982..8e53af8c04 100644 --- a/include/configs/guruplug.h +++ b/include/configs/guruplug.h @@ -1,5 +1,6 @@ /* - * (C) Copyright 2009 + * (C) Copyright 2009-2014 + * Gerald Kerma * Marvell Semiconductor * Written-by: Siddarth Gore * @@ -9,6 +10,8 @@ #ifndef _CONFIG_GURUPLUG_H #define _CONFIG_GURUPLUG_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Version number information */ @@ -22,18 +25,37 @@ #define CONFIG_MACH_GURUPLUG /* Machine type */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +/* + * Compression configuration + */ +#define CONFIG_BZIP2 +#define CONFIG_LZMA +#define CONFIG_LZO + +/* + * Enable device tree support + */ +#define CONFIG_OF_LIBFDT + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ + /* * Commands configuration */ #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ #include +#define CONFIG_CMD_BOOTZ #define CONFIG_CMD_DHCP #define CONFIG_CMD_ENV -#define CONFIG_CMD_FAT +#define CONFIG_CMD_IDE +#define CONFIG_CMD_MII #define CONFIG_CMD_NAND #define CONFIG_CMD_PING #define CONFIG_CMD_USB -#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT /* * mv-common.h should be defined after CMD configs since it used them @@ -55,24 +77,38 @@ * it has to be rounded to sector size */ #define CONFIG_ENV_SIZE 0x20000 /* 128k */ -#define CONFIG_ENV_ADDR 0x60000 -#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ +#define CONFIG_ENV_OFFSET 0xE0000 /* env starts here */ /* * Default environment variables */ -#define CONFIG_BOOTCOMMAND "setenv ethact egiga0; " \ - "${x_bootcmd_ethernet}; setenv ethact egiga1; " \ - "${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\ - "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ - "bootm 0x6400000;" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "x_bootcmd_ethernet=ping 192.168.2.1\0" \ - "x_bootcmd_usb=usb start\0" \ - "x_bootcmd_kernel=nand read.e 0x6400000 0x100000 0x400000\0" \ - "x_bootargs=console=ttyS0,115200\0" \ - "x_bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0" +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ + "ubi part root; " \ + "ubifsmount ubi:rootfs; " \ + "ubifsload 0x800000 ${kernel}; " \ + "ubifsload 0x700000 ${fdt}; " \ + "ubifsumount; " \ + "fdt addr 0x700000; fdt resize; fdt chosen; " \ + "bootz 0x800000 - 0x700000" + +#define CONFIG_MTDPARTS \ + "mtdparts=orion_nand:" \ + "896K(uboot),128K(uboot_env)," \ + "-@1M(root)\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=console=ttyS0,115200\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts="CONFIG_MTDPARTS \ + "kernel=/boot/zImage\0" \ + "fdt=/boot/guruplug-server-plus.dtb\0" \ + "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0" + +#define MTDIDS_DEFAULT "nand0=orion_nand" + +#define MTDPARTS_DEFAULT \ + "mtdparts="CONFIG_MTDPARTS /* * Ethernet Driver configuration @@ -89,6 +125,20 @@ #define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET #endif /*CONFIG_MVSATA_IDE*/ +/* + * File system + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS + #define CONFIG_SYS_ALT_MEMTEST #endif /* _CONFIG_GURUPLUG_H */ -- cgit From 5a82d53c7878b7ee5f6b191e6e7b63c4bfa60b19 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 28 Aug 2014 13:31:02 +0200 Subject: ARM: zynq: Show board information by default Show board information in bootlog and enable it by default. Signed-off-by: Michal Simek --- include/configs/zynq-common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 87b4fffeb9..3a62ec75db 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -181,6 +181,7 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_AUTO_COMPLETE #define CONFIG_BOARD_LATE_INIT +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_LONGHELP #define CONFIG_CLOCKS #define CONFIG_CMD_CLK -- cgit From e9d69c1c717649cf6ee909139ccf9c04e82a7075 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 24 Sep 2014 14:55:03 +0200 Subject: ARM: zynq: Use CMD_FS_GENERIC Based on: "am335x_evm: Enable CMD_EXT4 and CMD_FS_GENERIC, add bootpart to env" (sha1: 73a27a84e58cb99b4e64ed6a35eab5bc61f44f29) Fix filesystem specific commands for loading. Signed-off-by: Michal Simek --- include/configs/zynq-common.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 3a62ec75db..f968e7666d 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -100,6 +100,7 @@ # define CONFIG_DOS_PARTITION # define CONFIG_CMD_EXT4 # define CONFIG_CMD_EXT4_WRITE +# define CONFIG_CMD_FS_GENERIC #endif #define CONFIG_SYS_I2C_ZYNQ @@ -159,14 +160,14 @@ "cp.b ${nor_flash_off} ${load_addr} ${fit_size} && " \ "bootm ${load_addr}\0" \ "sdboot=echo Copying FIT from SD to RAM... && " \ - "fatload mmc 0 ${load_addr} ${fit_image} && " \ + "load mmc 0 ${load_addr} ${fit_image} && " \ "bootm ${load_addr}\0" \ "jtagboot=echo TFTPing FIT to RAM... && " \ "tftpboot ${load_addr} ${fit_image} && " \ "bootm ${load_addr}\0" \ "usbboot=if usb start; then " \ "echo Copying FIT from USB to RAM... && " \ - "fatload usb 0 ${load_addr} ${fit_image} && " \ + "load usb 0 ${load_addr} ${fit_image} && " \ "bootm ${load_addr}\0" \ "fi\0" -- cgit From dd1c351ffe33dcbfa977f9b8760b8a1fd443fa11 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 13 Jan 2015 16:27:14 +0100 Subject: ARM: zynq: Group ethernet configuration options together No functional chagnes. Signed-off-by: Michal Simek --- include/configs/zynq-common.h | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index f968e7666d..cbafba1cc3 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -47,6 +47,11 @@ # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN # define CONFIG_PHYLIB # define CONFIG_PHY_MARVELL +# define CONFIG_BOOTP_SERVERIP +# define CONFIG_BOOTP_BOOTPATH +# define CONFIG_BOOTP_GATEWAY +# define CONFIG_BOOTP_HOSTNAME +# define CONFIG_BOOTP_MAY_FAIL #endif /* SPI */ @@ -122,12 +127,6 @@ # define CONFIG_SYS_EEPROM_SIZE 1024 /* Bytes */ #endif -#define CONFIG_BOOTP_SERVERIP -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_MAY_FAIL - /* Total Size of Environment Sector */ #define CONFIG_ENV_SIZE (128 << 10) -- cgit From f20b37f353a9cb9012076da8dedc13c5903caf42 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 28 Oct 2014 16:59:32 +0530 Subject: ARM: zynq: provide config option to select emio Dont send always emio value as zero for zynq_gem_initialize send it based on config. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- include/configs/zynq-common.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index cbafba1cc3..0359e3de91 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -52,6 +52,12 @@ # define CONFIG_BOOTP_GATEWAY # define CONFIG_BOOTP_HOSTNAME # define CONFIG_BOOTP_MAY_FAIL +# if !defined(CONFIG_ZYNQ_GEM_EMIO0) +# define CONFIG_ZYNQ_GEM_EMIO0 0 +# endif +# if !defined(CONFIG_ZYNQ_GEM_EMIO1) +# define CONFIG_ZYNQ_GEM_EMIO1 0 +# endif #endif /* SPI */ -- cgit From 87f3dbdffca050b1721727cc9eab6bd066c341bd Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Mon, 25 Aug 2014 10:58:33 +0530 Subject: ARM: zynq: Enable DFU functionality in zynq Enable DFU functionality in zynq. This DFU functionality helps us to load linux images on to DDR and can boot linux using bootm. In order to load images the user should run dfu command "dfu 0 ram 0" from u-boot prompt and then send the images from host. The malloc size has been increased to match the DFU buffer requirements. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- include/configs/zynq-common.h | 49 +++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 47 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 0359e3de91..62adfc84af 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -101,6 +101,50 @@ # define CONFIG_USB_ULPI # define CONFIG_EHCI_IS_TDI # define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +# define CONFIG_CI_UDC /* ChipIdea CI13xxx UDC */ +# define CONFIG_USB_GADGET +# define CONFIG_USB_GADGET_DUALSPEED +# define CONFIG_USBDOWNLOAD_GADGET +# define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x600000 +# define DFU_DEFAULT_POLL_TIMEOUT 300 +# define CONFIG_DFU_FUNCTION +# define CONFIG_DFU_RAM +# define CONFIG_USB_GADGET_VBUS_DRAW 2 +# define CONFIG_G_DNL_VENDOR_NUM 0x03FD +# define CONFIG_G_DNL_PRODUCT_NUM 0x0300 +# define CONFIG_G_DNL_MANUFACTURER "Xilinx" +# define CONFIG_USB_GADGET +# define CONFIG_USB_CABLE_CHECK +# define CONFIG_CMD_DFU +# define DFU_ALT_INFO_RAM \ + "dfu_ram_info=" \ + "set dfu_alt_info " \ + "${kernel_image} ram 0x3000000 0x500000\\\\;" \ + "${devicetree_image} ram 0x2A00000 0x20000\\\\;" \ + "${ramdisk_image} ram 0x2000000 0x600000\0" \ + "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" + +# if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1) +# define CONFIG_DFU_MMC +# define DFU_ALT_INFO_MMC \ + "dfu_mmc_info=" \ + "set dfu_alt_info " \ + "${kernel_image} fat 0 1\\\\;" \ + "${devicetree_image} fat 0 1\\\\;" \ + "${ramdisk_image} fat 0 1\0" \ + "dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" +# define DFU_ALT_INFO \ + DFU_ALT_INFO_RAM \ + DFU_ALT_INFO_MMC +# else +# define DFU_ALT_INFO \ + DFU_ALT_INFO_RAM +# endif +#endif + +#if !defined(DFU_ALT_INFO) +# define DFU_ALT_INFO #endif #if defined(CONFIG_ZYNQ_SDHCI) || defined(CONFIG_ZYNQ_USB) @@ -174,7 +218,8 @@ "echo Copying FIT from USB to RAM... && " \ "load usb 0 ${load_addr} ${fit_image} && " \ "bootm ${load_addr}\0" \ - "fi\0" + "fi\0" \ + DFU_ALT_INFO #define CONFIG_BOOTCOMMAND "run $modeboot" #define CONFIG_BOOTDELAY 3 /* -1 to Disable autoboot */ @@ -205,7 +250,7 @@ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) -#define CONFIG_SYS_MALLOC_LEN 0x400000 +#define CONFIG_SYS_MALLOC_LEN 0xC00000 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ -- cgit From c4fa511425b4130b34d8ba407cca68e43addf694 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Mon, 8 Sep 2014 22:09:37 +0530 Subject: ARM: zynq: Add USB lthor download protocol support updated the zynq config to support the lthor download protocol. This lthor functionality helps us to load linux images on to DDR/MMC and can boot linux using bootm. In order to load images the user should run lthor command run "thor_ram" from u-boot prompt and then send the images from host using lthor utility. Define g_dnl_bind_fixup for zynq so that correct vendor and product ids assigned incase of DFU and lthor. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- include/configs/zynq-common.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 62adfc84af..2d28e89dd3 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -117,13 +117,16 @@ # define CONFIG_USB_GADGET # define CONFIG_USB_CABLE_CHECK # define CONFIG_CMD_DFU +# define CONFIG_CMD_THOR_DOWNLOAD +# define CONFIG_THOR_FUNCTION # define DFU_ALT_INFO_RAM \ "dfu_ram_info=" \ "set dfu_alt_info " \ "${kernel_image} ram 0x3000000 0x500000\\\\;" \ "${devicetree_image} ram 0x2A00000 0x20000\\\\;" \ "${ramdisk_image} ram 0x2000000 0x600000\0" \ - "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" + "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \ + "thor_ram=run dfu_ram_info && thordown 0 ram 0\0" # if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1) # define CONFIG_DFU_MMC @@ -133,7 +136,9 @@ "${kernel_image} fat 0 1\\\\;" \ "${devicetree_image} fat 0 1\\\\;" \ "${ramdisk_image} fat 0 1\0" \ - "dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" + "dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \ + "thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0" + # define DFU_ALT_INFO \ DFU_ALT_INFO_RAM \ DFU_ALT_INFO_MMC -- cgit From dc2884315d492b1eefd9d32443c1f0aa3c0a991e Mon Sep 17 00:00:00 2001 From: Anton Habegger Date: Thu, 22 Jan 2015 22:29:10 +0100 Subject: ubifs: Import atomic_long operations from Linux This commit is a preperation for a subsequent UBIFS commit which needs atomic_long operations. Therefor "include/asm-generic/atomic-long.h" is imported from 1860e37 Linux 3.15 Signed-off-by: Anton Habegger --- include/asm-generic/atomic-long.h | 260 ++++++++++++++++++++++++++++++++++++++ include/linux/compat.h | 1 - 2 files changed, 260 insertions(+), 1 deletion(-) create mode 100644 include/asm-generic/atomic-long.h (limited to 'include') diff --git a/include/asm-generic/atomic-long.h b/include/asm-generic/atomic-long.h new file mode 100644 index 0000000000..d0469ef2e3 --- /dev/null +++ b/include/asm-generic/atomic-long.h @@ -0,0 +1,260 @@ +#ifndef _ASM_GENERIC_ATOMIC_LONG_H +#define _ASM_GENERIC_ATOMIC_LONG_H +/* + * Copyright (C) 2005 Silicon Graphics, Inc. + * Christoph Lameter + * + * Allows to provide arch independent atomic definitions without the need to + * edit all arch specific atomic.h files. + */ + +#include + +/* + * Suppport for atomic_long_t + * + * Casts for parameters are avoided for existing atomic functions in order to + * avoid issues with cast-as-lval under gcc 4.x and other limitations that the + * macros of a platform may have. + */ + +#if BITS_PER_LONG == 64 + +typedef atomic64_t atomic_long_t; + +#define ATOMIC_LONG_INIT(i) ATOMIC64_INIT(i) + +static inline long atomic_long_read(atomic_long_t *l) +{ + atomic64_t *v = (atomic64_t *)l; + + return (long)atomic64_read(v); +} + +static inline void atomic_long_set(atomic_long_t *l, long i) +{ + atomic64_t *v = (atomic64_t *)l; + + atomic64_set(v, i); +} + +static inline void atomic_long_inc(atomic_long_t *l) +{ + atomic64_t *v = (atomic64_t *)l; + + atomic64_inc(v); +} + +static inline void atomic_long_dec(atomic_long_t *l) +{ + atomic64_t *v = (atomic64_t *)l; + + atomic64_dec(v); +} + +static inline void atomic_long_add(long i, atomic_long_t *l) +{ + atomic64_t *v = (atomic64_t *)l; + + atomic64_add(i, v); +} + +static inline void atomic_long_sub(long i, atomic_long_t *l) +{ + atomic64_t *v = (atomic64_t *)l; + + atomic64_sub(i, v); +} + +static inline int atomic_long_sub_and_test(long i, atomic_long_t *l) +{ + atomic64_t *v = (atomic64_t *)l; + + return atomic64_sub_and_test(i, v); +} + +static inline int atomic_long_dec_and_test(atomic_long_t *l) +{ + atomic64_t *v = (atomic64_t *)l; + + return atomic64_dec_and_test(v); +} + +static inline int atomic_long_inc_and_test(atomic_long_t *l) +{ + atomic64_t *v = (atomic64_t *)l; + + return atomic64_inc_and_test(v); +} + +static inline int atomic_long_add_negative(long i, atomic_long_t *l) +{ + atomic64_t *v = (atomic64_t *)l; + + return atomic64_add_negative(i, v); +} + +static inline long atomic_long_add_return(long i, atomic_long_t *l) +{ + atomic64_t *v = (atomic64_t *)l; + + return (long)atomic64_add_return(i, v); +} + +static inline long atomic_long_sub_return(long i, atomic_long_t *l) +{ + atomic64_t *v = (atomic64_t *)l; + + return (long)atomic64_sub_return(i, v); +} + +static inline long atomic_long_inc_return(atomic_long_t *l) +{ + atomic64_t *v = (atomic64_t *)l; + + return (long)atomic64_inc_return(v); +} + +static inline long atomic_long_dec_return(atomic_long_t *l) +{ + atomic64_t *v = (atomic64_t *)l; + + return (long)atomic64_dec_return(v); +} + +static inline long atomic_long_add_unless(atomic_long_t *l, long a, long u) +{ + atomic64_t *v = (atomic64_t *)l; + + return (long)atomic64_add_unless(v, a, u); +} + +#define atomic_long_inc_not_zero(l) atomic64_inc_not_zero((atomic64_t *)(l)) + +#define atomic_long_cmpxchg(l, old, new) \ + (atomic64_cmpxchg((atomic64_t *)(l), (old), (new))) +#define atomic_long_xchg(v, new) \ + (atomic64_xchg((atomic64_t *)(v), (new))) + +#else /* BITS_PER_LONG == 64 */ + +typedef atomic_t atomic_long_t; + +#define ATOMIC_LONG_INIT(i) ATOMIC_INIT(i) +static inline long atomic_long_read(atomic_long_t *l) +{ + atomic_t *v = (atomic_t *)l; + + return (long)atomic_read(v); +} + +static inline void atomic_long_set(atomic_long_t *l, long i) +{ + atomic_t *v = (atomic_t *)l; + + atomic_set(v, i); +} + +static inline void atomic_long_inc(atomic_long_t *l) +{ + atomic_t *v = (atomic_t *)l; + + atomic_inc(v); +} + +static inline void atomic_long_dec(atomic_long_t *l) +{ + atomic_t *v = (atomic_t *)l; + + atomic_dec(v); +} + +static inline void atomic_long_add(long i, atomic_long_t *l) +{ + atomic_t *v = (atomic_t *)l; + + atomic_add(i, v); +} + +static inline void atomic_long_sub(long i, atomic_long_t *l) +{ + atomic_t *v = (atomic_t *)l; + + atomic_sub(i, v); +} + +#ifndef __UBOOT__ +static inline int atomic_long_sub_and_test(long i, atomic_long_t *l) +{ + atomic_t *v = (atomic_t *)l; + + return atomic_sub_and_test(i, v); +} + +static inline int atomic_long_dec_and_test(atomic_long_t *l) +{ + atomic_t *v = (atomic_t *)l; + + return atomic_dec_and_test(v); +} + +static inline int atomic_long_inc_and_test(atomic_long_t *l) +{ + atomic_t *v = (atomic_t *)l; + + return atomic_inc_and_test(v); +} + +static inline int atomic_long_add_negative(long i, atomic_long_t *l) +{ + atomic_t *v = (atomic_t *)l; + + return atomic_add_negative(i, v); +} + +static inline long atomic_long_add_return(long i, atomic_long_t *l) +{ + atomic_t *v = (atomic_t *)l; + + return (long)atomic_add_return(i, v); +} + +static inline long atomic_long_sub_return(long i, atomic_long_t *l) +{ + atomic_t *v = (atomic_t *)l; + + return (long)atomic_sub_return(i, v); +} + +static inline long atomic_long_inc_return(atomic_long_t *l) +{ + atomic_t *v = (atomic_t *)l; + + return (long)atomic_inc_return(v); +} + +static inline long atomic_long_dec_return(atomic_long_t *l) +{ + atomic_t *v = (atomic_t *)l; + + return (long)atomic_dec_return(v); +} + +static inline long atomic_long_add_unless(atomic_long_t *l, long a, long u) +{ + atomic_t *v = (atomic_t *)l; + + return (long)atomic_add_unless(v, a, u); +} + +#define atomic_long_inc_not_zero(l) atomic_inc_not_zero((atomic_t *)(l)) + +#define atomic_long_cmpxchg(l, old, new) \ + (atomic_cmpxchg((atomic_t *)(l), (old), (new))) +#define atomic_long_xchg(v, new) \ + (atomic_xchg((atomic_t *)(v), (new))) +#endif /* __UBOOT__ */ + +#endif /* BITS_PER_LONG == 64 */ + +#endif /* _ASM_GENERIC_ATOMIC_LONG_H */ diff --git a/include/linux/compat.h b/include/linux/compat.h index b40133cb3c..6eac17f0b6 100644 --- a/include/linux/compat.h +++ b/include/linux/compat.h @@ -262,7 +262,6 @@ typedef struct { /* from include/linux/types.h */ -typedef int atomic_t; /** * struct callback_head - callback structure for use with RCU and task_work * @next: next update requests in a list -- cgit From ba21a453a58fc02b890f4064b293b1cb09fe7484 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Thu, 29 Jan 2015 10:38:20 +0000 Subject: malta: IDE support This patch adds IDE support to the MIPS Malta board. The IDE controller is enabled after probing the PCI bus and otherwise just makes use of U-boot generic IDE support. Signed-off-by: Paul Burton Cc: Daniel Schwierzeck --- include/configs/malta.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'include') diff --git a/include/configs/malta.h b/include/configs/malta.h index 684d249590..ed5da6cd73 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -106,6 +106,16 @@ #define CONFIG_ENV_ADDR \ (CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE) +/* + * IDE/ATA + */ +#define CONFIG_SYS_IDE_MAXBUS 1 +#define CONFIG_SYS_IDE_MAXDEVICE 2 +#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01f0 +#define CONFIG_SYS_ATA_DATA_OFFSET 0 +#define CONFIG_SYS_ATA_REG_OFFSET 0 + /* * Commands */ @@ -118,6 +128,7 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_IDE #define CONFIG_CMD_PCI #define CONFIG_CMD_PING -- cgit From a3bdaacaf61deb74565d1b9e9ad3497b6f7a4051 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Thu, 29 Jan 2015 10:38:22 +0000 Subject: malta: enable HUSH parser The malta board is used for development and thus the shell is interacted with often. Enable HUSH to make the experience a little more pleasant. Signed-off-by: Paul Burton Cc: Daniel Schwierzeck --- include/configs/malta.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/malta.h b/include/configs/malta.h index ed5da6cd73..4e64cc968d 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -71,6 +71,7 @@ sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_HUSH_PARSER #define CONFIG_AUTO_COMPLETE #define CONFIG_CMDLINE_EDITING -- cgit From d4d774e00e7232b524ddb20d992c5b12d84e3ef2 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Thu, 29 Jan 2015 10:38:23 +0000 Subject: malta: enable ELF loading The ability to load ELF files is sometimes useful on Malta boards, particularly for use with small embedded applications. Enable the loadelf command in the malta config. Signed-off-by: Paul Burton Cc: Daniel Schwierzeck --- include/configs/malta.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/malta.h b/include/configs/malta.h index 4e64cc968d..354672ecf8 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -129,6 +129,7 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF #define CONFIG_CMD_IDE #define CONFIG_CMD_PCI #define CONFIG_CMD_PING -- cgit From 6e721bdb541e313528ffebb8c88532b41ae6df7c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 13 Jan 2015 16:42:53 -0500 Subject: am335x_evm: Enable CONFIG_NAND_OMAP_GPMC_PREFETCH Signed-off-by: Tom Rini --- include/configs/am335x_evm.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 0004750518..d5e84ab46f 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -239,6 +239,7 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) /* NAND: driver related configs */ #define CONFIG_NAND_OMAP_GPMC +#define CONFIG_NAND_OMAP_GPMC_PREFETCH #define CONFIG_NAND_OMAP_ELM #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ -- cgit From 8dcd1b720e5c44bb4ca6f41181f3b937ae6e08c1 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Thu, 15 Jan 2015 10:26:36 +0100 Subject: Nokia RX-51: Use generic board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Generic board with #define CONFIG_SYS_GENERIC_BOARD is working fine. There is no visible difference between legacy and generic board code. Signed-off-by: Pali Rohár Acked-by: Pavel Machek --- include/configs/nokia_rx51.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 982b689f3c..46fc91e5e1 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -28,6 +28,7 @@ #define CONFIG_OMAP3_RX51 /* working with RX51 */ #define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */ #define CONFIG_OMAP_COMMON +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_MACH_TYPE MACH_TYPE_NOKIA_RX51 -- cgit From f3b4bc458de3285a04c5f60df6372ad5ca79fa60 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Wed, 28 Jan 2015 15:01:32 +0100 Subject: OMAP3: igep00x0: Fix boot hang and add support for status LED. Use the STATUS_LED APIs for indicating a boot progress instead of show_boot_progress. This patch also fixes a problem introduced with commit b3f4ca1135 (dm: omap3: Move to driver model for GPIO and serial). After that commit the board doesn't boot. Looks like the problem is the gpio_request call inside the function show_boot_progress. Signed-off-by: Enric Balletbo i Serra --- include/configs/omap3_igep00x0.h | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index b2b3750c1e..6295ec505f 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -29,11 +29,21 @@ #define CONFIG_REVISION_TAG 1 -/* define to enable boot progress via leds */ -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \ - (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) -#define CONFIG_SHOW_BOOT_PROGRESS +/* Status LED */ +#define CONFIG_STATUS_LED +#define CONFIG_BOARD_SPECIFIC_LED +#define CONFIG_GPIO_LED +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) +#define RED_LED_GPIO 27 +#endif +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) +#define RED_LED_GPIO 16 #endif +#define RED_LED_DEV 0 +#define STATUS_LED_BIT RED_LED_GPIO +#define STATUS_LED_STATE STATUS_LED_ON +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) +#define STATUS_LED_BOOT RED_LED_DEV /* GPIO banks */ #define CONFIG_OMAP3_GPIO_3 /* GPIO64 .. 95 is in GPIO bank 3 */ -- cgit From 1a1ad8e0903ec916d1e3ef8c18fa335d765a4342 Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Mon, 5 Jan 2015 18:13:36 +0100 Subject: fs: Add command to retrieve the filesystem type New command to determine the filesystem type of a given partition. Optionally stores the filesystem type in a environment variable. Signed-off-by: Sjoerd Simons Reviewed-by: Stephen Warren --- include/fs.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/fs.h b/include/fs.h index ffb6ce7ada..fd1e4ab1c0 100644 --- a/include/fs.h +++ b/include/fs.h @@ -109,4 +109,10 @@ int do_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], int do_fs_uuid(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], int fstype); +/* + * Determine the type of the specified filesystem and print it. Optionally it is + * possible to store the type directly in env. + */ +int do_fs_type(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); + #endif /* _FS_H */ -- cgit From 735b1cfeb2308d9114af1140b703be91b604c09e Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Mon, 5 Jan 2015 18:13:38 +0100 Subject: config_distro_bootcmd: Scan all partitions for boot files Not all devices use the convention that the boot scripts are on the first partition. For example on chromebooks it seems common for the first two partitions to be ChromeOS kernel partitions. So instead of just the first partition scan all partitions on a device with a filesystem u-boot can recognize. Signed-off-by: Sjoerd Simons --- include/config_distro_bootcmd.h | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index becbe3fa7c..676b351017 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -13,7 +13,7 @@ #define BOOTENV_SHARED_BLKDEV_BODY(devtypel) \ "if " #devtypel " dev ${devnum}; then " \ "setenv devtype " #devtypel "; " \ - "run scan_dev_for_boot; " \ + "run scan_dev_for_boot_part; " \ "fi\0" #define BOOTENV_SHARED_BLKDEV(devtypel) \ @@ -155,7 +155,6 @@ "boot_prefixes=/ /boot/\0" \ "boot_scripts=boot.scr.uimg boot.scr\0" \ BOOTENV_BOOT_TARGETS \ - "bootpart=1\0" \ \ "boot_extlinux=" \ "sysboot ${devtype} ${devnum}:${bootpart} any " \ @@ -186,12 +185,21 @@ "done\0" \ \ "scan_dev_for_boot=" \ - "echo Scanning ${devtype} ${devnum}...; " \ + "echo Scanning ${devtype} ${devnum}:${bootpart}...; " \ "for prefix in ${boot_prefixes}; do " \ "run scan_dev_for_extlinux; " \ "run scan_dev_for_scripts; " \ "done\0" \ \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "for bootpart in ${devplist}; do " \ + "if fstype ${devtype} ${devnum}:${bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + \ BOOT_TARGET_DEVICES(BOOTENV_DEV) \ \ "bootcmd=" BOOTENV_SET_SCSI_NEED_INIT \ -- cgit From 453c6cc19aaf4f03bbf4ef03493732a39d3780db Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Mon, 5 Jan 2015 18:13:39 +0100 Subject: distro_distro_bootcmd: use CONFIG_BOOTCOMMAND instead of setting bootcmd= Move the bootcmd commands into a seperate distro_bootcmd environment variable. Allowing a user to easily launch the distro boot sequence if the default bootcmd did not default to distro boot commands. Also set CONFIG_BOOTCOMMAND to "run distro_bootcmd" if it hasn't been configured yet rather then putting it directly in the environment. This allows boards to make the distro boot commands available without necessarily default to them or to use them as a fallback after running some board specific commands instead. Signed-off-by: Sjoerd Simons Reviewed-by: Stephen Warren --- include/config_distro_bootcmd.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index 676b351017..90ab21a727 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -202,9 +202,13 @@ \ BOOT_TARGET_DEVICES(BOOTENV_DEV) \ \ - "bootcmd=" BOOTENV_SET_SCSI_NEED_INIT \ + "distro_bootcmd=" BOOTENV_SET_SCSI_NEED_INIT \ "for target in ${boot_targets}; do " \ "run bootcmd_${target}; " \ "done\0" +#ifndef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "run distro_bootcmd" +#endif + #endif /* _CONFIG_CMD_DISTRO_BOOTCMD_H */ -- cgit From 44f145fd81f73a5c5adc490b0da91b80a4c7790a Mon Sep 17 00:00:00 2001 From: Guilherme Maciel Ferreira Date: Thu, 15 Jan 2015 02:39:59 -0200 Subject: linker_lists: fix misspellings Signed-off-by: Guilherme Maciel Ferreira --- include/linker_lists.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/linker_lists.h b/include/linker_lists.h index d37fba44dc..940c871281 100644 --- a/include/linker_lists.h +++ b/include/linker_lists.h @@ -23,7 +23,7 @@ /** * A linker list is constructed by grouping together linker input - * sections, each containning one entry of the list. Each input section + * sections, each containing one entry of the list. Each input section * contains a constant initialized variable which holds the entry's * content. Linker list input sections are constructed from the list * and entry names, plus a prefix which allows grouping all lists @@ -39,7 +39,7 @@ * This ensures uniqueness for both input section and C variable name. * * Note that the names differ only in the first character, "." for the - * setion and "_" for the variable, so that the linker cannot confuse + * section and "_" for the variable, so that the linker cannot confuse * section and symbol names. From now on, both names will be referred * to as * -- cgit From 39931f966adaeadd66dc7a905f7dddb93f66bac3 Mon Sep 17 00:00:00 2001 From: Guilherme Maciel Ferreira Date: Thu, 15 Jan 2015 02:54:42 -0200 Subject: dumpimage: fit: extract FIT images The dumpimage is able to extract components contained in a FIT image: $ ./dumpimage -T flat_dt -i CONTAINER.ITB -p INDEX FILE The CONTAINER.ITB is a regular FIT container file. The INDEX is the poisition of the sub-image to be retrieved, and FILE is the file (path+name) to save the extracted sub-image. For example, given the following kernel.its to build a kernel.itb: /dts-v1/; / { ... images { kernel@1 { description = "Kernel 2.6.32-34"; data = /incbin/("/boot/vmlinuz-2.6.32-34-generic"); type = "kernel"; arch = "ppc"; os = "linux"; compression = "gzip"; load = <00000000>; entry = <00000000>; hash@1 { algo = "md5"; }; }; ... }; ... }; The dumpimage can extract the 'kernel@1' node through the following command: $ ./dumpimage -T flat_dt -i kernel.itb -p 0 kernel Extracted: Image 0 (kernel@1) Description: Kernel 2.6.32-34 Created: Wed Oct 22 15:50:26 2014 Type: Kernel Image Compression: gzip compressed Data Size: 4040128 Bytes = 3945.44 kB = 3.85 MB Architecture: PowerPC OS: Linux Load Address: 0x00000000 Entry Point: 0x00000000 Hash algo: md5 Hash value: 22352ad39bdc03e2e50f9cc28c1c3652 Which results in the file 'kernel' being exactly the same as '/boot/vmlinuz-2.6.32-34-generic'. Signed-off-by: Guilherme Maciel Ferreira --- include/image.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/image.h b/include/image.h index ee3afe3567..d8618962fb 100644 --- a/include/image.h +++ b/include/image.h @@ -751,6 +751,7 @@ int fit_parse_conf(const char *spec, ulong addr_curr, int fit_parse_subimage(const char *spec, ulong addr_curr, ulong *addr, const char **image_name); +int fit_get_subimage_count(const void *fit, int images_noffset); void fit_print_contents(const void *fit); void fit_image_print(const void *fit, int noffset, const char *p); -- cgit From 233e42a985ce1e2ed2c33fbc2bee525a5cacdda9 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 13 Jan 2015 12:44:39 +0900 Subject: ARM: UniPhier: enable CONFIG_I2C_EEPROM Signed-off-by: Masahiro Yamada Acked-by: Simon Glass --- include/configs/uniphier.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 5a53c506c3..9ad47f6933 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -43,6 +43,9 @@ #define CONFIG_SDRAM1_SIZE 0x10000000 #endif +#define CONFIG_I2C_EEPROM +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 + /* * Support card address map */ -- cgit From 0365ffcc0bd6335afb0c866423f3fe401b28ffaa Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 14 Jan 2015 17:07:05 +0900 Subject: generic-board: show model name in board_init_f() too The common/board_r.c has show_model_r() to display the model name if the DTB has a "model" property. It sounds useful to have a similar function in common/board_f.c too because most of the boards show their board name before relocation. Instead of implementing the same function in both common/board_f.c and common/board_r.c, let's split it up into common/show_board_info.c. Signed-off-by: Masahiro Yamada Acked-by: Simon Glass --- include/common.h | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/common.h b/include/common.h index 4b3e0d3bbd..97c8f79fc7 100644 --- a/include/common.h +++ b/include/common.h @@ -228,12 +228,13 @@ int run_command_list(const char *cmd, int len, int flag); extern char console_buffer[]; /* arch/$(ARCH)/lib/board.c */ -void board_init_f(ulong); -void board_init_r (gd_t *, ulong) __attribute__ ((noreturn)); -int checkboard (void); -int checkflash (void); -int checkdram (void); -int last_stage_init(void); +void board_init_f(ulong); +void board_init_r(gd_t *, ulong) __attribute__ ((noreturn)); +int checkboard(void); +int show_board_info(void); +int checkflash(void); +int checkdram(void); +int last_stage_init(void); extern ulong monitor_flash_len; int mac_read_from_eeprom(void); extern u8 __dtb_dt_begin[]; /* embedded device tree blob */ -- cgit From 57068a7aeb19fee06933986926eaea3cf0128f16 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 5 Jan 2015 20:05:26 -0700 Subject: dm: fdt: Add a function to decode phandles with arguments For GPIOs and other functions we want to look up a phandle and then decode a list of arguments for that phandle. Each phandle can have a different number of arguments, specified by a property in the target node. This is the "#gpio-cells" property for GPIOs. Add a function to provide this feature, taken modified from Linux 3.18. Signed-off-by: Simon Glass --- include/fdtdec.h | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) (limited to 'include') diff --git a/include/fdtdec.h b/include/fdtdec.h index 8c2bd21b2d..8cf88dd10b 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -178,6 +178,59 @@ enum fdt_compat_id { COMPAT_COUNT, }; +#define MAX_PHANDLE_ARGS 16 +struct fdtdec_phandle_args { + int node; + int args_count; + uint32_t args[MAX_PHANDLE_ARGS]; +}; + +/** + * fdtdec_parse_phandle_with_args() - Find a node pointed by phandle in a list + * + * This function is useful to parse lists of phandles and their arguments. + * + * Example: + * + * phandle1: node1 { + * #list-cells = <2>; + * } + * + * phandle2: node2 { + * #list-cells = <1>; + * } + * + * node3 { + * list = <&phandle1 1 2 &phandle2 3>; + * } + * + * To get a device_node of the `node2' node you may call this: + * fdtdec_parse_phandle_with_args(blob, node3, "list", "#list-cells", 0, 1, + * &args); + * + * (This function is a modified version of __of_parse_phandle_with_args() from + * Linux 3.18) + * + * @blob: Pointer to device tree + * @src_node: Offset of device tree node containing a list + * @list_name: property name that contains a list + * @cells_name: property name that specifies the phandles' arguments count, + * or NULL to use @cells_count + * @cells_count: Cell count to use if @cells_name is NULL + * @index: index of a phandle to parse out + * @out_args: optional pointer to output arguments structure (will be filled) + * @return 0 on success (with @out_args filled out if not NULL), -ENOENT if + * @list_name does not exist, a phandle was not found, @cells_name + * could not be found, the arguments were truncated or there were too + * many arguments. + * + */ +int fdtdec_parse_phandle_with_args(const void *blob, int src_node, + const char *list_name, + const char *cells_name, + int cell_count, int index, + struct fdtdec_phandle_args *out_args); + /* GPIOs are numbered from 0 */ enum { FDT_GPIO_NONE = -1U, /* an invalid GPIO used to end our list */ -- cgit From ae7123f876357a81fc4c393239a378f1058cad5e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 5 Jan 2015 20:05:27 -0700 Subject: dm: gpio: Add a native driver model API So far driver model's GPIO uclass just implements the existing GPIO API. This has some limitations: - it requires manual device tree munging to support GPIOs in device tree (fdtdec_get_gpio() and friends) - it does not understand polarity - it is somewhat slower since we must scan for the GPIO device each time - Global GPIO numbering can change if other GPIO drivers are probed - it requires extra steps to set the GPIO direction and value The new functions have a dm_ prefix where necessary to avoid name conflicts but we can remove that when it is no-longer needed. The new struct gpio_desc holds all required information about the GPIO. For now this is intended to be stored by the client requesting the GPIO, but in future it might be brought into the uclass in some way. With these changes the old GPIO API still works, and uses the driver model API underneath. Signed-off-by: Simon Glass --- include/asm-generic/gpio.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'include') diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index 36a36c64b8..a827a56f5e 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -95,6 +95,22 @@ enum gpio_func_t { struct udevice; +struct gpio_desc { + struct udevice *dev; /* Device, NULL for invalid GPIO */ + unsigned long flags; +#define GPIOD_REQUESTED (1 << 0) /* Requested/claimed */ +#define GPIOD_IS_OUT (1 << 1) /* GPIO is an output */ +#define GPIOD_IS_IN (1 << 2) /* GPIO is an output */ +#define GPIOD_ACTIVE_LOW (1 << 3) /* value has active low */ +#define GPIOD_IS_OUT_ACTIVE (1 << 4) /* set output active */ + + uint offset; /* GPIO offset within the device */ + /* + * We could consider adding the GPIO label in here. Possibly we could + * use this structure for internal GPIO information. + */ +}; + /** * gpio_get_status() - get the current GPIO status as a string * -- cgit From 0dac4d51f50e9252dbc00075cf65eeba57017926 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 5 Jan 2015 20:05:28 -0700 Subject: dm: gpio: Add a driver GPIO translation method Only the GPIO driver knows about the full GPIO device tree binding used by a device. Add a method to allow the driver to provide this information to the uclass, including the GPIO offset within the device and flags such as the polarity. Signed-off-by: Simon Glass --- include/asm-generic/gpio.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'include') diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index a827a56f5e..c08c96340a 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -171,6 +171,8 @@ int gpio_get_raw_function(struct udevice *dev, int offset, const char **namep); int gpio_requestf(unsigned gpio, const char *fmt, ...) __attribute__ ((format (__printf__, 2, 3))); +struct fdtdec_phandle_args; + /** * struct struct dm_gpio_ops - Driver model GPIO operations * @@ -214,6 +216,33 @@ struct dm_gpio_ops { * @return current function - GPIOF_... */ int (*get_function)(struct udevice *dev, unsigned offset); + + /** + * xlate() - Translate phandle arguments into a GPIO description + * + * This function should set up the fields in desc according to the + * information in the arguments. The uclass will have set up: + * + * @desc->dev to @dev + * @desc->flags to 0 + * @desc->offset to the value of the first argument in args, if any, + * otherwise -1 (which is invalid) + * + * This method is optional so if the above defaults suit it can be + * omitted. Typical behaviour is to set up the GPIOD_ACTIVE_LOW flag + * in desc->flags. + * + * Note that @dev is passed in as a parameter to follow driver model + * uclass conventions, even though it is already available as + * desc->dev. + * + * @dev: GPIO device + * @desc: Place to put GPIO description + * @args: Arguments provided in descripion + * @return 0 if OK, -ve on error + */ + int (*xlate)(struct udevice *dev, struct gpio_desc *desc, + struct fdtdec_phandle_args *args); }; /** -- cgit From 3669e0e759118fed3d371e2427b4b47d3969bfd0 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 5 Jan 2015 20:05:29 -0700 Subject: dm: gpio: Add better functions to request GPIOs At present U-Boot sort-of supports the standard way of reading GPIOs from device tree nodes, but the support is incomplete, a bit clunky and only works for GPIO bindings where #gpio-cells is 2. Add new functions to request GPIOs, taking full account of the device tree binding. These permit requesting a GPIO with a simple call like: gpio_request_by_name(dev, "cd-gpios", 0, &desc, GPIOD_IS_IN); This will request the GPIO, looking at the device's node which might be this, for example: cd-gpios = <&gpio TEGRA_GPIO(B, 3) GPIO_ACTIVE_LOW>; The GPIO will be set to input mode in this case and polarity will be honoured by the GPIO calls. It is also possible to request and free a list of GPIOs. Signed-off-by: Simon Glass --- include/asm-generic/gpio.h | 199 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 199 insertions(+) (limited to 'include') diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index c08c96340a..26534150f1 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -111,6 +111,18 @@ struct gpio_desc { */ }; +/** + * dm_gpio_is_valid() - Check if a GPIO is gpio_is_valie + * + * @desc: GPIO description containing device, offset and flags, + * previously returned by gpio_request_by_name() + * @return true if valid, false if not + */ +static inline bool dm_gpio_is_valid(struct gpio_desc *desc) +{ + return desc->dev != NULL; +} + /** * gpio_get_status() - get the current GPIO status as a string * @@ -313,4 +325,191 @@ int gpio_lookup_name(const char *name, struct udevice **devp, */ unsigned gpio_get_values_as_int(const int *gpio_list); +/** + * gpio_request_by_name() - Locate and request a GPIO by name + * + * This operates by looking up the given list name in the device (device + * tree property) and requesting the GPIO for use. The property must exist + * in @dev's node. + * + * Use @flags to specify whether the GPIO should be an input or output. In + * principle this can also come from the device tree binding but most + * bindings don't provide this information. Specifically, when the GPIO uclass + * calls the xlate() method, it can return default flags, which are then + * ORed with this @flags. + * + * If we find that requesting the GPIO is not always needed we could add a + * new function or a new GPIOD_NO_REQUEST flag. + * + * At present driver model has no reference counting so if one device + * requests a GPIO which subsequently is unbound, the @desc->dev pointer + * will be invalid. However this will only happen if the GPIO device is + * unbound, not if it is removed, so this seems like a reasonable limitation + * for now. There is no real use case for unbinding drivers in normal + * operation. + * + * The device tree binding is doc/device-tree-bindings/gpio/gpio.txt in + * generate terms and each specific device may add additional details in + * a binding file in the same directory. + * + * @dev: Device requesting the GPIO + * @list_name: Name of GPIO list (e.g. "board-id-gpios") + * @index: Index number of the GPIO in that list use request (0=first) + * @desc: Returns GPIO description information. If there is no such + * GPIO, dev->dev will be NULL. + * @flags: Indicates the GPIO input/output settings (GPIOD_...) + * @return 0 if OK, -ENOENT if the GPIO does not exist, -EINVAL if there is + * something wrong with the list, or other -ve for another error (e.g. + * -EBUSY if a GPIO was already requested) + */ +int gpio_request_by_name(struct udevice *dev, const char *list_name, + int index, struct gpio_desc *desc, int flags); + +/** + * gpio_request_list_by_name() - Request a list of GPIOs + * + * Reads all the GPIOs from a list and requetss them. See + * gpio_request_by_name() for additional details. Lists should not be + * misused to hold unrelated or optional GPIOs. They should only be used + * for things like parallel data lines. A zero phandle terminates the list + * the list. + * + * This function will either succeed, and request all GPIOs in the list, or + * fail and request none (it will free already-requested GPIOs in case of + * an error part-way through). + * + * @dev: Device requesting the GPIO + * @list_name: Name of GPIO list (e.g. "board-id-gpios") + * @desc_list: Returns a list of GPIO description information + * @max_count: Maximum number of GPIOs to return (@desc_list must be at least + * this big) + * @flags: Indicates the GPIO input/output settings (GPIOD_...) + * @return number of GPIOs requested, or -ve on error + */ +int gpio_request_list_by_name(struct udevice *dev, const char *list_name, + struct gpio_desc *desc_list, int max_count, + int flags); + +/** + * gpio_get_list_count() - Returns the number of GPIOs in a list + * + * Counts the GPIOs in a list. See gpio_request_by_name() for additional + * details. + * + * @dev: Device requesting the GPIO + * @list_name: Name of GPIO list (e.g. "board-id-gpios") + * @return number of GPIOs (0 for an empty property) or -ENOENT if the list + * does not exist + */ +int gpio_get_list_count(struct udevice *dev, const char *list_name); + +/** + * gpio_request_by_name_nodev() - request GPIOs without a device + * + * This is a version of gpio_request_list_by_name() that does not use a + * device. Avoid it unless the caller is not yet using driver model + */ +int gpio_request_by_name_nodev(const void *blob, int node, + const char *list_name, + int index, struct gpio_desc *desc, int flags); + +/** + * gpio_request_list_by_name_nodev() - request GPIOs without a device + * + * This is a version of gpio_request_list_by_name() that does not use a + * device. Avoid it unless the caller is not yet using driver model + */ +int gpio_request_list_by_name_nodev(const void *blob, int node, + const char *list_name, + struct gpio_desc *desc_list, int max_count, + int flags); + +/** + * dm_gpio_free() - Free a single GPIO + * + * This frees a single GPIOs previously returned from gpio_request_by_name(). + * + * @dev: Device which requested the GPIO + * @desc: GPIO to free + * @return 0 if OK, -ve on error + */ +int dm_gpio_free(struct udevice *dev, struct gpio_desc *desc); + +/** + * gpio_free_list() - Free a list of GPIOs + * + * This frees a list of GPIOs previously returned from + * gpio_request_list_by_name(). + * + * @dev: Device which requested the GPIOs + * @desc: List of GPIOs to free + * @count: Number of GPIOs in the list + * @return 0 if OK, -ve on error + */ +int gpio_free_list(struct udevice *dev, struct gpio_desc *desc, int count); + +/** + * gpio_free_list_nodev() - free GPIOs without a device + * + * This is a version of gpio_free_list() that does not use a + * device. Avoid it unless the caller is not yet using driver model + */ +int gpio_free_list_nodev(struct gpio_desc *desc, int count); + +/** + * dm_gpio_get_value() - Get the value of a GPIO + * + * This is the driver model version of the existing gpio_get_value() function + * and should be used instead of that. + * + * For now, these functions have a dm_ prefix since they conflict with + * existing names. + * + * @desc: GPIO description containing device, offset and flags, + * previously returned by gpio_request_by_name() + * @return GPIO value (0 for inactive, 1 for active) or -ve on error + */ +int dm_gpio_get_value(struct gpio_desc *desc); + +int dm_gpio_set_value(struct gpio_desc *desc, int value); + +/** + * dm_gpio_set_dir() - Set the direction for a GPIO + * + * This sets up the direction according tot the provided flags. It will do + * nothing unless the direction is actually specified. + * + * @desc: GPIO description containing device, offset and flags, + * previously returned by gpio_request_by_name() + * @return 0 if OK, -ve on error + */ +int dm_gpio_set_dir(struct gpio_desc *desc); + +/** + * dm_gpio_set_dir_flags() - Set direction using specific flags + * + * This is like dm_gpio_set_dir() except that the flags value is provided + * instead of being used from desc->flags. This is needed because in many + * cases the GPIO description does not include direction information. + * Note that desc->flags is updated by this function. + * + * @desc: GPIO description containing device, offset and flags, + * previously returned by gpio_request_by_name() + * @flags: New flags to use + * @return 0 if OK, -ve on error, in which case desc->flags is not updated + */ +int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags); + +/** + * gpio_get_number() - Get the global GPIO number of a GPIO + * + * This should only be used for debugging or interest. It returns the nummber + * that should be used for gpio_get_value() etc. to access this GPIO. + * + * @desc: GPIO description containing device, offset and flags, + * previously returned by gpio_request_by_name() + * @return GPIO number, or -ve if not found + */ +int gpio_get_number(struct gpio_desc *desc); + #endif /* _ASM_GENERIC_GPIO_H_ */ -- cgit From 5d1c17e9a5803af9c65966e469437735ac29659e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 5 Jan 2015 20:05:30 -0700 Subject: dm: gpio: Mark the old GPIO API deprecated Add a deprecation notice to each function so that it is more obvious that we are moving GPIOs to driver model. Signed-off-by: Simon Glass --- include/asm-generic/gpio.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'include') diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index 26534150f1..3b96b8209a 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -10,6 +10,15 @@ /* * Generic GPIO API for U-Boot * + * -- + * NB: This is deprecated. Please use the driver model functions instead: + * + * - gpio_request_by_name() + * - dm_gpio_get_value() etc. + * + * For now we need a dm_ prefix on some functions to avoid name collision. + * -- + * * GPIOs are numbered from 0 to GPIO_COUNT-1 which value is defined * by the SOC/architecture. * @@ -26,6 +35,7 @@ */ /** + * @deprecated Please use driver model instead * Request a GPIO. This should be called before any of the other functions * are used on this GPIO. * @@ -39,6 +49,7 @@ int gpio_request(unsigned gpio, const char *label); /** + * @deprecated Please use driver model instead * Stop using the GPIO. This function should not alter pin configuration. * * @param gpio GPIO number @@ -47,6 +58,7 @@ int gpio_request(unsigned gpio, const char *label); int gpio_free(unsigned gpio); /** + * @deprecated Please use driver model instead * Make a GPIO an input. * * @param gpio GPIO number @@ -55,6 +67,7 @@ int gpio_free(unsigned gpio); int gpio_direction_input(unsigned gpio); /** + * @deprecated Please use driver model instead * Make a GPIO an output, and set its value. * * @param gpio GPIO number @@ -64,6 +77,7 @@ int gpio_direction_input(unsigned gpio); int gpio_direction_output(unsigned gpio, int value); /** + * @deprecated Please use driver model instead * Get a GPIO's value. This will work whether the GPIO is an input * or an output. * @@ -73,6 +87,7 @@ int gpio_direction_output(unsigned gpio, int value); int gpio_get_value(unsigned gpio); /** + * @deprecated Please use driver model instead * Set an output GPIO's value. The GPIO must already be an output or * this function may have no effect. * @@ -134,6 +149,8 @@ static inline bool dm_gpio_is_valid(struct gpio_desc *desc) * which means this is GPIO bank b, offset 4, currently set to input, current * value 1, [x] means that it is requested and the owner is 'sdmmc_cd' * + * TODO(sjg@chromium.org): This should use struct gpio_desc + * * @dev: Device to check * @offset: Offset of device GPIO to check * @buf: Place to put string @@ -146,6 +163,8 @@ int gpio_get_status(struct udevice *dev, int offset, char *buf, int buffsize); * * Note this returns GPIOF_UNUSED if the GPIO is not requested. * + * TODO(sjg@chromium.org): This should use struct gpio_desc + * * @dev: Device to check * @offset: Offset of device GPIO to check * @namep: If non-NULL, this is set to the nane given when the GPIO @@ -163,6 +182,8 @@ int gpio_get_function(struct udevice *dev, int offset, const char **namep); * Note this does not return GPIOF_UNUSED - it will always return the GPIO * driver's view of a pin function, even if it is not correctly set up. * + * TODO(sjg@chromium.org): This should use struct gpio_desc + * * @dev: Device to check * @offset: Offset of device GPIO to check * @namep: If non-NULL, this is set to the nane given when the GPIO -- cgit From a02af4aeece40e93bc7d79cd5dc912409efb7020 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 5 Jan 2015 20:05:31 -0700 Subject: dm: demo: Add a simple GPIO demonstration Add a new 'demo light' command which uses GPIOs to control imaginary lights. Each light is assigned a bit number in the overall value. This provides an example driver for using the new GPIO API. Signed-off-by: Simon Glass --- include/dm-demo.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/dm-demo.h b/include/dm-demo.h index a24fec6658..03722d0c14 100644 --- a/include/dm-demo.h +++ b/include/dm-demo.h @@ -25,10 +25,14 @@ struct dm_demo_pdata { struct demo_ops { int (*hello)(struct udevice *dev, int ch); int (*status)(struct udevice *dev, int *status); + int (*set_light)(struct udevice *dev, int light); + int (*get_light)(struct udevice *dev); }; int demo_hello(struct udevice *dev, int ch); int demo_status(struct udevice *dev, int *status); +int demo_set_light(struct udevice *dev, int light); +int demo_get_light(struct udevice *dev); int demo_list(void); int demo_parse_dt(struct udevice *dev); -- cgit From 32f8a19f6d9aa551dc64868fac4b662c088dfb1f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 5 Jan 2015 20:05:32 -0700 Subject: dm: cros_ec: Remove use of fdtdec GPIO support These functions are going away, so use the new uclass support instead. Signed-off-by: Simon Glass --- include/cros_ec.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/cros_ec.h b/include/cros_ec.h index 9e13146ecb..8457c80c5e 100644 --- a/include/cros_ec.h +++ b/include/cros_ec.h @@ -13,6 +13,7 @@ #include #include #include +#include #ifndef CONFIG_DM_CROS_EC /* Which interface is the device on? */ @@ -39,7 +40,7 @@ struct cros_ec_dev { unsigned int bus_num; /* Bus number (for I2C) */ unsigned int max_frequency; /* Maximum interface frequency */ #endif - struct fdt_gpio_state ec_int; /* GPIO used as EC interrupt line */ + struct gpio_desc ec_int; /* GPIO used as EC interrupt line */ int protocol_version; /* Protocol version to use */ int optimise_flash_write; /* Don't write erased flash blocks */ -- cgit From 0347960b8732b8d8506c9123c217b503666a4ad8 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 5 Jan 2015 20:05:38 -0700 Subject: dm: mmc: Remove use of fdtdec GPIO support These functions are going away, so use the new uclass support instead. Signed-off-by: Simon Glass --- include/sdhci.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/sdhci.h b/include/sdhci.h index aa4a0e9654..23893b5740 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -12,7 +12,7 @@ #include #include -#include +#include /* * Controller registers @@ -246,8 +246,8 @@ struct sdhci_host { int index; int bus_width; - struct fdt_gpio_state pwr_gpio; /* Power GPIO */ - struct fdt_gpio_state cd_gpio; /* Card Detect GPIO */ + struct gpio_desc pwr_gpio; /* Power GPIO */ + struct gpio_desc cd_gpio; /* Card Detect GPIO */ void (*set_control_reg)(struct sdhci_host *host); void (*set_clock)(int dev_index, unsigned int div); -- cgit From 009067c3b756de0f94f4a0d03718873614e756f1 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 5 Jan 2015 20:05:43 -0700 Subject: dm: fdt: Remove the old GPIO functions Now that we support device tree GPIO bindings directly in the driver model GPIO uclass we can remove these functions. Signed-off-by: Simon Glass --- include/fdtdec.h | 77 -------------------------------------------------------- 1 file changed, 77 deletions(-) (limited to 'include') diff --git a/include/fdtdec.h b/include/fdtdec.h index 8cf88dd10b..b02f1edb1d 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -231,39 +231,6 @@ int fdtdec_parse_phandle_with_args(const void *blob, int src_node, int cell_count, int index, struct fdtdec_phandle_args *out_args); -/* GPIOs are numbered from 0 */ -enum { - FDT_GPIO_NONE = -1U, /* an invalid GPIO used to end our list */ - - FDT_GPIO_ACTIVE_LOW = 1 << 0, /* input is active low (else high) */ -}; - -/* This is the state of a GPIO pin as defined by the fdt */ -struct fdt_gpio_state { - const char *name; /* name of the fdt property defining this */ - uint gpio; /* GPIO number, or FDT_GPIO_NONE if none */ - u8 flags; /* FDT_GPIO_... flags */ -}; - -/* This tells us whether a fdt_gpio_state record is valid or not */ -#define fdt_gpio_isvalid(x) ((x)->gpio != FDT_GPIO_NONE) - -/** - * Read the GPIO taking into account the polarity of the pin. - * - * @param gpio pointer to the decoded gpio - * @return value of the gpio if successful, < 0 if unsuccessful - */ -int fdtdec_get_gpio(struct fdt_gpio_state *gpio); - -/** - * Write the GPIO taking into account the polarity of the pin. - * - * @param gpio pointer to the decoded gpio - * @return 0 if successful - */ -int fdtdec_set_gpio(struct fdt_gpio_state *gpio, int val); - /** * Find the next numbered alias for a peripheral. This is used to enumerate * all the peripherals of a certain type. @@ -644,50 +611,6 @@ const u32 *fdtdec_locate_array(const void *blob, int node, */ int fdtdec_get_bool(const void *blob, int node, const char *prop_name); -/** - * Decode a single GPIOs from an FDT. - * - * If the property is not found, then the GPIO structure will still be - * initialised, with gpio set to FDT_GPIO_NONE. This makes it easy to - * provide optional GPIOs. - * - * @param blob FDT blob to use - * @param node Node to look at - * @param prop_name Node property name - * @param gpio gpio elements to fill from FDT - * @return 0 if ok, -FDT_ERR_NOTFOUND if the property is missing. - */ -int fdtdec_decode_gpio(const void *blob, int node, const char *prop_name, - struct fdt_gpio_state *gpio); - -/** - * Decode a list of GPIOs from an FDT. This creates a list of GPIOs with no - * terminating item. - * - * @param blob FDT blob to use - * @param node Node to look at - * @param prop_name Node property name - * @param gpio Array of gpio elements to fill from FDT. This will be - * untouched if either 0 or an error is returned - * @param max_count Maximum number of elements allowed - * @return number of GPIOs read if ok, -FDT_ERR_BADLAYOUT if max_count would - * be exceeded, or -FDT_ERR_NOTFOUND if the property is missing. - */ -int fdtdec_decode_gpios(const void *blob, int node, const char *prop_name, - struct fdt_gpio_state *gpio, int max_count); - -/** - * Set up a GPIO pin according to the provided gpio information. At present this - * just requests the GPIO. - * - * If the gpio is FDT_GPIO_NONE, no action is taken. This makes it easy to - * deal with optional GPIOs. - * - * @param gpio GPIO info to use for set up - * @return 0 if all ok or gpio was FDT_GPIO_NONE; -1 on error - */ -int fdtdec_setup_gpio(struct fdt_gpio_state *gpio); - /** * Look in the FDT for a config item with the given name and return its value * as a 32-bit integer. The property must have at least 4 bytes of data. The -- cgit From f9a4c2da72d04e13b05deecb800f232d2948eb85 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 12 Jan 2015 18:02:07 -0700 Subject: dm: i2c: Rename driver model I2C functions to permit compatibility Add a dm_ prefix to driver model I2C functions so that we can keep the old ones around. This is a little unfortunate, but on reflection it is too difficult to change the API. We can undo this rename when most boards and drivers are converted to use driver model for I2C. Signed-off-by: Simon Glass --- include/i2c.h | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/include/i2c.h b/include/i2c.h index 9c6a60cf9a..30d53c8a9d 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -75,7 +75,7 @@ struct dm_i2c_bus { }; /** - * i2c_read() - read bytes from an I2C chip + * dm_i2c_read() - read bytes from an I2C chip * * To obtain an I2C device (called a 'chip') given the I2C bus address you * can use i2c_get_chip(). To obtain a bus by bus number use @@ -91,13 +91,12 @@ struct dm_i2c_bus { * * @return 0 on success, -ve on failure */ -int i2c_read(struct udevice *dev, uint offset, uint8_t *buffer, - int len); +int dm_i2c_read(struct udevice *dev, uint offset, uint8_t *buffer, int len); /** - * i2c_write() - write bytes to an I2C chip + * dm_i2c_write() - write bytes to an I2C chip * - * See notes for i2c_read() above. + * See notes for dm_i2c_read() above. * * @dev: Chip to write to * @offset: Offset within chip to start writing @@ -106,11 +105,11 @@ int i2c_read(struct udevice *dev, uint offset, uint8_t *buffer, * * @return 0 on success, -ve on failure */ -int i2c_write(struct udevice *dev, uint offset, const uint8_t *buffer, - int len); +int dm_i2c_write(struct udevice *dev, uint offset, const uint8_t *buffer, + int len); /** - * i2c_probe() - probe a particular chip address + * dm_i2c_probe() - probe a particular chip address * * This can be useful to check for the existence of a chip on the bus. * It is typically implemented by writing the chip address to the bus @@ -122,8 +121,8 @@ int i2c_write(struct udevice *dev, uint offset, const uint8_t *buffer, * @devp: Returns the device found, or NULL if none * @return 0 if a chip was found at that address, -ve if not */ -int i2c_probe(struct udevice *bus, uint chip_addr, uint chip_flags, - struct udevice **devp); +int dm_i2c_probe(struct udevice *bus, uint chip_addr, uint chip_flags, + struct udevice **devp); /** * i2c_set_bus_speed() - set the speed of a bus -- cgit From 73845350b6281a7afeeb279475e6eb613d7a89f9 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 12 Jan 2015 18:02:08 -0700 Subject: dm: i2c: Add a compatbility layer For boards which use multiple I2C devices, or for SOCs which support multiple boards, we might want to convert these to driver model at different times. At present this is difficult because we need to either use CONFIG_DM_I2C for a board or not. Add a compatibility layer which implements the old API, thus allowing a board to move to driver model for I2C without requiring that everything it uses is moved in the same commit. Signed-off-by: Simon Glass --- include/i2c.h | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) (limited to 'include') diff --git a/include/i2c.h b/include/i2c.h index 30d53c8a9d..47529f4b28 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -184,6 +184,65 @@ int i2c_set_chip_offset_len(struct udevice *dev, uint offset_len); */ int i2c_deblock(struct udevice *bus); +#ifdef CONFIG_DM_I2C_COMPAT +/** + * i2c_probe() - Compatibility function for driver model + * + * Calls dm_i2c_probe() on the current bus + */ +int i2c_probe(uint8_t chip_addr); + +/** + * i2c_read() - Compatibility function for driver model + * + * Calls dm_i2c_read() with the device corresponding to @chip_addr, and offset + * set to @addr. @alen must match the current setting for the device. + */ +int i2c_read(uint8_t chip_addr, unsigned int addr, int alen, uint8_t *buffer, + int len); + +/** + * i2c_write() - Compatibility function for driver model + * + * Calls dm_i2c_write() with the device corresponding to @chip_addr, and offset + * set to @addr. @alen must match the current setting for the device. + */ +int i2c_write(uint8_t chip_addr, unsigned int addr, int alen, uint8_t *buffer, + int len); + +/** + * i2c_get_bus_num_fdt() - Compatibility function for driver model + * + * @return the bus number associated with the given device tree node + */ +int i2c_get_bus_num_fdt(int node); + +/** + * i2c_get_bus_num() - Compatibility function for driver model + * + * @return the 'current' bus number + */ +unsigned int i2c_get_bus_num(void); + +/** + * i2c_set_bus_num(): Compatibility function for driver model + * + * Sets the 'current' bus + */ +int i2c_set_bus_num(unsigned int bus); + +static inline void I2C_SET_BUS(unsigned int bus) +{ + i2c_set_bus_num(bus); +} + +static inline unsigned int I2C_GET_BUS(void) +{ + return i2c_get_bus_num(); +} + +#endif + /* * Not all of these flags are implemented in the U-Boot API */ -- cgit From 25ab4b0303f2df5e6b94ed92e37875a7c98f4de3 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 25 Jan 2015 08:26:55 -0700 Subject: dm: i2c: Provide an offset length parameter where needed Rather than assuming that the chip offset length is 1, allow it to be provided. This allows chips that don't use the default offset length to be used (at present they are only supported by the command line 'i2c' command which sets the offset length explicitly). Signed-off-by: Simon Glass Acked-by: Heiko Schocher --- include/i2c.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/i2c.h b/include/i2c.h index 47529f4b28..76090b7a93 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -388,10 +388,12 @@ struct dm_i2c_ops { * * @bus: Bus to examine * @chip_addr: Chip address for the new device + * @offset_len: Length of a register offset in bytes (normally 1) * @devp: Returns pointer to new device if found or -ENODEV if not * found */ -int i2c_get_chip(struct udevice *bus, uint chip_addr, struct udevice **devp); +int i2c_get_chip(struct udevice *bus, uint chip_addr, uint offset_len, + struct udevice **devp); /** * i2c_get_chip() - get a device to use to access a chip on a bus number @@ -401,10 +403,12 @@ int i2c_get_chip(struct udevice *bus, uint chip_addr, struct udevice **devp); * * @busnum: Bus number to examine * @chip_addr: Chip address for the new device + * @offset_len: Length of a register offset in bytes (normally 1) * @devp: Returns pointer to new device if found or -ENODEV if not * found */ -int i2c_get_chip_for_busnum(int busnum, int chip_addr, struct udevice **devp); +int i2c_get_chip_for_busnum(int busnum, int chip_addr, uint offset_len, + struct udevice **devp); /** * i2c_chip_ofdata_to_platdata() - Decode standard I2C platform data -- cgit From 040b69af7209d8fe0742352f4a72719df8dda9a5 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 25 Jan 2015 08:26:57 -0700 Subject: dm: core: Improve comments for uclass_first/next_device() Mention that the devices are probed ready for use. Signed-off-by: Simon Glass --- include/dm/uclass.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/dm/uclass.h b/include/dm/uclass.h index f6ec6d7e9f..2577ae6489 100644 --- a/include/dm/uclass.h +++ b/include/dm/uclass.h @@ -141,6 +141,8 @@ int uclass_get_device_by_of_offset(enum uclass_id id, int node, /** * uclass_first_device() - Get the first device in a uclass * + * The device returned is probed if necessary, and ready for use + * * @id: Uclass ID to look up * @devp: Returns pointer to the first device in that uclass, or NULL if none * @return 0 if OK (found or not found), -1 on error @@ -150,6 +152,8 @@ int uclass_first_device(enum uclass_id id, struct udevice **devp); /** * uclass_next_device() - Get the next device in a uclass * + * The device returned is probed if necessary, and ready for use + * * @devp: On entry, pointer to device to lookup. On exit, returns pointer * to the next device in the same uclass, or NULL if none * @return 0 if OK (found or not found), -1 on error -- cgit From cdc133bde9dd221319b9cf7fd99fcb4da8ba195c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 25 Jan 2015 08:27:01 -0700 Subject: dm: core: Allow parents to have platform data for their children For buses it is common for parents to need to know the address of the child on the bus, the bus speed to use for that child, and other information. This can be provided in platform data attached to each child. Add driver model support for this, including auto-allocation which can be requested using a new property to specify the size of the data. Signed-off-by: Simon Glass Reviewed-by: Masahiro Yamada --- include/dm/device.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'include') diff --git a/include/dm/device.h b/include/dm/device.h index 13598a15b6..096d84b7b6 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -26,6 +26,9 @@ struct driver_info; /* DM should init this device prior to relocation */ #define DM_FLAG_PRE_RELOC (1 << 2) +/* DM is responsible for allocating and freeing parent_platdata */ +#define DM_FLAG_ALLOC_PARENT_PDATA (1 << 3) + /** * struct udevice - An instance of a driver * @@ -46,6 +49,7 @@ struct driver_info; * @driver: The driver used by this device * @name: Name of device, typically the FDT node name * @platdata: Configuration data for this device + * @parent_platdata: The parent bus's configuration data for this device * @of_offset: Device tree node offset for this device (- for none) * @of_id: Pointer to the udevice_id structure which created the device * @parent: Parent of this device, or NULL for the top level device @@ -65,6 +69,7 @@ struct udevice { struct driver *driver; const char *name; void *platdata; + void *parent_platdata; int of_offset; const struct udevice_id *of_id; struct udevice *parent; @@ -146,6 +151,9 @@ struct udevice_id { * device_probe_child() pass it in. So far the use case for allocating it * is SPI, but I found that unsatisfactory. Since it is here I will leave it * until things are clearer. + * @per_child_platdata_auto_alloc_size: A bus likes to store information about + * its children. If non-zero this is the size of this data, to be allocated + * in the child's parent_platdata pointer. * @ops: Driver-specific operations. This is typically a list of function * pointers defined by the driver, to implement driver functions required by * the uclass. @@ -165,6 +173,7 @@ struct driver { int priv_auto_alloc_size; int platdata_auto_alloc_size; int per_child_auto_alloc_size; + int per_child_platdata_auto_alloc_size; const void *ops; /* driver-specific operations */ uint32_t flags; }; @@ -183,6 +192,16 @@ struct driver { */ void *dev_get_platdata(struct udevice *dev); +/** + * dev_get_parent_platdata() - Get the parent platform data for a device + * + * This checks that dev is not NULL, but no other checks for now + * + * @dev Device to check + * @return parent's platform data, or NULL if none + */ +void *dev_get_parent_platdata(struct udevice *dev); + /** * dev_get_parentdata() - Get the parent data for a device * -- cgit From ba8da9dc43ac8ae3351345df12dc7f9d1cd07ae0 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 25 Jan 2015 08:27:02 -0700 Subject: dm: core: Allow uclasses to specify platdata for a device's children In many cases the child platform data for a device's children is defined by the uclass rather than the individual devices. For example, a SPI bus needs to know the chip select and speed for each of its children. It makes sense to allow this information to be defined the SPI uclass rather than each individual driver. If the device provides a size value for its child platdata, then use it. Failng that, fall back to that provided by the uclass. Reviewed-by: Masahiro Yamada Signed-off-by: Simon Glass --- include/dm/uclass.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/dm/uclass.h b/include/dm/uclass.h index 2577ae6489..7d92d34bec 100644 --- a/include/dm/uclass.h +++ b/include/dm/uclass.h @@ -60,6 +60,10 @@ struct udevice; * @per_device_auto_alloc_size: Each device can hold private data owned * by the uclass. If required this will be automatically allocated if this * value is non-zero. + * @per_child_platdata_auto_alloc_size: A bus likes to store information about + * its children. If non-zero this is the size of this data, to be allocated + * in the child device's parent_platdata pointer. This value is only used as + * a falback if this member is 0 in the driver. * @ops: Uclass operations, providing the consistent interface to devices * within the uclass. */ @@ -74,6 +78,7 @@ struct uclass_driver { int (*destroy)(struct uclass *class); int priv_auto_alloc_size; int per_device_auto_alloc_size; + int per_child_platdata_auto_alloc_size; const void *ops; }; -- cgit From 0118ce79577f9b0881f99a6e4f8a79cd5014cb87 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 25 Jan 2015 08:27:03 -0700 Subject: dm: core: Add a post_bind method for parents Allow parent drivers to be called when a new child is bound to them. This allows a bus to set up information it needs for that child. Signed-off-by: Simon Glass Reviewed-by: Masahiro Yamada --- include/dm/device.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/dm/device.h b/include/dm/device.h index 096d84b7b6..50f1b4f508 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -132,6 +132,7 @@ struct udevice_id { * @remove: Called to remove a device, i.e. de-activate it * @unbind: Called to unbind a device from its driver * @ofdata_to_platdata: Called before probe to decode device tree data + * @child_post_bind: Called after a new child has been bound * @child_pre_probe: Called before a child device is probed. The device has * memory allocated but it has not yet been probed. * @child_post_remove: Called after a child device is removed. The device @@ -168,6 +169,7 @@ struct driver { int (*remove)(struct udevice *dev); int (*unbind)(struct udevice *dev); int (*ofdata_to_platdata)(struct udevice *dev); + int (*child_post_bind)(struct udevice *dev); int (*child_pre_probe)(struct udevice *dev); int (*child_post_remove)(struct udevice *dev); int priv_auto_alloc_size; -- cgit From b367053102e597eb21b0a5e86c63e8d10f368cb0 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 25 Jan 2015 08:27:04 -0700 Subject: dm: core: Add a function to get a device's uclass ID This is useful to check which uclass a device is in. Signed-off-by: Simon Glass Reviewed-by: Masahiro Yamada --- include/dm/device.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include') diff --git a/include/dm/device.h b/include/dm/device.h index 50f1b4f508..81afa8c628 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -245,6 +245,14 @@ struct udevice *dev_get_parent(struct udevice *child); */ ulong dev_get_of_data(struct udevice *dev); +/* + * device_get_uclass_id() - return the uclass ID of a device + * + * @dev: Device to check + * @return uclass ID for the device + */ +enum uclass_id device_get_uclass_id(struct udevice *dev); + /** * device_get_child() - Get the child of a device by index * -- cgit From 9cc36a2b89ebe5148d69d521745c1e1d26365c3a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 25 Jan 2015 08:27:05 -0700 Subject: dm: core: Add a flag to control sequence numbering At present we try to use the 'reg' property and device tree aliases to give devices a sequence number. The 'reg' property is often actually a memory address, so the sequence numbers thus-obtained are not useful. It would be better if the devices were just sequentially numbered in that case. In fact neither I2C nor SPI use this feature, so drop it. Some devices need us to look up an alias to number them within the uclass. Add a flag to control this, so it is not done unless it is needed. Adjust the tests to test this new behaviour. Signed-off-by: Simon Glass Reviewed-by: Masahiro Yamada --- include/dm/uclass.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/dm/uclass.h b/include/dm/uclass.h index 7d92d34bec..9000b22c38 100644 --- a/include/dm/uclass.h +++ b/include/dm/uclass.h @@ -40,6 +40,9 @@ struct uclass { struct udevice; +/* Members of this uclass sequence themselves with aliases */ +#define DM_UC_FLAG_SEQ_ALIAS (1 << 0) + /** * struct uclass_driver - Driver for the uclass * @@ -66,6 +69,7 @@ struct udevice; * a falback if this member is 0 in the driver. * @ops: Uclass operations, providing the consistent interface to devices * within the uclass. + * @flags: Flags for this uclass (DM_UC_...) */ struct uclass_driver { const char *name; @@ -80,6 +84,7 @@ struct uclass_driver { int per_device_auto_alloc_size; int per_child_platdata_auto_alloc_size; const void *ops; + uint32_t flags; }; /* Declare a new uclass_driver */ -- cgit From dac8db2ce66944828e441cccf25703b262a256cd Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 25 Jan 2015 08:27:06 -0700 Subject: dm: core: Allow uclasses to specify private data for a device's children In many cases the per-child private data for a device's children is defined by the uclass rather than the individual driver. For example, a SPI bus needs to store information about each of its children, but all SPI drivers store the same information. It makes sense to allow the uclass to define this data. If the driver provides a size value for its per-child private data, then use it. Failng that, fall back to that provided by the uclass. Signed-off-by: Simon Glass Reviewed-by: Masahiro Yamada --- include/dm/uclass.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/dm/uclass.h b/include/dm/uclass.h index 9000b22c38..ac6c85072c 100644 --- a/include/dm/uclass.h +++ b/include/dm/uclass.h @@ -63,6 +63,9 @@ struct udevice; * @per_device_auto_alloc_size: Each device can hold private data owned * by the uclass. If required this will be automatically allocated if this * value is non-zero. + * @per_child_auto_alloc_size: Each child device (of a parent in this + * uclass) can hold parent data for the device/uclass. This value is only + * used as a falback if this member is 0 in the driver. * @per_child_platdata_auto_alloc_size: A bus likes to store information about * its children. If non-zero this is the size of this data, to be allocated * in the child device's parent_platdata pointer. This value is only used as @@ -82,6 +85,7 @@ struct uclass_driver { int (*destroy)(struct uclass *class); int priv_auto_alloc_size; int per_device_auto_alloc_size; + int per_child_auto_alloc_size; int per_child_platdata_auto_alloc_size; const void *ops; uint32_t flags; -- cgit From 081f2fcbd9a95ba10677065359791f8fea3f8c58 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 25 Jan 2015 08:27:08 -0700 Subject: dm: core: Allow the uclass to set up a device's child after binding For buses, after a child is bound, allow the uclass to perform some processing. This can be used to figure out the address of the child (e.g. the chip select for SPI slaves) so that it is ready to be probed. This avoids bus drivers having to repeat the same process, which really should be done by the uclass, since it is common. Signed-off-by: Simon Glass Reviewed-by: Masahiro Yamada --- include/dm/uclass.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/dm/uclass.h b/include/dm/uclass.h index ac6c85072c..5c5b8f4208 100644 --- a/include/dm/uclass.h +++ b/include/dm/uclass.h @@ -55,6 +55,7 @@ struct udevice; * @pre_unbind: Called before a device is unbound from this uclass * @post_probe: Called after a new device is probed * @pre_remove: Called before a device is removed + * @child_post_bind: Called after a child is bound to a device in this uclass * @init: Called to set up the uclass * @destroy: Called to destroy the uclass * @priv_auto_alloc_size: If non-zero this is the size of the private data @@ -81,6 +82,7 @@ struct uclass_driver { int (*pre_unbind)(struct udevice *dev); int (*post_probe)(struct udevice *dev); int (*pre_remove)(struct udevice *dev); + int (*child_post_bind)(struct udevice *dev); int (*init)(struct uclass *class); int (*destroy)(struct uclass *class); int priv_auto_alloc_size; -- cgit From 83c7e434c9dd3ca81f8b763e23c1881b973bcf2f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 25 Jan 2015 08:27:10 -0700 Subject: dm: core: Allow uclass to set up a device's child before it is probed Some buses need to set up their devices before they can be used. This setup may well be common to all buses in a particular uclass. Support a common pre-probe method for the uclass, called before any bus devices are probed. Signed-off-by: Simon Glass Reviewed-by: Masahiro Yamada --- include/dm/test.h | 3 +++ include/dm/uclass-internal.h | 11 +++++++++++ include/dm/uclass.h | 1 + 3 files changed, 15 insertions(+) (limited to 'include') diff --git a/include/dm/test.h b/include/dm/test.h index f08c05da81..707c69e07f 100644 --- a/include/dm/test.h +++ b/include/dm/test.h @@ -67,6 +67,8 @@ enum { struct dm_test_priv { int ping_total; int op_count[DM_TEST_OP_COUNT]; + int uclass_flag; + int uclass_total; }; /** @@ -88,6 +90,7 @@ struct dm_test_uclass_priv { * * @sum: Test value used to check parent data works correctly * @flag: Used to track calling of parent operations + * @uclass_flag: Used to track calling of parent operations by uclass */ struct dm_test_parent_data { int sum; diff --git a/include/dm/uclass-internal.h b/include/dm/uclass-internal.h index f718f37aff..f2f254a825 100644 --- a/include/dm/uclass-internal.h +++ b/include/dm/uclass-internal.h @@ -43,6 +43,17 @@ int uclass_bind_device(struct udevice *dev); */ int uclass_unbind_device(struct udevice *dev); +/** + * uclass_pre_probe_child() - Deal with a child that is about to be probed + * + * Perform any pre-processing that is needed by the uclass before it can be + * probed. + * + * @dev: Pointer to the device + * #return 0 on success, -ve on error + */ +int uclass_pre_probe_child(struct udevice *dev); + /** * uclass_post_probe_device() - Deal with a device that has just been probed * diff --git a/include/dm/uclass.h b/include/dm/uclass.h index 5c5b8f4208..d6c40c60dd 100644 --- a/include/dm/uclass.h +++ b/include/dm/uclass.h @@ -83,6 +83,7 @@ struct uclass_driver { int (*post_probe)(struct udevice *dev); int (*pre_remove)(struct udevice *dev); int (*child_post_bind)(struct udevice *dev); + int (*child_pre_probe)(struct udevice *dev); int (*init)(struct uclass *class); int (*destroy)(struct uclass *class); int priv_auto_alloc_size; -- cgit From d0cff03e187cc1de3d6b477b92c376aae27c95e8 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 25 Jan 2015 08:27:12 -0700 Subject: dm: spi: Move slave details to child platdata At present we go through various contortions to store the SPI slave's chip select in its private data. This only exists when the slave is active so must be set up when it is probed. Until the device is probed we don't actually know what chip select it will appear on. However, now that we can support per-child platform data, we can use that instead. This allows us to set up the chip select when the child is bound, and avoid the messy contortions. Unfortunately this is a fairly large change and it seems to be difficult to break it down further. Signed-off-by: Simon Glass --- include/spi.h | 42 ++++++++++++++++++++++++++++++++---------- 1 file changed, 32 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/include/spi.h b/include/spi.h index ec17bd0bcc..c58e453559 100644 --- a/include/spi.h +++ b/include/spi.h @@ -56,20 +56,42 @@ #define SPI_DEFAULT_WORDLEN 8 #ifdef CONFIG_DM_SPI +/* TODO(sjg@chromium.org): Remove this and use max_hz from struct spi_slave */ struct dm_spi_bus { uint max_hz; }; +/** + * struct dm_spi_platdata - platform data for all SPI slaves + * + * This describes a SPI slave, a child device of the SPI bus. To obtain this + * struct from a spi_slave, use dev_get_parent_platdata(dev) or + * dev_get_parent_platdata(slave->dev). + * + * This data is immuatable. Each time the device is probed, @max_hz and @mode + * will be copied to struct spi_slave. + * + * @cs: Chip select number (0..n-1) + * @max_hz: Maximum bus speed that this slave can tolerate + * @mode: SPI mode to use for this device (see SPI mode flags) + */ +struct dm_spi_slave_platdata { + unsigned int cs; + uint max_hz; + uint mode; +}; + #endif /* CONFIG_DM_SPI */ /** * struct spi_slave - Representation of a SPI slave * * For driver model this is the per-child data used by the SPI bus. It can - * be accessed using dev_get_parentdata() on the slave device. Each SPI - * driver should define this child data in its U_BOOT_DRIVER() definition: - * - * .per_child_auto_alloc_size = sizeof(struct spi_slave), + * be accessed using dev_get_parentdata() on the slave device. The SPI uclass + * sets uip per_child_auto_alloc_size to sizeof(struct spi_slave), and the + * driver should not override it. Two platform data fields (max_hz and mode) + * are copied into this structure to provide an initial value. This allows + * them to be changed, since we should never change platform data in drivers. * * If not using driver model, drivers are expected to extend this with * controller-specific data. @@ -97,8 +119,8 @@ struct spi_slave { uint mode; #else unsigned int bus; -#endif unsigned int cs; +#endif u8 op_mode_rx; u8 op_mode_tx; unsigned int wordlen; @@ -545,16 +567,16 @@ int spi_chip_select(struct udevice *slave); int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp); /** - * spi_ofdata_to_platdata() - decode standard SPI platform data + * spi_slave_ofdata_to_platdata() - decode standard SPI platform data * - * This decodes the speed and mode from a device tree node and puts it into - * the spi_slave structure. + * This decodes the speed and mode for a slave from a device tree node * * @blob: Device tree blob * @node: Node offset to read from - * @spi: Place to put the decoded information + * @plat: Place to put the decoded information */ -int spi_ofdata_to_platdata(const void *blob, int node, struct spi_slave *spi); +int spi_slave_ofdata_to_platdata(const void *blob, int node, + struct dm_spi_slave_platdata *plat); /** * spi_cs_info() - Check information on a chip select -- cgit From e6f66ec0e757b49d39885303a94784a342803dd2 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 25 Jan 2015 08:27:13 -0700 Subject: dm: i2c: Move slave details to child platdata At present we go through various contortions to store the I2C's chip address in its private data. This only exists when the chip is active so must be set up when it is probed. Until the device is probed we don't actually record what address it will appear on. However, now that we can support per-child platform data, we can use that instead. This allows us to set up the address when the child is bound, and avoid the messy contortions. Unfortunately this is a fairly large change and it seems to be difficult to break it down further. Signed-off-by: Simon Glass Reviewed-by: Masahiro Yamada --- include/i2c.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/i2c.h b/include/i2c.h index 76090b7a93..95d6f28771 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -39,8 +39,8 @@ enum dm_i2c_chip_flags { * An I2C chip is a device on the I2C bus. It sits at a particular address * and normally supports 7-bit or 10-bit addressing. * - * To obtain this structure, use dev_get_parentdata(dev) where dev is the - * chip to examine. + * To obtain this structure, use dev_get_parent_platdata(dev) where dev is + * the chip to examine. * * @chip_addr: Chip address on bus * @offset_len: Length of offset in bytes. A single byte offset can -- cgit From dedff1a0007525b16737328ca714cd4330100618 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 25 Jan 2015 08:27:14 -0700 Subject: dm: tegra: Drop unused COMPAT features for I2C, SPI These have moved to driver model so we don't need the fdtdec support. Signed-off-by: Simon Glass --- include/fdtdec.h | 6 ------ 1 file changed, 6 deletions(-) (limited to 'include') diff --git a/include/fdtdec.h b/include/fdtdec.h index b02f1edb1d..965c5bae87 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -115,9 +115,6 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA20_USB, /* Tegra20 USB port */ COMPAT_NVIDIA_TEGRA30_USB, /* Tegra30 USB port */ COMPAT_NVIDIA_TEGRA114_USB, /* Tegra114 USB port */ - COMPAT_NVIDIA_TEGRA114_I2C, /* Tegra114 I2C w/single clock source */ - COMPAT_NVIDIA_TEGRA20_I2C, /* Tegra20 i2c */ - COMPAT_NVIDIA_TEGRA20_DVC, /* Tegra20 dvc (really just i2c) */ COMPAT_NVIDIA_TEGRA20_EMC, /* Tegra20 memory controller */ COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */ COMPAT_NVIDIA_TEGRA20_KBC, /* Tegra20 Keyboard */ @@ -127,9 +124,6 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */ COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */ COMPAT_NVIDIA_TEGRA20_SDMMC, /* Tegra20 SDMMC controller */ - COMPAT_NVIDIA_TEGRA20_SFLASH, /* Tegra 2 SPI flash controller */ - COMPAT_NVIDIA_TEGRA20_SLINK, /* Tegra 2 SPI SLINK controller */ - COMPAT_NVIDIA_TEGRA114_SPI, /* Tegra 114 SPI controller */ COMPAT_NVIDIA_TEGRA124_PCIE, /* Tegra 124 PCIe controller */ COMPAT_NVIDIA_TEGRA30_PCIE, /* Tegra 30 PCIe controller */ COMPAT_NVIDIA_TEGRA20_PCIE, /* Tegra 20 PCIe controller */ -- cgit From b9749eb5e4660fa6ec85c9a16acdbf3dd6609046 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 25 Jan 2015 08:27:15 -0700 Subject: dm: exynos: Drop unused COMPAT features for SPI This has moved to driver model so we don't need the fdtdec support. Signed-off-by: Simon Glass Acked-by: Minkyu Kang --- include/fdtdec.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/fdtdec.h b/include/fdtdec.h index 965c5bae87..231eed7892 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -134,7 +134,6 @@ enum fdt_compat_id { COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */ COMPAT_SAMSUNG_EXYNOS5_SOUND, /* Exynos Sound */ COMPAT_WOLFSON_WM8994_CODEC, /* Wolfson WM8994 Sound Codec */ - COMPAT_SAMSUNG_EXYNOS_SPI, /* Exynos SPI */ COMPAT_GOOGLE_CROS_EC, /* Google CROS_EC Protocol */ COMPAT_GOOGLE_CROS_EC_KEYB, /* Google CROS_EC Keyboard */ COMPAT_SAMSUNG_EXYNOS_EHCI, /* Exynos EHCI controller */ -- cgit From 49cad54788a64a296567abadcd736fdbe47cc3a3 Mon Sep 17 00:00:00 2001 From: Martin Dorwig Date: Mon, 26 Jan 2015 15:22:54 -0700 Subject: Export redesign this is an atempt to make the export of functions typesafe. I replaced the jumptable void ** by a struct (jt_funcs) with function pointers. The EXPORT_FUNC macro now has 3 fixed parameters and one variadic parameter The first is the name of the exported function, the rest of the parameters are used to format a functionpointer in the jumptable, the EXPORT_FUNC macros are expanded three times, 1. to declare the members of the struct 2. to initialize the structmember pointers 3. to call the functions in stubs.c Signed-off-by: Martin Dorwig Acked-by: Simon Glass Signed-off-by: Simon Glass (resending to the list since my tweaks are not quite trivial) --- include/_exports.h | 99 +++++++++++++++++++++++++++------------ include/asm-generic/global_data.h | 2 +- include/exports.h | 22 +++++---- 3 files changed, 83 insertions(+), 40 deletions(-) (limited to 'include') diff --git a/include/_exports.h b/include/_exports.h index 349a3c5522..594470328e 100644 --- a/include/_exports.h +++ b/include/_exports.h @@ -1,32 +1,73 @@ /* - * You do not need to use #ifdef around functions that may not exist + * You need to use #ifdef around functions that may not exist * in the final configuration (such as i2c). + * use a dummyfunction as first parameter to EXPORT_FUNC. + * As an example see the CONFIG_CMD_I2C section below */ -EXPORT_FUNC(get_version) -EXPORT_FUNC(getc) -EXPORT_FUNC(tstc) -EXPORT_FUNC(putc) -EXPORT_FUNC(puts) -EXPORT_FUNC(printf) -EXPORT_FUNC(install_hdlr) -EXPORT_FUNC(free_hdlr) -EXPORT_FUNC(malloc) -EXPORT_FUNC(free) -EXPORT_FUNC(udelay) -EXPORT_FUNC(get_timer) -EXPORT_FUNC(vprintf) -EXPORT_FUNC(do_reset) -EXPORT_FUNC(getenv) -EXPORT_FUNC(setenv) -EXPORT_FUNC(simple_strtoul) -EXPORT_FUNC(strict_strtoul) -EXPORT_FUNC(simple_strtol) -EXPORT_FUNC(strcmp) -EXPORT_FUNC(i2c_write) -EXPORT_FUNC(i2c_read) -EXPORT_FUNC(spi_init) -EXPORT_FUNC(spi_setup_slave) -EXPORT_FUNC(spi_free_slave) -EXPORT_FUNC(spi_claim_bus) -EXPORT_FUNC(spi_release_bus) -EXPORT_FUNC(spi_xfer) +#ifndef EXPORT_FUNC +#define EXPORT_FUNC(a, b, c, ...) +#endif + EXPORT_FUNC(get_version, unsigned long, get_version, void) + EXPORT_FUNC(getc, int, getc, void) + EXPORT_FUNC(tstc, int, tstc, void) + EXPORT_FUNC(putc, void, putc, const char) + EXPORT_FUNC(puts, void, puts, const char *) + EXPORT_FUNC(printf, int, printf, const char*, ...) +#if defined(CONFIG_X86) || defined(CONFIG_PPC) + EXPORT_FUNC(irq_install_handler, void, install_hdlr, + int, interrupt_handler_t, void*) + + EXPORT_FUNC(irq_free_handler, void, free_hdlr, int) +#else + EXPORT_FUNC(dummy, void, install_hdlr, void) + EXPORT_FUNC(dummy, void, free_hdlr, void) +#endif + EXPORT_FUNC(malloc, void *, malloc, size_t) + EXPORT_FUNC(free, void, free, void *) + EXPORT_FUNC(udelay, void, udelay, unsigned long) + EXPORT_FUNC(get_timer, unsigned long, get_timer, unsigned long) + EXPORT_FUNC(vprintf, int, vprintf, const char *, va_list) + EXPORT_FUNC(do_reset, int, do_reset, cmd_tbl_t *, + int , int , char * const []) + EXPORT_FUNC(getenv, char *, getenv, const char*) + EXPORT_FUNC(setenv, int, setenv, const char *, const char *) + EXPORT_FUNC(simple_strtoul, unsigned long, simple_strtoul, + const char *, char **, unsigned int) + EXPORT_FUNC(strict_strtoul, int, strict_strtoul, + const char *, unsigned int , unsigned long *) + EXPORT_FUNC(simple_strtol, long, simple_strtol, + const char *, char **, unsigned int) + EXPORT_FUNC(strcmp, int, strcmp, const char *cs, const char *ct) +#if defined(CONFIG_CMD_I2C) && \ + (!defined(CONFIG_DM_I2C) || defined(CONFIG_DM_I2C_COMPAT)) + EXPORT_FUNC(i2c_write, int, i2c_write, uchar, uint, int , uchar * , int) + EXPORT_FUNC(i2c_read, int, i2c_read, uchar, uint, int , uchar * , int) +#else + EXPORT_FUNC(dummy, void, i2c_write, void) + EXPORT_FUNC(dummy, void, i2c_read, void) +#endif + +#if !defined(CONFIG_CMD_SPI) || defined(CONFIG_DM_SPI) + EXPORT_FUNC(dummy, void, spi_init, void) + EXPORT_FUNC(dummy, void, spi_setup_slave, void) + EXPORT_FUNC(dummy, void, spi_free_slave, void) +#else + EXPORT_FUNC(spi_init, void, spi_init, void) + EXPORT_FUNC(spi_setup_slave, struct spi_slave *, spi_setup_slave, + unsigned int, unsigned int, unsigned int, unsigned int) + EXPORT_FUNC(spi_free_slave, void, spi_free_slave, struct spi_slave *) +#endif +#ifndef CONFIG_CMD_SPI + EXPORT_FUNC(dummy, void, spi_claim_bus, void) + EXPORT_FUNC(dummy, void, spi_release_bus, void) + EXPORT_FUNC(dummy, void, spi_xfer, void) +#else + EXPORT_FUNC(spi_claim_bus, int, spi_claim_bus, struct spi_slave *) + EXPORT_FUNC(spi_release_bus, void, spi_release_bus, struct spi_slave *) + EXPORT_FUNC(spi_xfer, int, spi_xfer, struct spi_slave *, + unsigned int, const void *, void *, unsigned long) +#endif + EXPORT_FUNC(ustrtoul, unsigned long, ustrtoul, + const char *, char **, unsigned int) + EXPORT_FUNC(ustrtoull, unsigned long long, ustrtoull, + const char *, char **, unsigned int) diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 3d14d5f117..6747619b1c 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -73,7 +73,7 @@ typedef struct global_data { const void *fdt_blob; /* Our device tree, NULL if none */ void *new_fdt; /* Relocated FDT */ unsigned long fdt_size; /* Space reserved for relocated FDT */ - void **jt; /* jump table */ + struct jt_funcs *jt; /* jump table */ char env_buf[32]; /* buffer for getenv() before reloc. */ #ifdef CONFIG_TRACE void *trace_buff; /* The trace buffer */ diff --git a/include/exports.h b/include/exports.h index 41d5085e16..205affe72d 100644 --- a/include/exports.h +++ b/include/exports.h @@ -3,6 +3,8 @@ #ifndef __ASSEMBLY__ +struct spi_slave; + /* These are declarations of exported functions available in C code */ unsigned long get_version(void); int getc(void); @@ -10,22 +12,23 @@ int tstc(void); void putc(const char); void puts(const char*); int printf(const char* fmt, ...); -void install_hdlr(int, void (*interrupt_handler_t)(void *), void*); +void install_hdlr(int, interrupt_handler_t, void*); void free_hdlr(int); void *malloc(size_t); void free(void*); void __udelay(unsigned long); unsigned long get_timer(unsigned long); int vprintf(const char *, va_list); -unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base); +unsigned long simple_strtoul(const char *cp, char **endp, unsigned int base); int strict_strtoul(const char *cp, unsigned int base, unsigned long *res); char *getenv (const char *name); int setenv (const char *varname, const char *varvalue); -long simple_strtol(const char *cp,char **endp,unsigned int base); -int strcmp(const char * cs,const char * ct); +long simple_strtol(const char *cp, char **endp, unsigned int base); +int strcmp(const char *cs, const char *ct); unsigned long ustrtoul(const char *cp, char **endp, unsigned int base); unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base); -#if defined(CONFIG_CMD_I2C) +#if defined(CONFIG_CMD_I2C) && \ + (!defined(CONFIG_DM_I2C) || defined(CONFIG_DM_I2C_COMPAT)) int i2c_write (uchar, uint, int , uchar* , int); int i2c_read (uchar, uint, int , uchar* , int); #endif @@ -34,15 +37,14 @@ void app_startup(char * const *); #endif /* ifndef __ASSEMBLY__ */ -enum { -#define EXPORT_FUNC(x) XF_ ## x , +struct jt_funcs { +#define EXPORT_FUNC(impl, res, func, ...) res(*func)(__VA_ARGS__); #include <_exports.h> #undef EXPORT_FUNC - - XF_MAX }; -#define XF_VERSION 6 + +#define XF_VERSION 7 #if defined(CONFIG_X86) extern gd_t *global_data; -- cgit From fc2f4246b4b3b750e8c5aa08440ec5e1c952088e Mon Sep 17 00:00:00 2001 From: Ruchika Gupta Date: Fri, 23 Jan 2015 16:01:50 +0530 Subject: rsa: Split the rsa-verify to separate the modular exponentiation Public exponentiation which is required in rsa verify functionality is tightly integrated with verification code in rsa_verify.c. The patch splits the file into twp separating the modular exponentiation. 1. rsa-verify.c - The file parses device tree keys node to fill a keyprop structure. The keyprop structure can then be converted to implementation specific format. (struct rsa_pub_key for sw implementation) - The parsed device tree node is then passed to a generic rsa_mod_exp function. 2. rsa-mod-exp.c Move the software specific functions related to modular exponentiation from rsa-verify.c to this file. Signed-off-by: Ruchika Gupta CC: Simon Glass Acked-by: Simon Glass --- include/u-boot/rsa-mod-exp.h | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 include/u-boot/rsa-mod-exp.h (limited to 'include') diff --git a/include/u-boot/rsa-mod-exp.h b/include/u-boot/rsa-mod-exp.h new file mode 100644 index 0000000000..59cd9ea2d8 --- /dev/null +++ b/include/u-boot/rsa-mod-exp.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2014, Ruchika Gupta. + * + * SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef _RSA_MOD_EXP_H +#define _RSA_MOD_EXP_H + +#include +#include + +/** + * struct key_prop - holder for a public key properties + * + * The struct has pointers to modulus (Typically called N), + * The inverse, R^2, exponent. These can be typecasted and + * used as byte arrays or converted to the required format + * as per requirement of RSA implementation. + */ +struct key_prop { + const void *rr; /* R^2 can be treated as byte array */ + const void *modulus; /* modulus as byte array */ + const void *public_exponent; /* public exponent as byte array */ + uint32_t n0inv; /* -1 / modulus[0] mod 2^32 */ + int num_bits; /* Key length in bits */ + uint32_t exp_len; /* Exponent length in number of uint8_t */ +}; + +/** + * rsa_mod_exp_sw() - Perform RSA Modular Exponentiation in sw + * + * Operation: out[] = sig ^ exponent % modulus + * + * @sig: RSA PKCS1.5 signature + * @sig_len: Length of signature in number of bytes + * @node: Node with RSA key elements like modulus, exponent, R^2, n0inv + * @out: Result in form of byte array + */ +int rsa_mod_exp_sw(const uint8_t *sig, uint32_t sig_len, + struct key_prop *node, uint8_t *out); + +#endif -- cgit From 31d2b4fd90f9305aad2e79872067e6c0243267de Mon Sep 17 00:00:00 2001 From: Ruchika Gupta Date: Fri, 23 Jan 2015 16:01:52 +0530 Subject: DM: crypto/rsa_mod_exp: Add rsa Modular Exponentiation DM driver Add a new rsa uclass for performing modular exponentiation and implement the software driver basing on this uclass. Signed-off-by: Ruchika Gupta CC: Simon Glass Acked-by: Simon Glass --- include/dm/uclass-id.h | 1 + include/u-boot/rsa-mod-exp.h | 34 +++++++++++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index f17c3c2b38..91bb90dcfb 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -33,6 +33,7 @@ enum uclass_id { UCLASS_I2C, /* I2C bus */ UCLASS_I2C_GENERIC, /* Generic I2C device */ UCLASS_I2C_EEPROM, /* I2C EEPROM device */ + UCLASS_MOD_EXP, /* RSA Mod Exp device */ UCLASS_COUNT, UCLASS_INVALID = -1, diff --git a/include/u-boot/rsa-mod-exp.h b/include/u-boot/rsa-mod-exp.h index 59cd9ea2d8..fce445a082 100644 --- a/include/u-boot/rsa-mod-exp.h +++ b/include/u-boot/rsa-mod-exp.h @@ -35,9 +35,41 @@ struct key_prop { * @sig: RSA PKCS1.5 signature * @sig_len: Length of signature in number of bytes * @node: Node with RSA key elements like modulus, exponent, R^2, n0inv - * @out: Result in form of byte array + * @out: Result in form of byte array of len equal to sig_len */ int rsa_mod_exp_sw(const uint8_t *sig, uint32_t sig_len, struct key_prop *node, uint8_t *out); +int rsa_mod_exp(struct udevice *dev, const uint8_t *sig, uint32_t sig_len, + struct key_prop *node, uint8_t *out); + +/** + * struct struct mod_exp_ops - Driver model for RSA Modular Exponentiation + * operations + * + * The uclass interface is implemented by all crypto devices which use + * driver model. + */ +struct mod_exp_ops { + /** + * Perform Modular Exponentiation + * + * Operation: out[] = sig ^ exponent % modulus + * + * @dev: RSA Device + * @sig: RSA PKCS1.5 signature + * @sig_len: Length of signature in number of bytes + * @node: Node with RSA key elements like modulus, exponent, + * R^2, n0inv + * @out: Result in form of byte array of len equal to sig_len + * + * This function computes exponentiation over the signature. + * Returns: 0 if exponentiation is successful, or a negative value + * if it wasn't. + */ + int (*mod_exp)(struct udevice *dev, const uint8_t *sig, + uint32_t sig_len, struct key_prop *node, + uint8_t *outp); +}; + #endif -- cgit From 11a9662ba9ed40829fd10acb3a0c75d148159921 Mon Sep 17 00:00:00 2001 From: Ruchika Gupta Date: Fri, 23 Jan 2015 16:01:53 +0530 Subject: configs: Move CONFIG_FIT_SIGNATURE to defconfig For the platforms which use,CONFIG_FIT_SIGNATURE, the required configs are moved to the platform's defconfig file. Selecting CONFIG_FIT_SIGNATURE using defconfig automatically resolves the dependencies for signature verification. The RSA library gets automatically selected and user does not have to define CONFIG_RSA manually. Signed-off-by: Ruchika Gupta CC: Simon Glass Acked-by: Simon Glass --- include/configs/am335x_evm.h | 4 ++-- include/configs/ids8313.h | 3 --- include/configs/sandbox.h | 3 --- include/configs/zynq-common.h | 6 ------ 4 files changed, 2 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 0004750518..f9bc23b407 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -23,8 +23,8 @@ # define CONFIG_TIMESTAMP # define CONFIG_LZO # ifdef CONFIG_ENABLE_VBOOT -# define CONFIG_FIT_SIGNATURE -# define CONFIG_RSA +# define CONFIG_FIT_SIGNATURE +# define CONFIG_RSA # endif #endif diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index f08483487d..2384864eb0 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -575,12 +575,9 @@ #define CONFIG_VERSION_VARIABLE -#define CONFIG_FIT -#define CONFIG_FIT_SIGNATURE #define CONFIG_IMAGE_FORMAT_LEGACY #define CONFIG_CMD_FDT #define CONFIG_CMD_HASH -#define CONFIG_RSA #define CONFIG_SHA1 #define CONFIG_SHA256 diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 657f751f3c..6fd29b9c73 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -41,9 +41,6 @@ #define CONFIG_OF_LIBFDT #define CONFIG_LMB -#define CONFIG_FIT -#define CONFIG_FIT_SIGNATURE -#define CONFIG_RSA #define CONFIG_CMD_FDT #define CONFIG_ANDROID_BOOT_IMAGE diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 2d28e89dd3..864528a5ea 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -276,17 +276,11 @@ #define CONFIG_OF_LIBFDT /* FIT support */ -#define CONFIG_FIT -#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ #define CONFIG_IMAGE_FORMAT_LEGACY /* enable also legacy image format */ /* FDT support */ #define CONFIG_DISPLAY_BOARDINFO_LATE -/* RSA support */ -#define CONFIG_FIT_SIGNATURE -#define CONFIG_RSA - /* Extend size of kernel image for uncompression */ #define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) -- cgit From c937ff6dc2ee3fcd8f97087427fe8ba5086852c4 Mon Sep 17 00:00:00 2001 From: Ruchika Gupta Date: Fri, 23 Jan 2015 16:01:54 +0530 Subject: lib/rsa: Modify rsa to use DM driver Modify rsa_verify to use the rsa driver of DM library .The tools will continue to use the same RSA sw library. CONFIG_RSA is now dependent on CONFIG_DM. All configurations which enable FIT based signatures have been modified to enable CONFIG_DM by default. Signed-off-by: Ruchika Gupta CC: Simon Glass Acked-by: Simon Glass --- include/configs/am335x_evm.h | 6 ++---- include/configs/sandbox.h | 1 - 2 files changed, 2 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index f9bc23b407..76ce7deb95 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -19,13 +19,11 @@ #include #ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_FIT # define CONFIG_FIT +#endif # define CONFIG_TIMESTAMP # define CONFIG_LZO -# ifdef CONFIG_ENABLE_VBOOT -# define CONFIG_FIT_SIGNATURE -# define CONFIG_RSA -# endif #endif #define CONFIG_SYS_BOOTM_LEN (16 << 20) diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 6fd29b9c73..e9d3f3226b 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -23,7 +23,6 @@ #define CONFIG_BOOTSTAGE #define CONFIG_BOOTSTAGE_REPORT -#define CONFIG_DM #define CONFIG_CMD_DEMO #define CONFIG_CMD_DM #define CONFIG_DM_DEMO -- cgit From 46fe2c04443f3d777791910da21649bb3ddf878f Mon Sep 17 00:00:00 2001 From: Ruchika Gupta Date: Fri, 23 Jan 2015 16:01:57 +0530 Subject: hash: Add function to find hash_algo struct with progressive hash The hash_algo structure has some implementations in which progressive hash API's are not defined. These are basically the hardware based implementations of SHA. An API is added to find the algo which has progressive hash API's defined. This can then be integrated with RSA checksum library which uses Progressive Hash API's. Signed-off-by: Ruchika Gupta CC: Simon Glass Acked-by: Simon Glass --- include/hash.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'include') diff --git a/include/hash.h b/include/hash.h index d8ec4f08e1..c0a7ebc6a6 100644 --- a/include/hash.h +++ b/include/hash.h @@ -127,6 +127,20 @@ int hash_block(const char *algo_name, const void *data, unsigned int len, */ int hash_lookup_algo(const char *algo_name, struct hash_algo **algop); +/** + * hash_progressive_lookup_algo() - Look up hash_algo for prog. hash support + * + * The function returns the pointer to the struct or -EPROTONOSUPPORT if the + * algorithm is not available with progressive hash support. + * + * @algo_name: Hash algorithm to look up + * @algop: Pointer to the hash_algo struct if found + * + * @return 0 if ok, -EPROTONOSUPPORT for an unknown algorithm. + */ +int hash_progressive_lookup_algo(const char *algo_name, + struct hash_algo **algop); + /** * hash_show() - Print out a hash algorithm and value * -- cgit From 2dd90027196175d0bcea411c933927d73994588d Mon Sep 17 00:00:00 2001 From: Ruchika Gupta Date: Fri, 23 Jan 2015 16:01:58 +0530 Subject: Use hash.c in mkimage Signed-off-by: Ruchika Gupta CC: Simon Glass Acked-by: Simon Glass --- include/hash.h | 34 ++++++++++++++++++---------------- 1 file changed, 18 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/include/hash.h b/include/hash.h index c0a7ebc6a6..f4eb100de0 100644 --- a/include/hash.h +++ b/include/hash.h @@ -17,7 +17,6 @@ enum { HASH_FLAG_ENV = 1 << 1, /* Allow env vars */ }; -#ifndef USE_HOSTCC #if defined(CONFIG_SHA1SUM_VERIFY) || defined(CONFIG_CRC32_VERIFY) #define CONFIG_HASH_VERIFY #endif @@ -77,6 +76,7 @@ struct hash_algo { int size); }; +#ifndef USE_HOSTCC /** * hash_command: Process a hash command for a particular algorithm * @@ -114,6 +114,23 @@ int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag, int hash_block(const char *algo_name, const void *data, unsigned int len, uint8_t *output, int *output_size); +/** + * hash_show() - Print out a hash algorithm and value + * + * You will get a message like this (without a newline at the end): + * + * "sha1 for 9eb3337c ... 9eb3338f ==> 7942ef1df479fd3130f716eb9613d107dab7e257" + * + * @algo: Algorithm used for hash + * @addr: Address of data that was hashed + * @len: Length of data that was hashed + * @output: Hash value to display + */ +void hash_show(struct hash_algo *algo, ulong addr, ulong len, + uint8_t *output); + +#endif /* !USE_HOSTCC */ + /** * hash_lookup_algo() - Look up the hash_algo struct for an algorithm * @@ -141,19 +158,4 @@ int hash_lookup_algo(const char *algo_name, struct hash_algo **algop); int hash_progressive_lookup_algo(const char *algo_name, struct hash_algo **algop); -/** - * hash_show() - Print out a hash algorithm and value - * - * You will get a message like this (without a newline at the end): - * - * "sha1 for 9eb3337c ... 9eb3338f ==> 7942ef1df479fd3130f716eb9613d107dab7e257" - * - * @algo: Algorithm used for hash - * @addr: Address of data that was hashed - * @len: Length of data that was hashed - * @output: Hash value to display - */ -void hash_show(struct hash_algo *algo, ulong addr, ulong len, - uint8_t *output); -#endif /* !USE_HOSTCC */ #endif -- cgit From b37b46f042ccfcfb97a9ef8b8a568812640a2a70 Mon Sep 17 00:00:00 2001 From: Ruchika Gupta Date: Fri, 23 Jan 2015 16:01:59 +0530 Subject: rsa: Use checksum algorithms from struct hash_algo Currently the hash functions used in RSA are called directly from the sha1 and sha256 libraries. Change the RSA checksum library to use the progressive hash API's registered with struct hash_algo. This will allow the checksum library to use the hardware accelerated progressive hash API's once available. Signed-off-by: Ruchika Gupta CC: Simon Glass Acked-by: Simon Glass Signed-off-by: Simon Glass (Fixed build error in am335x_boneblack_vboot due to duplicate CONFIG_DM) Change-Id: Ic44279432f88d4e8594c6e94feb1cfcae2443a54 --- include/configs/ti_am335x_common.h | 2 ++ include/image.h | 5 +++-- include/u-boot/rsa-checksum.h | 17 +++++++++++++---- 3 files changed, 18 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 5ed86d9365..598526bf95 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -20,7 +20,9 @@ #define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC #ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_DM # define CONFIG_DM +#endif # define CONFIG_CMD_DM # define CONFIG_DM_GPIO # define CONFIG_DM_SERIAL diff --git a/include/image.h b/include/image.h index ee3afe3567..dcbc72fc1e 100644 --- a/include/image.h +++ b/include/image.h @@ -927,8 +927,9 @@ struct checksum_algo { #if IMAGE_ENABLE_SIGN const EVP_MD *(*calculate_sign)(void); #endif - void (*calculate)(const struct image_region region[], - int region_count, uint8_t *checksum); + int (*calculate)(const char *name, + const struct image_region region[], + int region_count, uint8_t *checksum); const uint8_t *rsa_padding; }; diff --git a/include/u-boot/rsa-checksum.h b/include/u-boot/rsa-checksum.h index c996fb3e4c..3c69d85ecb 100644 --- a/include/u-boot/rsa-checksum.h +++ b/include/u-boot/rsa-checksum.h @@ -16,9 +16,18 @@ extern const uint8_t padding_sha256_rsa4096[]; extern const uint8_t padding_sha256_rsa2048[]; extern const uint8_t padding_sha1_rsa2048[]; -void sha256_calculate(const struct image_region region[], int region_count, - uint8_t *checksum); -void sha1_calculate(const struct image_region region[], int region_count, - uint8_t *checksum); +/** + * hash_calculate() - Calculate hash over the data + * + * @name: Name of algorithm to be used for hash calculation + * @region: Array having info of regions over which hash needs to be calculated + * @region_count: Number of regions in the region array + * @checksum: Buffer contanining the output hash + * + * @return 0 if OK, < 0 if error + */ +int hash_calculate(const char *name, + const struct image_region region[], int region_count, + uint8_t *checksum); #endif -- cgit From 480d49eb0e21e346da9d8bb2e82a6c4778b39049 Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Tue, 27 Jan 2015 13:36:29 +0100 Subject: arndale: config: disable max77686 support There is no MAX77686 pmic on this board, so the driver support should be removed. Signed-off-by: Przemyslaw Marczak Cc: Minkyu Kang --- include/configs/arndale.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/configs/arndale.h b/include/configs/arndale.h index d68993bb1f..3ad4a9ba91 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -51,8 +51,6 @@ /* PMIC */ #define CONFIG_PMIC #define CONFIG_POWER_I2C -#define CONFIG_POWER_MAX77686 - #define CONFIG_PREBOOT -- cgit From 8c94a83883c61f9685304078b42bb686498ea60a Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Tue, 27 Jan 2015 13:36:30 +0100 Subject: exynos5250: config: disable max77686 driver This PMIC is not common for all Exynos5250 based boards, so should be romoved from common config. Signed-off-by: Przemyslaw Marczak Acked-by: Simon Glass Cc: Simon Glass Cc: Minkyu Kang --- include/configs/exynos5250-common.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'include') diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h index 671431397f..ae0e5ff47b 100644 --- a/include/configs/exynos5250-common.h +++ b/include/configs/exynos5250-common.h @@ -28,9 +28,6 @@ #define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK -/* PMIC */ -#define CONFIG_POWER_MAX77686 - /* Sound */ #define CONFIG_CMD_SOUND #ifdef CONFIG_CMD_SOUND -- cgit From ba1b4b1a0beb6350b9e36addc1fd4803e39eab0b Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Tue, 27 Jan 2015 13:36:31 +0100 Subject: smdk5250: config: enable max77686 driver support This commit enable support for the above driver, which was disabled in common config. Signed-off-by: Przemyslaw Marczak Acked-by: Simon Glass Cc: Simon Glass Cc: Minkyu Kang --- include/configs/smdk5250.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 83953728dd..3b06d305db 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -18,6 +18,8 @@ #include +/* PMIC */ +#define CONFIG_POWER_MAX77686 #define CONFIG_BOARD_COMMON #define CONFIG_ARCH_EARLY_INIT_R -- cgit From 47b37958f6f0f0fafba53480d1ef13143dd0244b Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Tue, 27 Jan 2015 13:36:38 +0100 Subject: odroid u3: enable dm i2c support This patch enables CONFIG_DM_I2C and also CONFIG_DM_I2C_COMPAT. The last one should be removed when the dm pmic framework will be finished. Signed-off-by: Przemyslaw Marczak Acked-by: Simon Glass Cc: Minkyu Kang --- include/configs/odroid.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 807e96bbaa..9d5dbdce36 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -177,12 +177,11 @@ /* I2C */ #define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C +#define CONFIG_DM_I2C +#define CONFIG_DM_I2C_COMPAT #define CONFIG_SYS_I2C_S3C24X0 #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0 -#define CONFIG_MAX_I2C_NUM 8 -#define CONFIG_SYS_I2C_INIT_BOARD /* POWER */ #define CONFIG_POWER -- cgit From 189d80166b31db55b99190be3164c8d3348b57fc Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Tue, 27 Jan 2015 13:36:39 +0100 Subject: exynos5: enable dm i2c This patch enables CONFIG_DM_I2C and also CONFIG_DM_I2C_COMPAT. The last one should be removed when all the i2c peripheral drivers will use dm i2c framework. Signed-off-by: Przemyslaw Marczak Acked-by: Simon Glass Cc: Akshay Saraswat Cc: Minkyu Kang Cc: Simon Glass --- include/configs/exynos5-common.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index ad63f3c549..0ba39a23dd 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -126,12 +126,11 @@ #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) /* I2C */ -#define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_SYS_I2C +#define CONFIG_DM_I2C +#define CONFIG_DM_I2C_COMPAT #define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ #define CONFIG_SYS_I2C_S3C24X0 -#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 #define CONFIG_I2C_EDID -- cgit From d744d5613639088246b27edb9ce91ccbd663e5a5 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 26 Jan 2015 20:29:39 -0700 Subject: dm: i2c: Add two more I2C init functions to the compatibility layer These functions are useful in case the board calls them. Also fix a missing parameter caused by applying the wrong patch (actually I failed to send v2 and applied v1 by mistake). Signed-off-by: Simon Glass --- include/i2c.h | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/i2c.h b/include/i2c.h index 95d6f28771..27fe00f173 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -225,7 +225,7 @@ int i2c_get_bus_num_fdt(int node); unsigned int i2c_get_bus_num(void); /** - * i2c_set_bus_num(): Compatibility function for driver model + * i2c_set_bus_num() - Compatibility function for driver model * * Sets the 'current' bus */ @@ -241,6 +241,21 @@ static inline unsigned int I2C_GET_BUS(void) return i2c_get_bus_num(); } +/** + * i2c_init() - Compatibility function for driver model + * + * This function does nothing. + */ +void i2c_init(int speed, int slaveaddr); + +/** + * board_i2c_init() - Compatibility function for driver model + * + * @param blob Device tree blbo + * @return the number of I2C bus + */ +void board_i2c_init(const void *blob); + #endif /* -- cgit From 85df958ce267c602a4ec5f1e41f336c5a8d3b441 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 26 Jan 2015 20:29:40 -0700 Subject: dm: cros_ec: Convert cros_ec_i2c over to driver model Move this driver to use driver model and update the snow configuration to match. Signed-off-by: Simon Glass --- include/configs/snow.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/snow.h b/include/configs/snow.h index 7eaa58697e..ce6676eae7 100644 --- a/include/configs/snow.h +++ b/include/configs/snow.h @@ -22,6 +22,7 @@ #define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ #define CONFIG_POWER_TPS65090_I2C +#define CONFIG_DM_CROS_EC #define CONFIG_BOARD_COMMON #define CONFIG_ARCH_EARLY_INIT_R -- cgit From cc11b39288c402ca14ebf4e4cc15c7a72569034b Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 19 Jan 2015 16:39:11 -0700 Subject: distro_bootcmd: read DHCP boot script name from a variable Modify $bootcmd_dhcp to read the downloaded script filename from an environment variable rather than hard-coding it. This allows the user (or another script) to select a different script name if they want, without editing the whole value of $bootcmd_dhcp. Signed-off-by: Stephen Warren --- include/config_distro_bootcmd.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index 90ab21a727..49674f4537 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -110,7 +110,7 @@ #define BOOTENV_DEV_DHCP(devtypeu, devtypel, instance) \ "bootcmd_dhcp=" \ BOOTENV_RUN_USB_INIT \ - "if dhcp ${scriptaddr} boot.scr.uimg; then " \ + "if dhcp ${scriptaddr} ${boot_script_dhcp}; then " \ "source ${scriptaddr}; " \ "fi\0" #define BOOTENV_DEV_NAME_DHCP(devtypeu, devtypel, instance) \ @@ -154,6 +154,7 @@ BOOTENV_SHARED_IDE \ "boot_prefixes=/ /boot/\0" \ "boot_scripts=boot.scr.uimg boot.scr\0" \ + "boot_script_dhcp=boot.scr.uimg\0" \ BOOTENV_BOOT_TARGETS \ \ "boot_extlinux=" \ -- cgit From 9561723c76873c5f0d8b96e1aa5072ae68dab20b Mon Sep 17 00:00:00 2001 From: Chris Kuethe Date: Wed, 21 Jan 2015 20:52:33 -0800 Subject: arm: switch armltd vexpress to GENERIC_BOARD only tested tested under QEMU with vexpress_ca9x4 ("-M vexpress-a9") and vexpress_ca15_tc2 ("-M vexpress-a15"). Makes the ugly warning go away. Signed-off-by: Chris Kuethe --- include/configs/vexpress_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index 7e78f8ac8f..2dea921045 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -122,7 +122,7 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_SYS_L2CACHE_OFF 1 #define CONFIG_INITRD_TAG 1 - +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_OF_LIBFDT 1 /* Size of malloc() pool */ -- cgit From f91afc4d001010a31b53c232b3b1873cb789381e Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 23 Jan 2015 11:50:53 +0100 Subject: vexpress64: get rid of CONFIG_SYS_EXTRA_OPTIONS The Versatile Express ARMv8 semihosted FVP platform is still using the legacy CONFIG_SYS_EXTRA_OPTIONS method to configure some compile-time flags. Get rid of this and create a Kconfig entry for the FVP model, and a selectable bool for the semihosting library. The FVP subboard is now modeled as a target choice so we can eventually choose between different ARMv8 versatile express boards (FVP, base model, Juno...) this way. All dependent symbols are updated to reflect this. The 64bit Versatile Express board symbols are renamed VEXPRESS64 so we have some chance to see what is actually going on. Tested on the FVP fast model. Acked-by: Steve Rae Signed-off-by: Linus Walleij --- include/configs/vexpress_aemv8a.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 027d78b591..85894bedf8 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -11,9 +11,9 @@ /* We use generic board for v8 Versatile Express */ #define CONFIG_SYS_GENERIC_BOARD -#ifdef CONFIG_BASE_FVP +#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP #ifndef CONFIG_SEMIHOSTING -#error CONFIG_BASE_FVP requires CONFIG_SEMIHOSTING +#error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING #endif #define CONFIG_BOARD_LATE_INIT #define CONFIG_ARMV8_SWITCH_TO_EL1 @@ -21,8 +21,8 @@ #define CONFIG_REMAKE_ELF -#ifndef CONFIG_BASE_FVP -/* Base FVP not using GICv3 yet */ +#ifndef CONFIG_TARGET_VEXPRESS64_BASE_FVP +/* Base FVP and Juno not using GICv3 yet */ #define CONFIG_GICV3 #endif @@ -40,7 +40,7 @@ #define CONFIG_BOOTP_VCI_STRING "U-boot.armv8.vexpress_aemv8a" /* Link Definitions */ -#ifdef CONFIG_BASE_FVP +#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP /* ATF loads u-boot here for BASE_FVP model */ #define CONFIG_SYS_TEXT_BASE 0x88000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) @@ -54,7 +54,7 @@ /* SMP Spin Table Definitions */ -#ifdef CONFIG_BASE_FVP +#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP #define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) #else #define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) @@ -119,7 +119,7 @@ #define GICR_BASE (0x2f100000) #else -#ifdef CONFIG_BASE_FVP +#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP #define GICD_BASE (0x2f000000) #define GICC_BASE (0x2c000000) #else @@ -191,7 +191,7 @@ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Initial environment variables */ -#ifdef CONFIG_BASE_FVP +#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP #define CONFIG_EXTRA_ENV_SETTINGS \ "kernel_name=uImage\0" \ "kernel_addr_r=0x80000000\0" \ -- cgit From ffc103732c82faa945c85bbb7c5c34c30b6fac72 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 23 Jan 2015 14:41:10 +0100 Subject: vexpress64: support the Juno Development Platform The Juno Development Platform is a physical Versatile Express device with some differences from the emulated semihosting models. The main difference is that the system is split in a SoC and an FPGA where the SoC hosts the serial ports at totally different adresses. Signed-off-by: Linus Walleij --- include/configs/vexpress_aemv8a.h | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 85894bedf8..7fb28a54ba 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -21,7 +21,8 @@ #define CONFIG_REMAKE_ELF -#ifndef CONFIG_TARGET_VEXPRESS64_BASE_FVP +#if !defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) && \ + !defined(CONFIG_TARGET_VEXPRESS64_JUNO) /* Base FVP and Juno not using GICv3 yet */ #define CONFIG_GICV3 #endif @@ -44,6 +45,9 @@ /* ATF loads u-boot here for BASE_FVP model */ #define CONFIG_SYS_TEXT_BASE 0x88000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) +#elif CONFIG_TARGET_VEXPRESS64_JUNO +#define CONFIG_SYS_TEXT_BASE 0xe0000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) #else #define CONFIG_SYS_TEXT_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) @@ -88,10 +92,15 @@ #define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6)) #define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7)) +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO +#define V2M_UART0 0x7ff80000 +#define V2M_UART1 0x7ff70000 +#else /* Not Juno */ #define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9)) #define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10)) #define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11)) #define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12)) +#endif #define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15)) @@ -122,6 +131,9 @@ #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP #define GICD_BASE (0x2f000000) #define GICC_BASE (0x2c000000) +#elif CONFIG_TARGET_VEXPRESS64_JUNO +#define GICD_BASE (0x2C010000) +#define GICC_BASE (0x2C02f000) #else #define GICD_BASE (0x2C001000) #define GICC_BASE (0x2C002000) @@ -140,7 +152,11 @@ /* PL011 Serial Configuration */ #define CONFIG_PL011_SERIAL +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO +#define CONFIG_PL011_CLOCK 7273800 +#else #define CONFIG_PL011_CLOCK 24000000 +#endif #define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ (void *)CONFIG_SYS_SERIAL1} #define CONFIG_CONS_INDEX 0 @@ -161,6 +177,7 @@ #define CONFIG_CMD_ENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI +#define CONFIG_CMD_LOADB #define CONFIG_CMD_MEMORY #define CONFIG_CMD_MII #define CONFIG_CMD_NET -- cgit From ad40610b48bc3e248f5e79d94084427aa6a0b9e2 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 23 Jan 2015 15:28:22 +0100 Subject: sunxi: Only enable i2c support in the SPL when needed We do not need i2c support in the SPL when there is no PMIC (some sun4i boards), or when the PMIC is not using i2c such as on sun6i and sun8i. This reduces the SPL size from (e.g.) 21812 to 19260 bytes. Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- include/configs/sunxi-common.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 4a5cab25d4..6cfd7e1489 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -181,7 +181,10 @@ #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 /* 512 KiB */ /* I2C */ +#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER #define CONFIG_SPL_I2C_SUPPORT +#endif + #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MVTWSI #define CONFIG_SYS_I2C_SPEED 400000 -- cgit From 37d46dd3c4f3617b88a5797aab3600d3a4f32bd5 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 26 Jan 2015 16:59:12 +0100 Subject: sunxi: rsb: Move rsb_set_device_mode() call to rsb_init() It turns out that the device_mode_data is rsb specific, rather then slave specific, so integrate the rsb_set_device_mode() call into rsb_init(). Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- include/axp221.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/axp221.h b/include/axp221.h index 6f24a617b6..a20e25c2f8 100644 --- a/include/axp221.h +++ b/include/axp221.h @@ -12,7 +12,6 @@ #define AXP223_DEVICE_ADDR 0x3a3 #define AXP223_RUNTIME_ADDR 0x2d -#define AXP223_DEVICE_MODE_DATA 0x7c3e00 /* Page 0 addresses */ #define AXP221_CHIP_ID 0x03 -- cgit From 250e039da8c7e485dabdc84f0457b2a901757e28 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 27 Jan 2015 22:13:27 -0700 Subject: pci: Add a function to find a device by class There is an existing function prototype in the header file but it is not implemented. Implement something similar. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- include/pci.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'include') diff --git a/include/pci.h b/include/pci.h index 4fbb8f6729..004a048d2f 100644 --- a/include/pci.h +++ b/include/pci.h @@ -644,8 +644,7 @@ extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index); extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index); -extern pci_dev_t pci_find_class(int wanted_class, int wanted_sub_code, - int wanted_prog_if, int index); +pci_dev_t pci_find_class(unsigned int find_class, int index); extern int pci_hose_config_device(struct pci_controller *hose, pci_dev_t dev, -- cgit From 34236238359253ef5342843a3cca09dcca939262 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 27 Jan 2015 22:13:28 -0700 Subject: x86: pci: Add PCI IDs for Minnowboard Max This board includes a few IDs we have not seen before. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- include/pci_ids.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/pci_ids.h b/include/pci_ids.h index 26f4748685..1012abecef 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -1346,6 +1346,7 @@ #define PCI_VENDOR_ID_REALTEK 0x10ec #define PCI_DEVICE_ID_REALTEK_8139 0x8139 +#define PCI_DEVICE_ID_REALTEK_8168 0x8168 #define PCI_VENDOR_ID_XILINX 0x10ee #define PCI_DEVICE_ID_RME_DIGI96 0x3fc0 @@ -2594,6 +2595,10 @@ #define PCI_DEVICE_ID_INTEL_I960 0x0960 #define PCI_DEVICE_ID_INTEL_I960RM 0x0962 #define PCI_DEVICE_ID_INTEL_CENTERTON_ILB 0x0c60 +#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO 0x0f15 +#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD 0x0f16 +#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC 0x0f1c +#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA 0x0f23 #define PCI_DEVICE_ID_INTEL_82541ER 0x1078 #define PCI_DEVICE_ID_INTEL_82541GI_LF 0x107c #define PCI_DEVICE_ID_INTEL_82542 0x1000 -- cgit From bc17d8f4ac41a6a4bcc4b28f1c6216a5a034fa63 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 27 Jan 2015 22:13:34 -0700 Subject: x86: video: Allow video ROM execution to fall back to the other method If the BIOS emulator is not available, allow use of native execution if available, and vice versa. This can be controlled by the caller. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- include/pci_rom.h | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/pci_rom.h b/include/pci_rom.h index 4ba36eb1b7..2f1665d17a 100644 --- a/include/pci_rom.h +++ b/include/pci_rom.h @@ -33,14 +33,25 @@ struct pci_rom_data { uint16_t reserved_2; }; +/* + * Determines which execution method is used and whether we allow falling back + * to the other if the requested method is not available. + */ +enum pci_rom_emul { + PCI_ROM_EMULATE = 0 << 0, + PCI_ROM_USE_NATIVE = 1 << 0, + PCI_ROM_ALLOW_FALLBACK = 1 << 1, +}; + /** * pci_run_vga_bios() - Run the VGA BIOS in an x86 PC * * @dev: Video device containing the BIOS * @int15_handler: Function to call to handle int 0x15 - * @emulate: true to use the x86 emulator, false to run native + * @exec_method: flags from enum pci_rom_emul */ -int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate); +int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), + int exec_method); /** * board_map_oprom_vendev() - map several PCI IDs to the one the ROM expects -- cgit From 0e063dff5c8a555ad92e26edb5c6358a127d5c8f Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 5 Feb 2015 14:30:21 +0900 Subject: ARM: UniPhier: use "&&" instead of "; " in commands Run the next command only when the previous one succeeded. Signed-off-by: Masahiro Yamada --- include/configs/uniphier.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 9ad47f6933..43d2a4c359 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012-2014 Panasonic Corporation + * Copyright (C) 2012-2015 Panasonic Corporation * Author: Masahiro Yamada * * SPDX-License-Identifier: GPL-2.0+ @@ -235,11 +235,11 @@ "image_offset=0x00080000\0" \ "image_size=0x00f00000\0" \ "verify=n\0" \ - "norboot=run add_default_bootargs;" \ + "norboot=run add_default_bootargs &&" \ "bootm $image_offset\0" \ - "nandboot=run add_default_bootargs;" \ - "nand read $loadaddr $image_offset $image_size;" \ - "bootm\0" \ + "nandboot=run add_default_bootargs &&" \ + "nand read $loadaddr $image_offset $image_size &&" \ + "bootm\0" \ "add_default_bootargs=setenv bootargs $bootargs" \ " console=ttyS0,$baudrate\0" \ -- cgit From 75bc8e85b5aa44c8f834ec9518c8ca4a7c1d7067 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 5 Feb 2015 14:30:22 +0900 Subject: ARM: UniPhier: add environment variable to update images in NAND To boot UniPhier boards with the NAND boot mode, two images (u-boot-spl.bin and u-boot-dtb.img) must be written at the correct offset addresses. TFTP downloading is useful to update such images in the NAND device. We generally do: => nand erase 0 0x100000 => tftpboot u-boot-spl.bin => nand write $loadaddr 0 0x10000 => tftpboot u-boot-dtb.img => nand write $loadaddr 0x10000 0xf0000 It is a tedious and error-prone operation. This commit provides the shorthand: => run nandupdate Signed-off-by: Masahiro Yamada --- include/configs/uniphier.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 43d2a4c359..35bea1a72f 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -235,6 +235,11 @@ "image_offset=0x00080000\0" \ "image_size=0x00f00000\0" \ "verify=n\0" \ + "nandupdate=nand erase 0 0x100000 &&" \ + "tftpboot u-boot-spl.bin &&" \ + "nand write $loadaddr 0 0x10000 &&" \ + "tftpboot u-boot-dtb.img &&" \ + "nand write $loadaddr 0x10000 0xf0000\0" \ "norboot=run add_default_bootargs &&" \ "bootm $image_offset\0" \ "nandboot=run add_default_bootargs &&" \ -- cgit From 84ccd791afd580c35c73be2b395d4a1d3f24200c Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 5 Feb 2015 14:42:54 +0900 Subject: ARM: UniPhier: move pin_init() to board_early_init_f() Currently, I/O pin settings are not necessary for SPL. The board_early_init_f() seems a suitable place to call pin_init(). Signed-off-by: Masahiro Yamada --- include/configs/uniphier.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 35bea1a72f..15cb223997 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -95,6 +95,7 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_BOARD_LATE_INIT -- cgit From 35adfc4d259e7985abaffa32cb9578640d09225c Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 5 Feb 2015 14:42:55 +0900 Subject: ARM: UniPhier: move SPL init functions to spl_board_init() Now init functions called from board_postclk_init() and dram_init() are only necessary for SPL. Move them to spl_board_init() for clean-up. Signed-off-by: Masahiro Yamada --- include/configs/uniphier.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 15cb223997..12290ebec6 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -275,8 +275,6 @@ #define CONFIG_SPL_TEXT_BASE 0x00100000 #endif -#define CONFIG_BOARD_POSTCLK_INIT - #ifndef CONFIG_SPL_BUILD #define CONFIG_SKIP_LOWLEVEL_INIT #endif -- cgit From 08fda258ee127db50f76d6600cc6bf2268e0a178 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 5 Feb 2015 14:42:56 +0900 Subject: ARM: UniPhier: revive support card info Since commit 0365ffcc0bd6 (generic-board: show model name in board_init_f() too), the support card information has not been displayed because check_support_card() is invoked only when show_board_info() fails to get the model name from Device Tree. This commit adds misc_init_f() function to call check_support_card() from there. Signed-off-by: Masahiro Yamada --- include/configs/uniphier.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 12290ebec6..9420e6b48b 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -95,6 +95,7 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_MISC_INIT_F #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_BOARD_LATE_INIT -- cgit From 815451e0d12e72ea47b0ca2eb4ac610823bfb40c Mon Sep 17 00:00:00 2001 From: DrEagle Date: Wed, 17 Dec 2014 15:02:44 +0100 Subject: kirkwood: sheevaplug: fix style MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Gérald Kerma Reviewed-by: Luka Perkov --- include/configs/sheevaplug.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index 21c8bda9f3..3ebc989638 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -51,6 +51,7 @@ #define CONFIG_CMD_NAND #define CONFIG_CMD_PING #define CONFIG_CMD_USB + /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros -- cgit From 7f30f4b5b285cb91e1e25b5b61a04beabe8c470b Mon Sep 17 00:00:00 2001 From: DrEagle Date: Wed, 17 Dec 2014 15:02:45 +0100 Subject: kirkwood: sheevaplug: fix multiple defines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Gérald Kerma Reviewed-by: Luka Perkov --- include/configs/sheevaplug.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index 3ebc989638..589655ab19 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -142,6 +142,5 @@ #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ #define CONFIG_MTD_PARTITIONS #define CONFIG_CMD_MTDPARTS -#define CONFIG_LZO #endif /* _CONFIG_SHEEVAPLUG_H */ -- cgit From 9a5e0a7d5bd0e1758fcc59db524c1695d0dab7e0 Mon Sep 17 00:00:00 2001 From: DrEagle Date: Wed, 17 Dec 2014 15:02:48 +0100 Subject: kirkwood: sheevaplug: add FDT support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit LIBFDT feature is required to support new kernels. Signed-off-by: Gérald Kerma Reviewed-by: Luka Perkov --- include/configs/sheevaplug.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index 589655ab19..84029cb399 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -32,6 +32,11 @@ #define CONFIG_LZMA #define CONFIG_LZO +/* + * Enable device tree support + */ +#define CONFIG_OF_LIBFDT + /* * Miscellaneous configurable options */ -- cgit From e7778ec153e279e451bf7c55c05c76e76b095875 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 19 Jan 2015 11:33:47 +0100 Subject: arm: maxbcm: Enable SPL to include DDR training code into U-Boot This patch adds SPL support to the maxbcm MV78460 based board. Including the fixed DDR configuratrion needed for the DDR training code. And the the serdes PHY init code. Signed-off-by: Stefan Roese Reviewed-by: Luka Perkov --- include/configs/maxbcm.h | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) (limited to 'include') diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index 72217bdb57..4e962a3604 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -65,4 +65,51 @@ */ #include "mv-common.h" +/* + * Memory layout while starting into the bin_hdr via the + * BootROM: + * + * 0x4000.4000 - 0x4003.4000 headers space (192KiB) + * 0x4000.4030 bin_hdr start address + * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) + * 0x4007.fffc BootROM stack top + * + * The address space between 0x4007.fffc and 0x400f.fff is not locked in + * L2 cache thus cannot be used. + */ + +/* SPL */ +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x40004030 +#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10) + +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/mvebu-common/u-boot-spl.lds" + +/* SPL related SPI defines */ +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 + +/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ +#define CONFIG_SYS_MVEBU_DDR +#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ + #endif /* _CONFIG_DB_MV7846MP_GP_H */ -- cgit From 2554167cc158001cd1befb93e10829fc534bfada Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 19 Jan 2015 11:33:46 +0100 Subject: arm: db-mv784mp-gp: Enable SPL to include DDR training code into U-Boot This patch adds SPL support to the db-mv784mp-gp eval board. Signed-off-by: Stefan Roese Reviewed-by: Luka Perkov --- include/configs/db-mv784mp-gp.h | 49 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) (limited to 'include') diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index cb03e33b6e..1683a1582f 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -11,6 +11,8 @@ * High Level Configuration Options (easy to change) */ #define CONFIG_ARMADA_XP /* SOC Family Name */ +#define CONFIG_DB_784MP_GP /* Board target name for DDR training */ + #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ #define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_BOARDINFO_LATE @@ -65,4 +67,51 @@ */ #include "mv-common.h" +/* + * Memory layout while starting into the bin_hdr via the + * BootROM: + * + * 0x4000.4000 - 0x4003.4000 headers space (192KiB) + * 0x4000.4030 bin_hdr start address + * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) + * 0x4007.fffc BootROM stack top + * + * The address space between 0x4007.fffc and 0x400f.fff is not locked in + * L2 cache thus cannot be used. + */ + +/* SPL */ +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x40004030 +#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10) + +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/mvebu-common/u-boot-spl.lds" + +/* SPL related SPI defines */ +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 + +/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ +#define CONFIG_SYS_MVEBU_DDR +#define CONFIG_SPD_EEPROM 0x4e + #endif /* _CONFIG_DB_MV7846MP_GP_H */ -- cgit From 68102b81e8fb699087ec5757a75676c6c65af3fd Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 19 Jan 2015 11:33:39 +0100 Subject: arm: mvebu: maxbcm: Fix compilation warning and add Spansion SPI NOR support This patch fixes the following compilation warning for maxbcm: Building maxbcm board... text data bss dec hex filename 160075 6596 38240 204911 3206f ./u-boot board/maxbcm/maxbcm.c: In function 'reset_phy': board/maxbcm/maxbcm.c:68:6: warning: unused variable 'reg' [-Wunused-variable] u16 reg; ^ board/maxbcm/maxbcm.c:66:6: warning: unused variable 'devadr' [-Wunused-variable] u16 devadr = CONFIG_PHY_BASE_ADDR; ^ Additionally support Spansion SPI NOR flash is added. With larger SPI device support via the CONFIG_SPI_FLASH_BAR define. Signed-off-by: Stefan Roese Reviewed-by: Luka Perkov --- include/configs/maxbcm.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index 4e962a3604..5999d60146 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -43,6 +43,8 @@ #define CONFIG_SF_DEFAULT_SPEED 1000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 #define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_BAR /* Environment in SPI NOR flash */ #define CONFIG_ENV_IS_IN_SPI_FLASH -- cgit From 91785f70b9b7ebfd1a2da4772a8268b36f58fa3d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 27 Jan 2015 22:13:39 -0700 Subject: x86: mmc: Move common FSP functions into a common file Since these board functions seem to be the same for all boards which use FSP, move them into a common file. We can adjust this later if future FSPs need more flexibility. This creates a generic PCI MMC device. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng --- include/mmc.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'include') diff --git a/include/mmc.h b/include/mmc.h index 09101e2c87..56d97bbdcf 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -438,6 +438,20 @@ int board_mmc_init(bd_t *bis); int cpu_mmc_init(bd_t *bis); int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr); +struct pci_device_id; + +/** + * pci_mmc_init() - set up PCI MMC devices + * + * This finds all the matching PCI IDs and sets them up as MMC devices. + * + * @name: Name to use for devices + * @mmc_supported: PCI IDs to search for + * @num_ids: Number of elements in @mmc_supported + */ +int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported, + int num_ids); + /* Set block count limit because of 16 bit register limit on some hardware*/ #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535 -- cgit From abbdb262570f415b5eaea036486076669eff1e76 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 27 Jan 2015 22:13:44 -0700 Subject: scsi: bootstage: Measure time taken to scan the bus On some hardware this time can be significant. Add bootstage support for measuring this. The result can be obtained using 'bootstage report' or passed on to the Linux via the device tree. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- include/bootstage.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/bootstage.h b/include/bootstage.h index df13ab2f63..6b7588d38f 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -194,6 +194,7 @@ enum bootstage_id { BOOTSTAGE_ID_MAIN_CPU_READY, BOOTSTAGE_ID_ACCUM_LCD, + BOOTSTAGE_ID_ACCUM_SCSI, /* a few spare for the user, from here */ BOOTSTAGE_ID_USER, -- cgit From 8b4d659f4b3ce0e27253fa14066d380ea02b6695 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 27 Jan 2015 22:13:45 -0700 Subject: x86: Enable bootstage features Allow measuring of boot time using bootstage. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng --- include/configs/x86-common.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index ecedfc3ab1..66d4894256 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -245,6 +245,9 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTSTAGE +#define CONFIG_CMD_BOOTSTAGE + #define CONFIG_CMD_USB #define CONFIG_EXTRA_ENV_SETTINGS \ -- cgit From 3a1a18ff1867d6f94921a24992354d3a547666d6 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 27 Jan 2015 22:13:47 -0700 Subject: x86: Add support for Intel Minnowboard Max This is a relatively low-cost x86 board in a small form factor. The main peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800 series CPU. So far only the dual core 2GB variant is supported. This uses the existing FSP support. Binary blobs are required to make this board work. The microcode update is included as a patch (all 3000 lines of it). Change-Id: I0088c47fe87cf08ae635b343d32c332269062156 Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- include/configs/minnowmax.h | 72 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 include/configs/minnowmax.h (limited to 'include') diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h new file mode 100644 index 0000000000..823e051eb1 --- /dev/null +++ b/include/configs/minnowmax.h @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_X86_SERIAL +#define CONFIG_SMSC_LPC47M + +#define CONFIG_PCI_MEM_BUS 0xd0000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_PREF_BUS 0xc0000000 +#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS +#define CONFIG_PCI_PREF_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x2000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0xe000 + +#define CONFIG_SYS_EARLY_PCI_INIT +#define CONFIG_PCI_PNP +#define CONFIG_RTL8169 +#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ + "stdout=vga,serial\0" \ + "stderr=vga,serial\0" + +#define CONFIG_SCSI_DEV_LIST \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA} +#define CONFIG_SPI_FLASH_SST + +#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC_SDMA +#define CONFIG_CMD_MMC + +#undef CONFIG_USB_MAX_CONTROLLER_COUNT +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#define CONFIG_X86_OPTION_ROM_FILE vga.bin +#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 + +#ifndef CONFIG_SYS_COREBOOT +#define CONFIG_VIDEO_VESA +#endif +#define VIDEO_IO_OFFSET 0 +#define CONFIG_X86EMU_RAW_IO +#define CONFIG_VGA_AS_SINGLE_DEVICE + +#define CONFIG_FIT_SIGNATURE +#define CONFIG_RSA + +/* Avoid a warning in the Realtek Ethernet driver */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#endif /* __CONFIG_H */ -- cgit From 7df546a653462c91bc88bf9bf465ff2e39fde59e Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sat, 24 Jan 2015 17:17:08 +0800 Subject: x86: Remove CONFIG_SATA_INTEL from x86-common.h CONFIG_SATA_INTEL is not referenced anywhere, so remove it. Signed-off-by: Bin Meng Acked-by: Simon Glass --- include/configs/x86-common.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 66d4894256..062e6c2219 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -39,7 +39,6 @@ /* SATA AHCI storage */ #define CONFIG_SCSI_AHCI -#define CONFIG_SATA_INTEL #ifdef CONFIG_SCSI_AHCI #define CONFIG_LIBATA #define CONFIG_SYS_64BIT_LBA -- cgit From afee3fb8c807e1ac9713ecb31d895008e3b5251a Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 2 Feb 2015 22:35:28 +0800 Subject: x86: Add basic Intel Galileo board support New board/intel/galileo board directory with minimum codes, plus board dts, defconfig and configuration files. Signed-off-by: Bin Meng Reviewed-by: Simon Glass Acked-by: Simon Glass --- include/configs/galileo.h | 53 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 include/configs/galileo.h (limited to 'include') diff --git a/include/configs/galileo.h b/include/configs/galileo.h new file mode 100644 index 0000000000..bead2fc64e --- /dev/null +++ b/include/configs/galileo.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2015, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_X86_SERIAL + +/* ns16550 UART is memory-mapped in Quark SoC */ +#undef CONFIG_SYS_NS16550_PORT_MAPPED + +#define CONFIG_PCI_MEM_BUS 0x90000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x20000000 + +#define CONFIG_PCI_PREF_BUS 0xb0000000 +#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS +#define CONFIG_PCI_PREF_SIZE 0x20000000 + +#define CONFIG_PCI_IO_BUS 0x2000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0xe000 + +#define CONFIG_SYS_EARLY_PCI_INIT +#define CONFIG_PCI_PNP + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + +/* SATA is not supported in Quark SoC */ +#undef CONFIG_SCSI_AHCI +#undef CONFIG_CMD_SCSI + +/* Video is not supported in Quark SoC */ +#undef CONFIG_VIDEO +#undef CONFIG_CFB_CONSOLE + +#endif /* __CONFIG_H */ -- cgit From c89ada017fe24891818c08a9e4b7c5ae4a9224e5 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 5 Feb 2015 23:42:26 +0800 Subject: fdtdec: Add compatible id and string for Intel Quark MRC Add COMPAT_INTEL_QRK_MRC and "intel,quark-mrc" so that fdtdec can decode Intel Quark MRC node. Signed-off-by: Bin Meng Acked-by: Simon Glass --- include/fdtdec.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/fdtdec.h b/include/fdtdec.h index 231eed7892..1bc70dba21 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -167,6 +167,7 @@ enum fdt_compat_id { COMPAT_INTEL_GMA, /* Intel Graphics Media Accelerator */ COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */ COMPAT_INTEL_ICH_SPI, /* Intel ICH7/9 SPI controller */ + COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */ COMPAT_COUNT, }; -- cgit From b1420c813074d39cd2452d7bc45374561d1cf223 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 5 Feb 2015 23:42:27 +0800 Subject: dt-bindings: Add Intel Quark MRC bindings Add standard dt-bindings macros to be used by Intel Quark MRC node. Signed-off-by: Bin Meng Acked-by: Simon Glass --- include/dt-bindings/mrc/quark.h | 83 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 include/dt-bindings/mrc/quark.h (limited to 'include') diff --git a/include/dt-bindings/mrc/quark.h b/include/dt-bindings/mrc/quark.h new file mode 100644 index 0000000000..e3ca8a25a3 --- /dev/null +++ b/include/dt-bindings/mrc/quark.h @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2015, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Intel Quark MRC bindings include several properties + * as part of an Intel Quark MRC node. In most cases, + * the value of these properties uses the standard values + * defined in this header. + */ + +#ifndef _DT_BINDINGS_QRK_MRC_H_ +#define _DT_BINDINGS_QRK_MRC_H_ + +/* MRC platform data flags */ +#define MRC_FLAG_ECC_EN 0x00000001 +#define MRC_FLAG_SCRAMBLE_EN 0x00000002 +#define MRC_FLAG_MEMTEST_EN 0x00000004 +/* 0b DDR "fly-by" topology else 1b DDR "tree" topology */ +#define MRC_FLAG_TOP_TREE_EN 0x00000008 +/* If set ODR signal is asserted to DRAM devices on writes */ +#define MRC_FLAG_WR_ODT_EN 0x00000010 + +/* DRAM width */ +#define DRAM_WIDTH_X8 0 +#define DRAM_WIDTH_X16 1 +#define DRAM_WIDTH_X32 2 + +/* DRAM speed */ +#define DRAM_FREQ_800 0 +#define DRAM_FREQ_1066 1 + +/* DRAM type */ +#define DRAM_TYPE_DDR3 0 +#define DRAM_TYPE_DDR3L 1 + +/* DRAM rank mask */ +#define DRAM_RANK(n) (1 << (n)) + +/* DRAM channel mask */ +#define DRAM_CHANNEL(n) (1 << (n)) + +/* DRAM channel width */ +#define DRAM_CHANNEL_WIDTH_X8 0 +#define DRAM_CHANNEL_WIDTH_X16 1 +#define DRAM_CHANNEL_WIDTH_X32 2 + +/* DRAM address mode */ +#define DRAM_ADDR_MODE0 0 +#define DRAM_ADDR_MODE1 1 +#define DRAM_ADDR_MODE2 2 + +/* DRAM refresh rate */ +#define DRAM_REFRESH_RATE_195US 1 +#define DRAM_REFRESH_RATE_39US 2 +#define DRAM_REFRESH_RATE_785US 3 + +/* DRAM SR temprature range */ +#define DRAM_SRT_RANGE_NORMAL 0 +#define DRAM_SRT_RANGE_EXTENDED 1 + +/* DRAM ron value */ +#define DRAM_RON_34OHM 0 +#define DRAM_RON_40OHM 1 + +/* DRAM rtt nom value */ +#define DRAM_RTT_NOM_40OHM 0 +#define DRAM_RTT_NOM_60OHM 1 +#define DRAM_RTT_NOM_120OHM 2 + +/* DRAM rd odt value */ +#define DRAM_RD_ODT_OFF 0 +#define DRAM_RD_ODT_60OHM 1 +#define DRAM_RD_ODT_120OHM 2 +#define DRAM_RD_ODT_180OHM 3 + +/* DRAM density */ +#define DRAM_DENSITY_512M 0 +#define DRAM_DENSITY_1G 1 +#define DRAM_DENSITY_2G 2 +#define DRAM_DENSITY_4G 3 + +#endif /* _DT_BINDINGS_QRK_MRC_H_ */ -- cgit From 38fc1cdae0fb7a429222b7b85f8cdaefbd078e21 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 4 Feb 2015 16:26:11 +0800 Subject: x86: pci: Add pci ids for Quark SoC Add pci ids for Intel Quark SoC. Signed-off-by: Bin Meng Acked-by: Simon Glass --- include/pci_ids.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/pci_ids.h b/include/pci_ids.h index 1012abecef..dc2ca218a6 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -2592,6 +2592,10 @@ #define PCI_DEVICE_ID_INTEL_MFD_EMMC0 0x0823 #define PCI_DEVICE_ID_INTEL_MFD_EMMC1 0x0824 #define PCI_DEVICE_ID_INTEL_MRST_SD2 0x084F +#define PCI_DEVICE_ID_INTEL_QRK_SDIO 0x08A7 +#define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936 +#define PCI_DEVICE_ID_INTEL_QRK_EMAC 0x0937 +#define PCI_DEVICE_ID_INTEL_QRK_ILB 0x095E #define PCI_DEVICE_ID_INTEL_I960 0x0960 #define PCI_DEVICE_ID_INTEL_I960RM 0x0962 #define PCI_DEVICE_ID_INTEL_CENTERTON_ILB 0x0c60 -- cgit From 6df7ffea1399de57e5b3be6e3cd0986869087663 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 4 Feb 2015 16:26:13 +0800 Subject: x86: Add SD/MMC support to quark/galileo Intel Galileo board has a microSD slot which is routed from Quark SoC SDIO controller. Enable SD/MMC support so that we can use an SD card. Signed-off-by: Bin Meng Acked-by: Simon Glass --- include/configs/galileo.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include') diff --git a/include/configs/galileo.h b/include/configs/galileo.h index bead2fc64e..d745f4eb89 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -50,4 +50,11 @@ #undef CONFIG_VIDEO #undef CONFIG_CFB_CONSOLE +/* SD/MMC support */ +#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC_SDMA +#define CONFIG_CMD_MMC + #endif /* __CONFIG_H */ -- cgit From 1b15fac15d9720b4a31a54fe07fd181ff0a28a80 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 2 Feb 2015 21:25:08 +0800 Subject: bootstage: Fix typos in the comment There are two typos in the comment block in bootstage.h, fix them. Signed-off-by: Bin Meng Acked-by: Simon Glass --- include/bootstage.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/bootstage.h b/include/bootstage.h index 6b7588d38f..0276cb3f60 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -86,9 +86,9 @@ enum bootstage_id { BOOTSTAGE_ID_POST_FAIL_R, /* Post failure reported after reloc */ /* - * This set is reported ony by x86, and the meaning is different. In + * This set is reported only by x86, and the meaning is different. In * this case we are reporting completion of a particular stage. - * This should probably change in he x86 code (which doesn't report + * This should probably change in the x86 code (which doesn't report * errors in any case), but discussion this can perhaps wait until we * have a generic board implementation. */ -- cgit From 5a4c9c22872725d9b02fb11fdcec063ccea9536f Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Mon, 15 Dec 2014 13:24:38 +0800 Subject: ARM: atmel: sama5d4ek: enable SPL support The sama5d4ek support boot up from NAND flash, SD/MMC card and also the SPI flash. Signed-off-by: Bo Shen --- include/configs/sama5d4ek.h | 56 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) (limited to 'include') diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index 09ab4d7f25..9e1b86a347 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -20,7 +20,9 @@ #define CONFIG_ARCH_CPU_INIT +#ifndef CONFIG_SPL_BUILD #define CONFIG_SKIP_LOWLEVEL_INIT +#endif #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_DISPLAY_CPUINFO @@ -66,8 +68,12 @@ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS #define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x210000 +#else #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ @@ -219,4 +225,54 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x200000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#ifdef CONFIG_SYS_USE_MMC +#define CONFIG_SPL_LDSCRIPT arch/arm/cpu/at91-common/u-boot-spl.lds +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT + +#elif CONFIG_SYS_USE_NANDFLASH +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_PMECC_CAP 8 +#define CONFIG_PMECC_SECTOR_SIZE 512 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_OOBSIZE 224 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 +#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER + +#elif CONFIG_SYS_USE_SERIALFLASH +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 + +#endif #endif -- cgit From 0b2a9824203deccf8e5ffd0db69f6aa9b771eb26 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Mon, 15 Dec 2014 13:24:39 +0800 Subject: ARM: atmel: sama5d4_xplained: enable spl support Signed-off-by: Bo Shen --- include/configs/sama5d4_xplained.h | 56 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) (limited to 'include') diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index 996973d99b..6493d567b4 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -20,7 +20,9 @@ #define CONFIG_ARCH_CPU_INIT +#ifndef CONFIG_SPL_BUILD #define CONFIG_SKIP_LOWLEVEL_INIT +#endif #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_DISPLAY_CPUINFO @@ -66,8 +68,12 @@ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS #define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x210000 +#else #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ @@ -221,4 +227,54 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x200000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#ifdef CONFIG_SYS_USE_MMC +#define CONFIG_SPL_LDSCRIPT arch/arm/cpu/at91-common/u-boot-spl.lds +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT + +#elif CONFIG_SYS_USE_NANDFLASH +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_PMECC_CAP 8 +#define CONFIG_PMECC_SECTOR_SIZE 512 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_OOBSIZE 224 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 +#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER + +#elif CONFIG_SYS_USE_SERIALFLASH +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 + +#endif #endif -- cgit From f5702d7d7fcb2c6668ebb131454bec8f4db82be5 Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Mon, 19 Jan 2015 15:25:56 +0800 Subject: ARM: at91: mmc portA support is only for at91sam9g20ek_2mmc board Current the MMC support will enable MCI port A, Which is only exist for 2mmc board. So by default we need to disable MMC (port A) support. And only enable it for 2mmc board. Otherwise, dataflash won't work in at91sam9260ek board as MMC has confliction with Dataflash in the CLK pin. Signed-off-by: Josh Wu --- include/configs/at91sam9260ek.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index a6a80de88a..c4b2e1666f 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -90,7 +90,6 @@ #define CONFIG_CMD_PING 1 #define CONFIG_CMD_DHCP 1 #define CONFIG_CMD_NAND 1 -#define CONFIG_CMD_MMC #define CONFIG_CMD_FAT #define CONFIG_CMD_USB 1 @@ -133,14 +132,17 @@ # define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9260EK #endif -/* DataFlash */ #ifndef CONFIG_AT91SAM9G20EK_2MMC +/* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH 1 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000 /* CS1 */ #define AT91_SPI_CLK 15000000 +#else +/* Enable MMC. The MCCK is conflicted with DataFlash */ +#define CONFIG_CMD_MMC #endif #ifdef CONFIG_AT91SAM9G20EK -- cgit From c3814406b064f1910461bddd14bc09701353ceed Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Tue, 20 Jan 2015 10:33:31 +0800 Subject: ARM: at91: sama5d3_xplained: save environment in a FAT file in MMC card This patch will save U-Boot environment as a file: uboot.env, in FAT partition instead of saving it in raw sector of MMC card. This make us easier to manage the environment file. Signed-off-by: Josh Wu Acked-by: Bo Shen --- include/configs/sama5d3_xplained.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index 9458047c06..5a0ab284ab 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -169,13 +169,14 @@ "bootz 0x22000000 - 0x21000000" #elif CONFIG_SYS_USE_MMC /* bootstrap + u-boot + env in sd card */ -#define CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_OFFSET 0x2000 -#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_IS_IN_FAT +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_FILE "uboot.env" +#define FAT_ENV_DEVICE_AND_PART "0" +#define CONFIG_ENV_SIZE 0x4000 #define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d3_xplained.dtb; " \ "fatload mmc 0:1 0x22000000 zImage; " \ "bootz 0x22000000 - 0x21000000" -#define CONFIG_SYS_MMC_ENV_DEV 0 #else #define CONFIG_ENV_IS_NOWHERE #endif -- cgit From a248558ae2894dd7a5a18480dd7011b70ed4bc50 Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Tue, 20 Jan 2015 10:33:32 +0800 Subject: ARM: at91: sama5d3xek: save enviroment as a FAT file in MMC card This patch will save U-Boot environment as a file: uboot.env, in FAT partition instead of in raw sector of MMC card. This make us easier to manage the environment file. Signed-off-by: Josh Wu Acked-by: Bo Shen --- include/configs/sama5d3xek.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index f2849d794e..cccc1edbb8 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -191,6 +191,7 @@ #if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) #define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE #endif #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ @@ -215,13 +216,14 @@ "bootm 0x22000000 - 0x21000000" #elif CONFIG_SYS_USE_MMC /* bootstrap + u-boot + env in sd card */ -#define CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_OFFSET 0x2000 -#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_IS_IN_FAT +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_FILE "uboot.env" +#define FAT_ENV_DEVICE_AND_PART "0" +#define CONFIG_ENV_SIZE 0x4000 #define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 dtb; " \ "fatload mmc 0:1 0x22000000 uImage; " \ "bootm 0x22000000 - 0x21000000" -#define CONFIG_SYS_MMC_ENV_DEV 0 #else #define CONFIG_ENV_IS_NOWHERE #endif -- cgit From 26961772ff2abd89dddf6232a458f8ff7d49c4f8 Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Tue, 20 Jan 2015 10:33:33 +0800 Subject: ARM: at91: at91sam9x5: save environment to a FAT file in MMC card This patch will save U-Boot environment as a file: uboot.env, in FAT partition instead of saving it in raw sector of MMC card. This make us easier to manage the environment file. Signed-off-by: Josh Wu Acked-by: Bo Shen --- include/configs/at91sam9x5ek.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index b1d4baaff9..6d8b71dced 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -203,11 +203,12 @@ "bootm 0x22000000" #else /* CONFIG_SYS_USE_MMC */ /* bootstrap + u-boot + env + linux in mmc */ -#define CONFIG_ENV_IS_IN_MMC -/* For FAT system, most cases it should be in the reserved sector */ -#define CONFIG_ENV_OFFSET 0x2000 -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_IS_IN_FAT +#define CONFIG_FAT_WRITE +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_FILE "uboot.env" +#define FAT_ENV_DEVICE_AND_PART "0" +#define CONFIG_ENV_SIZE 0x4000 #endif #ifdef CONFIG_SYS_USE_MMC -- cgit From f624162f954b2f8ed31b8f00b548b89e23f5d1bb Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 21 Jan 2015 08:38:23 +0100 Subject: arm, at91, taurus: enable WDT enable WDT for the taurus board. Signed-off-by: Heiko Schocher --- include/configs/taurus.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 65468ad165..b61dc2d115 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -121,6 +121,12 @@ #define CONFIG_RMII #define CONFIG_AT91_WANTS_COMMON_PHY +#define CONFIG_AT91SAM9_WATCHDOG +#if !defined(CONFIG_SPL_BUILD) +/* Enable the watchdog */ +#define CONFIG_HW_WATCHDOG +#endif + /* USB */ #if defined(CONFIG_BOARD_TAURUS) #define CONFIG_USB_ATMEL -- cgit From 657006a1c46f11784757f9437ffaaa5e0c4dea72 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 21 Jan 2015 09:22:20 +0100 Subject: arm, at91: taurus remove MACH_TYPE definitions in config file remove MACH_TYPE definitions in config file, as they come from the defconfig. Signed-off-by: Heiko Schocher --- include/configs/taurus.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'include') diff --git a/include/configs/taurus.h b/include/configs/taurus.h index b61dc2d115..2cf4558daa 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -21,9 +21,6 @@ */ #include -#define MACH_TYPE_TAURUS 2067 -#define MACH_TYPE_AXM 2068 - #define CONFIG_SYS_GENERIC_BOARD #if defined(CONFIG_SPL_BUILD) -- cgit From 832325c18d1d68e0ee46810f788421865f6372d9 Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Tue, 3 Feb 2015 13:58:10 +0300 Subject: arc: remove CPU hard-coded selection from board description in include/configs With switch to Kconfig we only need very board-specific descriptions in include/configs. CPU selection is performed with either defconfig or manually via menuconfig. Signed-off-by: Alexey Brodkin --- include/configs/arcangel4-be.h | 1 - include/configs/arcangel4.h | 1 - include/configs/axs101.h | 1 - include/configs/tb100.h | 1 - 4 files changed, 4 deletions(-) (limited to 'include') diff --git a/include/configs/arcangel4-be.h b/include/configs/arcangel4-be.h index 76163ab2a0..2ca209e1e4 100644 --- a/include/configs/arcangel4-be.h +++ b/include/configs/arcangel4-be.h @@ -11,7 +11,6 @@ * CPU configuration */ #define CONFIG_SYS_BIG_ENDIAN -#define CONFIG_ARC700 #define CONFIG_ARC_MMU_VER 3 #define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ diff --git a/include/configs/arcangel4.h b/include/configs/arcangel4.h index 81934a45a8..2afb63d80d 100644 --- a/include/configs/arcangel4.h +++ b/include/configs/arcangel4.h @@ -10,7 +10,6 @@ /* * CPU configuration */ -#define CONFIG_ARC700 #define CONFIG_ARC_MMU_VER 3 #define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ diff --git a/include/configs/axs101.h b/include/configs/axs101.h index c61ddd6fb7..a8a9cb3cba 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -10,7 +10,6 @@ /* * CPU configuration */ -#define CONFIG_ARC700 #define CONFIG_ARC_MMU_VER 3 #define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ diff --git a/include/configs/tb100.h b/include/configs/tb100.h index e9218f7d81..a59834383a 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -12,7 +12,6 @@ /* * CPU configuration */ -#define CONFIG_ARC700 #define CONFIG_ARC_MMU_VER 3 #define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ -- cgit From 812980bdd6c9112014f3946d1cb2728a2121ba34 Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Tue, 3 Feb 2015 13:58:11 +0300 Subject: arc: add more flavours of ARC700 series CPU Now we may select a particular version of ARC700: * ARC750D or * ARC770D It allows more flexible (or more fine tuned) configuration of U-Boot. Before that change we relied on minimal configuration but now we may use specific features of each CPU. Moreover allows us to escape manual selection of options that exist in both CPUs but may have say different version like MMUv2 in ARC750D vs MMUv3 in ARC770D. Signed-off-by: Alexey Brodkin --- include/configs/arcangel4-be.h | 1 - include/configs/arcangel4.h | 1 - include/configs/axs101.h | 1 - include/configs/tb100.h | 1 - 4 files changed, 4 deletions(-) (limited to 'include') diff --git a/include/configs/arcangel4-be.h b/include/configs/arcangel4-be.h index 2ca209e1e4..a43590bef5 100644 --- a/include/configs/arcangel4-be.h +++ b/include/configs/arcangel4-be.h @@ -11,7 +11,6 @@ * CPU configuration */ #define CONFIG_SYS_BIG_ENDIAN -#define CONFIG_ARC_MMU_VER 3 #define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ diff --git a/include/configs/arcangel4.h b/include/configs/arcangel4.h index 2afb63d80d..565f70e165 100644 --- a/include/configs/arcangel4.h +++ b/include/configs/arcangel4.h @@ -10,7 +10,6 @@ /* * CPU configuration */ -#define CONFIG_ARC_MMU_VER 3 #define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ diff --git a/include/configs/axs101.h b/include/configs/axs101.h index a8a9cb3cba..b94687c230 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -10,7 +10,6 @@ /* * CPU configuration */ -#define CONFIG_ARC_MMU_VER 3 #define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ diff --git a/include/configs/tb100.h b/include/configs/tb100.h index a59834383a..f3539506c2 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -12,7 +12,6 @@ /* * CPU configuration */ -#define CONFIG_ARC_MMU_VER 3 #define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ -- cgit From 205e7a7b77726abeff57576e2ecf2c6d4dc07ccf Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Tue, 3 Feb 2015 13:58:13 +0300 Subject: arc: select cache settings via menuconfig This change allows to keep board description clean and minimalistic. This is especially helpful if one board may house different CPUs with different features. It is applicable to both FPGA-based boards or those that have CPUs mounted on interchnagable daughter-boards. Signed-off-by: Alexey Brodkin --- include/configs/arcangel4-be.h | 1 - include/configs/arcangel4.h | 1 - include/configs/axs101.h | 4 ---- include/configs/tb100.h | 1 - 4 files changed, 7 deletions(-) (limited to 'include') diff --git a/include/configs/arcangel4-be.h b/include/configs/arcangel4-be.h index a43590bef5..b0bc8bc081 100644 --- a/include/configs/arcangel4-be.h +++ b/include/configs/arcangel4-be.h @@ -11,7 +11,6 @@ * CPU configuration */ #define CONFIG_SYS_BIG_ENDIAN -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ /* diff --git a/include/configs/arcangel4.h b/include/configs/arcangel4.h index 565f70e165..3268c56f7d 100644 --- a/include/configs/arcangel4.h +++ b/include/configs/arcangel4.h @@ -10,7 +10,6 @@ /* * CPU configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ /* diff --git a/include/configs/axs101.h b/include/configs/axs101.h index b94687c230..ff3fad312e 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -10,12 +10,8 @@ /* * CPU configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ -/* NAND controller DMA doesn't work correctly with D$ enabled */ -#define CONFIG_SYS_DCACHE_OFF - /* * Board configuration */ diff --git a/include/configs/tb100.h b/include/configs/tb100.h index f3539506c2..32675c43d4 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -12,7 +12,6 @@ /* * CPU configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ /* -- cgit From 1f9ad44546ea872fc6671602eb411377dd424c9e Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Tue, 3 Feb 2015 13:58:14 +0300 Subject: arc: add selection of endianess in Kconfig This change allows to keep board description clean and minimalistic. This is especially helpful if one board may house different CPUs with different features. It is applicable to both FPGA-based boards or those that have CPUs mounted on interchnagable daughter-boards. Signed-off-by: Alexey Brodkin --- include/configs/arcangel4-be.h | 88 ------------------------------------------ 1 file changed, 88 deletions(-) delete mode 100644 include/configs/arcangel4-be.h (limited to 'include') diff --git a/include/configs/arcangel4-be.h b/include/configs/arcangel4-be.h deleted file mode 100644 index b0bc8bc081..0000000000 --- a/include/configs/arcangel4-be.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CONFIG_ARCANGEL4_H_ -#define _CONFIG_ARCANGEL4_H_ - -/* - * CPU configuration - */ -#define CONFIG_SYS_BIG_ENDIAN -#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ - -/* - * Board configuration - */ -#define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */ - -#define CONFIG_ARCH_EARLY_INIT_R - -/* - * Memory configuration - */ -#define CONFIG_SYS_TEXT_BASE 0x81000000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */ - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */ -#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */ -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - -#define CONFIG_SYS_NO_FLASH - -/* - * UART configuration - * - */ -#define CONFIG_ARC_SERIAL -#define CONFIG_ARC_UART_BASE 0xC0FC1000 -#define CONFIG_BAUDRATE 115200 - -/* - * Command line configuration - */ -#include - -#define CONFIG_CMD_ELF - -#define CONFIG_OF_LIBFDT - -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_MAXARGS 16 - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */ -#define CONFIG_ENV_OFFSET 0 - -/* - * Environment configuration - */ -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_BOOTARGS "console=ttyARC0,115200n8" -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR - -/* - * Console configuration - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "arcangel4# " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - -#endif /* _CONFIG_ARCANGEL4_H_ */ -- cgit From 6eb651ad29636682067f76de4f40c45119269f8b Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Tue, 3 Feb 2015 13:58:15 +0300 Subject: arc: hard-code CONFIG_SYS_GENERIC_BOARD into asm/config.h There're no other options for ARC except "generic board" so ther's no point to define CONFIG_SYS_GENERIC_BOARD per board. We now have it set fo all ARC boards. Signed-off-by: Alexey Brodkin --- include/configs/arcangel4.h | 1 - include/configs/axs101.h | 1 - include/configs/tb100.h | 1 - 3 files changed, 3 deletions(-) (limited to 'include') diff --git a/include/configs/arcangel4.h b/include/configs/arcangel4.h index 3268c56f7d..60f30777dc 100644 --- a/include/configs/arcangel4.h +++ b/include/configs/arcangel4.h @@ -15,7 +15,6 @@ /* * Board configuration */ -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */ #define CONFIG_ARCH_EARLY_INIT_R diff --git a/include/configs/axs101.h b/include/configs/axs101.h index ff3fad312e..2340d99346 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -15,7 +15,6 @@ /* * Board configuration */ -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */ #define CONFIG_ARCH_EARLY_INIT_R diff --git a/include/configs/tb100.h b/include/configs/tb100.h index 32675c43d4..c6878fc08e 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -17,7 +17,6 @@ /* * Board configuration */ -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_ARCH_EARLY_INIT_R /* -- cgit From bcba9742ce39e96b36b8dfc96066ee3a71561bab Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Tue, 3 Feb 2015 13:58:16 +0300 Subject: arc: get rid of useless CONFIG_SKIP_LOWLEVEL_INIT Currently there's nothing related to really low-level init on ARC so CONFIG_SKIP_LOWLEVEL_INIT definition makes no sense. Signed-off-by: Alexey Brodkin --- include/configs/arcangel4.h | 2 -- include/configs/axs101.h | 2 -- 2 files changed, 4 deletions(-) (limited to 'include') diff --git a/include/configs/arcangel4.h b/include/configs/arcangel4.h index 60f30777dc..003a45d96d 100644 --- a/include/configs/arcangel4.h +++ b/include/configs/arcangel4.h @@ -15,8 +15,6 @@ /* * Board configuration */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */ - #define CONFIG_ARCH_EARLY_INIT_R /* diff --git a/include/configs/axs101.h b/include/configs/axs101.h index 2340d99346..4064ed2331 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -15,8 +15,6 @@ /* * Board configuration */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */ - #define CONFIG_ARCH_EARLY_INIT_R #define ARC_FPGA_PERIPHERAL_BASE 0xE0000000 -- cgit From a1dbe57d2d45d311e402c357831bbf5c5157a32c Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Tue, 3 Feb 2015 13:58:17 +0300 Subject: arc: hard-code CONFIG_ARCH_EARLY_INIT_R in asm/config.h Common arch_early_init_r() is used in "arc/lib/cpu.c" for all ARC boards so there's no sense in separate per-board definitions. Signed-off-by: Alexey Brodkin --- include/configs/arcangel4.h | 5 ----- include/configs/axs101.h | 5 ----- include/configs/tb100.h | 5 ----- 3 files changed, 15 deletions(-) (limited to 'include') diff --git a/include/configs/arcangel4.h b/include/configs/arcangel4.h index 003a45d96d..80d6438ba1 100644 --- a/include/configs/arcangel4.h +++ b/include/configs/arcangel4.h @@ -12,11 +12,6 @@ */ #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ -/* - * Board configuration - */ -#define CONFIG_ARCH_EARLY_INIT_R - /* * Memory configuration */ diff --git a/include/configs/axs101.h b/include/configs/axs101.h index 4064ed2331..e9a32314fd 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -12,11 +12,6 @@ */ #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ -/* - * Board configuration - */ -#define CONFIG_ARCH_EARLY_INIT_R - #define ARC_FPGA_PERIPHERAL_BASE 0xE0000000 #define ARC_APB_PERIPHERAL_BASE 0xF0000000 #define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000) diff --git a/include/configs/tb100.h b/include/configs/tb100.h index c6878fc08e..54eca6f574 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -14,11 +14,6 @@ */ #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ -/* - * Board configuration - */ -#define CONFIG_ARCH_EARLY_INIT_R - /* * Memory configuration */ -- cgit From 836d2cc2eef58c0d42d3112725dac475d0bd553e Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Tue, 3 Feb 2015 13:58:18 +0300 Subject: arc: move SYS_MONITOR_BASE setup in Konfig Following SPARK ARC now has SYS_MONITOR_BASE setup via Kconfig. This makes "include/configs/*.h" cleaner and more flexible. Signed-off-by: Alexey Brodkin --- include/configs/arcangel4.h | 1 - include/configs/axs101.h | 1 - include/configs/tb100.h | 1 - 3 files changed, 3 deletions(-) (limited to 'include') diff --git a/include/configs/arcangel4.h b/include/configs/arcangel4.h index 80d6438ba1..5e4097fb82 100644 --- a/include/configs/arcangel4.h +++ b/include/configs/arcangel4.h @@ -15,7 +15,6 @@ /* * Memory configuration */ -#define CONFIG_SYS_TEXT_BASE 0x81000000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 diff --git a/include/configs/axs101.h b/include/configs/axs101.h index e9a32314fd..5fb8aca4bc 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -20,7 +20,6 @@ /* * Memory configuration */ -#define CONFIG_SYS_TEXT_BASE 0x81000000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 diff --git a/include/configs/tb100.h b/include/configs/tb100.h index 54eca6f574..46df40661d 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -17,7 +17,6 @@ /* * Memory configuration */ -#define CONFIG_SYS_TEXT_BASE 0x84000000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -- cgit From 0267ba5d869cdc482c0b947ef8de89ce7403ac8c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 30 Jan 2015 10:51:46 +0100 Subject: common: Move dram_init() declaration to common location Signed-off-by: Michal Simek Reviewed-by: Simon Glass --- include/common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/common.h b/include/common.h index 97c8f79fc7..91294547f5 100644 --- a/include/common.h +++ b/include/common.h @@ -183,6 +183,7 @@ typedef void (interrupt_handler_t)(void *); /* * Function Prototypes */ +int dram_init(void); void hang (void) __attribute__ ((noreturn)); -- cgit From 4dd097427aeb6848fcb19c31b805abe1a3906913 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 27 Jan 2015 14:25:38 +0100 Subject: microblaze: Enable SPL_NOR support when FLASH_BASE is setup Simplify SPL NOR init. Signed-off-by: Michal Simek --- include/configs/microblaze-generic.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index bb07060002..2e1e64247f 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -452,7 +452,10 @@ #define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds" #define CONFIG_SPL_RAM_DEVICE -#define CONFIG_SPL_NOR_SUPPORT +#ifdef CONFIG_SYS_FLASH_BASE +# define CONFIG_SPL_NOR_SUPPORT +# define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE +#endif /* for booting directly linux */ #define CONFIG_SPL_OS_BOOT @@ -491,7 +494,6 @@ /* Just for sure that there is a space for stack */ #define CONFIG_SPL_STACK_SIZE 0x100 -#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \ -- cgit From e945f6dc2814f5f0d30b5b7e23821b3fd4faff5b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 8 May 2014 16:08:44 +0200 Subject: microblaze: Move architecture to use generic board init Compile code with -fPIC to get GOT. Do not build SPL with fPIC because it increasing SPL size for nothing. Signed-off-by: Michal Simek --- include/configs/microblaze-generic.h | 64 +++++------------------------------- 1 file changed, 9 insertions(+), 55 deletions(-) (limited to 'include') diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 2e1e64247f..622bc95104 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -106,62 +106,16 @@ # define CONFIG_XILINX_TB_WATCHDOG #endif -/* - * memory layout - Example - * CONFIG_SYS_TEXT_BASE = 0x1200_0000; defined in config.mk - * CONFIG_SYS_SRAM_BASE = 0x1000_0000; - * CONFIG_SYS_SRAM_SIZE = 0x0400_0000; 64MB - * - * CONFIG_SYS_MONITOR_LEN = 0x40000 - * CONFIG_SYS_MALLOC_LEN = 3 * CONFIG_SYS_MONITOR_LEN = 0xC0000 - * - * CONFIG_SYS_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000 - * CONFIG_SYS_MONITOR_BASE = 0x13FF_F000 - CONFIG_SYS_MONITOR_LEN = 0x13FB_F000 - * CONFIG_SYS_MALLOC_BASE = 0x13FB_F000 - CONFIG_SYS_MALLOC_LEN = 0x13EF_F000 - * - * 0x1000_0000 CONFIG_SYS_SDRAM_BASE - * MEMTEST_AREA 64kB - * FREE - * 0x1200_0000 CONFIG_SYS_TEXT_BASE - * U-BOOT code - * 0x1202_0000 - * FREE - * - * STACK - * 0x13EF_F000 CONFIG_SYS_MALLOC_BASE - * MALLOC_AREA 768kB Alloc - * 0x13FB_F000 CONFIG_SYS_MONITOR_BASE - * MONITOR_CODE 256kB Env - * 0x13FF_F000 CONFIG_SYS_GBL_DATA_OFFSET - * GLOBAL_DATA 4kB bd, gd - * 0x1400_0000 CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - */ - +#ifndef CONFIG_OF_CONTROL /* ddr sdram - main memory */ -#define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START -#define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) - -/* global pointer */ -/* start of global data */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_SDRAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* monitor code */ -#define SIZE 0x40000 -#define CONFIG_SYS_MONITOR_LEN SIZE -#define CONFIG_SYS_MONITOR_BASE \ - (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET \ - - CONFIG_SYS_MONITOR_LEN - GENERATED_BD_INFO_SIZE) -#define CONFIG_SYS_MONITOR_END \ - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_MALLOC_LEN (SIZE * 3) -#define CONFIG_SYS_MALLOC_BASE \ - (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) - -/* stack */ -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_MALLOC_BASE +# define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START +# define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE +#endif + +#define CONFIG_SYS_MALLOC_LEN 0xC0000 + +/* Stack location before relocation */ +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_TEXT_BASE /* * CFI flash memory layout - Example -- cgit From 405e651d705e197babe423ef88e8224e2737fc06 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 30 Jan 2015 15:46:43 +0100 Subject: microblaze: Add support for CONFIG_SYS_MALLOC_F_LEN Create space for dm_init where calloc is called and malloc_base has to be initialized. Signed-off-by: Michal Simek --- include/configs/microblaze-generic.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 622bc95104..770acbea69 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -113,6 +113,7 @@ #endif #define CONFIG_SYS_MALLOC_LEN 0xC0000 +#define CONFIG_SYS_MALLOC_F_LEN 1024 /* Stack location before relocation */ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_TEXT_BASE -- cgit From ca7d22662e1ca1b05fd4cd3d1f80efec93c499ef Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 3 Feb 2015 16:24:48 +0100 Subject: microblaze: spl: Do not call mem_malloc_init and use early alloc This patch has some parts connected together: - Use _gd in bss section which is automatically cleared Location at SPL_MALLOC_END wasn't cleared at all - Use MALLOC_F_LEN(early alloc) instead of FULL MALLOC (mem_malloc_init is not called at all) - Simplify malloc and stack init. At the end of SPL addr is malloc area and below is stack Signed-off-by: Michal Simek --- include/configs/microblaze-generic.h | 32 +++++++++++--------------------- 1 file changed, 11 insertions(+), 21 deletions(-) (limited to 'include') diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 770acbea69..166ab4f056 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -113,7 +113,12 @@ #endif #define CONFIG_SYS_MALLOC_LEN 0xC0000 -#define CONFIG_SYS_MALLOC_F_LEN 1024 +#ifndef CONFIG_SPL_BUILD +# define CONFIG_SYS_MALLOC_F_LEN 1024 +#else +# define CONFIG_SYS_MALLOC_SIMPLE +# define CONFIG_SYS_MALLOC_F_LEN 0x150 +#endif /* Stack location before relocation */ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_TEXT_BASE @@ -426,25 +431,11 @@ /* BRAM start */ #define CONFIG_SYS_INIT_RAM_ADDR 0x0 /* BRAM size - will be generated */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 -/* Stack pointer prior relocation, must situated at on-chip RAM */ -#define CONFIG_SYS_SPL_MALLOC_END (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE 0x100000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100 - -/* - * The main reason to do it in this way is that MALLOC_START - * can't be defined - common/spl/spl.c - */ -#if (CONFIG_SYS_SPL_MALLOC_SIZE != 0) -# define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_SPL_MALLOC_END - \ - CONFIG_SYS_SPL_MALLOC_SIZE) -# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_START -#else -# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_END -#endif +# define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + CONFIG_SYS_MALLOC_F_LEN) /* Just for sure that there is a space for stack */ #define CONFIG_SPL_STACK_SIZE 0x100 @@ -453,8 +444,7 @@ #define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \ CONFIG_SYS_INIT_RAM_ADDR - \ - GENERATED_GBL_DATA_SIZE - \ - CONFIG_SYS_SPL_MALLOC_SIZE - \ + CONFIG_SYS_MALLOC_F_LEN - \ CONFIG_SPL_STACK_SIZE) #endif /* __CONFIG_H */ -- cgit From baaa7dd7061521509792ca158508b2c4554a7184 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Tue, 3 Feb 2015 13:32:20 +0200 Subject: lcd: move platform-specific structs to their own headers common/lcd code is full of platform-specific code and definitions, which ideally should reside with the respective driver code. Take a step towards that goal by moving platform-specific structs from lcd.h to their own header files. The structs for the generic case (the #else for all the platform-specific cases) is retained in lcd.h as the default case. Signed-off-by: Nikita Kiryanov Reviewed-by: Simon Glass Tested-by: Bo Shen Tested-by: Josh Wu Cc: Bo Shen Cc: Simon Glass Cc: Anatolij Gustschin --- include/atmel_lcd.h | 38 ++++++++++ include/exynos_lcd.h | 81 +++++++++++++++++++++ include/lcd.h | 201 ++------------------------------------------------- include/mpc823_lcd.h | 43 +++++++++++ include/pxa_lcd.h | 80 ++++++++++++++++++++ 5 files changed, 247 insertions(+), 196 deletions(-) create mode 100644 include/atmel_lcd.h create mode 100644 include/exynos_lcd.h create mode 100644 include/mpc823_lcd.h create mode 100644 include/pxa_lcd.h (limited to 'include') diff --git a/include/atmel_lcd.h b/include/atmel_lcd.h new file mode 100644 index 0000000000..fa8aa29454 --- /dev/null +++ b/include/atmel_lcd.h @@ -0,0 +1,38 @@ +/* + * atmel_lcd.h - Atmel LCD Controller structures + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ATMEL_LCD_H_ +#define _ATMEL_LCD_H_ + +typedef struct vidinfo { + ushort vl_col; /* Number of columns (i.e. 640) */ + ushort vl_row; /* Number of rows (i.e. 480) */ + u_long vl_clk; /* pixel clock in ps */ + + /* LCD configuration register */ + u_long vl_sync; /* Horizontal / vertical sync */ + u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ + u_long vl_tft; /* 0 = passive, 1 = TFT */ + u_long vl_cont_pol_low; /* contrast polarity is low */ + u_long vl_clk_pol; /* clock polarity */ + + /* Horizontal control register. */ + u_long vl_hsync_len; /* Length of horizontal sync */ + u_long vl_left_margin; /* Time from sync to picture */ + u_long vl_right_margin; /* Time from picture to sync */ + + /* Vertical control register. */ + u_long vl_vsync_len; /* Length of vertical sync */ + u_long vl_upper_margin; /* Time from sync to picture */ + u_long vl_lower_margin; /* Time from picture to sync */ + + u_long mmio; /* Memory mapped registers */ +} vidinfo_t; + +#endif diff --git a/include/exynos_lcd.h b/include/exynos_lcd.h new file mode 100644 index 0000000000..cf389dac69 --- /dev/null +++ b/include/exynos_lcd.h @@ -0,0 +1,81 @@ +/* + * exynos_lcd.h - Exynos LCD Controller structures + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _EXYNOS_LCD_H_ +#define _EXYNOS_LCD_H_ + +enum { + FIMD_RGB_INTERFACE = 1, + FIMD_CPU_INTERFACE = 2, +}; + +enum exynos_fb_rgb_mode_t { + MODE_RGB_P = 0, + MODE_BGR_P = 1, + MODE_RGB_S = 2, + MODE_BGR_S = 3, +}; + +typedef struct vidinfo { + ushort vl_col; /* Number of columns (i.e. 640) */ + ushort vl_row; /* Number of rows (i.e. 480) */ + ushort vl_width; /* Width of display area in millimeters */ + ushort vl_height; /* Height of display area in millimeters */ + + /* LCD configuration register */ + u_char vl_freq; /* Frequency */ + u_char vl_clkp; /* Clock polarity */ + u_char vl_oep; /* Output Enable polarity */ + u_char vl_hsp; /* Horizontal Sync polarity */ + u_char vl_vsp; /* Vertical Sync polarity */ + u_char vl_dp; /* Data polarity */ + u_char vl_bpix; /* Bits per pixel */ + + /* Horizontal control register. Timing from data sheet */ + u_char vl_hspw; /* Horz sync pulse width */ + u_char vl_hfpd; /* Wait before of line */ + u_char vl_hbpd; /* Wait end of line */ + + /* Vertical control register. */ + u_char vl_vspw; /* Vertical sync pulse width */ + u_char vl_vfpd; /* Wait before of frame */ + u_char vl_vbpd; /* Wait end of frame */ + u_char vl_cmd_allow_len; /* Wait end of frame */ + + unsigned int win_id; + unsigned int init_delay; + unsigned int power_on_delay; + unsigned int reset_delay; + unsigned int interface_mode; + unsigned int mipi_enabled; + unsigned int dp_enabled; + unsigned int cs_setup; + unsigned int wr_setup; + unsigned int wr_act; + unsigned int wr_hold; + unsigned int logo_on; + unsigned int logo_width; + unsigned int logo_height; + int logo_x_offset; + int logo_y_offset; + unsigned long logo_addr; + unsigned int rgb_mode; + unsigned int resolution; + + /* parent clock name(MPLL, EPLL or VPLL) */ + unsigned int pclk_name; + /* ratio value for source clock from parent clock. */ + unsigned int sclk_div; + + unsigned int dual_lcd_enabled; +} vidinfo_t; + +void init_panel_info(vidinfo_t *vid); + +#endif diff --git a/include/lcd.h b/include/lcd.h index 160f940d2a..fbba6a27f9 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -41,205 +41,15 @@ int bmp_display(ulong addr, int x, int y); void lcd_set_flush_dcache(int flush); #if defined CONFIG_MPC823 -/* - * LCD controller stucture for MPC823 CPU - */ -typedef struct vidinfo { - ushort vl_col; /* Number of columns (i.e. 640) */ - ushort vl_row; /* Number of rows (i.e. 480) */ - ushort vl_width; /* Width of display area in millimeters */ - ushort vl_height; /* Height of display area in millimeters */ - - /* LCD configuration register */ - u_char vl_clkp; /* Clock polarity */ - u_char vl_oep; /* Output Enable polarity */ - u_char vl_hsp; /* Horizontal Sync polarity */ - u_char vl_vsp; /* Vertical Sync polarity */ - u_char vl_dp; /* Data polarity */ - u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */ - u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ - u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */ - u_char vl_clor; /* Color, 0 = mono, 1 = color */ - u_char vl_tft; /* 0 = passive, 1 = TFT */ - - /* Horizontal control register. Timing from data sheet */ - ushort vl_wbl; /* Wait between lines */ - - /* Vertical control register */ - u_char vl_vpw; /* Vertical sync pulse width */ - u_char vl_lcdac; /* LCD AC timing */ - u_char vl_wbf; /* Wait between frames */ -} vidinfo_t; - +#include #elif defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \ defined CONFIG_CPU_MONAHANS -/* - * PXA LCD DMA descriptor - */ -struct pxafb_dma_descriptor { - u_long fdadr; /* Frame descriptor address register */ - u_long fsadr; /* Frame source address register */ - u_long fidr; /* Frame ID register */ - u_long ldcmd; /* Command register */ -}; - -/* - * PXA LCD info - */ -struct pxafb_info { - - /* Misc registers */ - u_long reg_lccr3; - u_long reg_lccr2; - u_long reg_lccr1; - u_long reg_lccr0; - u_long fdadr0; - u_long fdadr1; - - /* DMA descriptors */ - struct pxafb_dma_descriptor * dmadesc_fblow; - struct pxafb_dma_descriptor * dmadesc_fbhigh; - struct pxafb_dma_descriptor * dmadesc_palette; - - u_long screen; /* physical address of frame buffer */ - u_long palette; /* physical address of palette memory */ - u_int palette_size; -}; - -/* - * LCD controller stucture for PXA CPU - */ -typedef struct vidinfo { - ushort vl_col; /* Number of columns (i.e. 640) */ - ushort vl_row; /* Number of rows (i.e. 480) */ - ushort vl_width; /* Width of display area in millimeters */ - ushort vl_height; /* Height of display area in millimeters */ - - /* LCD configuration register */ - u_char vl_clkp; /* Clock polarity */ - u_char vl_oep; /* Output Enable polarity */ - u_char vl_hsp; /* Horizontal Sync polarity */ - u_char vl_vsp; /* Vertical Sync polarity */ - u_char vl_dp; /* Data polarity */ - u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ - u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ - u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */ - u_char vl_clor; /* Color, 0 = mono, 1 = color */ - u_char vl_tft; /* 0 = passive, 1 = TFT */ - - /* Horizontal control register. Timing from data sheet */ - ushort vl_hpw; /* Horz sync pulse width */ - u_char vl_blw; /* Wait before of line */ - u_char vl_elw; /* Wait end of line */ - - /* Vertical control register. */ - u_char vl_vpw; /* Vertical sync pulse width */ - u_char vl_bfw; /* Wait before of frame */ - u_char vl_efw; /* Wait end of frame */ - - /* PXA LCD controller params */ - struct pxafb_info pxa; -} vidinfo_t; - +#include #elif defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD) - -typedef struct vidinfo { - ushort vl_col; /* Number of columns (i.e. 640) */ - ushort vl_row; /* Number of rows (i.e. 480) */ - u_long vl_clk; /* pixel clock in ps */ - - /* LCD configuration register */ - u_long vl_sync; /* Horizontal / vertical sync */ - u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ - u_long vl_tft; /* 0 = passive, 1 = TFT */ - u_long vl_cont_pol_low; /* contrast polarity is low */ - u_long vl_clk_pol; /* clock polarity */ - - /* Horizontal control register. */ - u_long vl_hsync_len; /* Length of horizontal sync */ - u_long vl_left_margin; /* Time from sync to picture */ - u_long vl_right_margin; /* Time from picture to sync */ - - /* Vertical control register. */ - u_long vl_vsync_len; /* Length of vertical sync */ - u_long vl_upper_margin; /* Time from sync to picture */ - u_long vl_lower_margin; /* Time from picture to sync */ - - u_long mmio; /* Memory mapped registers */ -} vidinfo_t; - +#include #elif defined(CONFIG_EXYNOS_FB) - -enum { - FIMD_RGB_INTERFACE = 1, - FIMD_CPU_INTERFACE = 2, -}; - -enum exynos_fb_rgb_mode_t { - MODE_RGB_P = 0, - MODE_BGR_P = 1, - MODE_RGB_S = 2, - MODE_BGR_S = 3, -}; - -typedef struct vidinfo { - ushort vl_col; /* Number of columns (i.e. 640) */ - ushort vl_row; /* Number of rows (i.e. 480) */ - ushort vl_width; /* Width of display area in millimeters */ - ushort vl_height; /* Height of display area in millimeters */ - - /* LCD configuration register */ - u_char vl_freq; /* Frequency */ - u_char vl_clkp; /* Clock polarity */ - u_char vl_oep; /* Output Enable polarity */ - u_char vl_hsp; /* Horizontal Sync polarity */ - u_char vl_vsp; /* Vertical Sync polarity */ - u_char vl_dp; /* Data polarity */ - u_char vl_bpix; /* Bits per pixel */ - - /* Horizontal control register. Timing from data sheet */ - u_char vl_hspw; /* Horz sync pulse width */ - u_char vl_hfpd; /* Wait before of line */ - u_char vl_hbpd; /* Wait end of line */ - - /* Vertical control register. */ - u_char vl_vspw; /* Vertical sync pulse width */ - u_char vl_vfpd; /* Wait before of frame */ - u_char vl_vbpd; /* Wait end of frame */ - u_char vl_cmd_allow_len; /* Wait end of frame */ - - unsigned int win_id; - unsigned int init_delay; - unsigned int power_on_delay; - unsigned int reset_delay; - unsigned int interface_mode; - unsigned int mipi_enabled; - unsigned int dp_enabled; - unsigned int cs_setup; - unsigned int wr_setup; - unsigned int wr_act; - unsigned int wr_hold; - unsigned int logo_on; - unsigned int logo_width; - unsigned int logo_height; - int logo_x_offset; - int logo_y_offset; - unsigned long logo_addr; - unsigned int rgb_mode; - unsigned int resolution; - - /* parent clock name(MPLL, EPLL or VPLL) */ - unsigned int pclk_name; - /* ratio value for source clock from parent clock. */ - unsigned int sclk_div; - - unsigned int dual_lcd_enabled; -} vidinfo_t; - -void init_panel_info(vidinfo_t *vid); - +#include #else - typedef struct vidinfo { ushort vl_col; /* Number of columns (i.e. 160) */ ushort vl_row; /* Number of rows (i.e. 100) */ @@ -250,8 +60,7 @@ typedef struct vidinfo { void *priv; /* Pointer to driver-specific data */ } vidinfo_t; - -#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_ATMEL_LCD */ +#endif extern vidinfo_t panel_info; diff --git a/include/mpc823_lcd.h b/include/mpc823_lcd.h new file mode 100644 index 0000000000..7e210e3296 --- /dev/null +++ b/include/mpc823_lcd.h @@ -0,0 +1,43 @@ +/* + * mpc823_lcd.h - MPC823 LCD Controller structures + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MPC823_LCD_H_ +#define _MPC823_LCD_H_ + +/* + * LCD controller stucture for MPC823 CPU + */ +typedef struct vidinfo { + ushort vl_col; /* Number of columns (i.e. 640) */ + ushort vl_row; /* Number of rows (i.e. 480) */ + ushort vl_width; /* Width of display area in millimeters */ + ushort vl_height; /* Height of display area in millimeters */ + + /* LCD configuration register */ + u_char vl_clkp; /* Clock polarity */ + u_char vl_oep; /* Output Enable polarity */ + u_char vl_hsp; /* Horizontal Sync polarity */ + u_char vl_vsp; /* Vertical Sync polarity */ + u_char vl_dp; /* Data polarity */ + u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */ + u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ + u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */ + u_char vl_clor; /* Color, 0 = mono, 1 = color */ + u_char vl_tft; /* 0 = passive, 1 = TFT */ + + /* Horizontal control register. Timing from data sheet */ + ushort vl_wbl; /* Wait between lines */ + + /* Vertical control register */ + u_char vl_vpw; /* Vertical sync pulse width */ + u_char vl_lcdac; /* LCD AC timing */ + u_char vl_wbf; /* Wait between frames */ +} vidinfo_t; + +#endif diff --git a/include/pxa_lcd.h b/include/pxa_lcd.h new file mode 100644 index 0000000000..723f6ab766 --- /dev/null +++ b/include/pxa_lcd.h @@ -0,0 +1,80 @@ +/* + * pxa_lcd.h - PXA LCD Controller structures + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PXA_LCD_H_ +#define _PXA_LCD_H_ + +/* + * PXA LCD DMA descriptor + */ +struct pxafb_dma_descriptor { + u_long fdadr; /* Frame descriptor address register */ + u_long fsadr; /* Frame source address register */ + u_long fidr; /* Frame ID register */ + u_long ldcmd; /* Command register */ +}; + +/* + * PXA LCD info + */ +struct pxafb_info { + /* Misc registers */ + u_long reg_lccr3; + u_long reg_lccr2; + u_long reg_lccr1; + u_long reg_lccr0; + u_long fdadr0; + u_long fdadr1; + + /* DMA descriptors */ + struct pxafb_dma_descriptor *dmadesc_fblow; + struct pxafb_dma_descriptor *dmadesc_fbhigh; + struct pxafb_dma_descriptor *dmadesc_palette; + + u_long screen; /* physical address of frame buffer */ + u_long palette; /* physical address of palette memory */ + u_int palette_size; +}; + +/* + * LCD controller stucture for PXA CPU + */ +typedef struct vidinfo { + ushort vl_col; /* Number of columns (i.e. 640) */ + ushort vl_row; /* Number of rows (i.e. 480) */ + ushort vl_width; /* Width of display area in millimeters */ + ushort vl_height; /* Height of display area in millimeters */ + + /* LCD configuration register */ + u_char vl_clkp; /* Clock polarity */ + u_char vl_oep; /* Output Enable polarity */ + u_char vl_hsp; /* Horizontal Sync polarity */ + u_char vl_vsp; /* Vertical Sync polarity */ + u_char vl_dp; /* Data polarity */ + u_char vl_bpix;/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ + u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ + u_char vl_splt;/* Split display, 0 = single-scan, 1 = dual-scan */ + u_char vl_clor; /* Color, 0 = mono, 1 = color */ + u_char vl_tft; /* 0 = passive, 1 = TFT */ + + /* Horizontal control register. Timing from data sheet */ + ushort vl_hpw; /* Horz sync pulse width */ + u_char vl_blw; /* Wait before of line */ + u_char vl_elw; /* Wait end of line */ + + /* Vertical control register. */ + u_char vl_vpw; /* Vertical sync pulse width */ + u_char vl_bfw; /* Wait before of frame */ + u_char vl_efw; /* Wait end of frame */ + + /* PXA LCD controller params */ + struct pxafb_info pxa; +} vidinfo_t; + +#endif -- cgit From 38b550877fd819ce7842b73530dcbacc098c9f0f Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Tue, 3 Feb 2015 13:32:21 +0200 Subject: lcd: split configuration_get_cmap configuration_get_cmap() is multiple platform-specific functions stuffed into one function. Split it into multiple versions, and move each version to the appropriate driver to reduce the #ifdef complexity. Signed-off-by: Nikita Kiryanov Reviewed-by: Simon Glass Tested-by: Bo Shen Tested-by: Josh Wu Cc: Bo Shen Cc: Simon Glass Cc: Anatolij Gustschin --- include/lcd.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include') diff --git a/include/lcd.h b/include/lcd.h index fbba6a27f9..4ada617e02 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -60,8 +60,15 @@ typedef struct vidinfo { void *priv; /* Pointer to driver-specific data */ } vidinfo_t; + +static __maybe_unused ushort *configuration_get_cmap(void) +{ + return panel_info.cmap; +} #endif +ushort *configuration_get_cmap(void); + extern vidinfo_t panel_info; /* Video functions */ -- cgit From c8d2febcc7e328d1c4bb11131ecd0b9cbab2f4fb Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Tue, 3 Feb 2015 13:32:29 +0200 Subject: lcd: various cleanups This cleanup mostly focuses on removing unnecessary whitespace and comments which are superfluous and/or do not conform to the coding style. Signed-off-by: Nikita Kiryanov Reviewed-by: Simon Glass Tested-by: Bo Shen Tested-by: Josh Wu Cc: Simon Glass Cc: Anatolij Gustschin --- include/lcd.h | 102 ++++++++++++++++++++-------------------------------------- 1 file changed, 34 insertions(+), 68 deletions(-) (limited to 'include') diff --git a/include/lcd.h b/include/lcd.h index 4ada617e02..b0423205bf 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -13,21 +13,19 @@ #ifndef _LCD_H_ #define _LCD_H_ #include +#if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) +#include +#include +#endif extern char lcd_is_enabled; - extern int lcd_line_length; - extern struct vidinfo panel_info; void lcd_ctrl_init(void *lcdbase); void lcd_enable(void); - -/* setcolreg used in 8bpp/16bpp; initcolregs used in monochrome */ void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue); -void lcd_initcolregs(void); -/* gunzip_bmp used if CONFIG_VIDEO_BMP_GZIP */ struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp, void **alloc_addr); int bmp_display(ulong addr, int x, int y); @@ -53,11 +51,8 @@ void lcd_set_flush_dcache(int flush); typedef struct vidinfo { ushort vl_col; /* Number of columns (i.e. 160) */ ushort vl_row; /* Number of rows (i.e. 100) */ - u_char vl_bpix; /* Bits per pixel, 0 = 1 */ - ushort *cmap; /* Pointer to the colormap */ - void *priv; /* Pointer to driver-specific data */ } vidinfo_t; @@ -71,13 +66,11 @@ ushort *configuration_get_cmap(void); extern vidinfo_t panel_info; -/* Video functions */ - -void lcd_putc(const char c); -void lcd_puts(const char *s); -void lcd_printf(const char *fmt, ...); -void lcd_clear(void); -int lcd_display_bitmap(ulong bmp_image, int x, int y); +void lcd_putc(const char c); +void lcd_puts(const char *s); +void lcd_printf(const char *fmt, ...); +void lcd_clear(void); +int lcd_display_bitmap(ulong bmp_image, int x, int y); /** * Get the width of the LCD in pixels @@ -141,14 +134,6 @@ int lcd_dt_simplefb_enable_existing_node(void *blob); /* Update the LCD / flush the cache */ void lcd_sync(void); -/************************************************************************/ -/* ** BITMAP DISPLAY SUPPORT */ -/************************************************************************/ -#if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) -# include -# include -#endif - /* * Information about displays we are using. This is for configuring * the LCD controller and memory allocation. Someone has to know what @@ -163,38 +148,32 @@ void lcd_sync(void); #define LCD_COLOR8 3 #define LCD_COLOR16 4 #define LCD_COLOR32 5 -/*----------------------------------------------------------------------*/ + #if defined(CONFIG_LCD_INFO_BELOW_LOGO) -# define LCD_INFO_X 0 -# define LCD_INFO_Y (BMP_LOGO_HEIGHT + VIDEO_FONT_HEIGHT) +#define LCD_INFO_X 0 +#define LCD_INFO_Y (BMP_LOGO_HEIGHT + VIDEO_FONT_HEIGHT) #elif defined(CONFIG_LCD_LOGO) -# define LCD_INFO_X (BMP_LOGO_WIDTH + 4 * VIDEO_FONT_WIDTH) -# define LCD_INFO_Y VIDEO_FONT_HEIGHT +#define LCD_INFO_X (BMP_LOGO_WIDTH + 4 * VIDEO_FONT_WIDTH) +#define LCD_INFO_Y VIDEO_FONT_HEIGHT #else -# define LCD_INFO_X VIDEO_FONT_WIDTH -# define LCD_INFO_Y VIDEO_FONT_HEIGHT +#define LCD_INFO_X VIDEO_FONT_WIDTH +#define LCD_INFO_Y VIDEO_FONT_HEIGHT #endif /* Default to 8bpp if bit depth not specified */ #ifndef LCD_BPP -# define LCD_BPP LCD_COLOR8 +#define LCD_BPP LCD_COLOR8 #endif + #ifndef LCD_DF -# define LCD_DF 1 +#define LCD_DF 1 #endif /* Calculate nr. of bits per pixel and nr. of colors */ #define NBITS(bit_code) (1 << (bit_code)) #define NCOLORS(bit_code) (1 << NBITS(bit_code)) -/************************************************************************/ -/* ** CONSOLE CONSTANTS */ -/************************************************************************/ #if LCD_BPP == LCD_COLOR8 - -/* - * 8bpp color definitions - */ # define CONSOLE_COLOR_BLACK 0 # define CONSOLE_COLOR_RED 1 # define CONSOLE_COLOR_GREEN 2 @@ -203,38 +182,25 @@ void lcd_sync(void); # define CONSOLE_COLOR_MAGENTA 5 # define CONSOLE_COLOR_CYAN 6 # define CONSOLE_COLOR_GREY 14 -# define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */ - +# define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */ #elif LCD_BPP == LCD_COLOR32 -/* - * 32bpp color definitions - */ -# define CONSOLE_COLOR_RED 0x00ff0000 -# define CONSOLE_COLOR_GREEN 0x0000ff00 -# define CONSOLE_COLOR_YELLOW 0x00ffff00 -# define CONSOLE_COLOR_BLUE 0x000000ff -# define CONSOLE_COLOR_MAGENTA 0x00ff00ff -# define CONSOLE_COLOR_CYAN 0x0000ffff -# define CONSOLE_COLOR_GREY 0x00aaaaaa -# define CONSOLE_COLOR_BLACK 0x00000000 -# define CONSOLE_COLOR_WHITE 0x00ffffff /* Must remain last / highest*/ -# define NBYTES(bit_code) (NBITS(bit_code) >> 3) - -#else - -/* - * 16bpp color definitions - */ -# define CONSOLE_COLOR_BLACK 0x0000 -# define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */ - +#define CONSOLE_COLOR_RED 0x00ff0000 +#define CONSOLE_COLOR_GREEN 0x0000ff00 +#define CONSOLE_COLOR_YELLOW 0x00ffff00 +#define CONSOLE_COLOR_BLUE 0x000000ff +#define CONSOLE_COLOR_MAGENTA 0x00ff00ff +#define CONSOLE_COLOR_CYAN 0x0000ffff +#define CONSOLE_COLOR_GREY 0x00aaaaaa +#define CONSOLE_COLOR_BLACK 0x00000000 +#define CONSOLE_COLOR_WHITE 0x00ffffff /* Must remain last / highest */ +#define NBYTES(bit_code) (NBITS(bit_code) >> 3) +#else /* 16bpp color definitions */ +#define CONSOLE_COLOR_BLACK 0x0000 +#define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */ #endif /* color definitions */ -/************************************************************************/ #ifndef PAGE_SIZE -# define PAGE_SIZE 4096 +#define PAGE_SIZE 4096 #endif -/************************************************************************/ - #endif /* _LCD_H_ */ -- cgit From 033167c4c5a9a31768f690353ce26be021ad9c36 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Tue, 3 Feb 2015 13:32:31 +0200 Subject: lcd: dt: extract simplefb support We now have api functions that can support compiling simplefb code as its own module. Since this code is not part of the display functionality, extract it to its own file. Raspberry Pi is updated to accommodate the changes. Signed-off-by: Nikita Kiryanov Acked-by: Stephen Warren Reviewed-by: Simon Glass Tested-by: Bo Shen Tested-by: Josh Wu Cc: Simon Glass Cc: Anatolij Gustschin Cc: Stephen Warren --- include/fdt_simplefb.h | 14 ++++++++++++++ include/lcd.h | 3 --- 2 files changed, 14 insertions(+), 3 deletions(-) create mode 100644 include/fdt_simplefb.h (limited to 'include') diff --git a/include/fdt_simplefb.h b/include/fdt_simplefb.h new file mode 100644 index 0000000000..8c89a19b8e --- /dev/null +++ b/include/fdt_simplefb.h @@ -0,0 +1,14 @@ +/* + * Simplefb device tree support + * + * (C) Copyright 2015 + * Stephen Warren + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FDT_SIMPLEFB_H_ +#define _FDT_SIMPLEFB_H_ +int lcd_dt_simplefb_add_node(void *blob); +int lcd_dt_simplefb_enable_existing_node(void *blob); +#endif diff --git a/include/lcd.h b/include/lcd.h index b0423205bf..f049fd3489 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -128,9 +128,6 @@ void lcd_show_board_info(void); /* Return the size of the LCD frame buffer, and the line length */ int lcd_get_size(int *line_length); -int lcd_dt_simplefb_add_node(void *blob); -int lcd_dt_simplefb_enable_existing_node(void *blob); - /* Update the LCD / flush the cache */ void lcd_sync(void); -- cgit From 7bf71d1f55d31a81ade8dd0fc72f06e4672689d0 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Tue, 3 Feb 2015 13:32:32 +0200 Subject: lcd: split splash code into its own function lcd_logo() currently performs tasks well beyond just displaying the logo. It has code which displays splash image, it has logic which determines when the different display features are displayed, and it is coupled with the lcd console because it holds the responsibility of returning the lcd console base address. Make lcd_logo() just about the logo by: * Moving splash image display code into a dedicated function * Moving the logic regarding when various features are displayed to lcd_clear() (which is arguably not the correct name for housing such code either, but it is currently the most fitting location code wise) * Move the responsibility of setting the console base address to lcd_clear() too. Signed-off-by: Nikita Kiryanov Reviewed-by: Simon Glass Tested-by: Bo Shen Tested-by: Josh Wu Cc: Bo Shen Cc: Simon Glass Cc: Anatolij Gustschin --- include/splash.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/splash.h b/include/splash.h index 89ee7b22ec..4dbf754ace 100644 --- a/include/splash.h +++ b/include/splash.h @@ -21,7 +21,7 @@ #ifndef _SPLASH_H_ #define _SPLASH_H_ - +#include int splash_screen_prepare(void); @@ -31,6 +31,15 @@ void splash_get_pos(int *x, int *y); static inline void splash_get_pos(int *x, int *y) { } #endif +#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_LCD) +int lcd_splash(ulong addr); +#else +static inline int lcd_splash(ulong addr) +{ + return -ENOSYS; +} +#endif + #define BMP_ALIGN_CENTER 0x7FFF #endif -- cgit From 478b02f1a7043b673565075ea5016376f3293b23 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 7 Feb 2015 22:52:40 +0100 Subject: Add linux/compiler-gcc5.h to fix builds with gcc5 Add linux/compiler-gcc5/h from the kernel sources at: commit 5631b8fba640a4ab2f8a954f63a603fa34eda96b Author: Steven Noonan Date: Sat Oct 25 15:09:42 2014 -0700 compiler/gcc4+: Remove inaccurate comment about 'asm goto' miscompiles Signed-off-by: Hans de Goede --- include/linux/compiler-gcc5.h | 65 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 include/linux/compiler-gcc5.h (limited to 'include') diff --git a/include/linux/compiler-gcc5.h b/include/linux/compiler-gcc5.h new file mode 100644 index 0000000000..c8c5659525 --- /dev/null +++ b/include/linux/compiler-gcc5.h @@ -0,0 +1,65 @@ +#ifndef __LINUX_COMPILER_H +#error "Please don't include directly, include instead." +#endif + +#define __used __attribute__((__used__)) +#define __must_check __attribute__((warn_unused_result)) +#define __compiler_offsetof(a, b) __builtin_offsetof(a, b) + +/* Mark functions as cold. gcc will assume any path leading to a call + to them will be unlikely. This means a lot of manual unlikely()s + are unnecessary now for any paths leading to the usual suspects + like BUG(), printk(), panic() etc. [but let's keep them for now for + older compilers] + + Early snapshots of gcc 4.3 don't support this and we can't detect this + in the preprocessor, but we can live with this because they're unreleased. + Maketime probing would be overkill here. + + gcc also has a __attribute__((__hot__)) to move hot functions into + a special section, but I don't see any sense in this right now in + the kernel context */ +#define __cold __attribute__((__cold__)) + +#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__) + +#ifndef __CHECKER__ +# define __compiletime_warning(message) __attribute__((warning(message))) +# define __compiletime_error(message) __attribute__((error(message))) +#endif /* __CHECKER__ */ + +/* + * Mark a position in code as unreachable. This can be used to + * suppress control flow warnings after asm blocks that transfer + * control elsewhere. + * + * Early snapshots of gcc 4.5 don't support this and we can't detect + * this in the preprocessor, but we can live with this because they're + * unreleased. Really, we need to have autoconf for the kernel. + */ +#define unreachable() __builtin_unreachable() + +/* Mark a function definition as prohibited from being cloned. */ +#define __noclone __attribute__((__noclone__)) + +/* + * Tell the optimizer that something else uses this function or variable. + */ +#define __visible __attribute__((externally_visible)) + +/* + * GCC 'asm goto' miscompiles certain code sequences: + * + * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670 + * + * Work it around via a compiler barrier quirk suggested by Jakub Jelinek. + * + * (asm goto is automatically volatile - the naming reflects this.) + */ +#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0) + +#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP +#define __HAVE_BUILTIN_BSWAP32__ +#define __HAVE_BUILTIN_BSWAP64__ +#define __HAVE_BUILTIN_BSWAP16__ +#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */ -- cgit From bd2a4888b123713adec271d6c8040ca9f609aa2f Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 4 Feb 2015 00:43:36 +0100 Subject: sunxi: configs/sunxi-common.h: Enable CONFIG_CMD_PART The recent changes to config_distro_bootcmd.h require CONFIG_CMD_PART to be defined, as the default bootcmd not uses the "part" command. This fixes sunxi boards not booting with v2015.04-rc1. Signed-off-by: Hans de Goede --- include/configs/sunxi-common.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 6cfd7e1489..cea52dbf7b 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -85,6 +85,9 @@ #define CONFIG_CMD_MEMORY #define CONFIG_CMD_SETEXPR +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART + #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG #define CONFIG_INITRD_TAG -- cgit