From 19601dd99c8169e27457a96f03f0c3fef908a4c6 Mon Sep 17 00:00:00 2001 From: York Sun Date: Wed, 4 Nov 2015 10:03:17 -0800 Subject: driver/ddr/fsl: Update DDR4 RTT values DDR4 has different RTT value and code according to JEDEC spec. Update the macros and options . Signed-off-by: York Sun --- include/fsl_ddr_sdram.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include') diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index c79fce0898..4b022d4639 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -33,6 +33,15 @@ #define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */ #define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */ +#define DDR4_RTT_OFF 0 +#define DDR4_RTT_60_OHM 1 /* RZQ/4 */ +#define DDR4_RTT_120_OHM 2 /* RZQ/2 */ +#define DDR4_RTT_40_OHM 3 /* RZQ/6 */ +#define DDR4_RTT_240_OHM 4 /* RZQ/1 */ +#define DDR4_RTT_48_OHM 5 /* RZQ/5 */ +#define DDR4_RTT_80_OHM 6 /* RZQ/3 */ +#define DDR4_RTT_34_OHM 7 /* RZQ/7 */ + #define DDR2_RTT_OFF 0 #define DDR2_RTT_75_OHM 1 #define DDR2_RTT_150_OHM 2 -- cgit From a07bdad749ea080e009a82ba40e791dc7361ab54 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 20 Nov 2015 15:52:03 +0800 Subject: fsl/errata: move fsl_errata.h to common directory move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h to make it public for both ARM and POWER SoCs. Signed-off-by: Shengzhou Liu [York Sun: fix soc.h path in fsl_errata.h] Reviewed-by: York Sun --- include/fsl_errata.h | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 include/fsl_errata.h (limited to 'include') diff --git a/include/fsl_errata.h b/include/fsl_errata.h new file mode 100644 index 0000000000..aebe3d2925 --- /dev/null +++ b/include/fsl_errata.h @@ -0,0 +1,61 @@ +/* + * Copyright 2013 - 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FSL_ERRATA_H +#define _FSL_ERRATA_H + +#include +#if defined(CONFIG_PPC) +#include +#elif defined(CONFIG_LS102XA) +#include +#elif defined(CONFIG_FSL_LAYERSCAPE) +#include +#endif + + +#ifdef CONFIG_SYS_FSL_ERRATUM_A006379 +static inline bool has_erratum_a006379(void) +{ + u32 svr = get_svr(); + if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) || + ((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) || + ((SVR_SOC_VER(svr) == SVR_T4080) && SVR_MAJ(svr) <= 1) || + ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) || + ((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) || + ((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) || + ((SVR_SOC_VER(svr) == SVR_T2081) && SVR_MAJ(svr) <= 1)) + return true; + + return false; +} +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A007186 +static inline bool has_erratum_a007186(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + switch (soc) { + case SVR_T4240: + return IS_SVR_REV(svr, 2, 0); + case SVR_T4160: + return IS_SVR_REV(svr, 2, 0); + case SVR_B4860: + return IS_SVR_REV(svr, 2, 0); + case SVR_B4420: + return IS_SVR_REV(svr, 2, 0); + case SVR_T2081: + case SVR_T2080: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1); + } + + return false; +} +#endif + +#endif /* _FSL_ERRATA_H */ -- cgit From a46b1852de967f8a7de26e0b46e864c794a18c16 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 20 Nov 2015 15:52:04 +0800 Subject: fsl/ddr: updated ddr errata-A008378 for arm and power SoCs DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0, T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on LS102x Rev2. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- include/fsl_errata.h | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'include') diff --git a/include/fsl_errata.h b/include/fsl_errata.h index aebe3d2925..8441f91029 100644 --- a/include/fsl_errata.h +++ b/include/fsl_errata.h @@ -58,4 +58,35 @@ static inline bool has_erratum_a007186(void) } #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A008378 +static inline bool has_erratum_a008378(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + + switch (soc) { +#ifdef CONFIG_LS102XA + case SOC_VER_LS1020: + case SOC_VER_LS1021: + case SOC_VER_LS1022: + case SOC_VER_SLS1020: + return IS_SVR_REV(svr, 1, 0); +#endif +#ifdef CONFIG_PPC + case SVR_T1023: + case SVR_T1024: + return IS_SVR_REV(svr, 1, 0); + case SVR_T1020: + case SVR_T1022: + case SVR_T1040: + case SVR_T1042: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1); +#endif + default: + return false; + } +} +#endif + #endif /* _FSL_ERRATA_H */ -- cgit From e994dddbbe031c818758b2ea91f59697b07d94b6 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Mon, 23 Nov 2015 15:23:48 +0800 Subject: armv8/ls1043ardb: Add support for >2GB memory This patch also expose the complete DDR region(s) to Linux. Signed-off-by: Shaohui Xie Signed-off-by: Mingkai Hu Reviewed-by: York Sun --- include/configs/ls1043a_common.h | 1 + include/configs/ls1043ardb.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 6b9856a18f..677d28113c 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -44,6 +44,7 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL #define CPU_RELEASE_ADDR secondary_boot_func diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 7d113a0737..683407499a 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -27,7 +27,7 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 /* Physical Memory Map */ #define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_NR_DRAM_BANKS 2 #define CONFIG_SYS_SPD_BUS_NUM 0 -- cgit From b22b1dc6b7b5a74c7655a85b312ff3df0e69c4fe Mon Sep 17 00:00:00 2001 From: Pratiyush Mohan Srivastava Date: Sat, 31 Oct 2015 15:50:18 +0530 Subject: Enable console log from earlyconsole in Linux bootargs Remove 115200 from "earlycon" to avoid loss of initial log messages during linux kernel 4.1 bootup Signed-off-by: Pratiyush Mohan Srivastava Reviewed-by: York Sun --- include/configs/ls2080a_common.h | 2 +- include/configs/ls2080ardb.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 2e1fe7a4b1..969aed698c 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -271,7 +271,7 @@ unsigned long long get_qixis_addr(void); "console=ttyAMA0,38400n8\0" #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ - "earlycon=uart8250,mmio,0x21c0500,115200 " \ + "earlycon=uart8250,mmio,0x21c0500" \ "ramdisk_size=0x2000000 default_hugepagesz=2m" \ " hugepagesz=2m hugepages=16" #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 44a47d5889..faccc6f35b 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -313,7 +313,7 @@ unsigned long get_board_sys_clk(void); #undef CONFIG_BOOTARGS #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ - "earlycon=uart8250,mmio,0x21c0600,115200 " \ + "earlycon=uart8250,mmio,0x21c0600" \ "ramdisk_size=0x2000000 default_hugepagesz=2m" \ " hugepagesz=2m hugepages=16" -- cgit From e81495224f732f17ae6f379baf23b90cd1d5cb5f Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 4 Dec 2015 11:57:07 -0800 Subject: Reserve secure memory Secure memory is at the end of memory, separated and reserved from OS, tracked by gd->secure_ram. Secure memory can host MMU tables, security monitor, etc. This is different from PRAM used to reserve private memory. PRAM offers memory at the top of u-boot memory, not necessarily the real end of memory for systems with very large DDR. Using the end of memory simplifies MMU setup and avoid memory fragmentation. "bdinfo" command shows gd->secure_ram value if this memory is marked as secured. Signed-off-by: York Sun --- include/asm-generic/global_data.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'include') diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 1abdcaa6b7..5d8b043f14 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -59,6 +59,20 @@ typedef struct global_data { unsigned long relocaddr; /* Start address of U-Boot in RAM */ phys_size_t ram_size; /* RAM size */ +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#define MEM_RESERVE_SECURE_SECURED 0x1 +#define MEM_RESERVE_SECURE_MAINTAINED 0x2 +#define MEM_RESERVE_SECURE_ADDR_MASK (~0x3) + /* + * Secure memory addr + * This variable needs maintenance if the RAM base is not zero, + * or if RAM splits into non-consecutive banks. It also has a + * flag indicating the secure memory is marked as secure by MMU. + * Flags used: 0x1 secured + * 0x2 maintained + */ + phys_addr_t secure_ram; +#endif unsigned long mon_len; /* monitor len */ unsigned long irq_sp; /* irq stack pointer */ unsigned long start_addr_sp; /* start_addr_stackpointer */ -- cgit From c04921414c087e15f8fa82d808a25e9338a7e8d5 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 7 Dec 2015 11:08:58 -0800 Subject: armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun --- include/configs/ls2080a_common.h | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 969aed698c..4ae7d11685 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -195,10 +195,9 @@ unsigned long long get_qixis_addr(void); * 512MB aligned, so the min size to hide is 512MB. */ #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER) -#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) +#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (254UL * 1024 * 1024) #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) -#define CONFIG_SYS_MEM_TOP_HIDE_MIN (512UL * 1024 * 1024) -#define CONFIG_SYS_MEM_TOP_HIDE get_dram_size_to_hide() +#define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024) #endif /* PCIe */ @@ -290,10 +289,6 @@ unsigned long long get_qixis_addr(void); #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_MAXARGS 64 /* max command args */ -#ifndef __ASSEMBLY__ -unsigned long get_dram_size_to_hide(void); -#endif - #define CONFIG_PANIC_HANG /* do not reset board on panic */ #define CONFIG_SPL_BSS_START_ADDR 0x80100000 -- cgit From e8f954a756a825130d11b9c8fca70101dd8b3ac5 Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Tue, 8 Dec 2015 13:54:28 +0530 Subject: include/linux: move typdef for uintptr_t uintptr_t which is a typdef for unsigned long is needed for creating pointers (32 or 64 bit depending on Core) from 32 bit variables storing the address. If a 32 bit variable (u32) is typecasted to a pointer (void *), compiler gives a warning in case size of pointer on the core is 64 bit. The typdef has been moved from include/compiler.h to include/linux/types.h Signed-off-by: Aneesh Bansal Reviewed-by: York Sun --- include/compiler.h | 3 --- include/linux/types.h | 1 + 2 files changed, 1 insertion(+), 3 deletions(-) (limited to 'include') diff --git a/include/compiler.h b/include/compiler.h index 47c296e202..f853ed4787 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -115,9 +115,6 @@ typedef unsigned int uint; #ifdef CONFIG_USE_STDINT /* Provided by gcc. */ #include -#else -/* Type for `void *' pointers. */ -typedef unsigned long int uintptr_t; #endif #include diff --git a/include/linux/types.h b/include/linux/types.h index 6f75be4253..c7e8fdb9c2 100644 --- a/include/linux/types.h +++ b/include/linux/types.h @@ -124,6 +124,7 @@ typedef __UINT64_TYPE__ u_int64_t; typedef __INT64_TYPE__ int64_t; #endif +typedef unsigned long uintptr_t; /* * Below are truly Linux-specific types that should never collide with * any application/library that wants linux/types.h. -- cgit From 9711f52806655bcfa28fe5594b91fed430beb72e Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Tue, 8 Dec 2015 13:54:29 +0530 Subject: armv8/ls1043ardb: add SECURE BOOT target for NOR LS1043ARDB Secure Boot Target from NOR has been added. - Configs defined to enable esbc_validate. - ESBC Address in header is made 64 bit. - SMMU is re-configured in Bypass mode. Signed-off-by: Aneesh Bansal Reviewed-by: York Sun --- include/configs/ls1043ardb.h | 10 ++++++++++ include/fsl_validate.h | 9 ++++++++- 2 files changed, 18 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 683407499a..585114f3d5 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -291,4 +291,14 @@ #define CONFIG_CMD_EXT2 #endif +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#define CONFIG_CMD_BLOB +/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */ +#define CONFIG_ESBC_ADDR_64BIT +#endif + +#include + #endif /* __LS1043ARDB_H__ */ diff --git a/include/fsl_validate.h b/include/fsl_validate.h index 92dd98bb61..a62dc74e69 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -83,7 +83,9 @@ struct fsl_secboot_img_hdr { u32 sign_len; /* length of the signature in bytes */ union { u32 psgtable; /* ptr to SG table */ +#ifndef CONFIG_ESBC_ADDR_64BIT u32 pimg; /* ptr to ESBC client image */ +#endif }; union { u32 sg_entries; /* no of entries in SG table */ @@ -97,7 +99,12 @@ struct fsl_secboot_img_hdr { u32 reserved1[2]; u32 fsl_uid_1; u32 oem_uid_1; - u32 reserved2[2]; + union { + u32 reserved2[2]; +#ifdef CONFIG_ESBC_ADDR_64BIT + u64 pimg64; /* 64 bit pointer to ESBC Image */ +#endif + }; u32 ie_flag; u32 ie_key_sel; }; -- cgit From 989c5f0a8f8694ac92eb0d6cff8745ae8659364f Mon Sep 17 00:00:00 2001 From: Tang Yuantian Date: Wed, 9 Dec 2015 15:32:18 +0800 Subject: armv8: Add sata support on Layerscape ARMv8 board Freescale ARM-based Layerscape contains a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls2080aqds, ls2080ardb and ls1043aqds boards. Signed-off-by: Tang Yuantian Reviewed-by: York Sun --- include/configs/ls1043aqds.h | 17 +++++++++++++++++ include/configs/ls2080aqds.h | 18 ++++++++++++++++++ include/configs/ls2080ardb.h | 18 ++++++++++++++++++ 3 files changed, 53 insertions(+) (limited to 'include') diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 4aeb2382fc..398f1c3f77 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -88,6 +88,23 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg #endif +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_SYS_SATA AHCI_BASE_ADDR + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + /* * IFC Definitions */ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 54bcae9fe8..ba84248081 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -40,6 +40,24 @@ unsigned long get_board_ddr_clk(void); #endif #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 +#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index faccc6f35b..116dbcde5b 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -42,6 +42,24 @@ unsigned long get_board_sys_clk(void); #endif #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 +#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -- cgit