From 0088c298f0eeb90ec001f744e9959dea83dd563a Mon Sep 17 00:00:00 2001
From: Kumar Gala <galak@kernel.crashing.org>
Date: Thu, 26 Mar 2009 01:34:37 -0500
Subject: Add LSDMR (SDRAM Mode Register) definition on localbus

The masks for various bit defines of LSDMR are common and thus we can
define them in one place rather than replicating them in each config.h

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 include/asm-ppc/fsl_lbc.h | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

(limited to 'include')

diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h
index 9fa0b65949..bc1ebe6e31 100644
--- a/include/asm-ppc/fsl_lbc.h
+++ b/include/asm-ppc/fsl_lbc.h
@@ -397,6 +397,33 @@
 #define FPAR_LP_CI             0x000007FF
 #define FPAR_LP_CI_SHIFT       0
 
+/* LSDMR - SDRAM Machine Mode Register
+ */
+#define LSDMR_RFEN	(1 << (31 -  1))
+#define LSDMR_BSMA1516	(3 << (31 - 10))
+#define LSDMR_BSMA1617	(4 << (31 - 10))
+#define LSDMR_RFCR5	(3 << (31 - 16))
+#define LSDMR_RFCR16	(7 << (31 - 16))
+#define LSDMR_PRETOACT3 (3 << (31 - 19))
+#define LSDMR_PRETOACT7	(7 << (31 - 19))
+#define LSDMR_ACTTORW3	(3 << (31 - 22))
+#define LSDMR_ACTTORW7	(7 << (31 - 22))
+#define LSDMR_ACTTORW6	(6 << (31 - 22))
+#define LSDMR_BL8	(1 << (31 - 23))
+#define LSDMR_WRC2	(2 << (31 - 27))
+#define LSDMR_WRC4	(0 << (31 - 27))
+#define LSDMR_BUFCMD	(1 << (31 - 29))
+#define LSDMR_CL3	(3 << (31 - 31))
+
+#define LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define LSDMR_OP_MRW	(3 << (31 - 4))
+#define LSDMR_OP_PRECH	(4 << (31 - 4))
+#define LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define LSDMR_OP_RWINV	(7 << (31 - 4))
+
 /* LTESR - Transfer Error Status Register
  */
 #define LTESR_BM               0x80000000
-- 
cgit 


From b0fe93eda69721aef1fdef576164b668fad83bbd Mon Sep 17 00:00:00 2001
From: Kumar Gala <galak@kernel.crashing.org>
Date: Thu, 26 Mar 2009 01:34:38 -0500
Subject: 85xx: Use common LSDMR defines from asm/fsl_lbc.h

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 include/configs/MPC8540ADS.h | 59 ++++++++++----------------------------------
 include/configs/MPC8541CDS.h | 37 ++++++---------------------
 include/configs/MPC8548CDS.h | 37 ++++++---------------------
 include/configs/MPC8555CDS.h | 37 ++++++---------------------
 include/configs/MPC8560ADS.h | 59 ++++++++++----------------------------------
 include/configs/MPC8568MDS.h | 37 ++++++---------------------
 include/configs/sbc8548.h    | 37 ++++++---------------------
 7 files changed, 61 insertions(+), 242 deletions(-)

(limited to 'include')

diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 4aaad55b53..525361179b 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -197,57 +197,24 @@
 #define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
 #define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/
 
-/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_RFCR5	(3 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CONFIG_SYS_LBC_LSDMR_WRC2	(2 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
-#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
-#define CONFIG_SYS_LBC_LSDMR_COMMON	( CONFIG_SYS_LBC_LSDMR_BSMA1516	\
-				| CONFIG_SYS_LBC_LSDMR_RFCR5		\
-				| CONFIG_SYS_LBC_LSDMR_PRETOACT3	\
-				| CONFIG_SYS_LBC_LSDMR_ACTTORW3	\
-				| CONFIG_SYS_LBC_LSDMR_BL8		\
-				| CONFIG_SYS_LBC_LSDMR_WRC2		\
-				| CONFIG_SYS_LBC_LSDMR_CL3		\
-				| CONFIG_SYS_LBC_LSDMR_RFEN		\
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_BSMA1516	\
+				| LSDMR_RFCR5		\
+				| LSDMR_PRETOACT3	\
+				| LSDMR_ACTTORW3	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC2		\
+				| LSDMR_CL3		\
+				| LSDMR_RFEN		\
 				)
 
 /*
  * SDRAM Controller configuration sequence.
  */
-#define CONFIG_SYS_LBC_LSDMR_1		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
+#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 
 
 /*
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index fa82fbc6fd..813512c045 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -206,42 +206,19 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
 #define CONFIG_SYS_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/
 
-/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
 /*
  * Common settings for all Local Bus SDRAM commands.
  * At run time, either BSMA1516 (for CPU 1.1)
  *                  or BSMA1617 (for CPU 1.0) (old)
  * is OR'ed in too.
  */
-#define CONFIG_SYS_LBC_LSDMR_COMMON	( CONFIG_SYS_LBC_LSDMR_RFCR16		\
-				| CONFIG_SYS_LBC_LSDMR_PRETOACT7	\
-				| CONFIG_SYS_LBC_LSDMR_ACTTORW7	\
-				| CONFIG_SYS_LBC_LSDMR_BL8		\
-				| CONFIG_SYS_LBC_LSDMR_WRC4		\
-				| CONFIG_SYS_LBC_LSDMR_CL3		\
-				| CONFIG_SYS_LBC_LSDMR_RFEN		\
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
+				| LSDMR_PRETOACT7	\
+				| LSDMR_ACTTORW7	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC4		\
+				| LSDMR_CL3		\
+				| LSDMR_RFEN		\
 				)
 
 /*
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 95bce95147..7089ac77ed 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -228,42 +228,19 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
 #define CONFIG_SYS_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/
 
-/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
 /*
  * Common settings for all Local Bus SDRAM commands.
  * At run time, either BSMA1516 (for CPU 1.1)
  *		    or BSMA1617 (for CPU 1.0) (old)
  * is OR'ed in too.
  */
-#define CONFIG_SYS_LBC_LSDMR_COMMON	( CONFIG_SYS_LBC_LSDMR_RFCR16		\
-				| CONFIG_SYS_LBC_LSDMR_PRETOACT7	\
-				| CONFIG_SYS_LBC_LSDMR_ACTTORW7	\
-				| CONFIG_SYS_LBC_LSDMR_BL8		\
-				| CONFIG_SYS_LBC_LSDMR_WRC4		\
-				| CONFIG_SYS_LBC_LSDMR_CL3		\
-				| CONFIG_SYS_LBC_LSDMR_RFEN		\
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
+				| LSDMR_PRETOACT7	\
+				| LSDMR_ACTTORW7	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC4		\
+				| LSDMR_CL3		\
+				| LSDMR_RFEN		\
 				)
 
 /*
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 6bf09613b0..ef95118ffe 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -204,42 +204,19 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
 #define CONFIG_SYS_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/
 
-/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
 /*
  * Common settings for all Local Bus SDRAM commands.
  * At run time, either BSMA1516 (for CPU 1.1)
  *                  or BSMA1617 (for CPU 1.0) (old)
  * is OR'ed in too.
  */
-#define CONFIG_SYS_LBC_LSDMR_COMMON	( CONFIG_SYS_LBC_LSDMR_RFCR16		\
-				| CONFIG_SYS_LBC_LSDMR_PRETOACT7	\
-				| CONFIG_SYS_LBC_LSDMR_ACTTORW7	\
-				| CONFIG_SYS_LBC_LSDMR_BL8		\
-				| CONFIG_SYS_LBC_LSDMR_WRC4		\
-				| CONFIG_SYS_LBC_LSDMR_CL3		\
-				| CONFIG_SYS_LBC_LSDMR_RFEN		\
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
+				| LSDMR_PRETOACT7	\
+				| LSDMR_ACTTORW7	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC4		\
+				| LSDMR_CL3		\
+				| LSDMR_RFEN		\
 				)
 
 /*
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index a41f50a173..761a370d13 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -193,57 +193,24 @@
 #define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
 #define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/
 
-/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_RFCR5	(3 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CONFIG_SYS_LBC_LSDMR_WRC2	(2 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
-#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
-#define CONFIG_SYS_LBC_LSDMR_COMMON	( CONFIG_SYS_LBC_LSDMR_BSMA1516	\
-				| CONFIG_SYS_LBC_LSDMR_RFCR5		\
-				| CONFIG_SYS_LBC_LSDMR_PRETOACT3	\
-				| CONFIG_SYS_LBC_LSDMR_ACTTORW3	\
-				| CONFIG_SYS_LBC_LSDMR_BL8		\
-				| CONFIG_SYS_LBC_LSDMR_WRC2		\
-				| CONFIG_SYS_LBC_LSDMR_CL3		\
-				| CONFIG_SYS_LBC_LSDMR_RFEN		\
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_BSMA1516	\
+				| LSDMR_RFCR5		\
+				| LSDMR_PRETOACT3	\
+				| LSDMR_ACTTORW3	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC2		\
+				| LSDMR_CL3		\
+				| LSDMR_RFEN		\
 				)
 
 /*
  * SDRAM Controller configuration sequence.
  */
-#define CONFIG_SYS_LBC_LSDMR_1		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
+#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 
 
 /*
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 58ff52b33f..77224d98e7 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -187,42 +187,19 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
 #define CONFIG_SYS_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/
 
-/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
 /*
  * Common settings for all Local Bus SDRAM commands.
  * At run time, either BSMA1516 (for CPU 1.1)
  *                  or BSMA1617 (for CPU 1.0) (old)
  * is OR'ed in too.
  */
-#define CONFIG_SYS_LBC_LSDMR_COMMON	( CONFIG_SYS_LBC_LSDMR_RFCR16		\
-				| CONFIG_SYS_LBC_LSDMR_PRETOACT7	\
-				| CONFIG_SYS_LBC_LSDMR_ACTTORW7	\
-				| CONFIG_SYS_LBC_LSDMR_BL8		\
-				| CONFIG_SYS_LBC_LSDMR_WRC4		\
-				| CONFIG_SYS_LBC_LSDMR_CL3		\
-				| CONFIG_SYS_LBC_LSDMR_RFEN		\
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
+				| LSDMR_PRETOACT7	\
+				| LSDMR_ACTTORW7	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC4		\
+				| LSDMR_CL3		\
+				| LSDMR_RFEN		\
 				)
 
 /*
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 8141a46dc0..a2ff9557ce 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -241,42 +241,19 @@
 #define CONFIG_SYS_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
 #define CONFIG_SYS_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/
 
-/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
 /*
  * Common settings for all Local Bus SDRAM commands.
  * At run time, either BSMA1516 (for CPU 1.1)
  *                  or BSMA1617 (for CPU 1.0) (old)
  * is OR'ed in too.
  */
-#define CONFIG_SYS_LBC_LSDMR_COMMON	( CONFIG_SYS_LBC_LSDMR_RFCR16		\
-				| CONFIG_SYS_LBC_LSDMR_PRETOACT7	\
-				| CONFIG_SYS_LBC_LSDMR_ACTTORW7	\
-				| CONFIG_SYS_LBC_LSDMR_BL8		\
-				| CONFIG_SYS_LBC_LSDMR_WRC4		\
-				| CONFIG_SYS_LBC_LSDMR_CL3		\
-				| CONFIG_SYS_LBC_LSDMR_RFEN		\
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
+				| LSDMR_PRETOACT7	\
+				| LSDMR_ACTTORW7	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC4		\
+				| LSDMR_CL3		\
+				| LSDMR_RFEN		\
 				)
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
-- 
cgit 


From 540dcf1cb86961e11aa92c47671f27762c581d8c Mon Sep 17 00:00:00 2001
From: Kumar Gala <galak@kernel.crashing.org>
Date: Thu, 26 Mar 2009 01:34:39 -0500
Subject: 83xx: Use common LSDMR defines from asm/fsl_lbc.h

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
---
 include/configs/MPC8323ERDB.h | 26 ------------------
 include/configs/MPC832XEMDS.h | 26 ------------------
 include/configs/MPC8349EMDS.h | 62 +++++++++----------------------------------
 include/configs/MPC8360EMDS.h | 27 ++++---------------
 include/configs/sbc8349.h     | 62 +++++++++----------------------------------
 5 files changed, 31 insertions(+), 172 deletions(-)

(limited to 'include')

diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 4eab285712..9b8b0333ed 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -248,34 +248,8 @@
 #define CONFIG_SYS_LBC_LSRT	0x32000000	/* LB sdram refresh timer, about 6us */
 #define CONFIG_SYS_LBC_MRTPR	0x20000000	/* LB refresh timer prescal, 266MHz/32 */
 
-/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
 #define CONFIG_SYS_LBC_LSDMR_COMMON	0x0063b723
 
-/*
- * SDRAM Controller configuration sequence.
- */
-#define CONFIG_SYS_LBC_LSDMR_1		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
-
 #endif
 
 /*
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index ea1928eae9..c82cda2dd0 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -246,34 +246,8 @@
 #define CONFIG_SYS_LBC_LSRT	0x32000000	/* LB sdram refresh timer, about 6us */
 #define CONFIG_SYS_LBC_MRTPR	0x20000000	/* LB refresh timer prescal, 266MHz/32 */
 
-/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
 #define CONFIG_SYS_LBC_LSDMR_COMMON	0x0063b723
 
-/*
- * SDRAM Controller configuration sequence.
- */
-#define CONFIG_SYS_LBC_LSDMR_1		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
-
 #endif
 
 /*
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index b3c0e2dd5c..6cc27cb3ad 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -262,60 +262,24 @@
 #define CONFIG_SYS_LBC_LSRT	0x32000000    /* LB sdram refresh timer, about 6us */
 #define CONFIG_SYS_LBC_MRTPR	0x20000000    /* LB refresh timer prescal, 266MHz/32 */
 
-/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_RFCR5	(3 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_RFCR8	(5 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT6	(5 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CONFIG_SYS_LBC_LSDMR_WRC2	(2 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_WRC3	(3 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
-#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
-#define CONFIG_SYS_LBC_LSDMR_COMMON    ( CONFIG_SYS_LBC_LSDMR_RFEN            \
-				| CONFIG_SYS_LBC_LSDMR_BSMA1516	\
-				| CONFIG_SYS_LBC_LSDMR_RFCR8		\
-				| CONFIG_SYS_LBC_LSDMR_PRETOACT6	\
-				| CONFIG_SYS_LBC_LSDMR_ACTTORW3	\
-				| CONFIG_SYS_LBC_LSDMR_BL8		\
-				| CONFIG_SYS_LBC_LSDMR_WRC3		\
-				| CONFIG_SYS_LBC_LSDMR_CL3		\
+#define CONFIG_SYS_LBC_LSDMR_COMMON    ( LSDMR_RFEN            \
+				| LSDMR_BSMA1516	\
+				| LSDMR_RFCR8		\
+				| LSDMR_PRETOACT6	\
+				| LSDMR_ACTTORW3	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC3		\
+				| LSDMR_CL3		\
 				)
 
 /*
  * SDRAM Controller configuration sequence.
  */
-#define CONFIG_SYS_LBC_LSDMR_1		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
+#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 #endif
 
 /*
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index bdd6b87ad3..4b09de17fc 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -271,33 +271,16 @@
 #define CONFIG_SYS_LBC_LSRT	0x32000000 /* LB sdram refresh timer, about 6us */
 #define CONFIG_SYS_LBC_MRTPR	0x20000000 /* LB refresh timer prescal, 266MHz/32 */
 
-/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
 #define CONFIG_SYS_LBC_LSDMR_COMMON	0x0063b723
 
 /*
  * SDRAM Controller configuration sequence.
  */
-#define CONFIG_SYS_LBC_LSDMR_1		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
+#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 
 #endif
 
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index f476e3ed5e..db1d4ac030 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -227,60 +227,24 @@
 #define CONFIG_SYS_LBC_LSRT	0x32000000    /* LB sdram refresh timer, about 6us */
 #define CONFIG_SYS_LBC_MRTPR	0x20000000    /* LB refresh timer prescal, 266MHz/32 */
 
-/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_RFEN	(1 << (31 -  1))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_RFCR5	(3 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_RFCR8	(5 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_RFCR16	(7 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT6	(5 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_BL8	(1 << (31 - 23))
-#define CONFIG_SYS_LBC_LSDMR_WRC2	(2 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_WRC3	(3 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_WRC4	(0 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
-#define CONFIG_SYS_LBC_LSDMR_CL3	(3 << (31 - 31))
-
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
-
-#define CONFIG_SYS_LBC_LSDMR_COMMON    ( CONFIG_SYS_LBC_LSDMR_RFEN            \
-				| CONFIG_SYS_LBC_LSDMR_BSMA1516	\
-				| CONFIG_SYS_LBC_LSDMR_RFCR8		\
-				| CONFIG_SYS_LBC_LSDMR_PRETOACT6	\
-				| CONFIG_SYS_LBC_LSDMR_ACTTORW3	\
-				| CONFIG_SYS_LBC_LSDMR_BL8		\
-				| CONFIG_SYS_LBC_LSDMR_WRC3		\
-				| CONFIG_SYS_LBC_LSDMR_CL3		\
+#define CONFIG_SYS_LBC_LSDMR_COMMON    ( LSDMR_RFEN            \
+				| LSDMR_BSMA1516	\
+				| LSDMR_RFCR8		\
+				| LSDMR_PRETOACT6	\
+				| LSDMR_ACTTORW3	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC3		\
+				| LSDMR_CL3		\
 				)
 
 /*
  * SDRAM Controller configuration sequence.
  */
-#define CONFIG_SYS_LBC_LSDMR_1		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5		( CONFIG_SYS_LBC_LSDMR_COMMON \
-				| CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
+#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 #endif
 
 /*
-- 
cgit 


From c360ceac0286159f94d9d1a9496fc9858c8d9bec Mon Sep 17 00:00:00 2001
From: Dave Liu <daveliu@freescale.com>
Date: Sat, 14 Mar 2009 12:48:30 +0800
Subject: fsl-ddr: add the DDR3 SPD infrastructure

- support mirrored DIMMs, not support register DIMMs
- test passed on P2020DS board with MT9JSF12872AY-1G1D1
- test passed on MPC8569MDS board with MT8JSF12864HY-1G1D1

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Travis Wheatley <travis.wheatley@freescale.com>
---
 include/asm-ppc/fsl_ddr_dimm_params.h |  7 +++++++
 include/asm-ppc/fsl_ddr_sdram.h       | 31 ++++++++++++++++++++++++++++++-
 include/ddr_spd.h                     | 13 ++++++++++++-
 3 files changed, 49 insertions(+), 2 deletions(-)

(limited to 'include')

diff --git a/include/asm-ppc/fsl_ddr_dimm_params.h b/include/asm-ppc/fsl_ddr_dimm_params.h
index c794eedfe4..55923e09b3 100644
--- a/include/asm-ppc/fsl_ddr_dimm_params.h
+++ b/include/asm-ppc/fsl_ddr_dimm_params.h
@@ -33,9 +33,15 @@ typedef struct dimm_params_s {
 
 	/* used in computing base address of DIMMs */
 	unsigned long long base_address;
+	/* mirrored DIMMs */
+	unsigned int mirrored_dimm;	/* only for ddr3 */
 
 	/* DIMM timing parameters */
 
+	unsigned int mtb_ps;	/* medium timebase ps, only for ddr3 */
+	unsigned int tAA_ps;	/* minimum CAS latency time, only for ddr3 */
+	unsigned int tFAW_ps;	/* four active window delay, only for ddr3 */
+
 	/*
 	 * SDRAM clock periods
 	 * The range for these are 1000-10000 so a short should be sufficient
@@ -67,6 +73,7 @@ typedef struct dimm_params_s {
 
 	unsigned int refresh_rate_ps;
 
+	/* DDR3 doesn't need these as below */
 	unsigned int tIS_ps;	/* byte 32, spd->ca_setup */
 	unsigned int tIH_ps;	/* byte 33, spd->ca_hold */
 	unsigned int tDS_ps;	/* byte 34, spd->data_setup */
diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h
index 6e3b2559c9..c2e5aeebcb 100644
--- a/include/asm-ppc/fsl_ddr_sdram.h
+++ b/include/asm-ppc/fsl_ddr_sdram.h
@@ -19,6 +19,11 @@
 #define SDRAM_TYPE_LPDDR1  6
 #define SDRAM_TYPE_DDR3    7
 
+#define DDR_BL4		4	/* burst length 4 */
+#define DDR_BC4		DDR_BL4	/* burst chop for ddr3 */
+#define DDR_OTF		6	/* on-the-fly BC4 and BL8 */
+#define DDR_BL8		8	/* burst length 8 */
+
 #if defined(CONFIG_FSL_DDR1)
 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(1)
 typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
@@ -68,6 +73,18 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
 #define SDRAM_CFG_2T_EN			0x00008000
 #define SDRAM_CFG_BI			0x00000001
 
+#if defined(CONFIG_P4080)
+#define RD_TO_PRE_MASK		0xf
+#define RD_TO_PRE_SHIFT		13
+#define WR_DATA_DELAY_MASK	0xf
+#define WR_DATA_DELAY_SHIFT	9
+#else
+#define RD_TO_PRE_MASK		0x7
+#define RD_TO_PRE_SHIFT		13
+#define WR_DATA_DELAY_MASK	0x7
+#define WR_DATA_DELAY_SHIFT	10
+#endif
+
 /* Record of register values computed */
 typedef struct fsl_ddr_cfg_regs_s {
 	struct {
@@ -145,7 +162,11 @@ typedef struct memctl_options_s {
 	unsigned int dynamic_power;	/* DYN_PWR */
 	/* memory data width to use (16-bit, 32-bit, 64-bit) */
 	unsigned int data_bus_width;
-	unsigned int burst_length;	/* 4, 8 */
+	unsigned int burst_length;	/* BL4, OTF and BL8 */
+	/* On-The-Fly Burst Chop enable */
+	unsigned int OTF_burst_chop_en;
+	/* mirrior DIMMs for DDR3 */
+	unsigned int mirrored_dimm;
 
 	/* Global Timing Parameters */
 	unsigned int cas_latency_override;
@@ -164,9 +185,17 @@ typedef struct memctl_options_s {
 	unsigned int tCKE_clock_pulse_width_ps;	/* tCKE */
 	unsigned int tFAW_window_four_activates_ps;	/* tFAW --  FOUR_ACT */
 
+	/* Rtt impedance */
+	unsigned int rtt_override;		/* rtt_override enable */
+	unsigned int rtt_override_value;	/* that is Rtt_Nom for DDR3 */
+
 	/* Automatic self refresh */
 	unsigned int auto_self_refresh_en;
 	unsigned int sr_it;
+	/* ZQ calibration */
+	unsigned int zq_en;
+	/* Write leveling */
+	unsigned int wrlvl_en;
 } memctl_options_t;
 
 extern phys_size_t fsl_ddr_sdram(void);
diff --git a/include/ddr_spd.h b/include/ddr_spd.h
index 6fdcef0c0a..10402c5bbb 100644
--- a/include/ddr_spd.h
+++ b/include/ddr_spd.h
@@ -184,7 +184,7 @@ typedef struct ddr3_spd_eeprom_s {
 	unsigned char module_type;     /*  3 Key Byte / Module Type */
 	unsigned char density_banks;   /*  4 SDRAM Density and Banks */
 	unsigned char addressing;      /*  5 SDRAM Addressing */
-	unsigned char res_6;           /*  6 Reserved */
+	unsigned char module_vdd;      /*  6 Module nominal voltage, VDD */
 	unsigned char organization;    /*  7 Module Organization */
 	unsigned char bus_width;       /*  8 Module Memory Bus Width */
 	unsigned char ftb_div;         /*  9 Fine Timebase (FTB)
@@ -273,6 +273,7 @@ extern unsigned int ddr1_spd_check(const ddr1_spd_eeprom_t *spd);
 extern void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd);
 extern unsigned int ddr2_spd_check(const ddr2_spd_eeprom_t *spd);
 extern void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd);
+extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd);
 
 /*
  * Byte 2 Fundamental Memory Types.
@@ -289,4 +290,14 @@ extern void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd);
 #define SPD_MEMTYPE_DDR2_FBDIMM_PROBE	(0x0A)
 #define SPD_MEMTYPE_DDR3	(0x0B)
 
+/*
+ * Byte 3 Key Byte / Module Type for DDR3 SPD
+ */
+#define SPD_MODULETYPE_RDIMM		(0x01)
+#define SPD_MODULETYPE_UDIMM		(0x02)
+#define SPD_MODULETYPE_SODIMM		(0x03)
+#define SPD_MODULETYPE_MICRODIMM	(0x04)
+#define SPD_MODULETYPE_MINIRDIMM	(0x05)
+#define SPD_MODULETYPE_MINIUDIMM	(0x06)
+
 #endif /* _DDR_SPD_H_ */
-- 
cgit 


From 22b6dbc1696d927d938dd4e16f65d83c0d4fb3f4 Mon Sep 17 00:00:00 2001
From: Haiying Wang <Haiying.Wang@freescale.com>
Date: Fri, 27 Mar 2009 17:02:44 -0400
Subject: MPC85xx: Add MPC8569 CPU support

There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of
LBCR in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage,
then invalidate it after LBCR bit 13 is set.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 include/asm-ppc/immap_85xx.h | 13 ++++++++++++-
 include/asm-ppc/immap_qe.h   |  8 +++++---
 include/asm-ppc/processor.h  |  2 ++
 3 files changed, 19 insertions(+), 4 deletions(-)

(limited to 'include')

diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 094fb9c5d6..0810b8ef78 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1609,8 +1609,19 @@ typedef struct ccsr_gur {
 	char	res2[12];
 	uint	gpiocr;		/* 0xe0030 - GPIO control register */
 	char	res3[12];
+#if defined(CONFIG_MPC8569)
+	uint	plppar1;
+			/* 0xe0040 - Platform port pin assignment register 1 */
+	uint	plppar2;
+			/* 0xe0044 - Platform port pin assignment register 2 */
+	uint	plpdir1;
+			/* 0xe0048 - Platform port pin direction register 1 */
+	uint	plpdir2;
+			/* 0xe004c - Platform port pin direction register 2 */
+#else
 	uint	gpoutdr;	/* 0xe0040 - General-purpose output data register */
 	char	res4[12];
+#endif
 	uint	gpindr;		/* 0xe0050 - General-purpose input data register */
 	char	res5[12];
 	uint	pmuxcr;		/* 0xe0060 - Alternate function signal multiplex control */
@@ -1651,7 +1662,7 @@ typedef struct ccsr_gur {
 	uint	svr;		/* 0xe00a4 - System version register */
 	char	res10a[8];
 	uint	rstcr;		/* 0xe00b0 - Reset control register */
-#ifdef CONFIG_MPC8568
+#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
 	char	res10b[76];
 	par_io_t qe_par_io[7];  /* 0xe0100 - 0xe01bf */
 	char	res10c[3136];
diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h
index 39da3771c9..66a4735dda 100644
--- a/include/asm-ppc/immap_qe.h
+++ b/include/asm-ppc/immap_qe.h
@@ -20,7 +20,9 @@
 typedef struct qe_iram {
 	u32 iadd;		/* I-RAM Address Register */
 	u32 idata;		/* I-RAM Data Register    */
-	u8 res0[0x78];
+	u8 res0[0x4];
+	u32 iready;
+	u8 res1[0x70];
 } __attribute__ ((packed)) qe_iram_t;
 
 /* QE Interrupt Controller
@@ -580,7 +582,7 @@ typedef struct qe_immap {
 	u8 res14[0x300];
 	u8 res15[0x3A00];
 	u8 res16[0x8000];	/* 0x108000 -  0x110000 */
-#if defined(CONFIG_MPC8568)
+#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
 	u8 muram[0x10000];	/* 0x1_0000 -  0x2_0000 Multi-user RAM */
 	u8 res17[0x20000];	/* 0x2_0000 -  0x4_0000 */
 #else
@@ -592,7 +594,7 @@ typedef struct qe_immap {
 
 extern qe_map_t *qe_immr;
 
-#if defined(CONFIG_MPC8568)
+#if defined(CONFIG_MPC8568) || defined(CONFIG_MPC8569)
 #define QE_MURAM_SIZE		0x10000UL
 #elif defined(CONFIG_MPC8360)
 #define QE_MURAM_SIZE		0xc000UL
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 5b29de0fda..83e3581f39 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -955,6 +955,8 @@
 #define SVR_8567_E	0x807E00
 #define SVR_8568	0x807500
 #define SVR_8568_E	0x807D00
+#define SVR_8569	0x808000
+#define SVR_8569_E	0x808800
 #define SVR_8572	0x80E000
 #define SVR_8572_E	0x80E800
 #define SVR_P2020	0x80E200
-- 
cgit 


From 765547dc5e0e8cbe6b8f4ea8a5d6ff237935c352 Mon Sep 17 00:00:00 2001
From: Haiying Wang <Haiying.Wang@freescale.com>
Date: Fri, 27 Mar 2009 17:02:45 -0400
Subject: MPC85xx: Add MPC8569MDS board support

This patch adds MPC8569MDS board support. The UART, QE UEC1 and UEC2, BRD
EEPROM on I2C2 bus, PCI express and DDR3 SPD are supported in this patch.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Hillel Avni <Hillel.Avni@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 include/configs/MPC8569MDS.h | 454 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 454 insertions(+)
 create mode 100644 include/configs/MPC8569MDS.h

(limited to 'include')

diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
new file mode 100644
index 0000000000..b0af5dcf19
--- /dev/null
+++ b/include/configs/MPC8569MDS.h
@@ -0,0 +1,454 @@
+/*
+ * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc8569mds board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48/68 */
+#define CONFIG_MPC8569		1	/* MPC8569 specific */
+#define CONFIG_MPC8569MDS	1	/* MPC8569MDS board specific */
+
+#define CONFIG_FSL_ELBC		1	/* Has Enhance localbus controller */
+
+#define CONFIG_PCI		1	/* Disable PCI/PCIE */
+#define CONFIG_PCIE1		1	/* PCIE controller */
+#define CONFIG_FSL_PCI_INIT	1	/* use common fsl pci init code */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#define CONFIG_QE			/* Enable QE */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
+/*
+ * When initializing flash, if we cannot find the manufacturer ID,
+ * assume this is the AMD flash associated with the MDS board.
+ * This allows booting from a promjet.
+ */
+#define CONFIG_ASSUME_AMD_FLASH
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+/* Replace a call to get_clock_freq (after it is implemented)*/
+#define CONFIG_SYS_CLK_FREQ	66000000
+#define CONFIG_DDR_CLK_FREQ	66000000
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE				/* toggle L2 cache	*/
+#define CONFIG_BTB				/* toggle branch predition */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR
+						/* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR
+						/* PQII uses CONFIG_SYS_IMMR */
+
+#define CONFIG_SYS_PCI1_ADDR           (CONFIG_SYS_CCSRBAR+0x8000)
+#define CONFIG_SYS_PCIE1_ADDR          (CONFIG_SYS_CCSRBAR+0xa000)
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR3
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#define CONFIG_DDR_DLL			/* possible DLL fix needed */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+					/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS1    0x51    /* CTLR 0 DIMM 0 */
+#define SPD_EEPROM_ADDRESS2    0x52    /* CTLR 1 DIMM 0 */
+
+/* These are used when DDR doesn't use SPD.  */
+#define CONFIG_SYS_SDRAM_SIZE           1024		/* DDR is 1024MB */
+#define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
+#define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
+#define CONFIG_SYS_DDR_TIMING_3         0x00020000
+#define CONFIG_SYS_DDR_TIMING_0         0x00330004
+#define CONFIG_SYS_DDR_TIMING_1         0x6F6B4644
+#define CONFIG_SYS_DDR_TIMING_2         0x002888D0
+#define CONFIG_SYS_DDR_SDRAM_CFG	0x47000000
+#define CONFIG_SYS_DDR_SDRAM_CFG_2	0x04401040
+#define CONFIG_SYS_DDR_SDRAM_MODE	0x40401521
+#define CONFIG_SYS_DDR_SDRAM_MODE_2	0x8000C000
+#define CONFIG_SYS_DDR_SDRAM_INTERVAL	0x03E00000
+#define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	0x01000000
+#define CONFIG_SYS_DDR_TIMING_4         0x00220001
+#define CONFIG_SYS_DDR_TIMING_5         0x03402400
+#define CONFIG_SYS_DDR_ZQ_CNTL		0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CNTL	0x0655A604
+#define CONFIG_SYS_DDR_CDR_1		0x80040000
+#define CONFIG_SYS_DDR_CDR_2		0x00000000
+#define CONFIG_SYS_DDR_OCD_CTRL         0x00000000
+#define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
+#define CONFIG_SYS_DDR_CONTROL          0xc7000000      /* Type = DDR3 */
+#define CONFIG_SYS_DDR_CONTROL2         0x24400000
+
+#define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
+#define CONFIG_SYS_DDR_ERR_DIS          0x00000000
+#define CONFIG_SYS_DDR_SBE              0x00010000
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Local Bus Definitions
+ */
+
+#define CONFIG_SYS_FLASH_BASE		0xfe000000	/* start of FLASH 32M */
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_SYS_BCSR_BASE		0xf8000000
+#define CONFIG_SYS_BCSR_BASE_PHYS	CONFIG_SYS_BCSR_BASE
+
+/*Chip select 0 - Flash*/
+#define CONFIG_SYS_BR0_PRELIM		0xfe000801
+#define	CONFIG_SYS_OR0_PRELIM		0xfe000ff7
+
+/*Chip slelect 1 - BCSR*/
+#define CONFIG_SYS_BR1_PRELIM		0xf8000801
+#define	CONFIG_SYS_OR1_PRELIM		0xffffe9f7
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+
+/*
+ * SDRAM on the LocalBus
+ */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM	 */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+#define CONFIG_SYS_LBC_LCRR	0x00000004	/* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR	0x00040000	/* LB config reg */
+#define CONFIG_SYS_LBC_LSRT	0x20000000	/* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR	0x00000000	/* LB refresh timer prescal*/
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000  /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x4000	    /* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)	/* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX		1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser*/
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+#define CONFIG_SYS_64BIT_VSPRINTF	1
+#define CONFIG_SYS_64BIT_STRTOUL	1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
+#undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED	400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE	0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{{0,0x69}}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C2_OFFSET	0x3100
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_BUS_NUM       1
+
+#define PLPPAR1_I2C_BIT_MASK		0x0000000F
+#define PLPPAR1_I2C2_VAL		0x00000000
+#define PLPDIR1_I2C_BIT_MASK		0x0000000F
+#define PLPDIR1_I2C2_VAL		0x0000000F
+
+/*
+ * General PCI
+ * Memory Addresses are mapped 1-1. I/O is mapped from 0
+ */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xe2800000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe2800000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
+
+#define CONFIG_SYS_SRIO_MEM_VIRT	0xc0000000
+#define CONFIG_SYS_SRIO_MEM_BUS		0xc0000000
+#define CONFIG_SYS_SRIO_MEM_PHYS	0xc0000000
+
+#ifdef CONFIG_QE
+/*
+ * QE UEC ethernet configuration
+ */
+
+#define CONFIG_MIIM_ADDRESS	(CONFIG_SYS_CCSRBAR + 0x82120)
+#define CONFIG_UEC_ETH
+#define CONFIG_ETHPRIME         "FSL UEC0"
+#define CONFIG_PHY_MODE_NEED_CHANGE
+
+#define CONFIG_UEC_ETH1         /* GETH1 */
+#define CONFIG_HAS_ETH0
+
+#ifdef CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM        0       /* UCC1 */
+#define CONFIG_SYS_UEC1_RX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC1_TX_CLK         QE_CLK12
+#define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR       7
+#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID
+#endif
+
+#define CONFIG_UEC_ETH2         /* GETH2 */
+#define CONFIG_HAS_ETH1
+
+#ifdef CONFIG_UEC_ETH2
+#define CONFIG_SYS_UEC2_UCC_NUM        1       /* UCC2 */
+#define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC2_TX_CLK         QE_CLK17
+#define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR       1
+#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID
+#endif
+
+#endif /* CONFIG_QE */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#endif	/* CONFIG_PCI */
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI	1
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* 256K(one sector) for env */
+#define CONFIG_ENV_SIZE		0x2000
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/* QE microcode/firmware address */
+#define CONFIG_SYS_QE_FW_ADDR	0xfff00000
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+#endif
+
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	2048		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+						/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	32		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+						/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ	1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)
+					/* Initial Memory map for Linux*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_HOSTNAME mpc8569mds
+#define CONFIG_ROOTPATH  /nfsroot
+#define CONFIG_BOOTFILE  your.uImage
+
+#define CONFIG_SERVERIP  192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK   255.255.255.0
+
+#define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consoledev=ttyS0\0"						\
+	"ramdiskaddr=600000\0"						\
+	"ramdiskfile=your.ramdisk.u-boot\0"				\
+	"fdtaddr=400000\0"						\
+	"fdtfile=your.fdt.dtb\0"					\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+	"nfsroot=$serverip:$rootpath "					\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw "			\
+	"console=$consoledev,$baudrate $othbootargs\0"			\
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"run nfsargs;"							\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"run ramargs;"							\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
-- 
cgit 


From 7649a590b53ee548f41428bf20780f74ce9fc099 Mon Sep 17 00:00:00 2001
From: Kumar Gala <galak@kernel.crashing.org>
Date: Tue, 31 Mar 2009 23:02:38 -0500
Subject: 86xx: Cleanup MP support

* Use CONFIG_MP instead of CONFIG_NUM_CPUS to match 85xx
* Introduce determine_mp_bootpg() helper.  We'll need this to address a
  bug introduced in v2009.03 with 86xx MP booting.  We have to make sure
  to reserve the region of memory used for the MP bootpg() so other
  u-boot code doesn't use it.
* Added dummy versions of cpu_reset(), cpu_status() & cpu_release() to
  allow cmd_mp.c to build and work. In the future we should look at
  implementing all these functions. This could be common w/85xx if we
  use spin tables on 86xx.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 include/asm-ppc/mp.h          | 31 +++++++++++++++++++++++++++++++
 include/configs/MPC8641HPCN.h |  1 +
 include/configs/sbc8641d.h    |  1 +
 3 files changed, 33 insertions(+)
 create mode 100644 include/asm-ppc/mp.h

(limited to 'include')

diff --git a/include/asm-ppc/mp.h b/include/asm-ppc/mp.h
new file mode 100644
index 0000000000..8a5486f099
--- /dev/null
+++ b/include/asm-ppc/mp.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_MP_H_
+#define _ASM_MP_H_
+
+#include <lmb.h>
+
+void setup_mp(void);
+void cpu_mp_lmb_reserve(struct lmb *lmb);
+u32 determine_mp_bootpg(void);
+
+#endif
+
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 9d661010d3..d8042fb764 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -36,6 +36,7 @@
 #define CONFIG_MPC86xx		1	/* MPC86xx */
 #define CONFIG_MPC8641		1	/* MPC8641 specific */
 #define CONFIG_MPC8641HPCN	1	/* MPC8641HPCN board specific */
+#define CONFIG_MP		1	/* support multiple processors */
 #define CONFIG_NUM_CPUS		2	/* Number of CPUs in the system */
 #define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
 /*#define CONFIG_PHYS_64BIT	1*/	/* Place devices in 36-bit space */
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 1008812b71..ef0f627b6c 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -40,6 +40,7 @@
 #define CONFIG_MPC86xx		1	/* MPC86xx */
 #define CONFIG_MPC8641		1	/* MPC8641 specific */
 #define CONFIG_SBC8641D		1	/* SBC8641D board specific */
+#define CONFIG_MP		1	/* support multiple processors */
 #define CONFIG_NUM_CPUS         2       /* Number of CPUs in the system */
 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
 
-- 
cgit