From 6d1970fa8a8d315af2b5c2c6f0ad5e5c24a382b5 Mon Sep 17 00:00:00 2001
From: Kever Yang <kever.yang@rock-chips.com>
Date: Fri, 23 Jun 2017 16:11:05 +0800
Subject: rockchip: add sdram_common for common functions

There are some functions like sdram_size_mb can be re-used for
different rockchip SoCs, just put them into common file.
Add board_get_usable_ram_top() for ram_top init base on
SDRAM_MAX_SIZE.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Added SDRAM_MAX_SIZE definition for RK3036:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

fixup: 3036 fix for sdram_common
---
 include/configs/rk3036_common.h | 1 +
 include/configs/rk3188_common.h | 1 +
 include/configs/rk3288_common.h | 1 +
 include/configs/rk3328_common.h | 2 +-
 include/configs/rk3368_common.h | 2 ++
 include/configs/rk3399_common.h | 1 +
 6 files changed, 7 insertions(+), 1 deletion(-)

(limited to 'include')

diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index 836c5e3fed..1f6b5a1669 100644
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@@ -39,6 +39,7 @@
 #define CONFIG_SYS_SDRAM_BASE		0x60000000
 #define CONFIG_NR_DRAM_BANKS		1
 #define SDRAM_BANK_SIZE			(512UL << 20UL)
+#define SDRAM_MAX_SIZE                  (CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE)
 
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI
diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h
index a1e0eb7c8d..7f57dd3141 100644
--- a/include/configs/rk3188_common.h
+++ b/include/configs/rk3188_common.h
@@ -64,6 +64,7 @@
 #define CONFIG_SYS_SDRAM_BASE		0x60000000
 #define CONFIG_NR_DRAM_BANKS		1
 #define SDRAM_BANK_SIZE			(2UL << 30)
+#define SDRAM_MAX_SIZE			0x80000000
 
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index ecf2675255..7d6ef41368 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -48,6 +48,7 @@
 #define CONFIG_SYS_SDRAM_BASE		0
 #define CONFIG_NR_DRAM_BANKS		1
 #define SDRAM_BANK_SIZE			(2UL << 30)
+#define SDRAM_MAX_SIZE			0xfe000000
 
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
index 5a06244594..7f9f0c5534 100644
--- a/include/configs/rk3328_common.h
+++ b/include/configs/rk3328_common.h
@@ -9,7 +9,6 @@
 
 #include "rockchip-common.h"
 
-#define CONFIG_NR_DRAM_BANKS		1
 #define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_SYS_MAXARGS		16
 #define CONFIG_SYS_MALLOC_LEN		(32 << 20)
@@ -37,6 +36,7 @@
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
 #define CONFIG_SYS_SDRAM_BASE		0
 #define CONFIG_NR_DRAM_BANKS		1
+#define SDRAM_MAX_SIZE			0xff000000
 
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI
diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index 8ebf2324c5..b0c858c693 100644
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h
@@ -12,6 +12,8 @@
 #include <asm/arch/hardware.h>
 #include <linux/sizes.h>
 
+#define CONFIG_SYS_SDRAM_BASE		0
+#define SDRAM_MAX_SIZE			0xff000000
 #define CONFIG_NR_DRAM_BANKS		1
 #define CONFIG_SYS_MAXARGS		16
 #define CONFIG_BAUDRATE			115200
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index 44dad570d3..54ea97b164 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -51,6 +51,7 @@
 /* FAT sd card locations. */
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
 #define CONFIG_SYS_SDRAM_BASE		0
+#define SDRAM_MAX_SIZE			0xf8000000
 #define CONFIG_NR_DRAM_BANKS		1
 
 #define CONFIG_SF_DEFAULT_SPEED 20000000
-- 
cgit 


From b647442ce8a3c191677155ff29ca0c41dc8c6d0c Mon Sep 17 00:00:00 2001
From: Kever Yang <kever.yang@rock-chips.com>
Date: Fri, 23 Jun 2017 17:17:51 +0800
Subject: rockchip: rk322x: add dts file

The dts files are from kernel and with modify to adapt U-Boot.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---
 include/dt-bindings/clock/rk3228-cru.h | 238 +++++++++++++++++++++++++++++++++
 1 file changed, 238 insertions(+)
 create mode 100644 include/dt-bindings/clock/rk3228-cru.h

(limited to 'include')

diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
new file mode 100644
index 0000000000..13f9c864ca
--- /dev/null
+++ b/include/dt-bindings/clock/rk3228-cru.h
@@ -0,0 +1,238 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
+
+/* core clocks */
+#define PLL_APLL		1
+#define PLL_DPLL		2
+#define PLL_CPLL		3
+#define PLL_GPLL		4
+#define ARMCLK			5
+
+/* sclk gates (special clocks) */
+#define SCLK_SPI0		65
+#define SCLK_NANDC		67
+#define SCLK_SDMMC		68
+#define SCLK_SDIO		69
+#define SCLK_EMMC		71
+#define SCLK_TSADC		72
+#define SCLK_UART0		77
+#define SCLK_UART1		78
+#define SCLK_UART2		79
+#define SCLK_I2S0		80
+#define SCLK_I2S1		81
+#define SCLK_I2S2		82
+#define SCLK_SPDIF		83
+#define SCLK_TIMER0		85
+#define SCLK_TIMER1		86
+#define SCLK_TIMER2		87
+#define SCLK_TIMER3		88
+#define SCLK_TIMER4		89
+#define SCLK_TIMER5		90
+#define SCLK_I2S_OUT		113
+#define SCLK_SDMMC_DRV		114
+#define SCLK_SDIO_DRV		115
+#define SCLK_EMMC_DRV		117
+#define SCLK_SDMMC_SAMPLE	118
+#define SCLK_SDIO_SAMPLE	119
+#define SCLK_EMMC_SAMPLE	121
+#define SCLK_VOP		122
+#define SCLK_HDMI_HDCP		123
+#define SCLK_MAC_SRC		124
+#define SCLK_MAC_EXTCLK		125
+#define SCLK_MAC		126
+#define SCLK_MAC_REFOUT		127
+#define SCLK_MAC_REF		128
+#define SCLK_MAC_RX		129
+#define SCLK_MAC_TX		130
+#define SCLK_MAC_PHY		131
+#define SCLK_MAC_OUT		132
+
+/* dclk gates */
+#define DCLK_VOP		190
+#define DCLK_HDMI_PHY		191
+
+/* aclk gates */
+#define ACLK_DMAC		194
+#define ACLK_PERI		210
+#define ACLK_VOP		211
+#define ACLK_GMAC		212
+
+/* pclk gates */
+#define PCLK_GPIO0		320
+#define PCLK_GPIO1		321
+#define PCLK_GPIO2		322
+#define PCLK_GPIO3		323
+#define PCLK_GRF		329
+#define PCLK_I2C0		332
+#define PCLK_I2C1		333
+#define PCLK_I2C2		334
+#define PCLK_I2C3		335
+#define PCLK_SPI0		338
+#define PCLK_UART0		341
+#define PCLK_UART1		342
+#define PCLK_UART2		343
+#define PCLK_TSADC		344
+#define PCLK_PWM		350
+#define PCLK_TIMER		353
+#define PCLK_PERI		363
+#define PCLK_HDMI_CTRL		364
+#define PCLK_HDMI_PHY		365
+#define PCLK_GMAC		367
+
+/* hclk gates */
+#define HCLK_I2S0_8CH		442
+#define HCLK_I2S1_8CH		443
+#define HCLK_I2S2_2CH		444
+#define HCLK_SPDIF_8CH		445
+#define HCLK_VOP		452
+#define HCLK_NANDC		453
+#define HCLK_SDMMC		456
+#define HCLK_SDIO		457
+#define HCLK_EMMC		459
+#define HCLK_PERI		478
+
+#define CLK_NR_CLKS		(HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0_PO		0
+#define SRST_CORE1_PO		1
+#define SRST_CORE2_PO		2
+#define SRST_CORE3_PO		3
+#define SRST_CORE0		4
+#define SRST_CORE1		5
+#define SRST_CORE2		6
+#define SRST_CORE3		7
+#define SRST_CORE0_DBG		8
+#define SRST_CORE1_DBG		9
+#define SRST_CORE2_DBG		10
+#define SRST_CORE3_DBG		11
+#define SRST_TOPDBG		12
+#define SRST_ACLK_CORE		13
+#define SRST_NOC		14
+#define SRST_L2C		15
+
+#define SRST_CPUSYS_H		18
+#define SRST_BUSSYS_H		19
+#define SRST_SPDIF		20
+#define SRST_INTMEM		21
+#define SRST_ROM		22
+#define SRST_OTG_ADP		23
+#define SRST_I2S0		24
+#define SRST_I2S1		25
+#define SRST_I2S2		26
+#define SRST_ACODEC_P		27
+#define SRST_DFIMON		28
+#define SRST_MSCH		29
+#define SRST_EFUSE1024		30
+#define SRST_EFUSE256		31
+
+#define SRST_GPIO0		32
+#define SRST_GPIO1		33
+#define SRST_GPIO2		34
+#define SRST_GPIO3		35
+#define SRST_PERIPH_NOC_A	36
+#define SRST_PERIPH_NOC_BUS_H	37
+#define SRST_PERIPH_NOC_P	38
+#define SRST_UART0		39
+#define SRST_UART1		40
+#define SRST_UART2		41
+#define SRST_PHYNOC		42
+#define SRST_I2C0		43
+#define SRST_I2C1		44
+#define SRST_I2C2		45
+#define SRST_I2C3		46
+
+#define SRST_PWM		48
+#define SRST_A53_GIC		49
+#define SRST_DAP		51
+#define SRST_DAP_NOC		52
+#define SRST_CRYPTO		53
+#define SRST_SGRF		54
+#define SRST_GRF		55
+#define SRST_GMAC		56
+#define SRST_PERIPH_NOC_H	58
+#define SRST_MACPHY		63
+
+#define SRST_DMA		64
+#define SRST_NANDC		68
+#define SRST_USBOTG		69
+#define SRST_OTGC		70
+#define SRST_USBHOST0		71
+#define SRST_HOST_CTRL0		72
+#define SRST_USBHOST1		73
+#define SRST_HOST_CTRL1		74
+#define SRST_USBHOST2		75
+#define SRST_HOST_CTRL2		76
+#define SRST_USBPOR0		77
+#define SRST_USBPOR1		78
+#define SRST_DDRMSCH		79
+
+#define SRST_SMART_CARD		80
+#define SRST_SDMMC		81
+#define SRST_SDIO		82
+#define SRST_EMMC		83
+#define SRST_SPI		84
+#define SRST_TSP_H		85
+#define SRST_TSP		86
+#define SRST_TSADC		87
+#define SRST_DDRPHY		88
+#define SRST_DDRPHY_P		89
+#define SRST_DDRCTRL		90
+#define SRST_DDRCTRL_P		91
+#define SRST_HOST0_ECHI		92
+#define SRST_HOST1_ECHI		93
+#define SRST_HOST2_ECHI		94
+#define SRST_VOP_NOC_A		95
+
+#define SRST_HDMI_P		96
+#define SRST_VIO_ARBI_H		97
+#define SRST_IEP_NOC_A		98
+#define SRST_VIO_NOC_H		99
+#define SRST_VOP_A		100
+#define SRST_VOP_H		101
+#define SRST_VOP_D		102
+#define SRST_UTMI0		103
+#define SRST_UTMI1		104
+#define SRST_UTMI2		105
+#define SRST_UTMI3		106
+#define SRST_RGA		107
+#define SRST_RGA_NOC_A		108
+#define SRST_RGA_A		109
+#define SRST_RGA_H		110
+#define SRST_HDCP_A		111
+
+#define SRST_VPU_A		112
+#define SRST_VPU_H		113
+#define SRST_VPU_NOC_A		116
+#define SRST_VPU_NOC_H		117
+#define SRST_RKVDEC_A		118
+#define SRST_RKVDEC_NOC_A	119
+#define SRST_RKVDEC_H		120
+#define SRST_RKVDEC_NOC_H	121
+#define SRST_RKVDEC_CORE	122
+#define SRST_RKVDEC_CABAC	123
+#define SRST_IEP_A		124
+#define SRST_IEP_H		125
+#define SRST_GPU_A		126
+#define SRST_GPU_NOC_A		127
+
+#define SRST_CORE_DBG		128
+#define SRST_DBG_P		129
+#define SRST_TIMER0		130
+#define SRST_TIMER1		131
+#define SRST_TIMER2		132
+#define SRST_TIMER3		133
+#define SRST_TIMER4		134
+#define SRST_TIMER5		135
+#define SRST_VIO_H2P		136
+#define SRST_HDMIPHY		139
+#define SRST_VDAC		140
+#define SRST_TIMER_6CH_P	141
+
+#endif
-- 
cgit 


From 168eef7ada98c6bff53458013e42cdbc5adb3cd4 Mon Sep 17 00:00:00 2001
From: Kever Yang <kever.yang@rock-chips.com>
Date: Fri, 23 Jun 2017 17:17:52 +0800
Subject: rockchip: rk322x: add basic soc support

Enable soc support for SPL and U-boot skeleton.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---
 include/configs/rk322x_common.h | 93 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 93 insertions(+)
 create mode 100644 include/configs/rk322x_common.h

(limited to 'include')

diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h
new file mode 100644
index 0000000000..56565b6ddb
--- /dev/null
+++ b/include/configs/rk322x_common.h
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#ifndef __CONFIG_RK322X_COMMON_H
+#define __CONFIG_RK322X_COMMON_H
+
+#include <asm/arch/hardware.h>
+#include "rockchip-common.h"
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_MALLOC_LEN		(32 << 20)
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/*  64M */
+
+#define CONFIG_SYS_TIMER_RATE		(24 * 1000 * 1000)
+#define CONFIG_SYS_TIMER_BASE		0x110c00a0 /* TIMER5 */
+#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
+
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_TEXT_BASE		0x60000000
+#define CONFIG_SYS_INIT_SP_ADDR		0x60100000
+#define CONFIG_SYS_LOAD_ADDR		0x60800800
+#define CONFIG_SPL_STACK		0x10088000
+#define CONFIG_SPL_TEXT_BASE		0x10081004
+
+#define CONFIG_ROCKCHIP_MAX_INIT_SIZE	(28 << 10)
+#define CONFIG_ROCKCHIP_CHIP_TAG	"RK32"
+
+/* MMC/SD IP block */
+#define CONFIG_BOUNCE_BUFFER
+
+#define CONFIG_SYS_SDRAM_BASE		0x60000000
+#define CONFIG_NR_DRAM_BANKS		2
+#define SDRAM_BANK_SIZE			(512UL << 20UL)
+#define SDRAM_MAX_SIZE			0x80000000
+
+#ifndef CONFIG_SPL_BUILD
+/* usb otg */
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_DWC2_OTG
+#define CONFIG_USB_GADGET_VBUS_DRAW	0
+
+/* fastboot  */
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_USB_FUNCTION_FASTBOOT
+#define CONFIG_FASTBOOT_FLASH
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV	0
+#define CONFIG_FASTBOOT_BUF_ADDR	CONFIG_SYS_LOAD_ADDR
+#define CONFIG_FASTBOOT_BUF_SIZE	0x08000000
+
+/* usb mass storage */
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+#define CONFIG_CMD_USB_MASS_STORAGE
+
+#define CONFIG_USB_GADGET_DOWNLOAD
+#define CONFIG_G_DNL_MANUFACTURER	"Rockchip"
+#define CONFIG_G_DNL_VENDOR_NUM		0x2207
+#define CONFIG_G_DNL_PRODUCT_NUM	0x320a
+
+/* usb host */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_ETHER_ASIX
+#endif
+#define ENV_MEM_LAYOUT_SETTINGS \
+	"scriptaddr=0x60000000\0" \
+	"pxefile_addr_r=0x60100000\0" \
+	"fdt_addr_r=0x61f00000\0" \
+	"kernel_addr_r=0x62000000\0" \
+	"ramdisk_addr_r=0x64000000\0"
+
+#include <config_distro_bootcmd.h>
+
+/* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board,
+ * so limit the fdt reallocation to that */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdt_high=0x7fffffff\0" \
+	"partitions=" PARTS_DEFAULT \
+	ENV_MEM_LAYOUT_SETTINGS \
+	BOOTENV
+#endif
+
+#define CONFIG_PREBOOT
+
+#endif
-- 
cgit 


From b24a8ec15c926337763871f95baa6b6b019c97b6 Mon Sep 17 00:00:00 2001
From: Kever Yang <kever.yang@rock-chips.com>
Date: Fri, 23 Jun 2017 17:17:54 +0800
Subject: rockchip: add evb_rk3229 board

evb_rk3229 is a RK3229 based board, with:
- 8GB eMMC;
- 1GB DDR SDRAM;
- 2 USB2.0 HOST port;
- 1 MAC port;
- 1 HDMI port;
- IR;
- WiFi;

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---
 include/configs/evb_rk3229.h | 60 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)
 create mode 100644 include/configs/evb_rk3229.h

(limited to 'include')

diff --git a/include/configs/evb_rk3229.h b/include/configs/evb_rk3229.h
new file mode 100644
index 0000000000..8f8e50fb60
--- /dev/null
+++ b/include/configs/evb_rk3229.h
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/rk322x_common.h>
+
+
+/* Store env in emmc */
+#undef CONFIG_ENV_SIZE
+#define CONFIG_ENV_SIZE                 (32 << 10)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV          0
+#define CONFIG_SYS_MMC_ENV_PART         0
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+#ifndef CONFIG_SPL_BUILD
+/* Enable gpt partition table */
+#undef PARTS_DEFAULT
+#define PARTS_DEFAULT \
+	"uuid_disk=${uuid_gpt_disk};" \
+	"name=loader_a,start=4M,size=4M,uuid=${uuid_gpt_loader};" \
+	"name=loader_b,size=4M,uuid=${uuid_gpt_reserved};" \
+	"name=trust_a,size=4M,uuid=${uuid_gpt_reserved};" \
+	"name=trust_b,size=4M,uuid=${uuid_gpt_reserved};" \
+	"name=misc,size=4M,uuid=${uuid_gpt_misc};" \
+	"name=metadata,size=16M,uuid=${uuid_gpt_metadata};" \
+	"name=boot_a,size=32M,uuid=${uuid_gpt_boot_a};" \
+	"name=boot_b,size=32M,uuid=${uuid_gpt_boot_b};" \
+	"name=system_a,size=818M,uuid=${uuid_gpt_system_a};" \
+	"name=system_b,size=818M,uuid=${uuid_gpt_system_b};" \
+	"name=vendor_a,size=50M,uuid=${uuid_gpt_vendor_a};" \
+	"name=vendor_b,size=50M,uuid=${uuid_gpt_vendor_b};" \
+	"name=cache,size=100M,uuid=${uuid_gpt_cache};" \
+	"name=persist,size=4M,uuid=${uuid_gpt_persist};" \
+	"name=userdata,size=-,uuid=${uuid_gpt_userdata};\0" \
+
+#define CONFIG_PREBOOT
+
+#define CONFIG_ANDROID_BOOT_IMAGE
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND \
+	"mmc read 0x61000000 0x8000 0x5000;" \
+	"bootm 0x61000000" \
+
+/* Enable atags */
+#define CONFIG_SYS_BOOTPARAMS_LEN	(64*1024)
+#define CONFIG_INITRD_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+
+#endif
+
+#endif
-- 
cgit 


From 4ac72f5c5b751ad27515655bfd5aebc2231eadf9 Mon Sep 17 00:00:00 2001
From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Date: Mon, 3 Jul 2017 18:30:06 +0200
Subject: usb: Kconfig: migrate USB_DWC2 to Kconfig

This change migrates the USB_DWC2 configuration item to Kconfig
and runs moveconfig to adjust header files and defconfig.

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Split off into a separate patch:
Ran moveconfig to migrate other boards:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---
 include/configs/hikey.h          | 1 -
 include/configs/rk3036_common.h  | 1 -
 include/configs/rk3188_common.h  | 1 -
 include/configs/rk322x_common.h  | 1 -
 include/configs/rk3288_common.h  | 1 -
 include/configs/rpi.h            | 1 -
 include/configs/socfpga_common.h | 3 ---
 7 files changed, 9 deletions(-)

(limited to 'include')

diff --git a/include/configs/hikey.h b/include/configs/hikey.h
index 2b4fec4bd4..c7fb8a5f8e 100644
--- a/include/configs/hikey.h
+++ b/include/configs/hikey.h
@@ -54,7 +54,6 @@
 #define CONFIG_PL01X_SERIAL
 
 #ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2
 #define CONFIG_USB_DWC2_REG_ADDR 0xF72C0000
 /*#define CONFIG_DWC2_DFLT_SPEED_FULL*/
 #define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index 1f6b5a1669..18b7dce94e 100644
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@@ -72,7 +72,6 @@
 
 /* usb host */
 #ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_SMSC95XX
 #define CONFIG_USB_ETHER_ASIX
diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h
index 7f57dd3141..3ee9abd38d 100644
--- a/include/configs/rk3188_common.h
+++ b/include/configs/rk3188_common.h
@@ -85,7 +85,6 @@
 
 /* usb host support */
 #ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_SMSC95XX
 #define CONFIG_USB_ETHER_ASIX
diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h
index 56565b6ddb..a145b7434a 100644
--- a/include/configs/rk322x_common.h
+++ b/include/configs/rk322x_common.h
@@ -65,7 +65,6 @@
 
 /* usb host */
 #ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_SMSC95XX
 #define CONFIG_USB_ETHER_ASIX
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 7d6ef41368..488d67924a 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -81,7 +81,6 @@
 
 /* usb host support */
 #ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_SMSC95XX
 #define CONFIG_USB_ETHER_ASIX
diff --git a/include/configs/rpi.h b/include/configs/rpi.h
index d715eaad14..b31e2acce6 100644
--- a/include/configs/rpi.h
+++ b/include/configs/rpi.h
@@ -71,7 +71,6 @@
 #define CONFIG_VIDEO_BCM2835
 
 #ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_SMSC95XX
 #define CONFIG_TFTP_TSIZE
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index c17814bf01..1bed85e78b 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -224,9 +224,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 /*
  * USB
  */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2
-#endif
 
 /*
  * USB Gadget (DFU, UMS)
-- 
cgit 


From ad98f882e86d3b7231b8c02bbdf8f7eee735aee6 Mon Sep 17 00:00:00 2001
From: Wadim Egorov <w.egorov@phytec.de>
Date: Mon, 19 Jun 2017 12:36:39 +0200
Subject: power: regulator: rk8xx: Allow input current/charger shutdown
 configuration

The RK818 PMIC contains a charger. Add very basic charger functionality
to be able to regulate the USB input current and charger shutdown limits.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---
 include/power/rk8xx_pmic.h | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'include')

diff --git a/include/power/rk8xx_pmic.h b/include/power/rk8xx_pmic.h
index 589f8c4e1a..47a6b36e7e 100644
--- a/include/power/rk8xx_pmic.h
+++ b/include/power/rk8xx_pmic.h
@@ -189,5 +189,7 @@ struct rk8xx_priv {
 };
 
 int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt);
+int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma);
+int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt);
 
 #endif
-- 
cgit 


From bafcf2db4176940953a96339025d7b06e96cb22e Mon Sep 17 00:00:00 2001
From: Wadim Egorov <w.egorov@phytec.de>
Date: Mon, 19 Jun 2017 12:36:40 +0200
Subject: rockchip: Add basic support for phyCORE-RK3288 SoM based carrier
 board

The phyCORE-RK3288 is a SoM (System on Module) containing a RK3288 SoC.
The module can be connected to different carrier boards.
It can be also equipped with different RAM, SPI flash and eMMC variants.
The Rapid Development Kit option is using the following setup:

  - 1 GB DDR3 RAM (2 Banks)
  - 1x 4 KB EEPROM
  - DP83867 Gigabit Ethernet PHY
  - 16 MB SPI Flash
  - 4 GB eMMC Flash

Add basic support for the PCM-947 carrier board, a RK3288 based development
board made by PHYTEC. This board works in a combination with
the phyCORE-RK3288 System on Module.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---
 include/configs/phycore_rk3288.h | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 include/configs/phycore_rk3288.h

(limited to 'include')

diff --git a/include/configs/phycore_rk3288.h b/include/configs/phycore_rk3288.h
new file mode 100644
index 0000000000..aab43ed594
--- /dev/null
+++ b/include/configs/phycore_rk3288.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2017 PHYTEC Messtechnik GmbH
+ * Author: Wadim Egorov <w.egorov@phytec.de>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS
+#include <configs/rk3288_common.h>
+
+#undef BOOT_TARGET_DEVICES
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(MMC, mmc, 1)
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 1
+
+#endif
-- 
cgit