From d24bd2517a2b847f773453eab0ee5b1c8ebc74ba Mon Sep 17 00:00:00 2001 From: Felix Radensky Date: Sun, 27 Sep 2009 23:56:12 +0200 Subject: ppc4xx: Reorganize DDR2 ECC handling Reorganize DDR2 ECC handling to use common code for SPD DIMMs and soldered SDRAM. Also, use common code to display SDRAM info (ECC, CAS latency) for SPD and soldered SDRAM variants. Signed-off-by: Felix Radensky Signed-off-by: Stefan Roese --- include/ppc405.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/ppc405.h b/include/ppc405.h index 5e56897819..8a4ba3faf6 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -768,6 +768,10 @@ #define SDR0_SDCS_SDD (0x80000000 >> 31) +/* SDR0_SDSTP0 Serial Device Strap Register0 */ +#define SDR0_SDSTP0 0x0020 +#define SDR0_SDSTP0_PLB2xDV0_DECODE(n) ((((unsigned long)(n)) & 0x07)) + /* CUST0 Customer Configuration Register0 */ #define SDR0_CUST0 0x4000 #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ -- cgit