From efaf6f1bf6ebdd8f16b0d0c2960abe8d06f95af4 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 2 Oct 2009 18:54:20 -0400 Subject: mpc83xx: cosmetic comment update relating to SPD EEPROM commit 6d0f6bcf337c5261c08fabe12982178c2c489d76 did the big rename of CFG_ macros to CONFIG_SYS macros. But it missed a couple of instances within comments. Signed-off-by: Paul Gortmaker Signed-off-by: Kim Phillips --- include/configs/sbc8349.h | 2 +- include/configs/vme8349.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index bf7cf82d8e..4dea27d483 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -304,7 +304,7 @@ #define CONFIG_SYS_I2C1_OFFSET 0x3000 #define CONFIG_SYS_I2C2_OFFSET 0x3100 #define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C2_OFFSET -/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */ +/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ /* TSEC */ #define CONFIG_SYS_TSEC1_OFFSET 0x24000 diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index d0690feb17..f9db73b2dc 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -224,7 +224,7 @@ #define CONFIG_SYS_I2C1_OFFSET 0x3000 #define CONFIG_SYS_I2C2_OFFSET 0x3100 #define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C1_OFFSET -/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */ +/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */ -- cgit From 370ec734557d0b0f266e6d0953229ee12cae5edd Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 9 Oct 2009 02:22:11 -0400 Subject: Blackfin: Remove relocation fixups Blackfin pieces like commit 0630535e2d062dd73c1ceca5c6125c86d1127a49. Signed-off-by: Mike Frysinger --- include/asm-blackfin/config.h | 3 +++ include/asm-blackfin/global_data.h | 1 - 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-blackfin/config.h b/include/asm-blackfin/config.h index 25794dd4bf..327843d0b6 100644 --- a/include/asm-blackfin/config.h +++ b/include/asm-blackfin/config.h @@ -18,6 +18,9 @@ # define CONFIG_BFIN_SCRATCH_REG retn #endif +/* Relocation to SDRAM works on all Blackfin boards */ +#define CONFIG_RELOC_FIXUP_WORKS + /* Make sure the structure is properly aligned */ #if ((CONFIG_SYS_GBL_DATA_ADDR & -4) != CONFIG_SYS_GBL_DATA_ADDR) # error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned diff --git a/include/asm-blackfin/global_data.h b/include/asm-blackfin/global_data.h index 3194b72a53..b78b04cd6b 100644 --- a/include/asm-blackfin/global_data.h +++ b/include/asm-blackfin/global_data.h @@ -44,7 +44,6 @@ typedef struct global_data { unsigned long baudrate; unsigned long have_console; /* serial_init() was called */ phys_size_t ram_size; /* RAM size */ - unsigned long reloc_off; /* Relocation Offset */ unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid? */ #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) -- cgit From f7780ec977e545b83bc5068e0957d640f1d98f13 Mon Sep 17 00:00:00 2001 From: Dipen Dudhat Date: Thu, 8 Oct 2009 13:33:18 +0530 Subject: ppc/P1_P2_RDB: NAND Boot Support NAND Boot support for P1 and P2 series RDB platforms. This patch is derived from NAND Boot support on MPC8536DS. Signed-off-by: Dipen Dudhat Signed-off-by: Kumar Gala --- include/configs/P1_P2_RDB.h | 72 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 65 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 8e97ad0681..aacd4ca852 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -43,6 +43,12 @@ #define CONFIG_P2020 #endif +#ifdef CONFIG_MK_NAND +#define CONFIG_NAND_U_BOOT 1 +#define CONFIG_RAMBOOT_NAND 1 +#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000 +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ @@ -82,16 +88,34 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_MEMTEST_END 0x1fffffff #define CONFIG_PANIC_HANG /* do not reset board on panic */ + /* + * Config the L2 Cache as L2 SRAM + */ +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull +#else +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#endif +#define CONFIG_SYS_L2_SIZE (512 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) + /* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of */ /* CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ /* CONFIG_SYS_IMMR */ + +#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) +#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR +#else +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#endif + #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) @@ -158,6 +182,12 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_EMPTY_INFO @@ -177,7 +207,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ +#ifndef CONFIG_NAND_SPL #define CONFIG_SYS_NAND_BASE 0xffa00000 +#else +#define CONFIG_SYS_NAND_BASE 0xfff00000 +#endif #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -187,6 +221,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) +/* NAND boot: 4K NAND loader config */ +#define CONFIG_SYS_NAND_SPL_SIZE 0x1000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) +#define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) +#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) + /* NAND flash config */ #define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ | (2< 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 +#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_RAMBOOT_NAND) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE + #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#endif #else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) + #define CONFIG_ENV_IS_IN_FLASH 1 + #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 + #define CONFIG_ENV_ADDR 0xfff80000 + #else + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) + #endif + #define CONFIG_ENV_SIZE 0x2000 + #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -- cgit From fad15096e3b34927444ba5f6133742d40d78a425 Mon Sep 17 00:00:00 2001 From: Dipen Dudhat Date: Thu, 8 Oct 2009 13:33:29 +0530 Subject: ppc/P1_P2_RDB: On-chip BootROM support On Chip BootROM support for P1 and P2 series RDB platforms. This patch is derived from latest On Chip BootROM support on MPC8536DS Signed-off-by: Dipen Dudhat Signed-off-by: Kumar Gala --- include/configs/P1_P2_RDB.h | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index aacd4ca852..310242e0bd 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -49,6 +49,16 @@ #define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000 #endif +#ifdef CONFIG_MK_SDCARD +#define CONFIG_RAMBOOT_SDCARD 1 +#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000 +#endif + +#ifdef CONFIG_MK_SPIFLASH +#define CONFIG_RAMBOOT_SPIFLASH 1 +#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000 +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ @@ -182,7 +192,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ -#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) +#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \ + || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) #define CONFIG_SYS_RAMBOOT #else #undef CONFIG_SYS_RAMBOOT @@ -426,6 +437,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) + #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) + #define CONFIG_ENV_SIZE 0x2000 #endif #else #define CONFIG_ENV_IS_IN_FLASH 1 -- cgit From 26df6aa9916443077139f8f008fbc5f414ba05e5 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 2 Oct 2009 18:48:07 -0400 Subject: mpc86xx: delete unused MPC86xx_DDR_SDRAM_CLK_CNTL define This is an orphaned legacy leftover that is just polluting the config file namespace. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- include/configs/MPC8610HPCD.h | 2 -- include/configs/MPC8641HPCN.h | 2 -- include/configs/sbc8641d.h | 2 -- 3 files changed, 6 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 761932800e..7cb4ccdc19 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -102,8 +102,6 @@ #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ #define CONFIG_VERY_BIG_RAM -#define MPC86xx_DDR_SDRAM_CLK_CNTL - #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index b0ae25c224..a46f7c8bdd 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -141,8 +141,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ #define CONFIG_VERY_BIG_RAM -#define MPC86xx_DDR_SDRAM_CLK_CNTL - #define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 2865df55e9..682d241d3b 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -121,8 +121,6 @@ #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ #define CONFIG_VERY_BIG_RAM -#define MPC86xx_DDR_SDRAM_CLK_CNTL - #define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) -- cgit From 45def0ab9d1dedcd2a73939aad8373f760498762 Mon Sep 17 00:00:00 2001 From: Eric Millbrandt Date: Fri, 25 Sep 2009 17:47:43 -0500 Subject: galaxy5200: change cs1 configuration Correct the chip select configuration for the nand flash chip select. Signed-off-by: Eric Millbrandt --- include/configs/galaxy5200.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h index 3b67ea90bc..931acfbc77 100644 --- a/include/configs/galaxy5200.h +++ b/include/configs/galaxy5200.h @@ -210,7 +210,7 @@ /* Chip Select configuration for NAND flash */ #define CONFIG_SYS_CS1_START 0x20000000 #define CONFIG_SYS_CS1_SIZE 0x90000 -#define CONFIG_SYS_CS1_CFG 0x0002d900 +#define CONFIG_SYS_CS1_CFG 0x00025b00 /* Chip Select configuration for Epson S1D13513 */ #define CONFIG_SYS_CS3_START 0x10000000 -- cgit From 6dab6add2d8ee80905234b326abc3de11be1d178 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 30 Sep 2009 15:29:58 -0400 Subject: env: only build env_embedded and envcrc when needed The env code is protected by the ENV_IS_EMBEDDED define, so attempting to compile the code when this isn't defined is pointless. Now that the env headers have unified around CONFIG_ENV_IS_EMBEDDED, convert the build system to only build the env objects when this is enabled. And now that the env code is conditionally compiled, we can drop the source code checks. For people who want to extract the environment manually, add a new option CONFIG_BUILD_ENVCRC that only enables the envcrc utility. Signed-off-by: Mike Frysinger --- include/common.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/common.h b/include/common.h index f7c93bf5a6..7df9afab2b 100644 --- a/include/common.h +++ b/include/common.h @@ -719,4 +719,9 @@ int cpu_release(int nr, int argc, char *argv[]); #define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) +/* Pull in stuff for the build system */ +#ifdef DO_DEPS_ONLY +# include +#endif + #endif /* __COMMON_H_ */ -- cgit From c9ee39972a7758e883b73c6c0e3c3a14cd5b2f43 Mon Sep 17 00:00:00 2001 From: Martha Stan Date: Wed, 7 Oct 2009 04:38:46 -0400 Subject: mpc512x: fix System Clock Control constants for USB1 & USB2 Signer-off-by: Martha Stan --- include/asm-ppc/immap_512x.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h index bdc6ff2845..95350fd9b8 100644 --- a/include/asm-ppc/immap_512x.h +++ b/include/asm-ppc/immap_512x.h @@ -215,8 +215,8 @@ typedef struct clk512x { #define CLOCK_SCCR2_DIU_EN 0x80000000 #define CLOCK_SCCR2_AXE_EN 0x40000000 #define CLOCK_SCCR2_MEM_EN 0x20000000 -#define CLOCK_SCCR2_USB2_EN 0x10000000 -#define CLOCK_SCCR2_USB1_EN 0x08000000 +#define CLOCK_SCCR2_USB1_EN 0x10000000 +#define CLOCK_SCCR2_USB2_EN 0x08000000 #define CLOCK_SCCR2_I2C_EN 0x04000000 #define CLOCK_SCCR2_BDLC_EN 0x02000000 #define CLOCK_SCCR2_SDHC_EN 0x01000000 -- cgit From efd988ebaa241bab265b1511052350207cb7aaa0 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 19 Oct 2009 09:18:57 +0200 Subject: mcc200: fix build error Fix compile error: include/configs/mcc200.h:401:6: error: #elif with no expression Signed-off-by: Wolfgang Denk --- include/configs/mcc200.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index e5812ee8a2..7ef6385ef8 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -398,7 +398,7 @@ #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5) #elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9) #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5) -#elif +#else #error "Wrong QUART expander number." #endif -- cgit From 30d45c0d3ea2231f9131276ea113595959a0720e Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 21 Oct 2009 11:59:52 +0200 Subject: fdt: Add fdt_fixup_nor_flash_size() to fixup NOR FLASH size in dtb This function can be used to update the size in the "reg" property of the NOR FLASH device nodes. This is necessary for boards with non-fixed NOR FLASH sizes. Signed-off-by: Stefan Roese Acked-by: Gerald Van Baren Acked-by: Wolfgang Denk --- include/fdt_support.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/fdt_support.h b/include/fdt_support.h index 16734c5352..0a9dd0dd84 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -79,5 +79,7 @@ void ft_pci_setup(void *blob, bd_t *bd); void set_working_fdt_addr(void *addr); int fdt_resize(void *blob); +int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size); + #endif /* ifdef CONFIG_OF_LIBFDT */ #endif /* ifndef __FDT_SUPPORT_H */ -- cgit From 92b8964bed0d1b779d9e26be4e16755b5c635415 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 16 Oct 2009 10:01:09 +0200 Subject: ppc4xx: Update flash size in reg property of the NOR flash node Till now only the ranges in the ebc node are updated with the values currently configured in the PPC4xx EBC controller. With this patch now the NOR flash size is updated in the device tree blob as well. This is done by scanning the compatible nodes "cfi-flash" and "jedec-flash" for the correct chip select number. This size fixup is enabled for all AMCC eval board right now. Other 4xx boards may want to enable it as well, if this problem with multiple NOR FLASH sizes exists. Signed-off-by: Stefan Roese Cc: Wolfgang Denk --- include/configs/amcc-common.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index 51128a3b56..8cd97b86da 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -156,6 +156,8 @@ */ #define CONFIG_OF_LIBFDT #define CONFIG_OF_BOARD_SETUP +/* Update size in "reg" property of NOR FLASH device tree nodes */ +#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE /* * Booting and default environment -- cgit From 5e47f9535f53fd4cc05f32fb6166870f976fbb4e Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 19 Oct 2009 14:06:23 +0200 Subject: ppc4xx: Add function to check and dynamically change PCI sync clock PPC440EP(x)/PPC440GR(x): In asynchronous PCI mode, the synchronous PCI clock must meet certain requirements. The following equation describes the relationship that must be maintained between the asynchronous PCI clock and synchronous PCI clock. Select an appropriate PCI:PLB ratio to maintain the relationship: AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz This patch now adds a function to check and reconfigure the sync PCI clock to meet this requirement. This is in preparation for some AMCC boards (Sequoia/Rainier and Yosemite/Yellowstone) using this function to not violate the PCI clocking rules. Signed-off-by: Stefan Roese --- include/ppc440.h | 7 ++++++- include/ppc4xx.h | 2 ++ 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/ppc440.h b/include/ppc440.h index fe0db93b51..e54a977dc1 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -1701,9 +1701,14 @@ #define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ #endif /* CONFIG_440GX */ -#if defined (CONFIG_440EPX) || defined (CONFIG_440GRX) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define CPR0_ICFG_RLI_MASK 0x80000000 #define CPR0_SPCID_SPCIDV0_MASK 0x03000000 +#define CPR0_SPCID_SPCIDV0_DIV1 0x01000000 +#define CPR0_SPCID_SPCIDV0_DIV2 0x02000000 +#define CPR0_SPCID_SPCIDV0_DIV3 0x03000000 +#define CPR0_SPCID_SPCIDV0_DIV4 0x00000000 #define CPR0_PERD_PERDV0_MASK 0x07000000 #endif diff --git a/include/ppc4xx.h b/include/ppc4xx.h index 3bff00a559..5024db447f 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -221,6 +221,8 @@ static inline void set_mcsr(u32 val) asm volatile("mtspr 0x23c, %0" : "=r" (val) :); } +int ppc4xx_pci_sync_clock_config(u32 async); + #endif /* __ASSEMBLY__ */ /* for multi-cpu support */ -- cgit From cfc25874624a328f53ad59b1206e2103f2e62d74 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 19 Oct 2009 16:19:36 +0200 Subject: ppc4xx: Sequoia: Add chip_config command This patch removes the Sequoia "bootstrap" command and replaces it with the now common command "chip_config". Please note that the patches with the dynamic PCI sync clock configuration have to be applied, before this one should go in. This is because Sequoia has 2 different bootstrap EEPROMs, and the old bootstrap command configured different values depending on the detected PCI async clock (33 vs. 66MHz). With the PCI sync clock patches, this is not necessary anymore. The PCI sync clock will be configured correctly on-the-fly now. Signed-off-by: Stefan Roese --- include/configs/sequoia.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 89acacc7f6..9605ce25ba 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -243,6 +243,11 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 +/* I2C bootstrap EEPROM */ +#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52 +#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 +#define CONFIG_4xx_CONFIG_BLOCKSIZE 16 + /* I2C SYSMON (LM75, AD7414 is almost compatible) */ #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ #define CONFIG_DTT_AD7414 1 /* use AD7414 */ @@ -300,6 +305,7 @@ /* * Commands additional to the ones defined in amcc-common.h */ +#define CONFIG_CMD_CHIP_CONFIG #define CONFIG_CMD_DTT #define CONFIG_CMD_FAT #define CONFIG_CMD_NAND -- cgit From 70ed869ea5f6b1d13d7b140c83ec0dcd8a127ddc Mon Sep 17 00:00:00 2001 From: Vivek Mahajan Date: Tue, 27 Oct 2009 12:18:55 +0530 Subject: ppc/85xx/pci: fsl_pci_init: pcie agent mode support Originally written by Jason Jin and Mingkai Hu for mpc8536. When QorIQ based board is configured as a PCIe agent, then unlock/enable inbound PCI configuration cycles and init a 4K inbound memory window; so that a PCIe host can access the PCIe agents SDRAM at address 0x0 * Supported in fsl_pci_init_port() after adding pcie_ep as a param * Revamped copyright in drivers/pci/fsl_pci_init.c * Mods in 85xx based board specific pci init after this change Signed-off-by: Vivek Mahajan Signed-off-by: Kumar Gala --- include/asm-ppc/fsl_pci.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-ppc/fsl_pci.h b/include/asm-ppc/fsl_pci.h index 2790da7ed1..6b0c89bd3f 100644 --- a/include/asm-ppc/fsl_pci.h +++ b/include/asm-ppc/fsl_pci.h @@ -62,6 +62,7 @@ typedef struct pci_inbound_window { #define PIWAR_LOCAL 0x00f00000 #define PIWAR_READ_SNOOP 0x00050000 #define PIWAR_WRITE_SNOOP 0x00005000 +#define PIWAR_IWS_4K 0x0000000b u32 res2[3]; } pit_t; @@ -171,7 +172,7 @@ struct fsl_pci_info { }; int fsl_pci_init_port(struct fsl_pci_info *pci_info, - struct pci_controller *hose, int busno); + struct pci_controller *hose, int busno, int pcie_ep); #define SET_STD_PCI_INFO(x, num) \ { \ -- cgit From 5ccd29c3679b3669b0bde5c501c1aa0f325a7acb Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Fri, 23 Oct 2009 15:55:47 -0500 Subject: 85xx: MP Boot Page Translation update This change has 3 goals: - Have secondary cores be released into spin loops at their 'true' address in SDRAM. Previously, secondary cores were put into spin loops in the 0xfffffxxx address range which required that boot page translation was always enabled while cores were in their spin loops. - Allow the TLB window that the primary core uses to access the secondary cores boot page to be placed at any address. Previously, a TLB window at 0xfffff000 was always used to access the seconary cores' boot page. This TLB address requirement overlapped with other peripherals on some boards (eg XPedite5370). By default, the boot page TLB will still use the 0xfffffxxx address range, but this can be overridden on a board-by-board basis by defining a custom CONFIG_BPTR_VIRT_ADDR. Note that the TLB used to map the boot page remains in use while U-Boot executes. Previously it was only temporarily used, then restored to its initial value. - Allow Boot Page Translation to be disabled on bootup. Previously, Boot Page Translation was always left enabled after secondary cores were brought out of reset. This caused the 0xfffffxxx address range to somewhat "magically" be translated to an address in SDRAM. Some boards may not want this oddity in their memory map, so defining CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after the secondary cores are initialized. These changes are only applicable to 85xx boards with CONFIG_MP defined. Signed-off-by: Peter Tyser Signed-off-by: Kumar Gala --- include/asm-ppc/config.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include') diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h index eba79010b1..af0853b0d7 100644 --- a/include/asm-ppc/config.h +++ b/include/asm-ppc/config.h @@ -47,6 +47,16 @@ #define CONFIG_MAX_CPUS 1 #endif +/* + * Provide a default boot page translation virtual address that lines up with + * Freescale's default e500 reset page. + */ +#if (defined(CONFIG_E500) && defined(CONFIG_MP)) +#ifndef CONFIG_BPTR_VIRT_ADDR +#define CONFIG_BPTR_VIRT_ADDR 0xfffff000 +#endif +#endif + /* Relocation to SDRAM works on all PPC boards */ #define CONFIG_RELOC_FIXUP_WORKS -- cgit From 48618126f78f05042dae428811809b594f747eb9 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Fri, 23 Oct 2009 15:55:48 -0500 Subject: xpedite5370: Enable multi-core support Signed-off-by: Peter Tyser Signed-off-by: Kumar Gala --- include/configs/XPEDITE5370.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include') diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h index 26b798b4d8..7782df3678 100644 --- a/include/configs/XPEDITE5370.h +++ b/include/configs/XPEDITE5370.h @@ -48,6 +48,13 @@ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +/* + * Multicore config + */ +#define CONFIG_MP +#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */ +#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */ + /* * DDR config */ @@ -109,6 +116,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable + * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable -- cgit From 7f52ed5ef1b490da282ace3316be381a6abf96a5 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Thu, 15 Oct 2009 17:47:06 +0400 Subject: mpc85xx: Add eSDHC support for MPC8569E-MDS boards eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2 (in 1-bit mode). When eSDHC is used, we should switch u-boot console to UART1, and make the proper device-tree fixups. Because of an erratum in prototype boards it is impossible to use eSDHC without disabling UART0 (which makes it quite easy to 'brick' the board by simply issung 'setenv hwconfig esdhc', and not able to interact with U-Boot anylonger). So, but default we assume that the board is a prototype, which is a most safe assumption. There is no way to determine board revision from a register, so we use hwconfig. Signed-off-by: Anton Vorontsov Signed-off-by: Kumar Gala --- include/configs/MPC8569MDS.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'include') diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 32e747efb3..3d07a5b5dc 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -70,6 +70,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_ENABLE_36BIT_PHYS 1 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_HWCONFIG #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 @@ -206,6 +207,7 @@ extern unsigned long get_clock_freq(void); /* Serial Port */ #define CONFIG_CONS_INDEX 1 +#define CONFIG_SERIAL_MULTI 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL @@ -258,8 +260,10 @@ extern unsigned long get_clock_freq(void); #define PLPPAR1_I2C_BIT_MASK 0x0000000F #define PLPPAR1_I2C2_VAL 0x00000000 +#define PLPPAR1_ESDHC_VAL 0x0000000A #define PLPDIR1_I2C_BIT_MASK 0x0000000F #define PLPDIR1_I2C2_VAL 0x0000000F +#define PLPDIR1_ESDHC_VAL 0x00000006 /* * General PCI @@ -450,6 +454,18 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_MMC 1 + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + /* * Miscellaneous configurable options */ -- cgit From a29155e12286cc5ec2df72c1cab28e3659bfdad5 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Thu, 15 Oct 2009 17:47:08 +0400 Subject: mpc85xx: Add eLBC NAND support for MPC8569E-MDS boards Simply add some defines, and adjust TLBe setup to include some space for eLBC NAND. Signed-off-by: Anton Vorontsov Signed-off-by: Kumar Gala --- include/configs/MPC8569MDS.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'include') diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 3d07a5b5dc..17ea3bb14e 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -181,6 +181,29 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_EMPTY_INFO +/* Chip select 3 - NAND */ +#define CONFIG_SYS_NAND_BASE 0xFC000000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE 1 +#define CONFIG_CMD_NAND 1 +#define CONFIG_NAND_FSL_ELBC 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ + | (2< Date: Tue, 27 Oct 2009 00:03:32 +0100 Subject: Revert "env: only build env_embedded and envcrc when needed" Breaks building on many boards, and no really clean fix available yet. This reverts commit 6dab6add2d8ee80905234b326abc3de11be1d178. --- include/common.h | 5 ----- 1 file changed, 5 deletions(-) (limited to 'include') diff --git a/include/common.h b/include/common.h index 7df9afab2b..f7c93bf5a6 100644 --- a/include/common.h +++ b/include/common.h @@ -719,9 +719,4 @@ int cpu_release(int nr, int argc, char *argv[]); #define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) -/* Pull in stuff for the build system */ -#ifdef DO_DEPS_ONLY -# include -#endif - #endif /* __COMMON_H_ */ -- cgit From 246c69225c7b962d5c93e92282b78ca9fc5fefee Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Sun, 25 Oct 2009 15:12:56 -0500 Subject: Add 'editenv' command The editenv command can be used to edit an environment variable. Editing an environment variable is useful when one wants to tweak an existing variable, for example fix a typo or change the baudrate in the 'bootargs' environment variable. Signed-off-by: Peter Tyser --- include/config_cmd_all.h | 1 + include/config_cmd_default.h | 1 + 2 files changed, 2 insertions(+) (limited to 'include') diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index c747b4baa1..058fdf14fa 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -30,6 +30,7 @@ #define CONFIG_CMD_DOC /* Disk-On-Chip Support */ #define CONFIG_CMD_DTT /* Digital Therm and Thermostat */ #define CONFIG_CMD_ECHO /* echo arguments */ +#define CONFIG_CMD_EDITENV /* editenv */ #define CONFIG_CMD_EEPROM /* EEPROM read/write support */ #define CONFIG_CMD_ELF /* ELF (VxWorks) load/boot cmd */ #define CONFIG_CMD_SAVEENV /* saveenv */ diff --git a/include/config_cmd_default.h b/include/config_cmd_default.h index a5d87a68e8..6e3903c4d4 100644 --- a/include/config_cmd_default.h +++ b/include/config_cmd_default.h @@ -20,6 +20,7 @@ #define CONFIG_CMD_BOOTD /* bootd */ #define CONFIG_CMD_CONSOLE /* coninfo */ #define CONFIG_CMD_ECHO /* echo arguments */ +#define CONFIG_CMD_EDITENV /* editenv */ #define CONFIG_CMD_FPGA /* FPGA configuration Support */ #define CONFIG_CMD_IMI /* iminfo */ #define CONFIG_CMD_ITEST /* Integer (and string) test */ -- cgit From 4946775c6db52dba28f72ba3525764b54f1d4593 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 28 Oct 2009 00:49:47 +0100 Subject: Coding Style cleanup; update CHANGELOG, prepare -rc1 Signed-off-by: Wolfgang Denk --- include/asm-arm/arch-davinci/gpio_defs.h | 1 - include/configs/P1_P2_RDB.h | 1 - include/configs/davinci_dm6467evm.h | 1 - 3 files changed, 3 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-davinci/gpio_defs.h b/include/asm-arm/arch-davinci/gpio_defs.h index ec43969f5f..ff629761b5 100644 --- a/include/asm-arm/arch-davinci/gpio_defs.h +++ b/include/asm-arm/arch-davinci/gpio_defs.h @@ -50,4 +50,3 @@ struct davinci_gpio_bank { }; #endif - diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 310242e0bd..e2930c19b3 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -282,7 +282,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -//#define CONFIG_CONS_INDEX 2 #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h index 2a4cb79f88..6617941d8c 100644 --- a/include/configs/davinci_dm6467evm.h +++ b/include/configs/davinci_dm6467evm.h @@ -129,4 +129,3 @@ #endif #endif /* __CONFIG_H */ - -- cgit From fa36ae790eb10ce70935f9a78f07703719dca422 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 27 Oct 2009 15:15:55 +0100 Subject: cfi: Add weak default function for flash_cmd_reset() Currently the CFI driver issues both AMD and Intel reset commands. This is because the driver doesn't know yet which chips are connected. This dual reset seems to cause problems with the M29W128G chips as reported by Richard Retanubun. This patch now introduces a weak default function for the CFI reset command, still with both resets. This can be overridden by a board specific version if necessary. Signed-off-by: Stefan Roese Cc: Richard Retanubun --- include/mtd/cfi_flash.h | 157 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 157 insertions(+) create mode 100644 include/mtd/cfi_flash.h (limited to 'include') diff --git a/include/mtd/cfi_flash.h b/include/mtd/cfi_flash.h new file mode 100644 index 0000000000..2aa6911237 --- /dev/null +++ b/include/mtd/cfi_flash.h @@ -0,0 +1,157 @@ +/* + * (C) Copyright 2009 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __CFI_FLASH_H__ +#define __CFI_FLASH_H__ + +#define FLASH_CMD_CFI 0x98 +#define FLASH_CMD_READ_ID 0x90 +#define FLASH_CMD_RESET 0xff +#define FLASH_CMD_BLOCK_ERASE 0x20 +#define FLASH_CMD_ERASE_CONFIRM 0xD0 +#define FLASH_CMD_WRITE 0x40 +#define FLASH_CMD_PROTECT 0x60 +#define FLASH_CMD_PROTECT_SET 0x01 +#define FLASH_CMD_PROTECT_CLEAR 0xD0 +#define FLASH_CMD_CLEAR_STATUS 0x50 +#define FLASH_CMD_READ_STATUS 0x70 +#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 +#define FLASH_CMD_WRITE_BUFFER_PROG 0xE9 +#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 + +#define FLASH_STATUS_DONE 0x80 +#define FLASH_STATUS_ESS 0x40 +#define FLASH_STATUS_ECLBS 0x20 +#define FLASH_STATUS_PSLBS 0x10 +#define FLASH_STATUS_VPENS 0x08 +#define FLASH_STATUS_PSS 0x04 +#define FLASH_STATUS_DPS 0x02 +#define FLASH_STATUS_R 0x01 +#define FLASH_STATUS_PROTECT 0x01 + +#define AMD_CMD_RESET 0xF0 +#define AMD_CMD_WRITE 0xA0 +#define AMD_CMD_ERASE_START 0x80 +#define AMD_CMD_ERASE_SECTOR 0x30 +#define AMD_CMD_UNLOCK_START 0xAA +#define AMD_CMD_UNLOCK_ACK 0x55 +#define AMD_CMD_WRITE_TO_BUFFER 0x25 +#define AMD_CMD_WRITE_BUFFER_CONFIRM 0x29 + +#define AMD_STATUS_TOGGLE 0x40 +#define AMD_STATUS_ERROR 0x20 + +#define ATM_CMD_UNLOCK_SECT 0x70 +#define ATM_CMD_SOFTLOCK_START 0x80 +#define ATM_CMD_LOCK_SECT 0x40 + +#define FLASH_CONTINUATION_CODE 0x7F + +#define FLASH_OFFSET_MANUFACTURER_ID 0x00 +#define FLASH_OFFSET_DEVICE_ID 0x01 +#define FLASH_OFFSET_DEVICE_ID2 0x0E +#define FLASH_OFFSET_DEVICE_ID3 0x0F +#define FLASH_OFFSET_CFI 0x55 +#define FLASH_OFFSET_CFI_ALT 0x555 +#define FLASH_OFFSET_CFI_RESP 0x10 +#define FLASH_OFFSET_PRIMARY_VENDOR 0x13 +/* extended query table primary address */ +#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15 +#define FLASH_OFFSET_WTOUT 0x1F +#define FLASH_OFFSET_WBTOUT 0x20 +#define FLASH_OFFSET_ETOUT 0x21 +#define FLASH_OFFSET_CETOUT 0x22 +#define FLASH_OFFSET_WMAX_TOUT 0x23 +#define FLASH_OFFSET_WBMAX_TOUT 0x24 +#define FLASH_OFFSET_EMAX_TOUT 0x25 +#define FLASH_OFFSET_CEMAX_TOUT 0x26 +#define FLASH_OFFSET_SIZE 0x27 +#define FLASH_OFFSET_INTERFACE 0x28 +#define FLASH_OFFSET_BUFFER_SIZE 0x2A +#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C +#define FLASH_OFFSET_ERASE_REGIONS 0x2D +#define FLASH_OFFSET_PROTECT 0x02 +#define FLASH_OFFSET_USER_PROTECTION 0x85 +#define FLASH_OFFSET_INTEL_PROTECTION 0x81 + +#define CFI_CMDSET_NONE 0 +#define CFI_CMDSET_INTEL_EXTENDED 1 +#define CFI_CMDSET_AMD_STANDARD 2 +#define CFI_CMDSET_INTEL_STANDARD 3 +#define CFI_CMDSET_AMD_EXTENDED 4 +#define CFI_CMDSET_MITSU_STANDARD 256 +#define CFI_CMDSET_MITSU_EXTENDED 257 +#define CFI_CMDSET_SST 258 +#define CFI_CMDSET_INTEL_PROG_REGIONS 512 + +#ifdef CONFIG_SYS_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */ +# undef FLASH_CMD_RESET +# define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */ +#endif + +#define NUM_ERASE_REGIONS 4 /* max. number of erase regions */ + +typedef union { + unsigned char c; + unsigned short w; + unsigned long l; + unsigned long long ll; +} cfiword_t; + +/* CFI standard query structure */ +struct cfi_qry { + u8 qry[3]; + u16 p_id; + u16 p_adr; + u16 a_id; + u16 a_adr; + u8 vcc_min; + u8 vcc_max; + u8 vpp_min; + u8 vpp_max; + u8 word_write_timeout_typ; + u8 buf_write_timeout_typ; + u8 block_erase_timeout_typ; + u8 chip_erase_timeout_typ; + u8 word_write_timeout_max; + u8 buf_write_timeout_max; + u8 block_erase_timeout_max; + u8 chip_erase_timeout_max; + u8 dev_size; + u16 interface_desc; + u16 max_buf_write_size; + u8 num_erase_regions; + u32 erase_region_info[NUM_ERASE_REGIONS]; +} __attribute__((packed)); + +struct cfi_pri_hdr { + u8 pri[3]; + u8 major_version; + u8 minor_version; +} __attribute__((packed)); + +void flash_write_cmd(flash_info_t * info, flash_sect_t sect, + uint offset, u32 cmd); + +#endif /* __CFI_FLASH_H__ */ -- cgit From 353462f6ff9769091fb644d44d8025f20a4192d9 Mon Sep 17 00:00:00 2001 From: Eric Millbrandt Date: Wed, 28 Oct 2009 09:37:33 -0500 Subject: galaxy5200: Add default environment variables Extend bootdelay to 10 seconds. Set boot retry time to 120 seconds and use reset to retry. Define default bootcommand and bootargs for production. Signed-off-by: Eric Millbrandt --- include/configs/galaxy5200.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h index 931acfbc77..4be28b26a6 100644 --- a/include/configs/galaxy5200.h +++ b/include/configs/galaxy5200.h @@ -88,15 +88,21 @@ /* * Autobooting */ -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ +#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */ /* even with bootdelay=0 */ -#undef CONFIG_BOOTARGS +#define CONFIG_BOOT_RETRY_TIME 120 /* Reset if no command is entered */ +#define CONFIG_RESET_TO_RETRY #define CONFIG_PREBOOT "echo;" \ "echo Welcome to U-Boot;"\ "echo" +#define CONFIG_BOOTCOMMAND "go ff300004 0; go ff300004 2 2;" \ + "bootm ff040000 ff900000 fffc0000" +#define CONFIG_BOOTARGS "console=ttyPSC0,115200" +#define CONFIG_EXTRA_ENV_SETTINGS "epson=yes\0" + /* * IPB Bus clocking configuration. */ -- cgit From 264e42ee54f1d322805d9068168fd362b413fd09 Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Wed, 28 Oct 2009 11:04:53 -0400 Subject: Fix Compliation warning for SBC35-A9G20 board The patch fixes a compilation warning by defining CONFIG_SYS_64BIT_VSPRINTF in the config file Signed-off-by: Sandeep Paulraj --- include/configs/sbc35_a9g20.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/sbc35_a9g20.h b/include/configs/sbc35_a9g20.h index f4b34775a6..7a2dcd884b 100644 --- a/include/configs/sbc35_a9g20.h +++ b/include/configs/sbc35_a9g20.h @@ -161,6 +161,7 @@ #define CONFIG_ENV_OFFSET 0x60000 #define CONFIG_ENV_OFFSET_REDUND 0x80000 #define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #endif #define CONFIG_BOOTCOMMAND "nboot 0x21000000 0 400000" -- cgit From a38f85e180a30b6225808828ded1017b1a5418c6 Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Wed, 28 Oct 2009 11:05:03 -0400 Subject: Fix Compliation warning for TNY-A9260 and TNY-A9G20 The patch fixes a compilation warning by defining CONFIG_SYS_64BIT_VSPRINTF in the config file Signed-off-by: Sandeep Paulraj --- include/configs/tny_a9260.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/tny_a9260.h b/include/configs/tny_a9260.h index 4ad081b0ba..5b70a7bec8 100644 --- a/include/configs/tny_a9260.h +++ b/include/configs/tny_a9260.h @@ -138,6 +138,7 @@ #define CONFIG_ENV_OFFSET 0x60000 #define CONFIG_ENV_OFFSET_REDUND 0x80000 #define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #endif #define CONFIG_BOOTCOMMAND "nboot 0x21000000 0 400000" -- cgit From 98d92d8c9f4021629a45261ad5ec3f3595f3a27a Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 28 Oct 2009 22:07:56 +0100 Subject: sbc8349: fix incorrect comment The comment for the BR0_PRELIM port size initialization incorrectly stated 32 bit, while it's actually 16 bit. The code is correct. Reported-by: Guenter Koellner Signed-off-by: Wolfgang Denk --- include/configs/sbc8349.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 4dea27d483..7bef1195d3 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -158,7 +158,7 @@ /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \ - (2 << BR_PS_SHIFT) | /* 32 bit port size */ \ + (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ BR_V) /* valid */ #define CONFIG_SYS_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */ -- cgit