From 480f61790565d77432b70b4016b73f2ae27d530f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 18 Jun 2009 08:23:01 -0500 Subject: 86xx: Add CPU_TYPE_ENTRY support Unify with 83xx and 85xx and use CPU_TYPE_ENTRY. We are going to use this to convey the # of cores and DDR width in the near future so its good to keep in sync. Signed-off-by: Kumar Gala --- include/asm-ppc/processor.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index e7db1c6abf..65546adbca 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -1021,7 +1021,7 @@ struct cpu_type { struct cpu_type *identify_cpu(u32 ver); -#if defined(CONFIG_MPC85xx) +#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) #define CPU_TYPE_ENTRY(n, v) \ { .name = #n, .soc_ver = SVR_##v, } #else -- cgit From 156984a3611c28093919d3e3c042f722b5548253 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 18 Jun 2009 08:39:42 -0500 Subject: 8xxx: Fix PCI bus address setup for 36-bit configs We want the outbound PCI memory map to end at the 4G boundary so we can maximize the amount of space available for inbound mappings if we have large amounts of memory. This matches the device tree setup in the kernel for the 36-bit physical configs for the platforms that have one (MPC8641 HPCN & MPC8572 DS). Signed-off-by: Kumar Gala --- include/configs/MPC8572DS.h | 6 +++--- include/configs/MPC8641HPCN.h | 2 +- include/configs/P2020DS.h | 6 +++--- 3 files changed, 7 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 2aba689664..6f1b1a4c83 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -404,7 +404,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); /* controller 3, direct to uli, tgtid 3, Base address 8000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull #else #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 @@ -423,7 +423,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); /* controller 2, Slot 2, tgtid 2, Base address 9000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 @@ -442,7 +442,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); /* controller 1, Slot 1, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull #else #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index d8042fb764..035874b312 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -335,7 +335,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0x0000000c00000000ULL #else #define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_VIRT diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index a39ff26a7a..84b5686244 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -437,7 +437,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); /* controller 3, Slot 1, tgtid 3, Base address b000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull #else #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 @@ -456,7 +456,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); /* controller 2, direct to uli, tgtid 2, Base address 9000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 @@ -475,7 +475,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); /* controller 1, Slot 2, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull #else #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 -- cgit From 29c35182462feea09f322e51913759a53359a3e0 Mon Sep 17 00:00:00 2001 From: Roy Zang Date: Tue, 30 Jun 2009 13:56:23 +0800 Subject: 85xx: Add pci e1000 Ethernet support for P2020 board Signed-off-by: Roy Zang Signed-off-by: Kumar Gala --- include/configs/P2020DS.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 84b5686244..fddcce5e4f 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -46,6 +46,7 @@ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -- cgit From 017f11f68ef543e866be033bcb7b8058a8a380d8 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Tue, 30 Jun 2009 17:15:40 -0500 Subject: 8xxx: Break out DMA code to a common file DMA support is now enabled via the CONFIG_FSL_DMA define instead of the previous CONFIG_DDR_ECC Signed-off-by: Peter Tyser Signed-off-by: Kumar Gala --- include/asm-ppc/config.h | 7 +++++++ include/configs/PM854.h | 1 + include/configs/PM856.h | 1 + 3 files changed, 9 insertions(+) (limited to 'include') diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h index 0900f65b96..9c358aa413 100644 --- a/include/asm-ppc/config.h +++ b/include/asm-ppc/config.h @@ -29,4 +29,11 @@ #endif #endif +#ifndef CONFIG_FSL_DMA +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) && \ + (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) +#define CONFIG_FSL_DMA #endif +#endif + +#endif /* _ASM_CONFIG_H_ */ diff --git a/include/configs/PM854.h b/include/configs/PM854.h index 3f943aa437..4b9bcca79b 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -96,6 +96,7 @@ #undef CONFIG_DDR_SPD #define CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_FSL_DMA /* use DMA to init DDR ECC */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 43c2873e37..1db20bcceb 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -98,6 +98,7 @@ #undef CONFIG_DDR_SPD #define CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_FSL_DMA /* use DMA to init DDR ECC */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef -- cgit From 9c06071a6077ba95e9d43226156e39567d5d064a Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Tue, 30 Jun 2009 17:15:41 -0500 Subject: fsl_dma: Add bitfield definitions for common registers Signed-off-by: Peter Tyser Signed-off-by: Kumar Gala --- include/asm-ppc/fsl_dma.h | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'include') diff --git a/include/asm-ppc/fsl_dma.h b/include/asm-ppc/fsl_dma.h index aab8720977..c9ec6b59e6 100644 --- a/include/asm-ppc/fsl_dma.h +++ b/include/asm-ppc/fsl_dma.h @@ -29,12 +29,58 @@ typedef struct fsl_dma { uint mr; /* DMA mode register */ +#define FSL_DMA_MR_CS 0x00000001 /* Channel start */ +#define FSL_DMA_MR_CC 0x00000002 /* Channel continue */ +#define FSL_DMA_MR_CTM 0x00000004 /* Channel xfer mode */ +#define FSL_DMA_MR_CTM_DIRECT 0x00000004 /* Direct channel xfer mode */ +#define FSL_DMA_MR_CA 0x00000008 /* Channel abort */ +#define FSL_DMA_MR_CDSM 0x00000010 +#define FSL_DMA_MR_XFE 0x00000020 /* Extended features en */ +#define FSL_DMA_MR_EIE 0x00000040 /* Error interrupt en */ +#define FSL_DMA_MR_EOLSIE 0x00000080 /* End-of-lists interrupt en */ +#define FSL_DMA_MR_EOLNIE 0x00000100 /* End-of-links interrupt en */ +#define FSL_DMA_MR_EOSIE 0x00000200 /* End-of-seg interrupt en */ +#define FSL_DMA_MR_SRW 0x00000400 /* Single register write */ +#define FSL_DMA_MR_SAHE 0x00001000 /* Source addr hold enable */ +#define FSL_DMA_MR_DAHE 0x00002000 /* Dest addr hold enable */ +#define FSL_DMA_MR_SAHTS_MASK 0x0000c000 /* Source addr hold xfer size */ +#define FSL_DMA_MR_DAHTS_MASK 0x00030000 /* Dest addr hold xfer size */ +#define FSL_DMA_MR_EMS_EN 0x00040000 /* Ext master start en */ +#define FSL_DMA_MR_EMP_EN 0x00200000 /* Ext master pause en */ +#define FSL_DMA_MR_BWC_MASK 0x0f000000 /* Bandwidth/pause ctl */ +#define FSL_DMA_MR_BWC_DIS 0x0f000000 /* Bandwidth/pause ctl disable */ uint sr; /* DMA status register */ +#define FSL_DMA_SR_EOLSI 0x00000001 /* End-of-list interrupt */ +#define FSL_DMA_SR_EOSI 0x00000002 /* End-of-segment interrupt */ +#define FSL_DMA_SR_CB 0x00000004 /* Channel busy */ +#define FSL_DMA_SR_EOLNI 0x00000008 /* End-of-links interrupt */ +#define FSL_DMA_SR_PE 0x00000010 /* Programming error */ +#define FSL_DMA_SR_CH 0x00000020 /* Channel halted */ +#define FSL_DMA_SR_TE 0x00000080 /* Transfer error */ char res0[4]; uint clndar; /* DMA current link descriptor address register */ uint satr; /* DMA source attributes register */ +#define FSL_DMA_SATR_ESAD_MASK 0x000001ff /* Extended source addr */ +#define FSL_DMA_SATR_SREAD_NO_SNOOP 0x00040000 /* Read, don't snoop */ +#define FSL_DMA_SATR_SREAD_SNOOP 0x00050000 /* Read, snoop */ +#define FSL_DMA_SATR_SREAD_UNLOCK 0x00070000 /* Read, unlock l2 */ +#define FSL_DMA_SATR_STRAN_MASK 0x00f00000 /* Source interface */ +#define FSL_DMA_SATR_SSME 0x01000000 /* Source stride en */ +#define FSL_DMA_SATR_SPCIORDER 0x02000000 /* PCI transaction order */ +#define FSL_DMA_SATR_STFLOWLVL_MASK 0x0c000000 /* RIO flow level */ +#define FSL_DMA_SATR_SBPATRMU 0x20000000 /* Bypass ATMU */ uint sar; /* DMA source address register */ uint datr; /* DMA destination attributes register */ +#define FSL_DMA_DATR_EDAD_MASK 0x000001ff /* Extended dest addr */ +#define FSL_DMA_DATR_DWRITE_NO_SNOOP 0x00040000 /* Write, don't snoop */ +#define FSL_DMA_DATR_DWRITE_SNOOP 0x00050000 /* Write, snoop */ +#define FSL_DMA_DATR_DWRITE_ALLOC 0x00060000 /* Write, alloc l2 */ +#define FSL_DMA_DATR_DWRITE_LOCK 0x00070000 /* Write, lock l2 */ +#define FSL_DMA_DATR_DTRAN_MASK 0x00f00000 /* Dest interface */ +#define FSL_DMA_DATR_DSME 0x01000000 /* Dest stride en */ +#define FSL_DMA_DATR_DPCIORDER 0x02000000 /* PCI transaction order */ +#define FSL_DMA_DATR_DTFLOWLVL_MASK 0x0c000000 /* RIO flow level */ +#define FSL_DMA_DATR_DBPATRMU 0x20000000 /* Bypass ATMU */ uint dar; /* DMA destination address register */ uint bcr; /* DMA byte count register */ char res1[4]; -- cgit From 191c7118592cd182f2dc7f46b4f72d9bed0e2c76 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Tue, 30 Jun 2009 17:15:46 -0500 Subject: fsl_dma: Move dma function prototypes to common header file Signed-off-by: Peter Tyser Signed-off-by: Kumar Gala --- include/asm-ppc/fsl_dma.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/asm-ppc/fsl_dma.h b/include/asm-ppc/fsl_dma.h index c9ec6b59e6..978283a8c4 100644 --- a/include/asm-ppc/fsl_dma.h +++ b/include/asm-ppc/fsl_dma.h @@ -94,4 +94,9 @@ typedef struct fsl_dma { char res4[56]; } fsl_dma_t; +#ifdef CONFIG_FSL_DMA +void dma_init(void); +int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t n); +#endif + #endif /* _ASM_DMA_H_ */ -- cgit From 0d595f76bc9c7c8dff5bd31dffed87a840a03c56 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Tue, 30 Jun 2009 17:15:48 -0500 Subject: fsl_dma: Break out common memory initialization function Signed-off-by: Peter Tyser Signed-off-by: Kumar Gala --- include/asm-ppc/fsl_dma.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/asm-ppc/fsl_dma.h b/include/asm-ppc/fsl_dma.h index 978283a8c4..043669e433 100644 --- a/include/asm-ppc/fsl_dma.h +++ b/include/asm-ppc/fsl_dma.h @@ -97,6 +97,9 @@ typedef struct fsl_dma { #ifdef CONFIG_FSL_DMA void dma_init(void); int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t n); +#if (defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) +void dma_meminit(uint val, uint size); +#endif #endif #endif /* _ASM_DMA_H_ */ -- cgit From 5da6f806b400372b8a0664f3282c9e83a402eb66 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Tue, 30 Jun 2009 17:26:01 -0500 Subject: 86xx: XPedite5170 board support Initial support for Extreme Engineering Solutions XPedite5170 - a MPC8640-based 3U VPX single board computer with a PMC/XMC site. Signed-off-by: Peter Tyser Signed-off-by: Kumar Gala --- include/configs/XPEDITE5170.h | 756 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 756 insertions(+) create mode 100644 include/configs/XPEDITE5170.h (limited to 'include') diff --git a/include/configs/XPEDITE5170.h b/include/configs/XPEDITE5170.h new file mode 100644 index 0000000000..2553293306 --- /dev/null +++ b/include/configs/XPEDITE5170.h @@ -0,0 +1,756 @@ +/* + * Copyright 2009 Extreme Engineering Solutions, Inc. + * Copyright 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * xpedite5170 board configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_MPC86xx 1 /* MPC86xx */ +#define CONFIG_MPC8641 1 /* MPC8641 specific */ +#define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */ +#define CONFIG_SYS_BOARD_NAME "XPedite5170" +#define CONFIG_NUM_CPUS 1 /* Number of CPUs in the system */ +#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ +#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ +#define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ +#define CONFIG_ALTIVEC 1 + +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ +#define CONFIG_PCIE1 1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 1 /* PCIE controler 2 */ +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ + +/* + * DDR config + */ +#define CONFIG_FSL_DDR2 +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#define CONFIG_DDR_SPD +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ +#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ +#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ + +/* + * virtual address to be used for temporary mappings. There + * should be 128k free at this VA. + */ +#define CONFIG_SYS_SCRATCH_VA 0xe0000000 + +#ifndef __ASSEMBLY__ +extern unsigned long get_board_sys_clk(unsigned long dummy); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */ + +/* + * L2CR setup + */ +#define CONFIG_SYS_L2 +#define L2_INIT 0 +#define L2_ENABLE (L2CR_L2E) + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) + +/* + * Diagnostics + */ +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x20000000 + +/* + * Memory map + * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable + * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable + * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable + * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable + * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable + * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable + * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable + * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable + * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable + * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable + */ + +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_2 | LCRR_EADC_3) + +/* + * NAND flash configuration + */ +#define CONFIG_SYS_NAND_BASE 0xef800000 +#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ +#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2} +#define CONFIG_SYS_MAX_NAND_DEVICE 2 +#define CONFIG_NAND_ACTL +#define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */ +#define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */ +#define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */ +#define CONFIG_SYS_NAND_ACTL_DELAY 25 +#define CONFIG_SYS_NAND_QUIET_TEST +#define CONFIG_JFFS2_NAND + +/* + * NOR flash configuration + */ +#define CONFIG_SYS_FLASH_BASE 0xf8000000 +#define CONFIG_SYS_FLASH_BASE2 0xf0000000 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \ + {0xf7f00000, 0xc0000} } +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ + +/* + * Chip select configuration + */ +/* NOR Flash 0 on CS0 */ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\ + BR_PS_16 |\ + BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\ + OR_GPCM_CSNT |\ + OR_GPCM_XACS |\ + OR_GPCM_ACS_DIV2 |\ + OR_GPCM_SCY_8 |\ + OR_GPCM_TRLX |\ + OR_GPCM_EHTR |\ + OR_GPCM_EAD) + +/* NOR Flash 1 on CS1 */ +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\ + BR_PS_16 |\ + BR_V) +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM + +/* NAND flash on CS2 */ +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\ + BR_PS_8 |\ + BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\ + OR_GPCM_BCTLD |\ + OR_GPCM_CSNT |\ + OR_GPCM_ACS_DIV4 |\ + OR_GPCM_SCY_4 |\ + OR_GPCM_TRLX |\ + OR_GPCM_EHTR) + +/* Optional NAND flash on CS3 */ +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\ + BR_PS_8 |\ + BR_V) +#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM + +/* + * Use L1 as initial stack + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 +#define CONFIG_SYS_INIT_RAM_END 0x00004000 + +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} +#define CONFIG_BAUDRATE 115200 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * Use the HUSH parser + */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +#define CONFIG_SYS_64BIT_VSPRINTF 1 +#define CONFIG_SYS_64BIT_STRTOUL 1 + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SYS_I2C_SPEED 100000 /* M41T00 only supports 100 KHz */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE + +/* PEX8518 slave I2C interface */ +#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 + +/* I2C DS1631 temperature sensor */ +#define CONFIG_SYS_I2C_DS1621_ADDR 0x48 +#define CONFIG_DTT_DS1621 +#define CONFIG_DTT_SENSORS { 0 } + +/* I2C EEPROM - AT24C128B */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ + +/* I2C RTC */ +#define CONFIG_RTC_M41T11 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_M41T11_BASE_YEAR 2000 + +/* GPIO/EEPROM/SRAM */ +#define CONFIG_DS4510 +#define CONFIG_SYS_I2C_DS4510_ADDR 0x51 + +/* GPIO */ +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 +#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c +#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e +#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f +#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 + +/* + * PU = pulled high, PD = pulled low + * I = input, O = output, IO = input/output + */ +/* PCA9557 @ 0x18*/ +#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ +#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */ +#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ +#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */ +#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ +#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */ + +/* PCA9557 @ 0x1c*/ +#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */ +#define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */ +#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */ +#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */ +#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */ +#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */ +#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */ +#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */ + +/* PCA9557 @ 0x1e*/ +#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */ +#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */ + +/* PCA9557 @ 0x1f */ +#define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */ +#define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */ +#define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */ +#define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */ + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +/* PCIE1 - PEX8518 */ +#define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ +#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ + +/* PCIE2 - VPX P1 */ +#define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */ + +/* + * Networking options + */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC1_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define CONFIG_HAS_ETH0 + +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_PHY_ADDR 2 +#define TSEC2_PHYIDX 0 +#define CONFIG_HAS_ETH1 + +/* + * BAT mappings + */ +#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) +#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\ + BATU_BL_1M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU +#endif + +/* + * BAT0 2G Cacheable, non-guarded + * 0x0000_0000 2G DDR + */ +#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) +#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U + +/* + * BAT1 1G Cache-inhibited, guarded + * 0x8000_0000 1G PCI-Express 1 Memory + */ +#define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\ + BATU_BL_1G |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U + +/* + * BAT2 512M Cache-inhibited, guarded + * 0xc000_0000 512M PCI-Express 2 Memory + */ +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\ + BATU_BL_512M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U + +/* + * BAT3 1M Cache-inhibited, guarded + * 0xe000_0000 1M CCSR + */ +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\ + BATU_BL_1M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U + +/* + * BAT4 32M Cache-inhibited, guarded + * 0xe200_0000 16M PCI-Express 1 I/O + * 0xe300_0000 16M PCI-Express 2 I/0 + */ +#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\ + BATU_BL_32M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U + +/* + * BAT5 128K Cacheable, non-guarded + * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory) + */ +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\ + BATL_PP_RW |\ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\ + BATU_BL_128K |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L +#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U + +/* + * BAT6 256M Cache-inhibited, guarded + * 0xf000_0000 256M FLASH + */ +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\ + BATU_BL_256M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\ + BATL_PP_RW |\ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U + +/* Map the last 1M of flash where we're running from reset */ +#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE |\ + BATU_BL_1M |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\ + BATL_PP_RW |\ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY + +/* + * BAT7 64M Cache-inhibited, guarded + * 0xe800_0000 64K NAND FLASH + * 0xe804_0000 128K DUART Registers + */ +#define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT |\ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\ + BATU_BL_512K |\ + BATU_VS |\ + BATU_VP) +#define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\ + BATL_PP_RW |\ + BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U + +/* + * Command configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DS4510 +#define CONFIG_CMD_DS4510_INFO +#define CONFIG_CMD_DTT +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCA953X +#define CONFIG_CMD_PCA953X_INFO +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SNTP + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ +#define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */ +#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ +#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ +#define CONFIG_PANIC_HANG /* do not reset board on panic */ +#define CONFIG_PREBOOT /* enable preboot variable */ +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 +#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ + +/* + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Environment Configuration + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ +#define CONFIG_ENV_SIZE 0x8000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) + +/* + * Flash memory map: + * fffc0000 - ffffffff Pri FDT (256KB) + * fff80000 - fffbffff Pri U-Boot Environment (256 KB) + * fff00000 - fff7ffff Pri U-Boot (512 KB) + * fef00000 - ffefffff Pri OS image (16MB) + * f8000000 - feefffff Pri OS Use/Filesystem (111MB) + * + * f7fc0000 - f7ffffff Sec FDT (256KB) + * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB) + * f7f00000 - f7f7ffff Sec U-Boot (512 KB) + * f6f00000 - f7efffff Sec OS image (16MB) + * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) + */ +#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff00000) +#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f00000) +#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfffc0000) +#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7fc0000) +#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000) +#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000) + +#define CONFIG_PROG_UBOOT1 \ + "$download_cmd $loadaddr $ubootfile; " \ + "if test $? -eq 0; then " \ + "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ + "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ + "if test $? -ne 0; then " \ + "echo PROGRAM FAILED; " \ + "else; " \ + "echo PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_UBOOT2 \ + "$download_cmd $loadaddr $ubootfile; " \ + "if test $? -eq 0; then " \ + "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ + "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ + "if test $? -ne 0; then " \ + "echo PROGRAM FAILED; " \ + "else; " \ + "echo PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_BOOT_OS_NET \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "if test -n $fdtaddr; then " \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "bootm $osaddr - $fdtaddr; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi; " \ + "else; " \ + "bootm $osaddr; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_OS1 \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ + "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ + "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo OS PROGRAM FAILED; " \ + "else; " \ + "echo OS PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_OS2 \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ + "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ + "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo OS PROGRAM FAILED; " \ + "else; " \ + "echo OS PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_FDT1 \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ + "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ + "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo FDT PROGRAM FAILED; " \ + "else; " \ + "echo FDT PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_FDT2 \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ + "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ + "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo FDT PROGRAM FAILED; " \ + "else; " \ + "echo FDT PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=yes\0" \ + "download_cmd=tftp\0" \ + "console_args=console=ttyS0,115200\0" \ + "root_args=root=/dev/nfs rw\0" \ + "misc_args=ip=on\0" \ + "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ + "bootfile=/home/user/file\0" \ + "osfile=/home/user/uImage-XPedite5170\0" \ + "fdtfile=/home/user/xpedite5170.dtb\0" \ + "ubootfile=/home/user/u-boot.bin\0" \ + "fdtaddr=c00000\0" \ + "osaddr=0x1000000\0" \ + "loadaddr=0x1000000\0" \ + "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ + "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ + "prog_os1="CONFIG_PROG_OS1"\0" \ + "prog_os2="CONFIG_PROG_OS2"\0" \ + "prog_fdt1="CONFIG_PROG_FDT1"\0" \ + "prog_fdt2="CONFIG_PROG_FDT2"\0" \ + "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ + "bootcmd_flash1=run set_bootargs; " \ + "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ + "bootcmd_flash2=run set_bootargs; " \ + "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ + "bootcmd=run bootcmd_flash1\0" +#endif /* __CONFIG_H */ -- cgit From 546b1032907df70f2dd0f98f3ad09885a88411e5 Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Thu, 2 Jul 2009 16:14:40 +0530 Subject: 85xx: Adds GPIO registers to MPC85xx Memory Map. Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala --- include/asm-ppc/immap_85xx.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'include') diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index db2bdf0afa..0efef05214 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -341,6 +341,15 @@ typedef struct ccsr_pcix { char res11[476]; } ccsr_pcix_t; +typedef struct ccsr_gpio { + uint gpdir; + uint gpodr; + uint gpdat; + uint gpier; + uint gpimr; + uint gpicr; +} ccsr_gpio_t; + #define PCIX_COMMAND 0x62 #define POWAR_EN 0x80000000 #define POWAR_IO_READ 0x00080000 @@ -1648,6 +1657,8 @@ typedef struct ccsr_gur { #define CONFIG_SYS_MPC85xx_PCIX_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000) #define CONFIG_SYS_MPC85xx_PCIX2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET) +#define CONFIG_SYS_MPC85xx_GPIO_OFFSET (0xF000) +#define CONFIG_SYS_MPC85xx_GPIO_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET) #define CONFIG_SYS_MPC85xx_SATA1_OFFSET (0x18000) #define CONFIG_SYS_MPC85xx_SATA1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET) #define CONFIG_SYS_MPC85xx_SATA2_OFFSET (0x19000) -- cgit From 039594a4301dadceb267db5e8b9c8c78b1bb86b5 Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Thu, 2 Jul 2009 16:15:01 +0530 Subject: 8xxx: Second UART port added for MPC85xx, MPC83xx, MPC86xx processors Defining the next two configs allows to switch the serial port from the console using the setenv stdin and stdout 1. #define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */ 2. #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ Signed-off-by: Poonam Aggrwal Signed-off-by: Ed Swarthout Signed-off-by: Kumar Gala --- include/serial.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/serial.h b/include/serial.h index aca5221044..5722337269 100644 --- a/include/serial.h +++ b/include/serial.h @@ -24,7 +24,8 @@ extern struct serial_device * default_serial_console (void); #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \ - defined(CONFIG_MPC5xxx) + defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC83xx) || \ + defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) extern struct serial_device serial0_device; extern struct serial_device serial1_device; #if defined(CONFIG_SYS_NS16550_SERIAL) -- cgit From e94e460c6e8741f42dab6d8dd4b596ba5d9d79ae Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Tue, 30 Jun 2009 17:15:51 -0500 Subject: 83xx: Add support for fsl_dma driver Signed-off-by: Peter Tyser Reviewed-by: Ira W. Snyder Tested-by: Ira W. Snyder Acked-by: Kim Phillips Signed-off-by: Kumar Gala --- include/asm-ppc/config.h | 5 +++-- include/asm-ppc/fsl_dma.h | 36 ++++++++++++++++++++++++++++++++ include/asm-ppc/immap_83xx.h | 49 ++++---------------------------------------- include/mpc83xx.h | 16 --------------- 4 files changed, 43 insertions(+), 63 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h index 9c358aa413..ca143c7fef 100644 --- a/include/asm-ppc/config.h +++ b/include/asm-ppc/config.h @@ -30,8 +30,9 @@ #endif #ifndef CONFIG_FSL_DMA -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) && \ - (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) +#if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) && \ + !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) || \ + (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA))) #define CONFIG_FSL_DMA #endif #endif diff --git a/include/asm-ppc/fsl_dma.h b/include/asm-ppc/fsl_dma.h index 043669e433..11641912a6 100644 --- a/include/asm-ppc/fsl_dma.h +++ b/include/asm-ppc/fsl_dma.h @@ -27,6 +27,41 @@ #include +#ifdef CONFIG_MPC83xx +typedef struct fsl_dma { + uint mr; /* DMA mode register */ +#define FSL_DMA_MR_CS 0x00000001 /* Channel start */ +#define FSL_DMA_MR_CC 0x00000002 /* Channel continue */ +#define FSL_DMA_MR_CTM 0x00000004 /* Channel xfer mode */ +#define FSL_DMA_MR_CTM_DIRECT 0x00000004 /* Direct channel xfer mode */ +#define FSL_DMA_MR_EOTIE 0x00000080 /* End-of-transfer interrupt en */ +#define FSL_DMA_MR_PRC_MASK 0x00000c00 /* PCI read command */ +#define FSL_DMA_MR_SAHE 0x00001000 /* Source addr hold enable */ +#define FSL_DMA_MR_DAHE 0x00002000 /* Dest addr hold enable */ +#define FSL_DMA_MR_SAHTS_MASK 0x0000c000 /* Source addr hold xfer size */ +#define FSL_DMA_MR_DAHTS_MASK 0x00030000 /* Dest addr hold xfer size */ +#define FSL_DMA_MR_EMS_EN 0x00040000 /* Ext master start en */ +#define FSL_DMA_MR_IRQS 0x00080000 /* Interrupt steer */ +#define FSL_DMA_MR_DMSEN 0x00100000 /* Direct mode snooping en */ +#define FSL_DMA_MR_BWC_MASK 0x00e00000 /* Bandwidth/pause ctl */ +#define FSL_DMA_MR_DRCNT 0x0f000000 /* DMA request count */ + uint sr; /* DMA status register */ +#define FSL_DMA_SR_EOCDI 0x00000001 /* End-of-chain/direct interrupt */ +#define FSL_DMA_SR_EOSI 0x00000002 /* End-of-segment interrupt */ +#define FSL_DMA_SR_CB 0x00000004 /* Channel busy */ +#define FSL_DMA_SR_TE 0x00000080 /* Transfer error */ + uint cdar; /* DMA current descriptor address register */ + char res0[4]; + uint sar; /* DMA source address register */ + char res1[4]; + uint dar; /* DMA destination address register */ + char res2[4]; + uint bcr; /* DMA byte count register */ + uint ndar; /* DMA next descriptor address register */ + uint gsr; /* DMA general status register (DMA3 ONLY!) */ + char res3[84]; +} fsl_dma_t; +#else typedef struct fsl_dma { uint mr; /* DMA mode register */ #define FSL_DMA_MR_CS 0x00000001 /* Channel start */ @@ -93,6 +128,7 @@ typedef struct fsl_dma { uint dsr; /* DMA destination stride register */ char res4[56]; } fsl_dma_t; +#endif /* !CONFIG_MPC83xx */ #ifdef CONFIG_FSL_DMA void dma_init(void); diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index 8f945a1519..7c6a15185e 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -32,6 +32,7 @@ #include #include #include +#include /* * Local Access Window @@ -367,51 +368,7 @@ typedef struct dma83xx { u32 imisr; /* 0x80 Inbound message interrupt status register */ u32 imimr; /* 0x84 Inbound message interrupt mask register */ u32 res4[0x1E]; /* 0x88-0x99 reserved */ - u32 dmamr0; /* 0x100 DMA 0 mode register */ - u32 dmasr0; /* 0x104 DMA 0 status register */ - u32 dmacdar0; /* 0x108 DMA 0 current descriptor address register */ - u32 res5; /* 0x10C reserved */ - u32 dmasar0; /* 0x110 DMA 0 source address register */ - u32 res6; /* 0x114 reserved */ - u32 dmadar0; /* 0x118 DMA 0 destination address register */ - u32 res7; /* 0x11C reserved */ - u32 dmabcr0; /* 0x120 DMA 0 byte count register */ - u32 dmandar0; /* 0x124 DMA 0 next descriptor address register */ - u32 res8[0x16]; /* 0x128-0x179 reserved */ - u32 dmamr1; /* 0x180 DMA 1 mode register */ - u32 dmasr1; /* 0x184 DMA 1 status register */ - u32 dmacdar1; /* 0x188 DMA 1 current descriptor address register */ - u32 res9; /* 0x18C reserved */ - u32 dmasar1; /* 0x190 DMA 1 source address register */ - u32 res10; /* 0x194 reserved */ - u32 dmadar1; /* 0x198 DMA 1 destination address register */ - u32 res11; /* 0x19C reserved */ - u32 dmabcr1; /* 0x1A0 DMA 1 byte count register */ - u32 dmandar1; /* 0x1A4 DMA 1 next descriptor address register */ - u32 res12[0x16]; /* 0x1A8-0x199 reserved */ - u32 dmamr2; /* 0x200 DMA 2 mode register */ - u32 dmasr2; /* 0x204 DMA 2 status register */ - u32 dmacdar2; /* 0x208 DMA 2 current descriptor address register */ - u32 res13; /* 0x20C reserved */ - u32 dmasar2; /* 0x210 DMA 2 source address register */ - u32 res14; /* 0x214 reserved */ - u32 dmadar2; /* 0x218 DMA 2 destination address register */ - u32 res15; /* 0x21C reserved */ - u32 dmabcr2; /* 0x220 DMA 2 byte count register */ - u32 dmandar2; /* 0x224 DMA 2 next descriptor address register */ - u32 res16[0x16]; /* 0x228-0x279 reserved */ - u32 dmamr3; /* 0x280 DMA 3 mode register */ - u32 dmasr3; /* 0x284 DMA 3 status register */ - u32 dmacdar3; /* 0x288 DMA 3 current descriptor address register */ - u32 res17; /* 0x28C reserved */ - u32 dmasar3; /* 0x290 DMA 3 source address register */ - u32 res18; /* 0x294 reserved */ - u32 dmadar3; /* 0x298 DMA 3 destination address register */ - u32 res19; /* 0x29C reserved */ - u32 dmabcr3; /* 0x2A0 DMA 3 byte count register */ - u32 dmandar3; /* 0x2A4 DMA 3 next descriptor address register */ - u32 dmagsr; /* 0x2A8 DMA general status register */ - u32 res20[0x15]; /* 0x2AC-0x2FF reserved */ + struct fsl_dma dma[4]; } dma83xx_t; /* @@ -895,6 +852,8 @@ typedef struct immap { } immap_t; #endif +#define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000) +#define CONFIG_SYS_MPC83xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET) #define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000) #define CONFIG_SYS_MPC83xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET) #define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000 diff --git a/include/mpc83xx.h b/include/mpc83xx.h index c5bd6cb16a..fd742c7809 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -1041,22 +1041,6 @@ #define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ #define ECC_ERROR_MAN_SBEC_SHIFT 0 -/* DMAMR - DMA Mode Register - */ -#define DMA_CHANNEL_START 0x00000001 /* Bit - DMAMRn CS */ -#define DMA_CHANNEL_TRANSFER_MODE_DIRECT 0x00000004 /* Bit - DMAMRn CTM */ -#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN 0x00001000 /* Bit - DMAMRn SAHE */ -#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B 0x00000000 /* 2Bit- DMAMRn SAHTS 1byte */ -#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B 0x00004000 /* 2Bit- DMAMRn SAHTS 2bytes */ -#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B 0x00008000 /* 2Bit- DMAMRn SAHTS 4bytes */ -#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B 0x0000c000 /* 2Bit- DMAMRn SAHTS 8bytes */ -#define DMA_CHANNEL_SNOOP 0x00010000 /* Bit - DMAMRn DMSEN */ - -/* DMASR - DMA Status Register - */ -#define DMA_CHANNEL_BUSY 0x00000004 /* Bit - DMASRn CB */ -#define DMA_CHANNEL_TRANSFER_ERROR 0x00000080 /* Bit - DMASRn TE */ - /* CONFIG_ADDRESS - PCI Config Address Register */ #define PCI_CONFIG_ADDRESS_EN 0x80000000 -- cgit