From f5d8b1a1f9f08911636dc095c7f4f281a0dfc59d Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Thu, 24 Sep 2020 11:54:37 +0300 Subject: microblaze: start.S: Use board_init_f_alloc/init in early init Implement early init by calling generic board_init_f_alloc_reserve and board_init_f_init_reserve functions: * drop SYS_MALLOC_F_LEN related code, as allocation and gd->malloc_base assignment are taken care of by the generic functions * drop _gd logic Cc: Michal Simek Signed-off-by: Ovidiu Panait --- include/configs/microblaze-generic.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 8ca0e83c78..dfc2cd97d3 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -167,8 +167,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x100000 # define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - CONFIG_SYS_MALLOC_F_LEN) + CONFIG_SYS_INIT_RAM_SIZE) /* Just for sure that there is a space for stack */ #define CONFIG_SPL_STACK_SIZE 0x100 -- cgit From 581d6a6da7f619281f3bf6181a2cb438051b0e48 Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Tue, 22 Sep 2020 05:18:52 -0600 Subject: microblaze: trivial code fixes Set proper indentation for env variables in microblaze header file. Signed-off-by: T Karthik Reddy Signed-off-by: Michal Simek --- include/configs/microblaze-generic.h | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index dfc2cd97d3..642de612b7 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -131,15 +131,16 @@ #define CONFIG_SYS_USR_EXCEP /* user exception */ #ifndef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \ - "nor0=flash-0\0"\ - "mtdparts=mtdparts=flash-0:"\ - "256k(u-boot),256k(env),3m(kernel),"\ - "1m(romfs),1m(cramfs),-(jffs2)\0"\ - "nc=setenv stdout nc;"\ - "setenv stdin nc\0" \ - "serial=setenv stdout serial;"\ - "setenv stdin serial\0" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "unlock=yes\0"\ + "nor0=flash-0\0"\ + "mtdparts=mtdparts=flash-0:"\ + "256k(u-boot),256k(env),3m(kernel),"\ + "1m(romfs),1m(cramfs),-(jffs2)\0"\ + "nc=setenv stdout nc;"\ + "setenv stdin nc\0" \ + "serial=setenv stdout serial;"\ + "setenv stdin serial\0" #endif #if defined(CONFIG_XILINX_AXIEMAC) -- cgit From 44d2be8d6aa5b73a8d8ca1b1d36d2e1e794f449d Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Tue, 22 Sep 2020 05:18:55 -0600 Subject: microblaze: Add support for distro boot Add distro boot support for microblaze and enable jtag, qspi, dhcp, pxe boot targets for distro boot. Enable DISTRO_DEFAULTS config in microblaze defconfig and also enable support for spi xilinx driver & spi vendors to access spi flash by distro boot. Signed-off-by: T Karthik Reddy Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek --- include/configs/microblaze-generic.h | 49 ++++++++++++++++++++++++++++++++++-- 1 file changed, 47 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 642de612b7..2b41242350 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -125,11 +125,54 @@ #define CONFIG_SYS_LOAD_ADDR 0 #define CONFIG_HOSTNAME "microblaze-generic" -#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" /* architecture dependent code */ #define CONFIG_SYS_USR_EXCEP /* user exception */ +#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) +#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) +#else +#define BOOT_TARGET_DEVICES_PXE(func) +#endif + +#if defined(CONFIG_CMD_DHCP) +#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) +#else +#define BOOT_TARGET_DEVICES_DHCP(func) +#endif + +#if defined(CONFIG_SPI_FLASH) +# define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na) +#else +# define BOOT_TARGET_DEVICES_QSPI(func) +#endif + +#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ + "bootcmd_qspi=sf probe 0 0 0 && " \ + "sf read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \ + "echo QSPI: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo QSPI: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ + "qspi " + +#define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na) + +#define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \ + "bootcmd_jtag=echo JTAG: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo JTAG: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \ + "jtag " + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_JTAG(func) \ + BOOT_TARGET_DEVICES_QSPI(func) \ + BOOT_TARGET_DEVICES_DHCP(func) \ + BOOT_TARGET_DEVICES_PXE(func) + +#include + #ifndef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "unlock=yes\0"\ @@ -140,7 +183,9 @@ "nc=setenv stdout nc;"\ "setenv stdin nc\0" \ "serial=setenv stdout serial;"\ - "setenv stdin serial\0" + "setenv stdin serial\0"\ + "script_size_f=0x40000\0"\ + BOOTENV #endif #if defined(CONFIG_XILINX_AXIEMAC) -- cgit From 30f47c0f1bd84b9d46a3f99eca65f666991676a5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 8 Apr 2019 13:43:51 +0200 Subject: dt-bindings: arm64: versal: Add clk and power headers Add power and reset headers to be sources by Versal dtses. Signed-off-by: Michal Simek --- include/dt-bindings/clock/xlnx-versal-clk.h | 123 ++++++++++++++++++++++++++ include/dt-bindings/power/xlnx-versal-power.h | 42 +++++++++ 2 files changed, 165 insertions(+) create mode 100644 include/dt-bindings/clock/xlnx-versal-clk.h create mode 100644 include/dt-bindings/power/xlnx-versal-power.h (limited to 'include') diff --git a/include/dt-bindings/clock/xlnx-versal-clk.h b/include/dt-bindings/clock/xlnx-versal-clk.h new file mode 100644 index 0000000000..264d634d22 --- /dev/null +++ b/include/dt-bindings/clock/xlnx-versal-clk.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Xilinx Inc. + * + */ + +#ifndef _DT_BINDINGS_CLK_VERSAL_H +#define _DT_BINDINGS_CLK_VERSAL_H + +#define PMC_PLL 1 +#define APU_PLL 2 +#define RPU_PLL 3 +#define CPM_PLL 4 +#define NOC_PLL 5 +#define PLL_MAX 6 +#define PMC_PRESRC 7 +#define PMC_POSTCLK 8 +#define PMC_PLL_OUT 9 +#define PPLL 10 +#define NOC_PRESRC 11 +#define NOC_POSTCLK 12 +#define NOC_PLL_OUT 13 +#define NPLL 14 +#define APU_PRESRC 15 +#define APU_POSTCLK 16 +#define APU_PLL_OUT 17 +#define APLL 18 +#define RPU_PRESRC 19 +#define RPU_POSTCLK 20 +#define RPU_PLL_OUT 21 +#define RPLL 22 +#define CPM_PRESRC 23 +#define CPM_POSTCLK 24 +#define CPM_PLL_OUT 25 +#define CPLL 26 +#define PPLL_TO_XPD 27 +#define NPLL_TO_XPD 28 +#define APLL_TO_XPD 29 +#define RPLL_TO_XPD 30 +#define EFUSE_REF 31 +#define SYSMON_REF 32 +#define IRO_SUSPEND_REF 33 +#define USB_SUSPEND 34 +#define SWITCH_TIMEOUT 35 +#define RCLK_PMC 36 +#define RCLK_LPD 37 +#define WDT 38 +#define TTC0 39 +#define TTC1 40 +#define TTC2 41 +#define TTC3 42 +#define GEM_TSU 43 +#define GEM_TSU_LB 44 +#define MUXED_IRO_DIV2 45 +#define MUXED_IRO_DIV4 46 +#define PSM_REF 47 +#define GEM0_RX 48 +#define GEM0_TX 49 +#define GEM1_RX 50 +#define GEM1_TX 51 +#define CPM_CORE_REF 52 +#define CPM_LSBUS_REF 53 +#define CPM_DBG_REF 54 +#define CPM_AUX0_REF 55 +#define CPM_AUX1_REF 56 +#define QSPI_REF 57 +#define OSPI_REF 58 +#define SDIO0_REF 59 +#define SDIO1_REF 60 +#define PMC_LSBUS_REF 61 +#define I2C_REF 62 +#define TEST_PATTERN_REF 63 +#define DFT_OSC_REF 64 +#define PMC_PL0_REF 65 +#define PMC_PL1_REF 66 +#define PMC_PL2_REF 67 +#define PMC_PL3_REF 68 +#define CFU_REF 69 +#define SPARE_REF 70 +#define NPI_REF 71 +#define HSM0_REF 72 +#define HSM1_REF 73 +#define SD_DLL_REF 74 +#define FPD_TOP_SWITCH 75 +#define FPD_LSBUS 76 +#define ACPU 77 +#define DBG_TRACE 78 +#define DBG_FPD 79 +#define LPD_TOP_SWITCH 80 +#define ADMA 81 +#define LPD_LSBUS 82 +#define CPU_R5 83 +#define CPU_R5_CORE 84 +#define CPU_R5_OCM 85 +#define CPU_R5_OCM2 86 +#define IOU_SWITCH 87 +#define GEM0_REF 88 +#define GEM1_REF 89 +#define GEM_TSU_REF 90 +#define USB0_BUS_REF 91 +#define UART0_REF 92 +#define UART1_REF 93 +#define SPI0_REF 94 +#define SPI1_REF 95 +#define CAN0_REF 96 +#define CAN1_REF 97 +#define I2C0_REF 98 +#define I2C1_REF 99 +#define DBG_LPD 100 +#define TIMESTAMP_REF 101 +#define DBG_TSTMP 102 +#define CPM_TOPSW_REF 103 +#define USB3_DUAL_REF 104 +#define OUTCLK_MAX 105 +#define REF_CLK 106 +#define PL_ALT_REF_CLK 107 +#define MUXED_IRO 108 +#define PL_EXT 109 +#define PL_LB 110 +#define MIO_50_OR_51 111 +#define MIO_24_OR_25 112 + +#endif diff --git a/include/dt-bindings/power/xlnx-versal-power.h b/include/dt-bindings/power/xlnx-versal-power.h new file mode 100644 index 0000000000..1b75175edc --- /dev/null +++ b/include/dt-bindings/power/xlnx-versal-power.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 - 2020 Xilinx, Inc. + */ + +#ifndef _DT_BINDINGS_VERSAL_POWER_H +#define _DT_BINDINGS_VERSAL_POWER_H + +#define PM_DEV_USB_0 (0x18224018U) +#define PM_DEV_GEM_0 (0x18224019U) +#define PM_DEV_GEM_1 (0x1822401aU) +#define PM_DEV_SPI_0 (0x1822401bU) +#define PM_DEV_SPI_1 (0x1822401cU) +#define PM_DEV_I2C_0 (0x1822401dU) +#define PM_DEV_I2C_1 (0x1822401eU) +#define PM_DEV_CAN_FD_0 (0x1822401fU) +#define PM_DEV_CAN_FD_1 (0x18224020U) +#define PM_DEV_UART_0 (0x18224021U) +#define PM_DEV_UART_1 (0x18224022U) +#define PM_DEV_GPIO (0x18224023U) +#define PM_DEV_TTC_0 (0x18224024U) +#define PM_DEV_TTC_1 (0x18224025U) +#define PM_DEV_TTC_2 (0x18224026U) +#define PM_DEV_TTC_3 (0x18224027U) +#define PM_DEV_SWDT_FPD (0x18224029U) +#define PM_DEV_OSPI (0x1822402aU) +#define PM_DEV_QSPI (0x1822402bU) +#define PM_DEV_GPIO_PMC (0x1822402cU) +#define PM_DEV_SDIO_0 (0x1822402eU) +#define PM_DEV_SDIO_1 (0x1822402fU) +#define PM_DEV_RTC (0x18224034U) +#define PM_DEV_ADMA_0 (0x18224035U) +#define PM_DEV_ADMA_1 (0x18224036U) +#define PM_DEV_ADMA_2 (0x18224037U) +#define PM_DEV_ADMA_3 (0x18224038U) +#define PM_DEV_ADMA_4 (0x18224039U) +#define PM_DEV_ADMA_5 (0x1822403aU) +#define PM_DEV_ADMA_6 (0x1822403bU) +#define PM_DEV_ADMA_7 (0x1822403cU) +#define PM_DEV_AI (0x18224072U) + +#endif -- cgit From 305d31885f2f35db486594d051d9aa3a4ed201c5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 28 Jul 2020 12:51:08 +0200 Subject: dm: core: Add support for getting node from aliases Add support for getting a node/property from aliases. The similar functionality is provided for chosen node and this implemenatation is copy of it. Signed-off-by: Michal Simek Reviewed-by: Simon Glass --- include/dm/ofnode.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'include') diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index 4b7af37056..ced7f6ffb2 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -605,6 +605,28 @@ const char *ofnode_read_chosen_string(const char *propname); */ ofnode ofnode_get_chosen_node(const char *propname); +/** + * ofnode_read_aliases_prop() - get the value of a aliases property + * + * This looks for a property within the /aliases node and returns its value + * + * @propname: Property name to look for + * @sizep: Returns size of property, or FDT_ERR_... error code if function + * returns NULL + * @return property value if found, else NULL + */ +const void *ofnode_read_aliases_prop(const char *propname, int *sizep); + +/** + * ofnode_get_aliases_node() - get a referenced node from the aliases node + * + * This looks up a named property in the aliases node and uses that as a path to + * look up a code. + * + * @return the referenced node if present, else ofnode_null() + */ +ofnode ofnode_get_aliases_node(const char *propname); + struct display_timing; /** * ofnode_decode_display_timing() - decode display timings -- cgit From c2a2c83278666cacb85761b8db55a3de8031c459 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 22 Oct 2020 10:59:08 +0200 Subject: xilinx: zynq: Change types from u32 to uint32_t MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change parameter type to avoid compilation error: In file included from ./tools/../lib/rsa/rsa-verify.c:23:0, from tools/lib/rsa/rsa-verify.c:1: include/u-boot/rsa-mod-exp.h:69:18: error: unknown type name ‘u32’; did you mean ‘__u32’? int zynq_pow_mod(u32 *keyptr, u32 *inout); ^~~ __u32 include/u-boot/rsa-mod-exp.h:69:31: error: unknown type name ‘u32’; did you mean ‘__u32’? int zynq_pow_mod(u32 *keyptr, u32 *inout); ^~~ __u32 Fixes: 37e3a36a5475 ("xilinx: zynq: Add support to secure images") Signed-off-by: Michal Simek --- include/u-boot/rsa-mod-exp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/u-boot/rsa-mod-exp.h b/include/u-boot/rsa-mod-exp.h index 1da8af1bb8..7b7c2915a9 100644 --- a/include/u-boot/rsa-mod-exp.h +++ b/include/u-boot/rsa-mod-exp.h @@ -66,7 +66,7 @@ int rsa_mod_exp(struct udevice *dev, const uint8_t *sig, uint32_t sig_len, struct key_prop *node, uint8_t *out); #if defined(CONFIG_CMD_ZYNQ_RSA) -int zynq_pow_mod(u32 *keyptr, u32 *inout); +int zynq_pow_mod(uint32_t *keyptr, uint32_t *inout); #endif /** -- cgit From f2b03760104acf7ede36fc9958aa2dee3b8238ae Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 22 Oct 2020 10:37:00 +0200 Subject: xilinx: Remove additional newline in config files Trivial fix. Fixes: e519f03a1846 ("cmd: mem: Remove CONFIG_SYS_MEMTEST_SCRATCH mapping") Signed-off-by: Michal Simek --- include/configs/xilinx_versal.h | 1 - include/configs/xilinx_versal_mini.h | 1 - include/configs/xilinx_zynqmp_mini.h | 1 - 3 files changed, 3 deletions(-) (limited to 'include') diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index 8b416327b5..f1d2594f3b 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -18,7 +18,6 @@ #define GICD_BASE 0xF9000000 #define GICR_BASE 0xF9080000 - #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE /* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */ diff --git a/include/configs/xilinx_versal_mini.h b/include/configs/xilinx_versal_mini.h index 0b201a2b4d..00c9718819 100644 --- a/include/configs/xilinx_versal_mini.h +++ b/include/configs/xilinx_versal_mini.h @@ -10,7 +10,6 @@ #ifndef __CONFIG_VERSAL_MINI_H #define __CONFIG_VERSAL_MINI_H - #define CONFIG_EXTRA_ENV_SETTINGS #include diff --git a/include/configs/xilinx_zynqmp_mini.h b/include/configs/xilinx_zynqmp_mini.h index 3f57423b78..ef9c768e48 100644 --- a/include/configs/xilinx_zynqmp_mini.h +++ b/include/configs/xilinx_zynqmp_mini.h @@ -10,7 +10,6 @@ #ifndef __CONFIG_ZYNQMP_MINI_H #define __CONFIG_ZYNQMP_MINI_H - #define CONFIG_EXTRA_ENV_SETTINGS #include -- cgit From 7a49a16ec54e03ea6a383c1b97a78acc059c2df8 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Fri, 23 Oct 2020 04:58:57 -0600 Subject: Revert "mmc: zynq: parse dt when probing" This reverts commit 942b5fc03218d1c94468fc658e7dec65dabcc830. This is partial revert of the above commit. mmc_of_parse() is reading no-1-8-v from device tree and if set, it is clearing the UHS speed capabilities of cfg->host_caps. cfg->host_caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400 | MMC_MODE_HS400_ES); This is still missing to clear UHS speeds like SDHCI_SUPPORT_SDR104, SDHCI_SUPPORT_SDR50 and SDHCI_SUPPORT_DDR50. Even if we clear the flags SDHCI_SUPPORT_XXX in mmc_of_parse(), these speed flags are getting set again in cfg->host_caps in sdhci_setup_cfg(). The reason for this is, SDHCI_SUPPORT_XXX flags are cleared only if controller is not capable of supporting MMC_VDD_165_195 volts. if (caps & SDHCI_CAN_VDD_180) cfg->voltages |= MMC_VDD_165_195; if (!(cfg->voltages & MMC_VDD_165_195)) caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); It means "no-1-8-v", which is read from DT is not coming in to effect. So it is better we keep the host quirks(SDHCI_QUIRK_NO_1_8_V) to clear UHS speeds based on no-1-8-v from device tree. Hence revert the functionality related to no-1-8-v only, rest is fine in the patch. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek Reviewed-by: Jaehoon Chung Reviewed-by: Peng Fan --- include/sdhci.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/sdhci.h b/include/sdhci.h index f69d5f81fb..1fd20ec086 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -244,6 +244,7 @@ #define SDHCI_QUIRK_BROKEN_HISPD_MODE BIT(5) #define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6) #define SDHCI_QUIRK_USE_WIDE8 (1 << 8) +#define SDHCI_QUIRK_NO_1_8_V (1 << 9) /* to make gcc happy */ struct sdhci_host; -- cgit From 17a42abb40dd006b5f0e96d69e4894bef4c04ba8 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Fri, 23 Oct 2020 04:58:58 -0600 Subject: mmc: Define timing macro's Define timing macro's for all the available speeds of mmc. This is done similar to linux. Replace speed macro's used with these new timing macro's wherever applicable. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek Reviewed-by: Peng Fan --- include/mmc.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'include') diff --git a/include/mmc.h b/include/mmc.h index ac7b54f1a7..1d377e0281 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -360,6 +360,19 @@ enum mmc_voltage { #define MMC_NUM_BOOT_PARTITION 2 #define MMC_PART_RPMB 3 /* RPMB partition number */ +/* timing specification used */ +#define MMC_TIMING_LEGACY 0 +#define MMC_TIMING_MMC_HS 1 +#define MMC_TIMING_SD_HS 2 +#define MMC_TIMING_UHS_SDR12 3 +#define MMC_TIMING_UHS_SDR25 4 +#define MMC_TIMING_UHS_SDR50 5 +#define MMC_TIMING_UHS_SDR104 6 +#define MMC_TIMING_UHS_DDR50 7 +#define MMC_TIMING_MMC_DDR52 8 +#define MMC_TIMING_MMC_HS200 9 +#define MMC_TIMING_MMC_HS400 10 + /* Driver model support */ /** -- cgit From 728d21b8c75e3c13a19b4a555d08a4478efa8fe6 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Fri, 23 Oct 2020 04:59:04 -0600 Subject: mmc: zynq_sdhci: Add common function to set input/output tapdelays Remove setting tapdelays for different speeds separately. Instead use the ITAP and OTAP delay values which are read from the device tree. If the DT does not contain tap delay values, the predefined values will be used for the same. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek Reviewed-by: Peng Fan --- include/zynqmp_tap_delay.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/zynqmp_tap_delay.h b/include/zynqmp_tap_delay.h index b07e3e0692..7b713438f7 100644 --- a/include/zynqmp_tap_delay.h +++ b/include/zynqmp_tap_delay.h @@ -10,10 +10,11 @@ #ifdef CONFIG_ARCH_ZYNQMP void zynqmp_dll_reset(u8 deviceid); -void arasan_zynqmp_set_tapdelay(u8 device_id, u8 uhsmode, u8 bank); +void arasan_zynqmp_set_tapdelay(u8 device_id, u32 itap_delay, u32 otap_delay); #else inline void zynqmp_dll_reset(u8 deviceid) {} -inline void arasan_zynqmp_set_tapdelay(u8 device_id, u8 uhsmode, u8 bank) {} +inline void arasan_zynqmp_set_tapdelay(u8 device_id, u32 itap_delay, + u32 otap_delay) {} #endif #endif -- cgit