From 0693923cd240f5d401be0a53cddcf0fb1d9ad9d3 Mon Sep 17 00:00:00 2001 From: Albert Aribaud Date: Mon, 11 Oct 2010 13:13:29 +0200 Subject: edminiv2: add support for ELF relocations Signed-off-by: Albert Aribaud --- include/configs/edminiv2.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index ccfc66053b..43e5e870f0 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -223,4 +223,9 @@ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 #define CONFIG_SYS_MAXARGS 16 +/* additions for new relocation code, must be added to all boards */ +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - CONFIG_SYS_GBL_DATA_SIZE) + #endif /* _CONFIG_EDMINIV2_H */ -- cgit From 9710504d200599a6e7e7ac0046adca43cfccaf0f Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 11 Oct 2010 14:08:14 +0200 Subject: arm926ejs, tx25: add support for ELF relocations Signed-off-by: Heiko Schocher --- include/configs/tx25.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/tx25.h b/include/configs/tx25.h index bcc8140df0..996afa3b07 100644 --- a/include/configs/tx25.h +++ b/include/configs/tx25.h @@ -41,7 +41,7 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 -#define CONFIG_SYS_NAND_U_BOOT_DST (0x81fc0000) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x81200000) #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST #define CONFIG_SYS_NAND_PAGE_SIZE 2048 -- cgit From ff9f475d5d46da7e4acf523a61aef65638765670 Mon Sep 17 00:00:00 2001 From: Jason Liu Date: Mon, 18 Oct 2010 11:09:26 +0800 Subject: MX5: rename mx51 to mx5 Rename mx51 to mx5 in order to support more mx51 like-style SOCs such as MX53 and the followings. Signed-off-by: Jason Liu --- include/configs/mx51evk.h | 4 ++-- include/configs/vision2.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 8864f3ab78..6165473270 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -30,8 +30,8 @@ #define CONFIG_MX51 /* in a mx51 */ #define CONFIG_SKIP_RELOCATE_UBOOT -#define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */ -#define CONFIG_MX51_CLK32 32768 +#define CONFIG_SYS_MX5_HCLK 24000000 +#define CONFIG_SYS_MX5_CLK32 32768 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/vision2.h b/include/configs/vision2.h index 44a6f8be69..a2ecbe50d6 100644 --- a/include/configs/vision2.h +++ b/include/configs/vision2.h @@ -29,8 +29,8 @@ #define CONFIG_MX51 /* in a mx51 */ #define CONFIG_L2_OFF -#define CONFIG_MX51_HCLK_FREQ 24000000 -#define CONFIG_MX51_CLK32 32768 +#define CONFIG_SYS_MX5_HCLK 24000000 +#define CONFIG_SYS_MX5_CLK32 32768 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -- cgit From c8d76eaf606096eddbe62b8a86545f5116f5189c Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 18 Oct 2010 23:43:37 +0200 Subject: Rename TEXT_BASE: fix merge conflicts Commit 14d0a02a "Rename TEXT_BASE into CONFIG_SYS_TEXT_BASE" missed a few places, especially for boards that were added inbetween. Fix the remaining issues. Signed-off-by: Wolfgang Denk --- include/configs/a4m072.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h index 6dcebe6f44..24a04ebefb 100644 --- a/include/configs/a4m072.h +++ b/include/configs/a4m072.h @@ -37,6 +37,8 @@ #define CONFIG_A4M072 1 /* ... on A4M072 board */ #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ +#define CONFIG_SYS_TEXT_BASE 0xFE000000 + #define CONFIG_MISC_INIT_R #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ @@ -125,7 +127,7 @@ #define CONFIG_CMD_PCI #endif -#if (TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */ +#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */ #define CONFIG_SYS_LOWBOOT 1 #define CONFIG_SYS_LOWBOOT32 1 #endif @@ -238,7 +240,7 @@ #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) # define CONFIG_SYS_RAMBOOT 1 #endif -- cgit From 68a75d0b544fb8e7efb85bed1597285f61186cef Mon Sep 17 00:00:00 2001 From: Magnus Lilja Date: Sat, 16 Oct 2010 19:47:06 +0200 Subject: i.MX31: Fix Litekit board to use new ARM relocation support. Tested on hardware. Boots Linux nicely. Signed-off-by: Magnus Lilja --- include/configs/imx31_litekit.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include') diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index 88c62d11e1..94252371bc 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -147,6 +147,13 @@ #define PHYS_SDRAM_1 CSD0_BASE #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) +#undef CONFIG_SYS_ARM_WITHOUT_RELOC +#define CONFIG_SYS_SDRAM_BASE CSD0_BASE +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_END IRAM_SIZE +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) + /*----------------------------------------------------------------------- * FLASH and environment organization */ -- cgit From b952c24adeb7bfdb09f60d5d1f49fa86a2686c1c Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 19 Oct 2010 11:10:06 +0200 Subject: QONG: fix and update board config file Fix flash memory map and other updates for QONG board: - adjust/fix "kernel_addr" settings - adjust/fix mtdparts NOR flash settings - add mtdparts NAND flash mapping - sort command list - enable "setexpr" command - enable ext2 support - delete bogus comment Signed-off-by: Wolfgang Denk Cc: Stefano Babic --- include/configs/qong.h | 32 ++++++++++++++------------------ 1 file changed, 14 insertions(+), 18 deletions(-) (limited to 'include') diff --git a/include/configs/qong.h b/include/configs/qong.h index f26ced1d7f..426d90d7de 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -102,6 +102,7 @@ #define CONFIG_USB_STORAGE #define CONFIG_DOS_PARTITION #define CONFIG_SUPPORT_VFAT +#define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #endif /* CONFIG_CMD_USB */ @@ -124,25 +125,16 @@ #include #define CONFIG_CMD_CACHE -#define CONFIG_CMD_PING +#define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_NET #define CONFIG_CMD_MII #define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR #define CONFIG_CMD_SPI -#define CONFIG_CMD_DATE -#define BOARD_LATE_INIT -/* - * You can compile in a MAC address and your custom net settings by using - * the following syntax. - * - * #define CONFIG_ETHADDR xx:xx:xx:xx:xx:xx - * #define CONFIG_SERVERIP - * #define CONFIG_IPADDR - * #define CONFIG_GATEWAYIP - * #define CONFIG_NETMASK - */ +#define BOARD_LATE_INIT #define CONFIG_BOOTDELAY 5 @@ -164,7 +156,7 @@ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ "addmisc=setenv bootargs ${bootargs}\0" \ "uboot_addr=A0000000\0" \ - "kernel_addr=A00A0000\0" \ + "kernel_addr=A00C0000\0" \ "ramdisk_addr=A0300000\0" \ "u-boot=qong/u-boot.bin\0" \ "kernel_addr_r=80800000\0" \ @@ -296,10 +288,14 @@ extern int qong_nand_rdy(void *chip); #define CONFIG_LZO #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ #define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=physmap-flash.0" +#define MTDIDS_DEFAULT "nor0=physmap-flash.0," \ + "nand0=gen_nand" #define MTDPARTS_DEFAULT \ - "mtdparts=physmap-flash.0:384k(U-Boot),128k(env1)," \ - "128k(env2),2432k(kernel),13m(ramdisk),-(user)" + "mtdparts=physmap-flash.0:" \ + "512k(U-Boot),128k(env1),128k(env2)," \ + "2304k(kernel),13m(ramdisk),-(user);" \ + "gen_nand:" \ + "128m(nand)" /* additions for new relocation code, must be added to all boards */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -- cgit From 333d86d15af8c94f0bf45b5dc5eeae05b64a2163 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 19 Oct 2010 11:27:05 +0200 Subject: NC650/CP850: remove code for yet another corpse The NC650 / CP850 boards have long been unmaintained and left broken. As obviously nobody is interested in that code any more, we may as well remove it. Signed-off-by: Wolfgang Denk --- include/configs/NC650.h | 451 ------------------------------------------------ 1 file changed, 451 deletions(-) delete mode 100644 include/configs/NC650.h (limited to 'include') diff --git a/include/configs/NC650.h b/include/configs/NC650.h deleted file mode 100644 index df1c1ca427..0000000000 --- a/include/configs/NC650.h +++ /dev/null @@ -1,451 +0,0 @@ -/* - * (C) Copyright 2006, 2007 Detlev Zundel, dzu@denx.de - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC852T 1 -#define CONFIG_NC650 1 - -#define CONFIG_SYS_TEXT_BASE 0x40700000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -/* - * 10 MHz - PLL input clock - */ -#define CONFIG_8xx_OSCLK 10000000 - -/* - * 50 MHz - default CPU clock - */ -#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 - -/* - * 15 MHz - CPU minimum clock - */ -#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 - -/* - * 133 MHz - CPU maximum clock - */ -#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 - -#define CONFIG_SYS_MEASURE_CPUCLK -#define CONFIG_SYS_8XX_XIN CONFIG_8xx_OSCLK - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "\nEnter password - autoboot in %d seconds...\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "ids" -#define CONFIG_BOOT_RETRY_TIME 900 -#define CONFIG_BOOT_RETRY_MIN 30 - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" - -#define CONFIG_WATCHDOG /* watchdog enabled */ - -#undef CONFIG_STATUS_LED /* Status LED disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ -#define FEC_ENET -#define CONFIG_MII -#define CONFIG_SYS_DISCOVER_PHY 1 - - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7f - -/* - * Software (bit-bang) I2C driver configuration - */ -#if defined(CONFIG_IDS852_REV1) - -#define SCL 0x1000 /* PA 3 */ -#define SDA 0x2000 /* PA 2 */ - -#define __I2C_DIR immr->im_ioport.iop_padir -#define __I2C_DAT immr->im_ioport.iop_padat -#define __I2C_PAR immr->im_ioport.iop_papar - -#elif defined(CONFIG_IDS852_REV2) - -#define SCL 0x0002 /* PB 30 */ -#define SDA 0x0001 /* PB 31 */ - -#define __I2C_PAR immr->im_cpm.cp_pbpar -#define __I2C_DIR immr->im_cpm.cp_pbdir -#define __I2C_DAT immr->im_cpm.cp_pbdat - -#endif - -#define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \ - __I2C_DIR |= (SDA|SCL); } -#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0) -#define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; } -#define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; } -#define I2C_DELAY { udelay(5); } -#define I2C_ACTIVE { __I2C_DIR |= SDA; } -#define I2C_TRISTATE { __I2C_DIR &= ~SDA; } - -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_NAND -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 -#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x00740000 - -#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/* - * NAND flash support - */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ - SCCR_DFLCD000 | SCCR_DFALCD00) - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ - -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: Default value of OR0 after reset */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ - OR_SCY_15_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V) - -/* - * BR2 and OR2 (NAND Flash) - addressed through UPMB on rev 1 - * rev2 only uses the chipselect - */ -#define CONFIG_SYS_NAND_BASE 0x50000000 -#define CONFIG_SYS_NAND_SIZE 0x04000000 - -#define CONFIG_SYS_OR_TIMING_NAND (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ - OR_SCY_15_CLK | OR_EHTR | OR_TRLX) - -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_UPMB | BR_V ) -#define CONFIG_SYS_OR2_PRELIM (((-CONFIG_SYS_NAND_SIZE) & OR_AM_MSK) | OR_BI ) - -/* - * BR3 and OR3 (SDRAM) - */ -#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - - /* - * SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) - */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR3_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM) -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V) - -/* - * BR4 and OR4 (CPLD) - */ -#define CONFIG_SYS_CPLD_BASE 0x80000000 /* CPLD */ -#define CONFIG_SYS_CPLD_SIZE 0x10000 /* only 16 used */ - -#define CONFIG_SYS_OR_TIMING_CPLD (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ - OR_SCY_1_CLK) - -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_CPLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) -#define CONFIG_SYS_OR4_PRELIM (((-CONFIG_SYS_CPLD_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_CPLD) - -/* - * BR5 and OR5 (SRAM) - */ -#define CONFIG_SYS_SRAM_BASE 0x60000000 -#define CONFIG_SYS_SRAM_SIZE 0x00080000 - -#define CONFIG_SYS_OR_TIMING_SRAM (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ - OR_SCY_15_CLK | OR_EHTR | OR_TRLX) - -#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) -#define CONFIG_SYS_OR5_PRELIM (((-CONFIG_SYS_SRAM_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_SRAM) - -#if defined(CONFIG_CP850) -/* - * BR6 and OR6 (DPRAM) - only on CP850 - */ -#define CONFIG_SYS_OR6_PRELIM 0xffff8170 -#define CONFIG_SYS_BR6_PRELIM 0xa0000401 -#define DPRAM_BASE_ADDR 0xa0000000 - -#define CONFIG_MISC_INIT_R 1 -#endif - -/* - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - */ -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 39 - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* - * MBMR settings for NAND flash - */ - -#define CONFIG_SYS_MBMR_NAND ( MBMR_WLFB_5X ) - -#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ -#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */ - -/* - * JFFS2 partitions - */ - -/* No command line, one static partition */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nand0" -#define CONFIG_JFFS2_PART_SIZE 0x00400000 -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor0=nc650-0,nand0=nc650-nand" - -#define MTDPARTS_DEFAULT "mtdparts=nc650-0:1m(kernel1),1m(kernel2)," \ - "4m(cramfs1),1m(cramfs2)," \ - "256k(u-boot),128k(env);" \ - "nc650-nand:4m(jffs1),28m(jffs2)" - -#endif /* __CONFIG_H */ -- cgit From 99fa97e955f642deedb9f2de38e0215a8b3a40ac Mon Sep 17 00:00:00 2001 From: Andreas Bießmann Date: Mon, 18 Oct 2010 22:58:29 +0200 Subject: at91rm9200ek: convert to at91 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch removes some functionality from at91rm9200ek board but the remaining functionality does now work with newer at91 code and arm-relocation. Currently missing features are: - dataflash booting (due to missing HW for testing) - MMC/SD-Card - first stage bootloader support is completely removed (not needed for NOR) Cause this board was (some days ago) reference for all at91rm9200 based boards this should be a good starting point to convert all remaining at91rm9200 borads to at91 code. Aside from that this is a good base to get some drivers between at91sam/at91rm/avr32 merged. Signed-off-by: Andreas Bießmann Signed-off-by: Reinhard Meyer --- include/configs/at91rm9200ek.h | 275 +++++++++++------------------------------ 1 file changed, 74 insertions(+), 201 deletions(-) (limited to 'include') diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h index 145c3c37da..6b2dd63b47 100644 --- a/include/configs/at91rm9200ek.h +++ b/include/configs/at91rm9200ek.h @@ -1,4 +1,8 @@ /* + * Copyright (C) 2010 Andreas Bießmann + * + * based on previous work by + * * Ulf Samuelsson * Rick Bronson * @@ -23,40 +27,52 @@ * MA 02111-1307 USA */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __AT91RM9200EK_CONFIG_H__ +#define __AT91RM9200EK_CONFIG_H__ -#define CONFIG_AT91_LEGACY +#include -/* ARM asynchronous clock */ -/* - * from 18.432 MHz crystal - * (18432000 / 4 * 39) - */ -#define AT91C_MAIN_CLOCK 179712000 /* - * peripheral clock - * (AT91C_MASTER_CLOCK / 3) + * AT91C_XTAL_CLOCK is the frequency of external xtal in hertz + * AT91C_MAIN_CLOCK is the frequency of PLLA output + * AT91C_MASTER_CLOCK is the peripherial clock + * CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely + * set in arch/arm/cpu/arm920t/at91/timer.c) + * CONFIG_SYS_HZ is the tick rate for timer tc0 */ -#define AT91C_MASTER_CLOCK 59904000 +#define AT91C_XTAL_CLOCK 18432000 +#define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39) +#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3 ) +#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) +#define CONFIG_SYS_HZ 1000 -#define AT91_SLOW_CLOCK 32768 /* slow clock */ +/* CPU configuration */ +#define CONFIG_ARM920T +#define CONFIG_AT91RM9200 +#define CONFIG_AT91RM9200EK +#define CONFIG_CPUAT91 +#define USE_920T_MMU -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ -#define CONFIG_AT91RM9200EK 1 /* on an AT91RM9200EK Board */ -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define USE_920T_MMU 1 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* + * Memory Configuration + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE SZ_32M -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END \ + (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K) /* * LowLevel Init */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 +#define CONFIG_SYS_USE_MAIN_OSCILLATOR /* flash */ #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ @@ -73,50 +89,26 @@ #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 #define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ #define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */ +#define CONFIG_SYS_SDRAM1 CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */ #define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ #define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ -#else -#define CONFIG_SKIP_RELOCATE_UBOOT #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ -/* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */ -#define CONFIG_SYS_AT91C_BRGR_DIVISOR 33 - -/* - * Memory Configuration - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x02000000 /* 32 megs */ - -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END \ - (CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144) - /* * Hardware drivers */ - /* - * UART Configuration - * - * define one of these to choose the DBGU, - * USART0 or USART1 as console + * Choose a USART for serial console + * CONFIG_DBGU is DBGU unit on J10 + * CONFIG_USART1 is USART1 on J14 */ #define CONFIG_AT91RM9200_USART #define CONFIG_DBGU -#undef CONFIG_USART0 -#undef CONFIG_USART1 -/* don't include RTS/CTS flow control support */ -#undef CONFIG_HWFLOW -/* disable modem initialization stuff */ -#undef CONFIG_MODEM_SUPPORT #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } #define CONFIG_BAUDRATE 115200 @@ -130,156 +122,60 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_MII #define CONFIG_CMD_PING - -#undef CONFIG_CMD_BDI -#undef CONFIG_CMD_IMI #undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_MISC -#undef CONFIG_CMD_LOADS - -#include /* needed for port definitions */ -/* Options for MMC/SD Card */ -#define CONFIG_DOS_PARTITION 1 -#undef CONFIG_MMC -#define CONFIG_SYS_MMC_BASE 0xFFFB4000 -#define CONFIG_SYS_MMC_BLOCKSIZE 512 /* * Network Driver Setting */ -#define CONFIG_NET_MULTI 1 -#ifdef CONFIG_NET_MULTI -#define CONFIG_DRIVER_AT91EMAC 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 -#else -#define CONFIG_DRIVER_ETHER 1 -#endif -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_AT91C_USE_RMII - -/* - * AC Characteristics - * DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns - */ -#define DATAFLASH_TCSS (0xC << 16) -#define DATAFLASH_TCHS (0x1 << 24) - -#if defined(CONFIG_HAS_DATAFLASH) -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) -#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 -#define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384 -/* Logical adress for CS0 */ -#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 -/* Logical adress for CS3 */ -#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 -#define CONFIG_SYS_SUPPORT_BLOCK_ERASE 1 -#define CONFIG_SYS_DATAFLASH_MMC_PIO AT91C_PIO_PB22 -#endif +#define CONFIG_NET_MULTI +#define CONFIG_DRIVER_AT91EMAC +#define CONFIG_SYS_RX_ETH_BUFFER 16 +#define CONFIG_RMII +#define CONFIG_MII /* * NOR Flash */ -#define CONFIG_SYS_FLASH_BASE 0x10000000 -#define PHYS_FLASH_SIZE 0x800000 /* 8MB */ -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_BASE 0x10000000 +#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE +#define PHYS_FLASH_SIZE SZ_8M +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 #define CONFIG_SYS_FLASH_PROTECTION /* * Environment Settings */ -#ifdef CONFIG_ENV_IS_IN_DATAFLASH -/* - * Datasflash Environment Settings - */ -#define CONFIG_ENV_OFFSET 0x4200 -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) -/* 8 * 1056 really , but start.s is not OK with this*/ -#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_IS_IN_FLASH -#else -/* - * NOR Flash Environment Settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 - -#ifdef CONFIG_SKIP_LOWLEVEL_INIT -/* - * between boot.bin and u-boot.bin.gz - */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0xe000) -#define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */ -#else /* * after u-boot.bin */ #define CONFIG_ENV_ADDR \ (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */ +#define CONFIG_ENV_SIZE SZ_64K /* sectors are 64K here */ /* The following #defines are needed to get flash environment right */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN \ - (CONFIG_SYS_BOOT_SIZE + CONFIG_SYS_U_BOOT_SIZE) -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -#endif /* CONFIG_ENV_IS_IN_DATAFLASH */ +#define CONFIG_SYS_MONITOR_LEN SZ_256K /* * Boot option */ #define CONFIG_BOOTDELAY 3 -#ifdef CONFIG_SKIP_LOWLEVEL_INIT -/* boot.bin, env, u-boot.bin.gz */ -#define CONFIG_SYS_BOOT_SIZE 0x6000 /* 24 KBytes */ -#define CONFIG_SYS_U_BOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x10000) -#define CONFIG_SYS_U_BOOT_SIZE 0x10000 /* 64 KBytes */ -#else -/* u-boot.bin */ -#define CONFIG_SYS_BOOT_SIZE 0x0 /* 0 KBytes */ -#define CONFIG_SYS_U_BOOT_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_U_BOOT_SIZE 0x40000 /* 128 KBytes */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ -#define CONFIG_ENV_OVERWRITE 1 - -/* - * USB Config - */ -#define CONFIG_CMD_USB -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_USB_KEYBOARD 1 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_DOS_PARTITION 1 - -#undef CONFIG_SYS_USB_OHCI_BOARD_INIT -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 -#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 - -/* - * I2C - */ -#define CONFIG_HARD_I2C - -#ifdef CONFIG_HARD_I2C -#define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_SPEED 0 /* not used */ -#define CONFIG_SYS_I2C_SLAVE 0 /* not used */ -#endif +/* default load address */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_16M +#define CONFIG_ENV_OVERWRITE /* * Shell Settings */ -#define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT "U-Boot> " #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ @@ -288,41 +184,18 @@ #define CONFIG_SYS_PBSIZE \ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#ifndef __ASSEMBLY__ -/*----------------------------------------------------------------------- - * Board specific extension for bd_info - * - * This structure is embedded in the global bd_info (bd_t) structure - * and can be used by the board specific code (eg board/...) - */ - -struct bd_info_ext { - /* helper variable for board environment handling - * - * env_crc_valid == 0 => uninitialised - * env_crc_valid > 0 => environment crc in flash is valid - * env_crc_valid < 0 => environment crc in flash is invalid - */ - int env_crc_valid; -}; -#endif - -#define CONFIG_SYS_HZ 1000 -/* - * AT91C_TC0_CMR is implicitly set to - * AT91C_TC_TIMER_DIV1_CLOCK - */ -#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) - /* * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024 \ - , 0x1000) +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \ + SZ_4K) /* size in bytes reserved for initial data */ #define CONFIG_SYS_GBL_DATA_SIZE 128 -#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */ -#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* Unsure if to big or to small*/ -#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* Unsure if to big or to small*/ -#endif +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \ + - CONFIG_SYS_GBL_DATA_SIZE) + +#define CONFIG_STACKSIZE SZ_32K /* regular stack */ +#define CONFIG_STACKSIZE_IRQ SZ_4K /* Unsure if to big or to small*/ +#define CONFIG_STACKSIZE_FIQ SZ_4K /* Unsure if to big or to small*/ +#endif /* __AT91RM9200EK_CONFIG_H__ */ -- cgit From 3b83522bcf99bb4cdf1b792f391e3b93b6ed5ce5 Mon Sep 17 00:00:00 2001 From: Andreas Bießmann Date: Mon, 18 Oct 2010 22:58:31 +0200 Subject: at91rm9200ek: enbable USB support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch enables USB for at91rm9200ek board. Signed-off-by: Andreas Bießmann Signed-off-by: Reinhard Meyer --- include/configs/at91rm9200ek.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'include') diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h index 6b2dd63b47..b386057c0e 100644 --- a/include/configs/at91rm9200ek.h +++ b/include/configs/at91rm9200ek.h @@ -122,6 +122,7 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_MII #define CONFIG_CMD_PING +#define CONFIG_CMD_USB #undef CONFIG_CMD_FPGA /* @@ -145,6 +146,20 @@ #define CONFIG_SYS_MAX_FLASH_SECT 256 #define CONFIG_SYS_FLASH_PROTECTION +/* + * USB Config + */ +#define CONFIG_USB_ATMEL 1 +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_USB_KEYBOARD 1 +#define CONFIG_USB_STORAGE 1 +#define CONFIG_DOS_PARTITION 1 + +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 + /* * Environment Settings */ -- cgit From 3ba8bf7c6d6c09b9823b08b03d2d155907313238 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 9 Sep 2010 09:50:39 +0200 Subject: PXA: pxa-regs.h cleanup Signed-off-by: Marek Vasut --- include/configs/cradle.h | 2 -- include/configs/delta.h | 1 + include/configs/zylonite.h | 1 + 3 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/cradle.h b/include/configs/cradle.h index 200b61e0c7..998e179208 100644 --- a/include/configs/cradle.h +++ b/include/configs/cradle.h @@ -339,8 +339,6 @@ #define LED_IRDA1 2 #define LED_IRDA2 4 #define LED_IRDA3 6 -#define CRADLE_LED_SET_REG GPSR2 -#define CRADLE_LED_CLR_REG GPCR2 /* SuperIO defines */ #define CRADLE_SIO_INDEX 0x2e diff --git a/include/configs/delta.h b/include/configs/delta.h index 9c46c5bdbc..d930fb4b2b 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -28,6 +28,7 @@ * (easy to change) */ #define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */ +#define CONFIG_CPU_PXA320 #define CONFIG_DELTA 1 /* Delta board */ /* #define CONFIG_LCD 1 */ diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h index d0fc13888e..c8aa0461f6 100644 --- a/include/configs/zylonite.h +++ b/include/configs/zylonite.h @@ -35,6 +35,7 @@ * (easy to change) */ #define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */ +#define CONFIG_CPU_PXA320 #define CONFIG_ZYLONITE 1 /* Zylonite board */ /* #define CONFIG_LCD 1 */ -- cgit From aaa2a2fc9b81e0619da85244f5e9193a0a60003a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 18 Jul 2010 05:23:19 +0200 Subject: PXA: Palm Tungsten|C Support This patch adds support for the Palm Tungsten|C PXA255 board. The support includes: - LCD - MMC - UART - NOR Signed-off-by: Marek Vasut --- include/configs/palmtc.h | 245 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 245 insertions(+) create mode 100644 include/configs/palmtc.h (limited to 'include') diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h new file mode 100644 index 0000000000..f4fc9cd50d --- /dev/null +++ b/include/configs/palmtc.h @@ -0,0 +1,245 @@ +/* + * Palm Tungsten|C configuration file + * + * Copyright (C) 2009-2010 Marek Vasut + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* + * High Level Board Configuration Options + */ +#define CONFIG_PXA250 1 /* Intel PXA255 CPU */ +#define CONFIG_PALMTC 1 /* Palm Tungsten|C board */ + +/* + * Environment settings + */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_MALLOC_LEN (128*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +#define CONFIG_BOOTCOMMAND \ + "if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \ + "source 0xa0000000; " \ + "else " \ + "bootm 0x80000; " \ + "fi; " +#define CONFIG_BOOTARGS \ + "console=tty0 console=ttyS0,115200" +#define CONFIG_TIMESTAMP +#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS + +#define CONFIG_LZMA /* LZMA compression support */ + +/* + * Serial Console Configuration + * STUART - the lower serial port on Colibri board + */ +#define CONFIG_PXA_SERIAL +#define CONFIG_FFUART 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Bootloader Components Configuration + */ +#include + +#undef CONFIG_CMD_NET +#define CONFIG_CMD_ENV +#define CONFIG_CMD_MMC +#define CONFIG_LCD + +/* + * MMC Card Configuration + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_PXA_MMC +#define CONFIG_SYS_MMC_BASE 0xF0000000 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#endif + +/* + * LCD + */ +#ifdef CONFIG_LCD +#define CONFIG_ACX517AKN +#define CONFIG_VIDEO_LOGO +#define CONFIG_CMD_BMP +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) +#endif + +/* + * KGDB + */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * HUSH Shell Configuration + */ +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_SYS_LONGHELP +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "$ " +#else +#define CONFIG_SYS_PROMPT "=> " +#endif +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_DEVICE_NULLDEV 1 + +/* + * Clock Configuration + */ +#undef CONFIG_SYS_CLKS_IN_HZ +#define CONFIG_SYS_HZ 3686400 /* Timer @ 3686400 Hz */ +#define CONFIG_SYS_CPUSPEED 0x161 /* 400MHz;L=1 M=3 T=1 */ + +/* + * Stack sizes + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * DRAM Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ +#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ + +#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE + +/* + * NOR FLASH + */ +#ifdef CONFIG_CMD_FLASH +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 64 + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 + +#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_PROTECTION + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x40000 +#else +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_NOWHERE +#endif + +#define CONFIG_SYS_MONITOR_BASE 0x0 +#define CONFIG_SYS_MONITOR_LEN 0x40000 + +#define CONFIG_ENV_SIZE 0x4000 +#define CONFIG_ENV_ADDR 0x40000 + +/* + * GPIO settings + */ +#define CONFIG_SYS_GAFR0_L_VAL 0x00011004 +#define CONFIG_SYS_GAFR0_U_VAL 0xa5000008 +#define CONFIG_SYS_GAFR1_L_VAL 0x60888050 +#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50aaa +#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa +#define CONFIG_SYS_GAFR2_U_VAL 0x00000000 +#define CONFIG_SYS_GPCR0_VAL 0x0 +#define CONFIG_SYS_GPCR1_VAL 0x0 +#define CONFIG_SYS_GPCR2_VAL 0x0 +#define CONFIG_SYS_GPDR0_VAL 0xcfff8140 +#define CONFIG_SYS_GPDR1_VAL 0xfcbfbef3 +#define CONFIG_SYS_GPDR2_VAL 0x0001ffff +#define CONFIG_SYS_GPSR0_VAL 0x00010f8f +#define CONFIG_SYS_GPSR1_VAL 0x00bf5de5 +#define CONFIG_SYS_GPSR2_VAL 0x03fe0800 + +#define CONFIG_SYS_PSSR_VAL PSSR_RDH + +/* Clock setup: + * CKEN[1] - PWM1 ; CKEN[6] - FFUART + * CKEN[12] - MMC ; CKEN[16] - LCD + */ +#define CONFIG_SYS_CKEN 0x00011042 +#define CONFIG_SYS_CCCR 0x00000161 + +/* + * Memory settings + */ +#define CONFIG_SYS_MSC0_VAL 0x800092c2 +#define CONFIG_SYS_MSC1_VAL 0x80008000 +#define CONFIG_SYS_MSC2_VAL 0x80008000 +#define CONFIG_SYS_MDCNFG_VAL 0x00001ac9 +#define CONFIG_SYS_MDREFR_VAL 0x00118018 +#define CONFIG_SYS_MDMRS_VAL 0x00220032 +#define CONFIG_SYS_FLYCNFG_VAL 0x01fe01fe +#define CONFIG_SYS_SXCNFG_VAL 0x00000000 + +/* + * PCMCIA and CF Interfaces + */ +#define CONFIG_SYS_MECR_VAL 0x00000000 +#define CONFIG_SYS_MCMEM0_VAL 0x00010504 +#define CONFIG_SYS_MCMEM1_VAL 0x00010504 +#define CONFIG_SYS_MCATT0_VAL 0x00010504 +#define CONFIG_SYS_MCATT1_VAL 0x00010504 +#define CONFIG_SYS_MCIO0_VAL 0x00010e04 +#define CONFIG_SYS_MCIO1_VAL 0x00010e04 + +#endif /* __CONFIG_H */ -- cgit From 6375dadab39991cca679b186f2949ccde5dac174 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 19 Jul 2010 11:23:07 +0200 Subject: PXA: Add initial Palm LifeDrive support Signed-off-by: Marek Vasut --- include/configs/palmld.h | 273 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 273 insertions(+) create mode 100644 include/configs/palmld.h (limited to 'include') diff --git a/include/configs/palmld.h b/include/configs/palmld.h new file mode 100644 index 0000000000..affc116b9f --- /dev/null +++ b/include/configs/palmld.h @@ -0,0 +1,273 @@ +/* + * Palm LifeDrive configuration file + * + * Copyright (C) 2010 Marek Vasut + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Board Configuration Options + */ +#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */ +#define CONFIG_PALMLD 1 /* Palm LifeDrive board */ + +/* + * Environment settings + */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_MALLOC_LEN (128*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +#define CONFIG_BOOTCOMMAND \ + "if mmcinfo && fatload mmc 0 0xa0000000 uboot.script ; then " \ + "source 0xa0000000; " \ + "else " \ + "bootm 0x0x60000; " \ + "fi; " +#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,9600" +#define CONFIG_TIMESTAMP +#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS + +#define CONFIG_LZMA /* LZMA compression support */ + +/* + * Serial Console Configuration + */ +#define CONFIG_PXA_SERIAL +#define CONFIG_FFUART 1 +#define CONFIG_BAUDRATE 9600 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Bootloader Components Configuration + */ +#include + +#undef CONFIG_CMD_NET +#define CONFIG_CMD_ENV +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_MMC +#define CONFIG_CMD_IDE +#define CONFIG_LCD + +/* + * MMC Card Configuration + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_PXA_MMC_GENERIC +#define CONFIG_SYS_MMC_BASE 0xF0000000 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#endif + +/* + * LCD + */ +#ifdef CONFIG_LCD +#define CONFIG_LQ038J7DH53 +#define CONFIG_VIDEO_LOGO +#define CONFIG_CMD_BMP +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) +#endif + +/* + * KGDB + */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * HUSH Shell Configuration + */ +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_SYS_LONGHELP +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "$ " +#else +#define CONFIG_SYS_PROMPT "=> " +#endif +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_DEVICE_NULLDEV 1 + +/* + * Clock Configuration + */ +#undef CONFIG_SYS_CLKS_IN_HZ +#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */ +#define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */ + +/* + * Stack sizes + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * DRAM Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ + +#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ +#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */ + +#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE + +/* + * NOR FLASH + */ +#ifdef CONFIG_CMD_FLASH +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x00080000 /* 512 KB */ +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER 1 + +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_FLASH_LEGACY_512Kx16 + +#define CONFIG_SYS_MONITOR_BASE 0 +#define CONFIG_SYS_MONITOR_LEN 0x40000 + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 + +#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_LOCK_TOUT (25*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_UNLOCK_TOUT (25*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_PROTECTION + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#else +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_NOWHERE +#endif + +#define CONFIG_ENV_ADDR 0x40000 +#define CONFIG_ENV_SIZE 0x4000 + +/* + * IDE + */ +#ifdef CONFIG_CMD_IDE +#define CONFIG_LBA48 +#undef CONFIG_IDE_LED +#undef CONFIG_IDE_RESET + +#define __io + +#define CONFIG_SYS_IDE_MAXBUS 1 +#define CONFIG_SYS_IDE_MAXDEVICE 1 + +#define CONFIG_SYS_ATA_BASE_ADDR 0x20000000 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0 + +#define CONFIG_SYS_ATA_DATA_OFFSET 0x10 +#define CONFIG_SYS_ATA_REG_OFFSET 0x10 +#define CONFIG_SYS_ATA_ALT_OFFSET 0x10 + +#define CONFIG_SYS_ATA_STRIDE 1 +#endif + +/* + * GPIO settings + */ +#define CONFIG_SYS_GAFR0_L_VAL 0x00000000 +#define CONFIG_SYS_GAFR0_U_VAL 0xa5180012 +#define CONFIG_SYS_GAFR1_L_VAL 0x69988056 +#define CONFIG_SYS_GAFR1_U_VAL 0xaaa580aa +#define CONFIG_SYS_GAFR2_L_VAL 0x6aaaaaaa +#define CONFIG_SYS_GAFR2_U_VAL 0x01040001 +#define CONFIG_SYS_GAFR3_L_VAL 0x540a950c +#define CONFIG_SYS_GAFR3_U_VAL 0x00000009 +#define CONFIG_SYS_GPCR0_VAL 0x00000000 +#define CONFIG_SYS_GPCR1_VAL 0x00000000 +#define CONFIG_SYS_GPCR2_VAL 0x00000000 +#define CONFIG_SYS_GPCR3_VAL 0x00000000 +#define CONFIG_SYS_GPDR0_VAL 0xc26b0000 +#define CONFIG_SYS_GPDR1_VAL 0xfcdfaa93 +#define CONFIG_SYS_GPDR2_VAL 0x7bbaffff +#define CONFIG_SYS_GPDR3_VAL 0x006ff38d +#define CONFIG_SYS_GPSR0_VAL 0x0d9e45ee +#define CONFIG_SYS_GPSR1_VAL 0x03affdae +#define CONFIG_SYS_GPSR2_VAL 0x07554000 +#define CONFIG_SYS_GPSR3_VAL 0x01bc0785 + +#define CONFIG_SYS_PSSR_VAL 0x30 + +/* + * Clock settings + */ +#define CONFIG_SYS_CKEN 0x01ffffff +#define CONFIG_SYS_CCCR 0x02000210 + +/* + * Memory settings + */ +#define CONFIG_SYS_MSC0_VAL 0x7ff844c8 +#define CONFIG_SYS_MSC1_VAL 0x7ff86ab4 +#define CONFIG_SYS_MSC2_VAL 0x7ff87ff8 +#define CONFIG_SYS_MDCNFG_VAL 0x0B880acd +#define CONFIG_SYS_MDREFR_VAL 0x201fa031 +#define CONFIG_SYS_MDMRS_VAL 0x00320032 +#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 +#define CONFIG_SYS_SXCNFG_VAL 0x40044004 + +/* + * PCMCIA and CF Interfaces + */ +#define CONFIG_SYS_MECR_VAL 0x00000003 +#define CONFIG_SYS_MCMEM0_VAL 0x0001c391 +#define CONFIG_SYS_MCMEM1_VAL 0x0001c391 +#define CONFIG_SYS_MCATT0_VAL 0x0001c391 +#define CONFIG_SYS_MCATT1_VAL 0x0001c391 +#define CONFIG_SYS_MCIO0_VAL 0x00014611 +#define CONFIG_SYS_MCIO1_VAL 0x0001c391 + +#endif /* __CONFIG_H */ -- cgit From f905432c04c54ef169b4ffe6dd310ddf72a67c86 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 22 Jul 2010 16:51:52 +0200 Subject: PXA: Voipac270 improvements 128MB NOR module support. Define __io to get harddrive working. Fix saving of environment into OneNAND. Boot from harddrive when possible. Add missing MAINTAINERS entry. Signed-off-by: Marek Vasut --- include/configs/vpac270.h | 106 ++++++++++++++++++++++++++-------------------- 1 file changed, 61 insertions(+), 45 deletions(-) (limited to 'include') diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index d3e22d9018..694a8f92c4 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -10,7 +10,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -19,8 +19,8 @@ * MA 02111-1307 USA */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __CONFIG_H +#define __CONFIG_H /* * High Level Board Configuration Options @@ -28,20 +28,13 @@ #define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */ #define CONFIG_VPAC270 1 /* Voipac PXA270 board */ -#undef BOARD_LATE_INIT -#undef CONFIG_SKIP_RELOCATE_UBOOT -#undef CONFIG_USE_IRQ -#undef CONFIG_SKIP_LOWLEVEL_INIT - /* * Environment settings */ -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_MALLOC_LEN (128*1024) #define CONFIG_SYS_GBL_DATA_SIZE 128 -#define CONFIG_ENV_OVERWRITE /* override default environment */ - #define CONFIG_BOOTCOMMAND \ "if mmc init && fatload mmc 0 0xa4000000 uImage; then " \ "bootm 0xa4000000; " \ @@ -49,6 +42,9 @@ "if usb reset && fatload usb 0 0xa4000000 uImage; then " \ "bootm 0xa4000000; " \ "fi; " \ + "if ide reset && fatload ide 0 0xa4000000 uImage; then " \ + "bootm 0xa4000000; " \ + "fi; " \ "bootm 0x40000;" #define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200" #define CONFIG_TIMESTAMP @@ -97,9 +93,9 @@ #define CONFIG_NET_MULTI 1 #define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DM9000_BASE 0x08000300 /* CS2 */ -#define DM9000_IO (CONFIG_DM9000_BASE) -#define DM9000_DATA (CONFIG_DM9000_BASE + 4) +#define CONFIG_DM9000_BASE 0x08000300 /* CS2 */ +#define DM9000_IO (CONFIG_DM9000_BASE) +#define DM9000_DATA (CONFIG_DM9000_BASE + 4) #define CONFIG_NET_RETRY_COUNT 10 #define CONFIG_BOOTP_BOOTFILESIZE @@ -116,6 +112,7 @@ #define CONFIG_PXA_MMC #define CONFIG_SYS_MMC_BASE 0xF0000000 #define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 #define CONFIG_DOS_PARTITION #endif @@ -123,8 +120,8 @@ * KGDB */ #ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* @@ -133,16 +130,17 @@ #define CONFIG_SYS_HUSH_PARSER 1 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LONGHELP #ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "$ " #else -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "=> " #endif -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_DEVICE_NULLDEV 1 /* @@ -150,12 +148,10 @@ */ #undef CONFIG_SYS_CLKS_IN_HZ #define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */ -#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */ +#define CONFIG_SYS_CPUSPEED 0x190 /* 312MHz */ /* * Stack sizes - * - * The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE (128*1024) /* regular stack */ #ifdef CONFIG_USE_IRQ @@ -166,17 +162,24 @@ /* * DRAM Map */ -#define CONFIG_NR_DRAM_BANKS 2 /* We have 2 banks of DRAM */ +#define CONFIG_NR_DRAM_BANKS 2 /* 2 banks of DRAM */ #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ + +#ifdef CONFIG_256M_U_BOOT #define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #2 */ #define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ +#endif #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ +#ifdef CONFIG_256M_U_BOOT #define CONFIG_SYS_DRAM_SIZE 0x10000000 /* 256 MB DRAM */ +#else +#define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */ +#endif -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ #define CONFIG_SYS_LOAD_ADDR (0x5c000000) @@ -185,14 +188,22 @@ */ #if defined(CONFIG_CMD_FLASH) /* NOR */ #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +#ifdef CONFIG_256M_U_BOOT #define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */ +#endif #define CONFIG_SYS_FLASH_CFI #define CONFIG_FLASH_CFI_DRIVER 1 #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) +#ifdef CONFIG_256M_U_BOOT #define CONFIG_SYS_MAX_FLASH_BANKS 2 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } +#else +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#endif #define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) #define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) @@ -200,25 +211,26 @@ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 #define CONFIG_SYS_FLASH_PROTECTION 1 -#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x4000 #elif defined(CONFIG_CMD_ONENAND) /* OneNAND */ #define CONFIG_SYS_NO_FLASH #define CONFIG_SYS_ONENAND_BASE 0x00000000 + #define CONFIG_ENV_IS_IN_ONENAND 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 #else /* No flash */ #define CONFIG_SYS_NO_FLASH #define CONFIG_SYS_ENV_IS_NOWHERE #endif -#define CONFIG_SYS_MONITOR_BASE 0x000000 +#define CONFIG_SYS_MONITOR_BASE 0x0 #define CONFIG_SYS_MONITOR_LEN 0x40000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SECT_SIZE 0x40000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#define CONFIG_ENV_ADDR 0x40000 +#define CONFIG_ENV_SIZE 0x4000 /* * IDE @@ -230,15 +242,15 @@ #define __io -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 +#define CONFIG_SYS_IDE_MAXBUS 1 +#define CONFIG_SYS_IDE_MAXDEVICE 1 -#define CONFIG_SYS_ATA_BASE_ADDR 0x0c000000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0 +#define CONFIG_SYS_ATA_BASE_ADDR 0x0c000000 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0 -#define CONFIG_SYS_ATA_DATA_OFFSET 0x120 -#define CONFIG_SYS_ATA_REG_OFFSET 0x120 -#define CONFIG_SYS_ATA_ALT_OFFSET 0x120 +#define CONFIG_SYS_ATA_DATA_OFFSET 0x120 +#define CONFIG_SYS_ATA_REG_OFFSET 0x120 +#define CONFIG_SYS_ATA_ALT_OFFSET 0x120 #define CONFIG_SYS_ATA_STRIDE 2 #endif @@ -284,7 +296,11 @@ #define CONFIG_SYS_MSC0_VAL 0x3ffc95fa #define CONFIG_SYS_MSC1_VAL 0x02ccf974 #define CONFIG_SYS_MSC2_VAL 0x00000000 +#ifdef CONFIG_256M_U_BOOT #define CONFIG_SYS_MDCNFG_VAL 0x8ad30ad3 +#else +#define CONFIG_SYS_MDCNFG_VAL 0x88000ad3 +#endif #define CONFIG_SYS_MDREFR_VAL 0x201fe01e #define CONFIG_SYS_MDMRS_VAL 0x00000000 #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 @@ -306,13 +322,13 @@ * LCD */ #ifdef CONFIG_LCD -#define CONFIG_VOIPAC_LCD +#define CONFIG_VOIPAC_LCD #endif /* * USB */ -#ifdef CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB #define CONFIG_USB_OHCI_NEW #define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_BOARD_INIT -- cgit From 10da95a13af7266cf1e6332e7abc37c0d5682b43 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 26 Jul 2010 06:30:25 +0200 Subject: PXA: Balloon3 board support The following hardware is currently supported: - UART - USB Host - FPGA Signed-off-by: Marek Vasut --- include/configs/balloon3.h | 269 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 269 insertions(+) create mode 100644 include/configs/balloon3.h (limited to 'include') diff --git a/include/configs/balloon3.h b/include/configs/balloon3.h new file mode 100644 index 0000000000..9066a24304 --- /dev/null +++ b/include/configs/balloon3.h @@ -0,0 +1,269 @@ +/* + * Balloon3 configuration file + * + * Copyright (C) 2010 Marek Vasut + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Board Configuration Options + */ +#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */ +#define CONFIG_BALLOON3 1 /* Balloon3 board */ + +/* + * Environment settings + */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_MALLOC_LEN (128*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +#define CONFIG_BOOTCOMMAND \ + "if usb reset && fatload usb 0 0xa4000000 uImage; then " \ + "bootm 0xa4000000; " \ + "fi; " \ + "bootm 0x40000;" +#define CONFIG_BOOTARGS "console=tty0 console=ttyS2,115200" +#define CONFIG_TIMESTAMP +#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS + +#define CONFIG_LZMA /* LZMA compression support */ + +/* + * Serial Console Configuration + */ +#define CONFIG_PXA_SERIAL +#define CONFIG_STUART 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Bootloader Components Configuration + */ +#include + +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_USB +#define CONFIG_CMD_FPGA +#undef CONFIG_LCD + +/* + * KGDB + */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * HUSH Shell Configuration + */ +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_SYS_LONGHELP +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "$ " +#else +#define CONFIG_SYS_PROMPT "=> " +#endif +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_DEVICE_NULLDEV 1 + +/* + * Clock Configuration + */ +#undef CONFIG_SYS_CLKS_IN_HZ +#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */ +#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */ + +/* + * Stack sizes + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * DRAM Map + */ +#define CONFIG_NR_DRAM_BANKS 3 /* 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ +#define PHYS_SDRAM_2 0xb0000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ +#define PHYS_SDRAM_3 0x80000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_3_SIZE 0x08000000 /* 128 MB */ + +#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ +#define CONFIG_SYS_DRAM_SIZE 0x18000000 /* 384 MB DRAM */ + +#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR 0xa1000000 + +/* + * NOR FLASH + */ +#ifdef CONFIG_CMD_FLASH +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 + +#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_ENV_IS_IN_FLASH +#else +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_ENV_IS_NOWHERE +#endif + +#define CONFIG_SYS_MONITOR_BASE 0x000000 +#define CONFIG_SYS_MONITOR_LEN 0x40000 + +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR 0x40000 +#define CONFIG_ENV_SECT_SIZE 0x10000 + +/* + * GPIO settings + */ +#define CONFIG_SYS_GPSR0_VAL 0x307dc7fd +#define CONFIG_SYS_GPSR1_VAL 0x03cffa4e +#define CONFIG_SYS_GPSR2_VAL 0x7131c000 +#define CONFIG_SYS_GPSR3_VAL 0x01e1f3ff + +#define CONFIG_SYS_GPCR0_VAL 0x0 +#define CONFIG_SYS_GPCR1_VAL 0x0 +#define CONFIG_SYS_GPCR2_VAL 0x0 +#define CONFIG_SYS_GPCR3_VAL 0x0 + +#define CONFIG_SYS_GPDR0_VAL 0xc0f98e02 +#define CONFIG_SYS_GPDR1_VAL 0xfcffa8b7 +#define CONFIG_SYS_GPDR2_VAL 0x22e3ffff +#define CONFIG_SYS_GPDR3_VAL 0x000201fe + +#define CONFIG_SYS_GAFR0_L_VAL 0x96c00000 +#define CONFIG_SYS_GAFR0_U_VAL 0xa5e5459b +#define CONFIG_SYS_GAFR1_L_VAL 0x699b759a +#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a5aa +#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa +#define CONFIG_SYS_GAFR2_U_VAL 0x01f9a6aa +#define CONFIG_SYS_GAFR3_L_VAL 0x54510003 +#define CONFIG_SYS_GAFR3_U_VAL 0x00001599 + +#define CONFIG_SYS_PSSR_VAL 0x30 + +/* + * Clock settings + */ +#define CONFIG_SYS_CKEN 0xffffffff +#define CONFIG_SYS_CCCR 0x00000290 + +/* + * Memory settings + */ +#define CONFIG_SYS_MSC0_VAL 0x7ff07ff8 +#define CONFIG_SYS_MSC1_VAL 0x7ff07ff0 +#define CONFIG_SYS_MSC2_VAL 0x74a42491 +#define CONFIG_SYS_MDCNFG_VAL 0x89d309d3 +#define CONFIG_SYS_MDREFR_VAL 0x001d8018 +#define CONFIG_SYS_MDMRS_VAL 0x00220022 +#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 +#define CONFIG_SYS_SXCNFG_VAL 0x00000000 +#define CONFIG_SYS_MEM_BUF_IMP 0x0f + +/* + * PCMCIA and CF Interfaces + */ +#define CONFIG_SYS_MECR_VAL 0x00000000 +#define CONFIG_SYS_MCMEM0_VAL 0x00014307 +#define CONFIG_SYS_MCMEM1_VAL 0x00014307 +#define CONFIG_SYS_MCATT0_VAL 0x0001c787 +#define CONFIG_SYS_MCATT1_VAL 0x0001c787 +#define CONFIG_SYS_MCIO0_VAL 0x0001430f +#define CONFIG_SYS_MCIO1_VAL 0x0001430f + +/* + * LCD + */ +#ifdef CONFIG_LCD +#define CONFIG_BALLOON3LCD +#define CONFIG_VIDEO_LOGO +#define CONFIG_CMD_BMP +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) +#endif + +/* + * USB + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_BOARD_INIT +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "balloon3" +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#endif + +/* + * FPGA + */ +#ifdef CONFIG_CMD_FPGA +#define CONFIG_FPGA +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_SPARTAN3 +#define CONFIG_SYS_FPGA_PROG_FEEDBACK +#define CONFIG_SYS_FPGA_WAIT 1000 +#define CONFIG_MAX_FPGA_DEVICES 1 +#endif + +#endif /* __CONFIG_H */ -- cgit From b2b67baca318d7f3a5940c5a07f924601fa4c885 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Thu, 26 Aug 2010 23:24:18 +0400 Subject: PXA: cleanup vpac270 config and set CONFIG_SYS_HZ to 1000 * CONFIG_SYS_CLKS_IN_HZ is not used anywhere, so removing it * CONFIG_SYS_HZ is set to 1000 on most architectures, so it seems to be the safe default Signed-off-by: Mikhail Kshevetskiy --- include/configs/vpac270.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index 694a8f92c4..4c18d3a788 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -146,8 +146,7 @@ /* * Clock Configuration */ -#undef CONFIG_SYS_CLKS_IN_HZ -#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */ +#define CONFIG_SYS_HZ 1000 /* Timer @ 3250000 Hz */ #define CONFIG_SYS_CPUSPEED 0x190 /* 312MHz */ /* -- cgit From 11934fbf520a02e3ddff95607c60e79efad7dab1 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Thu, 26 Aug 2010 23:24:19 +0400 Subject: PXA: fix environment sector size, kernel and environment location for vpac270 Define ENV_ADDR as MONITOR_BASE + MONITOR_LEN. Fix environment sector size (NOR: 32Kb for first four sectors and 128Kb for other; OneNAND: 128Kb). Last but not least: we have MONITOR_LEN = 0x40000 and one sector for environment (size = 0x20000), so the kernel may start from 0x00060000 only. Signed-off-by: Mikhail Kshevetskiy --- include/configs/vpac270.h | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index 4c18d3a788..b8440a1241 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -45,7 +45,7 @@ "if ide reset && fatload ide 0 0xa4000000 uImage; then " \ "bootm 0xa4000000; " \ "fi; " \ - "bootm 0x40000;" + "bootm 0x60000;" #define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200" #define CONFIG_TIMESTAMP #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ @@ -185,6 +185,12 @@ /* * NOR FLASH */ +#define CONFIG_SYS_MONITOR_BASE 0x0 +#define CONFIG_SYS_MONITOR_LEN 0x40000 +#define CONFIG_ENV_ADDR \ + (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SIZE 0x4000 + #if defined(CONFIG_CMD_FLASH) /* NOR */ #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ @@ -211,7 +217,16 @@ #define CONFIG_SYS_FLASH_PROTECTION 1 #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x4000 + +/* + * The first four sectors of the NOR flash are 0x8000 bytes big, the rest of the + * flash consists of 0x20000 bytes big sectors. + */ +#if (CONFIG_ENV_ADDR <= 0x18000) +#define CONFIG_ENV_SECT_SIZE 0x8000 +#else +#define CONFIG_ENV_SECT_SIZE 0x20000 +#endif #elif defined(CONFIG_CMD_ONENAND) /* OneNAND */ #define CONFIG_SYS_NO_FLASH @@ -225,12 +240,6 @@ #define CONFIG_SYS_ENV_IS_NOWHERE #endif -#define CONFIG_SYS_MONITOR_BASE 0x0 -#define CONFIG_SYS_MONITOR_LEN 0x40000 - -#define CONFIG_ENV_ADDR 0x40000 -#define CONFIG_ENV_SIZE 0x4000 - /* * IDE */ -- cgit From 6ef6eb91cda895de3366068fc2caf25328786f4d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 23 Sep 2010 09:46:57 +0200 Subject: PXA: Add necessary information for RELOC Signed-off-by: Marek Vasut --- include/configs/balloon3.h | 3 +++ include/configs/cerf250.h | 3 +++ include/configs/colibri_pxa270.h | 3 +++ include/configs/cradle.h | 3 +++ include/configs/csb226.h | 3 +++ include/configs/delta.h | 3 +++ include/configs/innokom.h | 3 +++ include/configs/lubbock.h | 3 +++ include/configs/palmld.h | 3 +++ include/configs/palmtc.h | 3 +++ include/configs/pleb2.h | 3 +++ include/configs/pxa255_idp.h | 3 +++ include/configs/trizepsiv.h | 3 +++ include/configs/vpac270.h | 3 +++ include/configs/wepep250.h | 4 ++++ include/configs/xaeniax.h | 3 +++ include/configs/xm250.h | 3 +++ include/configs/xsengine.h | 3 +++ include/configs/zipitz2.h | 3 +++ include/configs/zylonite.h | 2 ++ 20 files changed, 60 insertions(+) (limited to 'include') diff --git a/include/configs/balloon3.h b/include/configs/balloon3.h index 9066a24304..5e2a2851f1 100644 --- a/include/configs/balloon3.h +++ b/include/configs/balloon3.h @@ -130,6 +130,9 @@ #define CONFIG_SYS_LOAD_ADDR 0xa1000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * NOR FLASH */ diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h index 477b94aa61..98b69e3712 100644 --- a/include/configs/cerf250.h +++ b/include/configs/cerf250.h @@ -161,6 +161,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * GPIO settings */ diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index 277ff67bf0..5f457f80de 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -169,6 +169,9 @@ #define CONFIG_SYS_LOAD_ADDR (0xa1000000) +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * NOR FLASH */ diff --git a/include/configs/cradle.h b/include/configs/cradle.h index 998e179208..d1c1a48e0c 100644 --- a/include/configs/cradle.h +++ b/include/configs/cradle.h @@ -145,6 +145,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * FLASH and environment organization */ diff --git a/include/configs/csb226.h b/include/configs/csb226.h index 0661d65aba..ae05734a09 100644 --- a/include/configs/csb226.h +++ b/include/configs/csb226.h @@ -181,6 +181,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + # if 0 /* FIXME: switch to _documented_ registers */ /* diff --git a/include/configs/delta.h b/include/configs/delta.h index d930fb4b2b..d53acbfebc 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -218,6 +218,9 @@ #undef CONFIG_SYS_SKIP_DRAM_SCRUB +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * NAND Flash */ diff --git a/include/configs/innokom.h b/include/configs/innokom.h index 9cb0d42eac..007ccebf43 100644 --- a/include/configs/innokom.h +++ b/include/configs/innokom.h @@ -192,6 +192,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * JFFS2 partitions * diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h index 0a6921044c..3a99ec25c4 100644 --- a/include/configs/lubbock.h +++ b/include/configs/lubbock.h @@ -176,6 +176,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + #define FPGA_REGS_BASE_PHYSICAL 0x08000000 /* diff --git a/include/configs/palmld.h b/include/configs/palmld.h index affc116b9f..926728b15f 100644 --- a/include/configs/palmld.h +++ b/include/configs/palmld.h @@ -154,6 +154,9 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * NOR FLASH */ diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h index f4fc9cd50d..fe87648ac6 100644 --- a/include/configs/palmtc.h +++ b/include/configs/palmtc.h @@ -155,6 +155,9 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * NOR FLASH */ diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h index 9e694118c5..3b6e60afe9 100644 --- a/include/configs/pleb2.h +++ b/include/configs/pleb2.h @@ -179,6 +179,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * GPIO settings */ diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h index 6c1defc9ae..4581674ed3 100644 --- a/include/configs/pxa255_idp.h +++ b/include/configs/pxa255_idp.h @@ -292,6 +292,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * GPIO settings */ diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h index fa5aae8a5c..474349537b 100644 --- a/include/configs/trizepsiv.h +++ b/include/configs/trizepsiv.h @@ -212,6 +212,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * GPIO settings */ diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index b8440a1241..1bcd2f3e04 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -181,6 +181,9 @@ #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ #define CONFIG_SYS_LOAD_ADDR (0x5c000000) +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_GBL_DATA_SIZE + CONFIG_STACKSIZE + PHYS_SDRAM_1) /* * NOR FLASH diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h index 9a20cce457..a961a27922 100644 --- a/include/configs/wepep250.h +++ b/include/configs/wepep250.h @@ -183,6 +183,10 @@ #define CONFIG_ENV_ADDR 0x20000 /* absolute address for now */ #define CONFIG_ENV_SIZE 0x2000 +#define PHYS_SDRAM_1 WEP_SDRAM_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + #undef CONFIG_ENV_OVERWRITE /* env is not writable now */ /* diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h index 1329f0f3d8..67d4106d6f 100644 --- a/include/configs/xaeniax.h +++ b/include/configs/xaeniax.h @@ -167,6 +167,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * FLASH and environment organization */ diff --git a/include/configs/xm250.h b/include/configs/xm250.h index cd56ce72e7..2ff9a2813a 100644 --- a/include/configs/xm250.h +++ b/include/configs/xm250.h @@ -174,6 +174,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * FLASH and environment organization */ diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h index f68461bb22..9606b5316b 100644 --- a/include/configs/xsengine.h +++ b/include/configs/xsengine.h @@ -53,6 +53,9 @@ #define CONFIG_SYS_DRAM_BASE 0xa0000000 #define CONFIG_SYS_DRAM_SIZE 0x04000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* FLASH organization */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index a5a873ba3c..642c5753bb 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -175,6 +175,9 @@ unsigned char zipitz2_spi_read(void); #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * NOR FLASH */ diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h index c8aa0461f6..c33ca2de91 100644 --- a/include/configs/zylonite.h +++ b/include/configs/zylonite.h @@ -190,6 +190,8 @@ #undef CONFIG_SYS_SKIP_DRAM_SCRUB +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) /* * NAND Flash -- cgit From 720a650caa510bf8e941f8da247fc572958f3c3d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 28 Sep 2010 15:50:49 +0200 Subject: PXA: Fix vpac270 for Reloc Signed-off-by: Marek Vasut --- include/configs/vpac270.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index 1bcd2f3e04..1923a177a1 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -34,7 +34,7 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_SYS_MALLOC_LEN (128*1024) #define CONFIG_SYS_GBL_DATA_SIZE 128 - +#define CONFIG_ARCH_CPU_INIT #define CONFIG_BOOTCOMMAND \ "if mmc init && fatload mmc 0 0xa4000000 uImage; then " \ "bootm 0xa4000000; " \ @@ -51,7 +51,7 @@ #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS - +#define CONFIG_SYS_TEXT_BASE 0x0 #define CONFIG_LZMA /* LZMA compression support */ /* @@ -183,7 +183,7 @@ #define CONFIG_SYS_LOAD_ADDR (0x5c000000) #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_GBL_DATA_SIZE + CONFIG_STACKSIZE + PHYS_SDRAM_1) + (PHYS_SDRAM_1 + CONFIG_SYS_GBL_DATA_SIZE + 2048) /* * NOR FLASH -- cgit From 24e84c3dcbfc732888fecc502b7b560b4e372876 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 30 Sep 2010 12:22:38 +0200 Subject: PXA: Fix ZipitZ2 for Reloc Signed-off-by: Marek Vasut --- include/configs/zipitz2.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index 642c5753bb..ce65d1f1c6 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -41,8 +41,9 @@ #define CONFIG_ENV_ADDR 0x40000 #define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + CONFIG_STACKSIZE) +#define CONFIG_SYS_MALLOC_LEN (128*1024) #define CONFIG_SYS_GBL_DATA_SIZE 512 +#define CONFIG_ARCH_CPU_INIT #define CONFIG_BOOTCOMMAND \ "if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \ @@ -56,7 +57,7 @@ #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS - +#define CONFIG_SYS_TEXT_BASE 0x0 #define CONFIG_LZMA /* LZMA compression support */ /* @@ -176,7 +177,7 @@ unsigned char zipitz2_spi_read(void); #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1 + 2048) /* * NOR FLASH @@ -221,7 +222,7 @@ unsigned char zipitz2_spi_read(void); #define CONFIG_SYS_GPCR3_VAL 0x00000000 #define CONFIG_SYS_GPDR0_VAL 0xdafcee00 #define CONFIG_SYS_GPDR1_VAL 0xffa3aaab -#define CONFIG_SYS_GPDR2_VAL 0x8fe1ffff +#define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff #define CONFIG_SYS_GPDR3_VAL 0x001b1f8a #define CONFIG_SYS_GPSR0_VAL 0x06080400 #define CONFIG_SYS_GPSR1_VAL 0x007f0000 -- cgit From 20ae5193e325ad005ca9e15377838e0763069658 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 3 Oct 2010 01:05:55 +0200 Subject: PXA: Fix Balloon3 for Reloc Signed-off-by: Marek Vasut --- include/configs/balloon3.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/balloon3.h b/include/configs/balloon3.h index 5e2a2851f1..ae60f2eb3c 100644 --- a/include/configs/balloon3.h +++ b/include/configs/balloon3.h @@ -34,18 +34,19 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_SYS_MALLOC_LEN (128*1024) #define CONFIG_SYS_GBL_DATA_SIZE 128 - +#define CONFIG_ARCH_CPU_INIT #define CONFIG_BOOTCOMMAND \ + "fpga load 0x0 0x50000 0x62638; " \ "if usb reset && fatload usb 0 0xa4000000 uImage; then " \ "bootm 0xa4000000; " \ "fi; " \ - "bootm 0x40000;" + "bootm 0xd0000;" #define CONFIG_BOOTARGS "console=tty0 console=ttyS2,115200" #define CONFIG_TIMESTAMP #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS - +#define CONFIG_SYS_TEXT_BASE 0x0 #define CONFIG_LZMA /* LZMA compression support */ /* @@ -131,7 +132,8 @@ #define CONFIG_SYS_LOAD_ADDR 0xa1000000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_SP_ADDR \ + (PHYS_SDRAM_1 + CONFIG_SYS_GBL_DATA_SIZE + 2048) /* * NOR FLASH -- cgit From 451a0c39ae8553cb7f1ae3385211c0c17d391465 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 16 Oct 2010 21:32:11 +0200 Subject: PXA: Fix vpac270 OneNAND booter NOTE: The modification in Makefile will be superseded by a pending patch! Signed-off-by: Marek Vasut --- include/configs/vpac270.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index 1923a177a1..fc680fcd83 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -180,7 +180,8 @@ #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ -#define CONFIG_SYS_LOAD_ADDR (0x5c000000) +#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 +#define CONFIG_SYS_IPL_LOAD_ADDR (0x5c000000) #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR \ (PHYS_SDRAM_1 + CONFIG_SYS_GBL_DATA_SIZE + 2048) -- cgit From f97e9c65b3906cd656c14ed0fd35eae0c1649857 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 3 Oct 2010 18:27:36 +0200 Subject: Build: PXA: Fix Vpac270 build variants Signed-off-by: Marek Vasut --- include/configs/vpac270.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index fc680fcd83..c9d9c69cda 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -75,7 +75,7 @@ #undef CONFIG_LCD #define CONFIG_CMD_IDE -#ifdef CONFIG_ONENAND_U_BOOT +#ifdef CONFIG_ONENAND #undef CONFIG_CMD_FLASH #define CONFIG_CMD_ONENAND #else @@ -165,13 +165,13 @@ #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ -#ifdef CONFIG_256M_U_BOOT +#ifdef CONFIG_RAM_256M #define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #2 */ #define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ #endif #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ -#ifdef CONFIG_256M_U_BOOT +#ifdef CONFIG_RAM_256M #define CONFIG_SYS_DRAM_SIZE 0x10000000 /* 256 MB DRAM */ #else #define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */ @@ -198,7 +198,7 @@ #if defined(CONFIG_CMD_FLASH) /* NOR */ #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#ifdef CONFIG_256M_U_BOOT +#ifdef CONFIG_RAM_256M #define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */ #endif @@ -206,7 +206,7 @@ #define CONFIG_FLASH_CFI_DRIVER 1 #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) -#ifdef CONFIG_256M_U_BOOT +#ifdef CONFIG_RAM_256M #define CONFIG_SYS_MAX_FLASH_BANKS 2 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } #else @@ -308,7 +308,7 @@ #define CONFIG_SYS_MSC0_VAL 0x3ffc95fa #define CONFIG_SYS_MSC1_VAL 0x02ccf974 #define CONFIG_SYS_MSC2_VAL 0x00000000 -#ifdef CONFIG_256M_U_BOOT +#ifdef CONFIG_RAM_256M #define CONFIG_SYS_MDCNFG_VAL 0x8ad30ad3 #else #define CONFIG_SYS_MDCNFG_VAL 0x88000ad3 -- cgit From 80bf2bb501c719d7b1925c0146c3d3a86b40b92d Mon Sep 17 00:00:00 2001 From: Kristoffer Ericson Date: Fri, 15 Oct 2010 23:31:43 +0200 Subject: Add support for HP Jornada flashrom boards This patch adds support for the HP Jornada flashboards that were made in 2008. Older flashroms should work if memory registers are adjusted. Signed-off-by: Kristoffer Ericson Adpted for TEXT_BASE -> CONFIG_SYS_TEXT_BASE rename. Removed now redundant board/jornada/config.mk file. Removed unused empty jornada_init() function to silence "jornada.c:35: warning: 'jornada_init' defined but not used" Signed-off-by: Wolfgang Denk --- include/configs/jornada.h | 155 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 155 insertions(+) create mode 100644 include/configs/jornada.h (limited to 'include') diff --git a/include/configs/jornada.h b/include/configs/jornada.h new file mode 100644 index 0000000000..69a045cc32 --- /dev/null +++ b/include/configs/jornada.h @@ -0,0 +1,155 @@ +/* + * Copyright 2010 (C) + * Kristoffer Ericson + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_SA1110 1 /* This is an SA110 CPU */ +#define CONFIG_JORNADA700 1 /* on an HP Jornada 700 series */ +#define CONFIG_SYS_FLASH_PROTECTION 1 +#define CONFIG_SYS_ARM_WITHOUT_RELOC 1 + +#define CONFIG_SYS_TEXT_BASE 0xC1F00000 + +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE +#undef CONFIG_USE_IRQ + +/* Console setting */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size for initial data */ + +/* + * select serial console configuration + */ +#define CONFIG_SA1100_SERIAL 1 +#define CONFIG_SERIAL3 1 /* we use serial 3 */ +#define CONFIG_BAUDRATE 19200 +#define CONFIG_LOADS_ECHO 1 + +/* + * Command line configuration. + */ +#include +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_JFFS2 +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_MISC +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTARGS "root=/dev/hda1 console=ttySA0,19200n8 console=tty1" +#define CONFIG_BOOTCOMMAND "run boot_kernel" +#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */ +#define CONFIG_SYS_LOAD_ADDR 0xc0000000 + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "HP Jornada# " +#define CONFIG_SYS_CBSIZE 256 /* console buffsize */ +#define CONFIG_SYS_PBSIZE (256+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE 256 /* Boot Argument Buffer Size */ +#define CONFIG_SYS_MEMTEST_START 0xc0040000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0xc2000000 /* 4..128 MB */ +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_CPUSPEED 0x0a /* core clock 206MHz */ +#define CONFIG_SYS_BAUDRATE_TABLE { 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_FLASH_CFI_WIDTH FLASH_CFI_32BIT +#define CONFIG_SYS_FLASH_BASE 0x00000000 +#define CONFIG_SYS_FLASH_ERASE_TOUT (4096) +#define CONFIG_SYS_FLASH_WRITE_TOUT (4096) +#define CONFIG_SYS_FLASH_INCREMENT 0x02000000 +#define PHYS_FLASH_1 0x00000000 /* starts at 0x0 */ +#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */ +#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256KB Sectors */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 260 +#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 } +#define CONFIG_SYS_FLASH_EMPTY_INFO 1 +#define CONFIG_SYS_MONITOR_LEN 0x00040000 +#define CONFIG_SYS_MONITOR_BASE 0x00000000 +#define CONFIG_FLASH_SHOW_PROGRESS 1 + +/* Environment */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR 0x00040000 +#define CONFIG_ENV_OFFSET 0x00040000 +#define CONFIG_ENV_SIZE 0x00040000 +#define CONFIG_ENV_SECT_SIZE 0x00040000 +#define CONFIG_ENV_OVERWRITE 1 + +/* + Monitor - 0x00000000 - 0x00040000 (256kb) + Environment - 0x00040000 - 0x00080000 (256kb) + Kernel - 0x00080000 - 0x00380000 (3mb) + Rootfs - 0x00380000 - 0x........ (rest) +*/ + +#define CONFIG_NR_DRAM_BANKS 2 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE +#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CONFIG_SYS_INIT_SP_ADDR 0x0 +#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_2 0xc4000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */ + +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=jornada7xx-0" +#define MTDPARTS_DEFAULT "mtdparts=jornada7xx-0:256k(u-boot),256k(env),"\ + "3m(kernel),-(user);" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "flash_kernel=protect off all; " \ + "erase 00080000 0037ffff;cp.b c0000000 00080000 00300000;\0" \ + "flash_uboot=protect off all; " \ + "erase 00000000 0003ffff;cp.b c0000000 00000000 00040000;\0" \ + "boot_kernel=cp.b 00080000 c0000000 00300000;bootm;\0" +#endif /* __CONFIG_H */ -- cgit From cebcf7da2106d1294c71528b8e2f3532818ef989 Mon Sep 17 00:00:00 2001 From: Jens Scharsig Date: Tue, 19 Oct 2010 19:37:15 +0200 Subject: update board EB+CPUx9K2 * update to support arm reloaction * unnecessary environment variables removed Signed-off-by: Jens Scharsig --- include/configs/eb_cpux9k2.h | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-) (limited to 'include') diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h index 4ff4a85cb5..8d8af93792 100644 --- a/include/configs/eb_cpux9k2.h +++ b/include/configs/eb_cpux9k2.h @@ -42,7 +42,7 @@ #define CONFIG_MISC_INIT_R /*--------------------------------------------------------------------------*/ - +#define CONFIG_SYS_TEXT_BASE 0x00000000 #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ #define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */ @@ -98,12 +98,14 @@ */ #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */ +#define CONFIG_SYS_INIT_SP_ADDR 0x00204000 /* use internal SRAM */ + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - PHYS_SDRAM_SIZE - 0x00400000 - \ + CONFIG_SYS_SDRAM_SIZE - 0x00400000 - \ CONFIG_SYS_MALLOC_LEN) #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* PIOC as D16/D31 */ @@ -249,6 +251,7 @@ /* FLASH organization */ /* NOR-FLASH */ +#define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_FLASH_CFI_DRIVER 1 @@ -396,16 +399,6 @@ "nandboot=run bootargsdefaults;" \ "set bootargs $(bootargs) root=initramfs boot=nand " \ ";bootm $(kerneladdr)\0" \ - "uu=run update_uboot\0" \ - "ur=run update_root;run nk\0" \ - "nk=run bootargsdefaults;set bootargs $(bootargs) root=initramfs " \ - "boot=local " \ - ";echo $(bootargs)" \ - ";dhcp uImage_cpux9k2;bootm\0" \ - "nn=run bootargsdefaults;set bootargs $(bootargs) root=initramfs " \ - "boot=nand " \ - ";echo $(bootargs)" \ - ";dhcp uImage_cpux9k2;bootm\0" \ " " /*--------------------------------------------------------------------------*/ -- cgit From c56ded6a6e8962272c8dd893cac49fd7f60fb9d1 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 19 Oct 2010 09:22:23 +0200 Subject: FPGA: Add missing prototype Add prototype function for ispVMFreeMem to remove warnings when support for Lattice FPGA is compiled. Signed-off-by: Stefano Babic --- include/lattice.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/lattice.h b/include/lattice.h index 33d2ac3df3..75729b605a 100755 --- a/include/lattice.h +++ b/include/lattice.h @@ -308,6 +308,7 @@ int lattice_info(Lattice_desc *desc); void ispVMStart(void); void ispVMEnd(void); +extern void ispVMFreeMem(void); signed char ispVMCode(void); void ispVMDelay(unsigned short int a_usMicroSecondDelay); void ispVMCalculateCRC32(unsigned char a_ucData); -- cgit From 8790ac039983212b1691529780216e8411143b21 Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 28 Sep 2010 15:20:35 -0700 Subject: Setup POST word for generic mpc85xx Using PIC TFRR register for post word load/store for generic MPC85xx. Signed-off-by: York Sun Signed-off-by: Kumar Gala --- include/post.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/post.h b/include/post.h index 625da5593f..daa9047118 100644 --- a/include/post.h +++ b/include/post.h @@ -57,8 +57,8 @@ #define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR) #elif defined (CONFIG_MPC85xx) -#include -#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR) +#include +#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + offsetof(ccsr_pic_t, tfrr)) #elif defined (CONFIG_4xx) #define _POST_WORD_ADDR \ -- cgit From 4672e1ea2d64a1937a5a2ba0c13b8000034ef668 Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 28 Sep 2010 15:20:36 -0700 Subject: Enable POST memory test for corenet_ds Signed-off-by: York Sun Signed-off-by: Kumar Gala --- include/configs/corenet_ds.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index c021d82611..c85bffce09 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -86,6 +86,7 @@ #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ #endif +#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 #define CONFIG_SYS_ALT_MEMTEST -- cgit From 84bc00300f2e0fa0a2d5907589fdff613f72e704 Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 28 Sep 2010 15:20:37 -0700 Subject: Enable POST memory test for P2020DS Signed-off-by: York Sun Signed-off-by: Kumar Gala --- include/configs/P2020DS.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index e7cdb92fb0..8c7d5287c8 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -77,8 +77,9 @@ #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ #endif -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x7fffffff +#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 #define CONFIG_PANIC_HANG /* do not reset board on panic */ /* -- cgit From 28a966715be78fc35147086e68fc80aeb21235b1 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 18 Oct 2010 13:46:49 -0700 Subject: Adding fixed sdram setting for cornet_ds board 800, 900, 1000, 1200MT/s data rate parameters are added for fixed sdram setting. SPD based parameters and fixed parameters can be toggled by hwconfig. To use fixed parameters, hwconfig=fsl_ddr:sdram=fixed To use SPD parameters, hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1 Signed-off-by: York Sun Signed-off-by: Kumar Gala --- include/configs/corenet_ds.h | 60 +------------------------------------------- 1 file changed, 1 insertion(+), 59 deletions(-) (limited to 'include') diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index c85bffce09..85147d0021 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -130,68 +130,10 @@ #define CONFIG_DDR_SPD #define CONFIG_FSL_DDR3 -#ifdef CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 -#else -#define CONFIG_SYS_SDRAM_SIZE 4096 - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f -#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_TIMING_3 0x01031000 -#define CONFIG_SYS_DDR_TIMING_0 0x55440804 -#define CONFIG_SYS_DDR_TIMING_1 0x74713a66 -#define CONFIG_SYS_DDR_TIMING_2 0x0fb8911b -#define CONFIG_SYS_DDR_MODE_1 0x00421850 -#define CONFIG_SYS_DDR_MODE_2 0x00100000 -#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL 0x10400100 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 -#define CONFIG_SYS_DDR_TIMING_4 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5 0x03401500 -#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655a608 -#define CONFIG_SYS_DDR_CONTROL 0xc7048000 -#define CONFIG_SYS_DDR_CONTROL2 0x24400011 -#define CONFIG_SYS_DDR_CDR1 0x00000000 -#define CONFIG_SYS_DDR_CDR2 0x00000000 -#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d -#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 -#define CONFIG_SYS_DDR_SBE 0x00010000 -#define CONFIG_SYS_DDR_DEBUG_18 0x40100400 - -#define CONFIG_SYS_DDR2_CS0_BNDS 0x008000bf -#define CONFIG_SYS_DDR2_CS1_BNDS 0x00C000ff -#define CONFIG_SYS_DDR2_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG -#define CONFIG_SYS_DDR2_CS1_CONFIG CONFIG_SYS_DDR_CS1_CONFIG -#define CONFIG_SYS_DDR2_TIMING_3 CONFIG_SYS_DDR_TIMING_3 -#define CONFIG_SYS_DDR2_TIMING_0 CONFIG_SYS_DDR_TIMING_0 -#define CONFIG_SYS_DDR2_TIMING_1 CONFIG_SYS_DDR_TIMING_1 -#define CONFIG_SYS_DDR2_TIMING_2 CONFIG_SYS_DDR_TIMING_2 -#define CONFIG_SYS_DDR2_MODE_1 CONFIG_SYS_DDR_MODE_1 -#define CONFIG_SYS_DDR2_MODE_2 CONFIG_SYS_DDR_MODE_2 -#define CONFIG_SYS_DDR2_MODE_CTRL CONFIG_SYS_DDR_MODE_CTRL -#define CONFIG_SYS_DDR2_INTERVAL CONFIG_SYS_DDR_INTERVAL -#define CONFIG_SYS_DDR2_DATA_INIT CONFIG_SYS_DDR_DATA_INIT -#define CONFIG_SYS_DDR2_CLK_CTRL CONFIG_SYS_DDR_CLK_CTRL -#define CONFIG_SYS_DDR2_TIMING_4 CONFIG_SYS_DDR_TIMING_4 -#define CONFIG_SYS_DDR2_TIMING_5 CONFIG_SYS_DDR_TIMING_5 -#define CONFIG_SYS_DDR2_ZQ_CNTL CONFIG_SYS_DDR_ZQ_CNTL -#define CONFIG_SYS_DDR2_WRLVL_CNTL CONFIG_SYS_DDR_WRLVL_CNTL -#define CONFIG_SYS_DDR2_CONTROL CONFIG_SYS_DDR_CONTROL -#define CONFIG_SYS_DDR2_CONTROL2 CONFIG_SYS_DDR_CONTROL2 -#define CONFIG_SYS_DDR2_CDR1 CONFIG_SYS_DDR_CDR1 -#define CONFIG_SYS_DDR2_CDR2 CONFIG_SYS_DDR_CDR2 -#define CONFIG_SYS_DDR2_ERR_INT_EN CONFIG_SYS_DDR_ERR_INT_EN -#define CONFIG_SYS_DDR2_ERR_DIS CONFIG_SYS_DDR_ERR_DIS -#define CONFIG_SYS_DDR2_SBE CONFIG_SYS_DDR_SBE -#define CONFIG_SYS_DDR2_DEBUG_18 CONFIG_SYS_DDR_DEBUG_18 - -#endif +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ /* * Local Bus Definitions -- cgit From 06412756e76aeceb44168966fd5d5d660162881f Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Wed, 29 Sep 2010 13:37:28 -0500 Subject: tqm85xx: Update PCI code Update to use the recent, common FSL PCI initialization code. Signed-off-by: Peter Tyser CC: sr@denx.de Signed-off-by: Kumar Gala --- include/configs/TQM85xx.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 59655b1c6f..d5c116f5b8 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -380,11 +380,11 @@ * General PCI * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE (CONFIG_SYS_CCSRBAR + 0x02000000) -#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE +#define CONFIG_SYS_PCI1_IO_BUS (CONFIG_SYS_CCSRBAR + 0x02000000) +#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BUS #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ #ifdef CONFIG_PCIE1 @@ -393,16 +393,16 @@ * Addresses are mapped 1-1. */ #ifdef CONFIG_TQM_BIGFLASH -#define CONFIG_SYS_PCIE1_MEM_BASE 0xb0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xb0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0xaf000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0xaf000000 #else /* !CONFIG_TQM_BIGFLASH */ -#define CONFIG_SYS_PCIE1_MEM_BASE 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0xef000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0xef000000 #endif /* CONFIG_TQM_BIGFLASH */ -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE -#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BASE +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS +#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS #define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */ #endif /* CONFIG_PCIE1 */ -- cgit From 834a45d7ee81ef185cc834b44b2dae7b637631e2 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 7 Oct 2010 14:16:25 +0200 Subject: ppc4xx/POST: Add board specific UART POST test to lwmon5 Add CONFIG_POST_UART to implement a board specific UART POST test. This is done since lwmon5 needs to set POST_ALWAYS to run this test on each reboot. And we don't want to change the default behavious of this this. Signed-off-by: Stefan Roese --- include/configs/lwmon5.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'include') diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index d003710125..a4e92cce3b 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -193,6 +193,17 @@ #define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \ CONFIG_SYS_NS16550_COM2 } +#define CONFIG_POST_UART { \ + "UART test", \ + "uart", \ + "This test verifies the UART operation.", \ + POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL, \ + &uart_post_test, \ + NULL, \ + NULL, \ + CONFIG_SYS_POST_UART \ + } + #define CONFIG_POST_WATCHDOG { \ "Watchdog timer test", \ "watchdog", \ -- cgit From 4adcbdc6be6d01f99c6694972f150a6cce109878 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 11 Oct 2010 15:50:10 +0200 Subject: ppc4xx: Enable NOR flash support in sequoia_ramboot target Until now, the Sequoia RAM-booting image disabled NOR flash support as this image was mainly created for NAND-only boards. This patch now enables NOR flash support for this RAM-booting version as well. Signed-off-by: Stefan Roese --- include/configs/amcc-common.h | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'include') diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index b9f1f6bafe..7453bf83b3 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -81,17 +81,6 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO -#if defined(CONFIG_SYS_RAMBOOT) -/* - * Disable NOR FLASH commands on RAM-booting version. One main reason for this - * RAM-booting version is boards with NAND and without NOR. This image can - * be used for initial NAND programming. - */ -#define CONFIG_SYS_NO_FLASH -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_IMLS -#endif - /* * Miscellaneous configurable options */ -- cgit From acfbbb90b27971abaca1800dba22b1dc60a33369 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 15 Oct 2010 08:41:01 +0200 Subject: ppc4xx: Fix default environment for AMCC boards Commit 0ad7f0950a9bc0a69b3cd5f34ccf7da25fcf1c6d [ppc4xx: cleanup default environment for AMCC boards] broke the default env for many PPC4xx boards. The '\0' character got removed at the end of some environment commands like "update". This patch adds the missing '\0' characters again. Signed-off-by: Stefan Roese --- include/configs/amcc-common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index 7453bf83b3..b5d3e102b2 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -271,13 +271,13 @@ "load=tftp 200000 ${u-boot}\0" \ "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \ "era " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \ - "cp.b ${fileaddr} " xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}" \ + "cp.b ${fileaddr} " xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ "upd=run load update\0" \ #define CONFIG_AMCC_DEF_ENV_NAND_UPD \ "u-boot-nand=" xstr(CONFIG_HOSTNAME) "/u-boot-nand.bin\0" \ "nload=tftp 200000 ${u-boot-nand}\0" \ - "nupdate=nand erase 0 100000;nand write 200000 0 100000" \ + "nupdate=nand erase 0 100000;nand write 200000 0 100000\0" \ "nupd=run nload nupdate\0" #endif /* __AMCC_COMMON_H */ -- cgit From 66fca016057b1c6b697552cc7220ebada9d4f82d Mon Sep 17 00:00:00 2001 From: Thomas Weber Date: Mon, 18 Oct 2010 15:38:15 +0200 Subject: Devkit8000: Adapt changes to ARM relocation support Fix compilation of Devkit8000 after introduction of ARM relocation support. Signed-off-by: Thomas Weber Adapt to TEXT_BASE => CONFIG_SYS_TEXT_BASE rename. Signed-off-by: Wolfgang Denk --- include/configs/devkit8000.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 281577153f..c47e17c779 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -38,6 +38,8 @@ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */ +#define CONFIG_SYS_TEXT_BASE 0x80008000 + #define CONFIG_SDRC /* The chip has SDRC controller */ #include /* get chip and board defs */ @@ -306,4 +308,7 @@ extern unsigned int boot_flash_sec; extern unsigned int boot_flash_type; #endif +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE) + #endif /* __CONFIG_H */ -- cgit