From 3483f28ebfaf968112ede2f075b9769a007cacdd Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Sat, 20 Jan 2018 19:16:04 +0100 Subject: MIPS: add support for Broadcom MIPS BCM6318 SoC family MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Daniel Schwierzeck --- include/configs/bmips_bcm6318.h | 25 +++++++++++++++ include/dt-bindings/clock/bcm6318-clock.h | 37 ++++++++++++++++++++++ .../power-domain/bcm6318-power-domain.h | 13 ++++++++ include/dt-bindings/reset/bcm6318-reset.h | 26 +++++++++++++++ 4 files changed, 101 insertions(+) create mode 100644 include/configs/bmips_bcm6318.h create mode 100644 include/dt-bindings/clock/bcm6318-clock.h create mode 100644 include/dt-bindings/power-domain/bcm6318-power-domain.h create mode 100644 include/dt-bindings/reset/bcm6318-reset.h (limited to 'include') diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h new file mode 100644 index 0000000000..454a7b7f7b --- /dev/null +++ b/include/configs/bmips_bcm6318.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_BMIPS_BCM6318_H +#define __CONFIG_BMIPS_BCM6318_H + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 166500000 + +/* RAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* U-Boot */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 + +#if defined(CONFIG_BMIPS_BOOT_RAM) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#endif + +#endif /* __CONFIG_BMIPS_BCM6318_H */ diff --git a/include/dt-bindings/clock/bcm6318-clock.h b/include/dt-bindings/clock/bcm6318-clock.h new file mode 100644 index 0000000000..1e3dc16f90 --- /dev/null +++ b/include/dt-bindings/clock/bcm6318-clock.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM6318_H +#define __DT_BINDINGS_CLOCK_BCM6318_H + +#define BCM6318_CLK_ADSL_ASB 0 +#define BCM6318_CLK_USB_ASB 1 +#define BCM6318_CLK_MIPS_ASB 2 +#define BCM6318_CLK_PCIE_ASB 3 +#define BCM6318_CLK_PHYMIPS_ASB 4 +#define BCM6318_CLK_ROBOSW_ASB 5 +#define BCM6318_CLK_SAR_ASB 6 +#define BCM6318_CLK_SDR_ASB 7 +#define BCM6318_CLK_SWREG_ASB 8 +#define BCM6318_CLK_PERIPH_ASB 9 +#define BCM6318_CLK_CPUBUS160 10 +#define BCM6318_CLK_ADSL 11 +#define BCM6318_CLK_SAR125 12 +#define BCM6318_CLK_MIPS 13 +#define BCM6318_CLK_PCIE 14 +#define BCM6318_CLK_ROBOSW250 16 +#define BCM6318_CLK_ROBOSW025 17 +#define BCM6318_CLK_SDR 19 +#define BCM6318_CLK_USB 20 +#define BCM6318_CLK_HSSPI 25 +#define BCM6318_CLK_PCIE25 27 +#define BCM6318_CLK_PHYMIPS 28 +#define BCM6318_CLK_AFE 29 +#define BCM6318_CLK_QPROC 30 + +#endif /* __DT_BINDINGS_CLOCK_BCM6318_H */ diff --git a/include/dt-bindings/power-domain/bcm6318-power-domain.h b/include/dt-bindings/power-domain/bcm6318-power-domain.h new file mode 100644 index 0000000000..fb075d2c1c --- /dev/null +++ b/include/dt-bindings/power-domain/bcm6318-power-domain.h @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM6318_H +#define __DT_BINDINGS_POWER_DOMAIN_BCM6318_H + +#define BCM6318_PWR_PCIE 0 +#define BCM6318_PWR_USB 1 + +#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM6318_H */ diff --git a/include/dt-bindings/reset/bcm6318-reset.h b/include/dt-bindings/reset/bcm6318-reset.h new file mode 100644 index 0000000000..781d7fbc4d --- /dev/null +++ b/include/dt-bindings/reset/bcm6318-reset.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_RESET_BCM6318_H +#define __DT_BINDINGS_RESET_BCM6318_H + +#define BCM6318_RST_SPI 0 +#define BCM6318_RST_EPHY 1 +#define BCM6318_RST_SAR 2 +#define BCM6318_RST_ENETSW 3 +#define BCM6318_RST_USBD 4 +#define BCM6318_RST_USBH 5 +#define BCM6318_RST_PCIE_CORE 6 +#define BCM6318_RST_PCIE 7 +#define BCM6318_RST_PCIE_EXT 8 +#define BCM6318_RST_PCIE_HARD 9 +#define BCM6318_RST_ADSL 10 +#define BCM6318_RST_PHYMIPS 11 +#define BCM6318_RST_HOSTMIPS 11 + +#endif /* __DT_BINDINGS_RESET_BCM6318_H */ -- cgit