From b32e11a7158063c6cd773087a2b3b5736da0a273 Mon Sep 17 00:00:00 2001 From: Nitin Jain Date: Fri, 16 Feb 2018 17:29:54 +0530 Subject: fpga: zynqmp: Add support to get the PCAP status for fpga info command This patch adds support for ZynqMP platform to print FPGA PCAP status for "fpga status" command. Signed-off-by: Nitin Jain Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- include/zynqmppl.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/zynqmppl.h b/include/zynqmppl.h index 4c8c2f88f0..8b3ce8ef77 100644 --- a/include/zynqmppl.h +++ b/include/zynqmppl.h @@ -12,6 +12,7 @@ #define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID 0xC2000018 #define ZYNQMP_SIP_SVC_PM_FPGA_LOAD 0xC2000016 +#define ZYNQMP_SIP_SVC_PM_FPGA_STATUS 0xC2000017 #define ZYNQMP_FPGA_OP_INIT (1 << 0) #define ZYNQMP_FPGA_OP_LOAD (1 << 1) #define ZYNQMP_FPGA_OP_DONE (1 << 2) -- cgit From 1a82f59b311e02083a07a9153f4d81d2644ef795 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 28 Mar 2018 15:20:48 +0200 Subject: arm64: zynqmp: Enable pxe and dhcp if commands are enabled Targets without net can't use pxe or dhcp boot methods. Signed-off-by: Michal Simek --- include/configs/xilinx_zynqmp.h | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 8cdc72206c..7c6e451f1b 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -172,12 +172,24 @@ # define BOOT_TARGET_DEVICES_USB(func) #endif +#if defined(CONFIG_CMD_PXE) +# define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) +#else +# define BOOT_TARGET_DEVICES_PXE(func) +#endif + +#if defined(CONFIG_CMD_DHCP) +# define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) +#else +# define BOOT_TARGET_DEVICES_DHCP(func) +#endif + #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_DEVICES_MMC(func) \ BOOT_TARGET_DEVICES_USB(func) \ BOOT_TARGET_DEVICES_SCSI(func) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) + BOOT_TARGET_DEVICES_PXE(func) \ + BOOT_TARGET_DEVICES_DHCP(func) #include -- cgit From 704744f81bd478e9b1ef4fae9b14201f17bd8fe3 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 4 Apr 2018 10:46:49 +0200 Subject: arm64: zynqmp: Remove pinctrl settings This part hasn't been pushed to mainline yet that's why remove it. The patch can be reverted in future when this is pushed there. Reported-by: Alexander Graf Signed-off-by: Michal Simek Reviewed-by: Alexander Graf --- include/dt-bindings/pinctrl/pinctrl-zynqmp.h | 30 ---------------------------- 1 file changed, 30 deletions(-) delete mode 100644 include/dt-bindings/pinctrl/pinctrl-zynqmp.h (limited to 'include') diff --git a/include/dt-bindings/pinctrl/pinctrl-zynqmp.h b/include/dt-bindings/pinctrl/pinctrl-zynqmp.h deleted file mode 100644 index e1b81fe5ef..0000000000 --- a/include/dt-bindings/pinctrl/pinctrl-zynqmp.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * MIO pin configuration defines for Xilinx ZynqMP - * - * Copyright (C) 2017 Xilinx, Inc. - * Author: Chirag Parekh - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H -#define _DT_BINDINGS_PINCTRL_ZYNQMP_H - -/* Bit value for IO standards */ -#define IO_STANDARD_LVCMOS33 0 -#define IO_STANDARD_LVCMOS18 1 - -/* Bit values for Slew Rates */ -#define SLEW_RATE_FAST 0 -#define SLEW_RATE_SLOW 1 - -/* Bit values for Pin inputs */ -#define PIN_INPUT_TYPE_CMOS 0 -#define PIN_INPUT_TYPE_SCHMITT 1 - -#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ -- cgit From 6d0340931ec3d833a3c9525014d78424fba644a4 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 28 Mar 2018 14:37:47 +0200 Subject: arm64: zynqmp: Add support for zcu100 aka Ultra96 board Add support for Xilinx zcu100. Signed-off-by: Michal Simek --- include/configs/xilinx_zynqmp_zcu100.h | 36 ++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 include/configs/xilinx_zynqmp_zcu100.h (limited to 'include') diff --git a/include/configs/xilinx_zynqmp_zcu100.h b/include/configs/xilinx_zynqmp_zcu100.h new file mode 100644 index 0000000000..bfb85d6b75 --- /dev/null +++ b/include/configs/xilinx_zynqmp_zcu100.h @@ -0,0 +1,36 @@ +/* + * Configuration for Xilinx ZynqMP zcu100 + * + * (C) Copyright 2015 - 2016 Xilinx, Inc. + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQMP_ZCU100_H +#define __CONFIG_ZYNQMP_ZCU100_H + +/* FIXME Will go away soon */ +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_NUM_I2C_BUSES 9 +#define CONFIG_SYS_I2C_BUSES { \ + {0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9548, 0x75, 0} } }, \ + {0, {{I2C_MUX_PCA9548, 0x75, 1} } }, \ + {0, {{I2C_MUX_PCA9548, 0x75, 2} } }, \ + {0, {{I2C_MUX_PCA9548, 0x75, 3} } }, \ + {0, {{I2C_MUX_PCA9548, 0x75, 4} } }, \ + {0, {{I2C_MUX_PCA9548, 0x75, 5} } }, \ + {0, {{I2C_MUX_PCA9548, 0x75, 6} } }, \ + {0, {{I2C_MUX_PCA9548, 0x75, 7} } }, \ + } + +#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \ + ZYNQMP_USB1_XHCI_BASEADDR} + +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +#include + +#endif /* __CONFIG_ZYNQMP_ZCU100_H */ -- cgit From 10aaa3584bc4381f86253acc136d641c7dce64eb Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 28 Mar 2018 15:00:25 +0200 Subject: arm64: zynqmp: Add support for zc1751 dc3 zc1751 is based board with dc3 extenstion card which is used for silicon validation. Signed-off-by: Michal Simek --- include/configs/xilinx_zynqmp_zc1751_xm017_dc3.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 include/configs/xilinx_zynqmp_zc1751_xm017_dc3.h (limited to 'include') diff --git a/include/configs/xilinx_zynqmp_zc1751_xm017_dc3.h b/include/configs/xilinx_zynqmp_zc1751_xm017_dc3.h new file mode 100644 index 0000000000..cdc0062c3b --- /dev/null +++ b/include/configs/xilinx_zynqmp_zc1751_xm017_dc3.h @@ -0,0 +1,20 @@ +/* + * Configuration for Xilinx ZynqMP zc1751 XM017 DC3 + * + * (C) Copyright 2015 Xilinx, Inc. + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQMP_ZC1751_XM017_DC3_H +#define __CONFIG_ZYNQMP_ZC1751_XM017_DC3_H + +#define CONFIG_ZYNQ_SDHCI1 + +#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \ + ZYNQMP_USB1_XHCI_BASEADDR} + +#include + +#endif /* __CONFIG_ZYNQMP_ZC1751_XM017_DC3_H */ -- cgit From f7c8e491e9a493239471cb4eb77fc940c526bcf3 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 28 Mar 2018 15:36:36 +0200 Subject: arm64: zynqmp: Add support for zcu104 customer board Xilinx zcu104 is another customer board. It is sort of zcu102 clone with some differences. Signed-off-by: Michal Simek --- include/configs/xilinx_zynqmp_zcu104.h | 36 ++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 include/configs/xilinx_zynqmp_zcu104.h (limited to 'include') diff --git a/include/configs/xilinx_zynqmp_zcu104.h b/include/configs/xilinx_zynqmp_zcu104.h new file mode 100644 index 0000000000..f8cdade763 --- /dev/null +++ b/include/configs/xilinx_zynqmp_zcu104.h @@ -0,0 +1,36 @@ +/* + * Configuration for Xilinx ZynqMP zcu104 + * + * (C) Copyright 2017 Xilinx, Inc. + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQMP_ZCU104_H +#define __CONFIG_ZYNQMP_ZCU104_H + +#define CONFIG_ZYNQ_SDHCI1 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_NUM_I2C_BUSES 9 +#define CONFIG_SYS_I2C_BUSES { \ + {0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9548, 0x74, 0} } }, \ + {0, {{I2C_MUX_PCA9548, 0x74, 1} } }, \ + {0, {{I2C_MUX_PCA9548, 0x74, 2} } }, \ + {0, {{I2C_MUX_PCA9548, 0x74, 3} } }, \ + {0, {{I2C_MUX_PCA9548, 0x74, 4} } }, \ + {0, {{I2C_MUX_PCA9548, 0x74, 5} } }, \ + {0, {{I2C_MUX_PCA9548, 0x74, 6} } }, \ + {0, {{I2C_MUX_PCA9548, 0x74, 7} } }, \ + } + +#define CONFIG_PCA953X + +#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR} + +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +#include + +#endif /* __CONFIG_ZYNQMP_ZCU104_H */ -- cgit From cf0bcd7d02e9f1774a3a6643ec4739c8c0aef217 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 28 Mar 2018 15:43:51 +0200 Subject: arm64: zynqmp: Add support for Xilinx zcu106-revA Xilinx zcu106 is a customer board. It is reusing some parts from zcu102. Signed-off-by: Michal Simek --- include/configs/xilinx_zynqmp_zcu106.h | 47 ++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 include/configs/xilinx_zynqmp_zcu106.h (limited to 'include') diff --git a/include/configs/xilinx_zynqmp_zcu106.h b/include/configs/xilinx_zynqmp_zcu106.h new file mode 100644 index 0000000000..0f0d8c6d42 --- /dev/null +++ b/include/configs/xilinx_zynqmp_zcu106.h @@ -0,0 +1,47 @@ +/* + * Configuration for Xilinx ZynqMP zcu106 + * + * (C) Copyright 2016 Xilinx, Inc. + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQMP_ZCU106_H +#define __CONFIG_ZYNQMP_ZCU106_H + +#define CONFIG_ZYNQ_SDHCI1 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_NUM_I2C_BUSES 18 +#define CONFIG_SYS_I2C_BUSES { \ + {0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \ + {0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \ + {0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \ + {1, {I2C_NULL_HOP} }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \ + } + +#define CONFIG_PCA953X + +#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR} + +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_ZYNQ_EEPROM_BUS 5 +#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54 + +#include + +#endif /* __CONFIG_ZYNQMP_ZCU106_H */ -- cgit From f190eaf002bf1434587d57c726b3dabfabbc8074 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 28 Mar 2018 15:55:27 +0200 Subject: arm64: zynqmp: Add support for Xilinx zcu111-revA Xilinx zcu111 is a customer board. It is reusing some parts from zcu102. Signed-off-by: Michal Simek --- include/configs/xilinx_zynqmp_zcu111.h | 50 ++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 include/configs/xilinx_zynqmp_zcu111.h (limited to 'include') diff --git a/include/configs/xilinx_zynqmp_zcu111.h b/include/configs/xilinx_zynqmp_zcu111.h new file mode 100644 index 0000000000..c488c2133c --- /dev/null +++ b/include/configs/xilinx_zynqmp_zcu111.h @@ -0,0 +1,50 @@ +/* + * Configuration for Xilinx ZynqMP zcu111 + * + * (C) Copyright 2017 Xilinx, Inc. + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQMP_ZCU111_H +#define __CONFIG_ZYNQMP_ZCU111_H + +#define CONFIG_ZYNQ_SDHCI1 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_NUM_I2C_BUSES 21 +#define CONFIG_SYS_I2C_BUSES { \ + {0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \ + {0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \ + {0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \ + {0, {{I2C_MUX_PCA9544, 0x75, 3} } }, \ + {1, {I2C_NULL_HOP} }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 5} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 6} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \ + } + +#define CONFIG_PCA953X + +#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR} + +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_ZYNQ_EEPROM_BUS 5 +#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54 + +#include + +#endif /* __CONFIG_ZYNQMP_ZCU111_H */ -- cgit