From fcb774777562bb7bcdc53c608d0e6bae906ce0f6 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Tue, 28 Apr 2009 13:19:50 -0700 Subject: davinci_nand: cleanup I (minor) Minor cleanup for DaVinci NAND code: - Use I/O addresses from nand_chip; CONFIG_SYS_NAND_BASE won't be defined when there are multiple chipselect lines in use (as with common 2 GByte chips). - Cleanup handling of EMIF control registers * Only need one pointer pointing to them * Remove incorrect and unused struct supersetting them - Use the standard waitfunc; we don't need a custom version - Partial legacy cleanup: * Don't initialize every board like it's a DM6446 EVM * #ifdef a bit more code for BROKEN_ECC Sanity checked with small page NAND on dm355 and dm6446 EVMs; and large page on dm355 EVM (packaged as two devices, not one). Signed-off-by: David Brownell Signed-off-by: Scott Wood --- include/asm-arm/arch-davinci/nand_defs.h | 54 -------------------------------- 1 file changed, 54 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-davinci/nand_defs.h b/include/asm-arm/arch-davinci/nand_defs.h index 187d3c3437..8450b8c690 100644 --- a/include/asm-arm/arch-davinci/nand_defs.h +++ b/include/asm-arm/arch-davinci/nand_defs.h @@ -31,60 +31,6 @@ #define MASK_CLE 0x10 #define MASK_ALE 0x0a -#define NAND_CE0CLE ((volatile u_int8_t *)(CONFIG_SYS_NAND_BASE + 0x10)) -#define NAND_CE0ALE ((volatile u_int8_t *)(CONFIG_SYS_NAND_BASE + 0x0a)) -#define NAND_CE0DATA ((volatile u_int8_t *)CONFIG_SYS_NAND_BASE) - -typedef struct { - u_int32_t NRCSR; - u_int32_t AWCCR; - u_int8_t RSVD0[8]; - u_int32_t AB1CR; - u_int32_t AB2CR; - u_int32_t AB3CR; - u_int32_t AB4CR; - u_int8_t RSVD1[32]; - u_int32_t NIRR; - u_int32_t NIMR; - u_int32_t NIMSR; - u_int32_t NIMCR; - u_int8_t RSVD2[16]; - u_int32_t NANDFCR; - u_int32_t NANDFSR; - u_int8_t RSVD3[8]; - u_int32_t NANDF1ECC; - u_int32_t NANDF2ECC; - u_int32_t NANDF3ECC; - u_int32_t NANDF4ECC; - u_int8_t RSVD4[4]; - u_int32_t IODFTECR; - u_int32_t IODFTGCR; - u_int8_t RSVD5[4]; - u_int32_t IODFTMRLR; - u_int32_t IODFTMRMR; - u_int32_t IODFTMRMSBR; - u_int8_t RSVD6[20]; - u_int32_t MODRNR; - u_int8_t RSVD7[76]; - u_int32_t CE0DATA; - u_int32_t CE0ALE; - u_int32_t CE0CLE; - u_int8_t RSVD8[4]; - u_int32_t CE1DATA; - u_int32_t CE1ALE; - u_int32_t CE1CLE; - u_int8_t RSVD9[4]; - u_int32_t CE2DATA; - u_int32_t CE2ALE; - u_int32_t CE2CLE; - u_int8_t RSVD10[4]; - u_int32_t CE3DATA; - u_int32_t CE3ALE; - u_int32_t CE3CLE; -} nand_registers; - -typedef volatile nand_registers *nandregs; - #define NAND_READ_START 0x00 #define NAND_READ_END 0x30 #define NAND_STATUS 0x70 -- cgit From 6e29ed8e576a6900c5d8dcde36b423ac576894dc Mon Sep 17 00:00:00 2001 From: David Brownell Date: Tue, 28 Apr 2009 13:19:53 -0700 Subject: davinci_nand: cleanup II (CONFIG_SYS_DAVINCI_BROKEN_ECC) Remove CONFIG_SYS_DAVINCI_BROKEN_ECC option. It's not just nasty; it's also unused by any current boards, and doesn't even match the main U-Boot distributions from TI (which use soft ECC, or 4-bit ECC on newer chips that support it). DaVinci GIT kernels since 2.6.24, and mainline Linux since 2.6.30, match non-BROKEN code paths for 1-bit HW ECC. The BROKEN code paths do seem to partially match what MontaVista/TI kernels (4.0/2.6.10, and 5.0/2.6.18) do ... but only for small pages. Large page support is really broken (and it's unclear just what software it was trying to match!), and the ECC layout was making three more bytes available for use by filesystem (or whatever) code. Since this option itself seems broken, remove it. Add a comment about the MV/TI compat issue, and the most straightforward way to address it (should someone really need to solve it). Signed-off-by: David Brownell Signed-off-by: Scott Wood --- include/asm-arm/arch-davinci/nand_defs.h | 69 -------------------------------- 1 file changed, 69 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-davinci/nand_defs.h b/include/asm-arm/arch-davinci/nand_defs.h index 8450b8c690..70094e756d 100644 --- a/include/asm-arm/arch-davinci/nand_defs.h +++ b/include/asm-arm/arch-davinci/nand_defs.h @@ -35,73 +35,4 @@ #define NAND_READ_END 0x30 #define NAND_STATUS 0x70 -#ifdef CONFIG_SYS_NAND_HW_ECC -#define NAND_Ecc_P1e (1 << 0) -#define NAND_Ecc_P2e (1 << 1) -#define NAND_Ecc_P4e (1 << 2) -#define NAND_Ecc_P8e (1 << 3) -#define NAND_Ecc_P16e (1 << 4) -#define NAND_Ecc_P32e (1 << 5) -#define NAND_Ecc_P64e (1 << 6) -#define NAND_Ecc_P128e (1 << 7) -#define NAND_Ecc_P256e (1 << 8) -#define NAND_Ecc_P512e (1 << 9) -#define NAND_Ecc_P1024e (1 << 10) -#define NAND_Ecc_P2048e (1 << 11) - -#define NAND_Ecc_P1o (1 << 16) -#define NAND_Ecc_P2o (1 << 17) -#define NAND_Ecc_P4o (1 << 18) -#define NAND_Ecc_P8o (1 << 19) -#define NAND_Ecc_P16o (1 << 20) -#define NAND_Ecc_P32o (1 << 21) -#define NAND_Ecc_P64o (1 << 22) -#define NAND_Ecc_P128o (1 << 23) -#define NAND_Ecc_P256o (1 << 24) -#define NAND_Ecc_P512o (1 << 25) -#define NAND_Ecc_P1024o (1 << 26) -#define NAND_Ecc_P2048o (1 << 27) - -#define TF(v) (v ? 1 : 0) - -#define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0) -#define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1) -#define P1e(a) (TF(a & NAND_Ecc_P1e) << 2) -#define P1o(a) (TF(a & NAND_Ecc_P1o) << 3) -#define P2e(a) (TF(a & NAND_Ecc_P2e) << 4) -#define P2o(a) (TF(a & NAND_Ecc_P2o) << 5) -#define P4e(a) (TF(a & NAND_Ecc_P4e) << 6) -#define P4o(a) (TF(a & NAND_Ecc_P4o) << 7) - -#define P8e(a) (TF(a & NAND_Ecc_P8e) << 0) -#define P8o(a) (TF(a & NAND_Ecc_P8o) << 1) -#define P16e(a) (TF(a & NAND_Ecc_P16e) << 2) -#define P16o(a) (TF(a & NAND_Ecc_P16o) << 3) -#define P32e(a) (TF(a & NAND_Ecc_P32e) << 4) -#define P32o(a) (TF(a & NAND_Ecc_P32o) << 5) -#define P64e(a) (TF(a & NAND_Ecc_P64e) << 6) -#define P64o(a) (TF(a & NAND_Ecc_P64o) << 7) - -#define P128e(a) (TF(a & NAND_Ecc_P128e) << 0) -#define P128o(a) (TF(a & NAND_Ecc_P128o) << 1) -#define P256e(a) (TF(a & NAND_Ecc_P256e) << 2) -#define P256o(a) (TF(a & NAND_Ecc_P256o) << 3) -#define P512e(a) (TF(a & NAND_Ecc_P512e) << 4) -#define P512o(a) (TF(a & NAND_Ecc_P512o) << 5) -#define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6) -#define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7) - -#define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0) -#define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1) -#define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2) -#define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3) -#define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4) -#define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5) -#define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6) -#define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7) - -#define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0) -#define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1) -#endif - #endif -- cgit From 0c1684437ef810c503df29e8d73f63191aa63862 Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Wed, 29 Apr 2009 09:47:09 -0400 Subject: ARM DaVinci: Changing ALE Mask Value The ALE mask used by DaVinci SOCs is wrong. The patch changes the mask value from '0xa' to '0x8'. This is the mask we use for all TI releases. Signed-off-by: Sandeep Paulraj Signed-off-by: Scott Wood --- include/asm-arm/arch-davinci/nand_defs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-arm/arch-davinci/nand_defs.h b/include/asm-arm/arch-davinci/nand_defs.h index 70094e756d..ba75cd66c5 100644 --- a/include/asm-arm/arch-davinci/nand_defs.h +++ b/include/asm-arm/arch-davinci/nand_defs.h @@ -29,7 +29,7 @@ #include #define MASK_CLE 0x10 -#define MASK_ALE 0x0a +#define MASK_ALE 0x08 #define NAND_READ_START 0x00 #define NAND_READ_END 0x30 -- cgit From 496863b2440dd7cd69a1ad2443a9badd5f8968d1 Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Sat, 9 May 2009 12:35:20 -0400 Subject: NAND DaVinci: Update to ALE/CLE Mask values All DaVinci SOC's use a CLE mask of 0x10 and an ALE mask of 0x8 except the DM646x. This was decided by the design team driving the design. This patch updates the CLE and ALE values for DM646x. Updated patches for DM646x will be sent shortly. This applies to u-boot-nand-flash git Signed-off-by: Sandeep Paulraj Signed-off-by: Scott Wood --- include/asm-arm/arch-davinci/nand_defs.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/asm-arm/arch-davinci/nand_defs.h b/include/asm-arm/arch-davinci/nand_defs.h index ba75cd66c5..f2020728d6 100644 --- a/include/asm-arm/arch-davinci/nand_defs.h +++ b/include/asm-arm/arch-davinci/nand_defs.h @@ -28,8 +28,13 @@ #include +#ifdef CONFIG_SOC_DM646x +#define MASK_CLE 0x80000 +#define MASK_ALE 0x40000 +#else #define MASK_CLE 0x10 #define MASK_ALE 0x08 +#endif #define NAND_READ_START 0x00 #define NAND_READ_END 0x30 -- cgit From 154b5484ac7dcbcd0fb5ba388d930b02f87fa302 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Sun, 10 May 2009 15:43:01 -0700 Subject: davinci_nand chipselect/init cleanup Update chipselect handling in davinci_nand.c so that it can handle 2 GByte chips the same way Linux does: as one device, even though it has two halves with independent chip selects. For such chips the "nand info" command reports: Device 0: 2x nand0, sector size 128 KiB Switch to use the default chipselect function unless the board really needs its own. The logic for the Sonata board moves out of the driver into board-specific code. (Which doesn't affect current build breakage if its NAND support is enabled...) Signed-off-by: David Brownell Signed-off-by: Scott Wood --- include/asm-arm/arch-davinci/nand_defs.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/asm-arm/arch-davinci/nand_defs.h b/include/asm-arm/arch-davinci/nand_defs.h index f2020728d6..386540e418 100644 --- a/include/asm-arm/arch-davinci/nand_defs.h +++ b/include/asm-arm/arch-davinci/nand_defs.h @@ -40,4 +40,6 @@ #define NAND_READ_END 0x30 #define NAND_STATUS 0x70 +extern void davinci_nand_init(struct nand_chip *nand); + #endif -- cgit From cd84423a09f3a08029fe41c1db96168debd0b51f Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 25 May 2009 22:42:28 -0400 Subject: mtd: nand: new base driver for memory mapped nand devices The BF537-STAMP Blackfin board had a driver for working with NAND devices that are simply memory mapped. Since there is nothing Blackfin specific about this, generalize the driver a bit so that everyone can leverage it. Signed-off-by: Mike Frysinger Signed-off-by: Scott Wood --- include/configs/bf537-stamp.h | 44 ++++++++++++++++----------------------- include/configs/bfin_adi_common.h | 3 +++ 2 files changed, 21 insertions(+), 26 deletions(-) (limited to 'include') diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index 0a86e83fbf..98300db7b5 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -151,36 +151,28 @@ /* * NAND Settings */ -/* #define CONFIG_BF537_NAND */ -#ifdef CONFIG_BF537_NAND -# define CONFIG_CMD_NAND -#endif - -#define CONFIG_SYS_NAND_ADDR 0x20212000 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND_ADDR +/* #define CONFIG_NAND_PLAT */ +#define CONFIG_SYS_NAND_BASE 0x20212000 #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define SECTORSIZE 512 -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define BFIN_NAND_READY PF3 - -#define NAND_WAIT_READY(nand) \ + +#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) +#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) +#define BFIN_NAND_READY PF3 +#define BFIN_NAND_WRITE(addr, cmd) \ do { \ - int timeout = 0; \ - while (!(*pPORTFIO & PF3)) \ - if (timeout++ > 100000) \ - break; \ + bfin_write8(addr, cmd); \ + SSYNC(); \ } while (0) -#define BFIN_NAND_CLE (1 << 2) /* A2 -> Command Enable */ -#define BFIN_NAND_ALE (1 << 1) /* A1 -> Address Enable */ -#define WRITE_NAND_COMMAND(d, adr) bfin_write8(adr | BFIN_NAND_CLE, d) -#define WRITE_NAND_ADDRESS(d, adr) bfin_write8(adr | BFIN_NAND_ALE, d) -#define WRITE_NAND(d, adr) bfin_write8(adr, d) -#define READ_NAND(adr) bfin_read8(adr) +#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) +#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) +#define NAND_PLAT_DEV_READY(chip) (bfin_read_PORTFIO() & BFIN_NAND_READY) +#define NAND_PLAT_INIT() \ + do { \ + bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~BFIN_NAND_READY); \ + bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() & ~BFIN_NAND_READY); \ + bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() | BFIN_NAND_READY); \ + } while (0) /* diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index 4149a29471..1ca2e51420 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -38,6 +38,9 @@ # define CONFIG_CMD_USB_STORAGE # define CONFIG_DOS_PARTITION # endif +# ifdef CONFIG_NAND_PLAT +# define CONFIG_CMD_NAND +# endif # ifdef CONFIG_POST # define CONFIG_CMD_DIAG # endif -- cgit From 378adfcdf4bbd77ee4cbc3276d4733e218308a21 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sat, 16 May 2009 14:27:40 +0200 Subject: mtd: nand: use loff_t for offset nand_util currently uses size_t which is arch dependent and not always a unsigned long. Now use loff_t, as does the linux mtd layer. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Scott Wood --- include/nand.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/nand.h b/include/nand.h index 065a42c3ee..23f3ca1db8 100644 --- a/include/nand.h +++ b/include/nand.h @@ -38,22 +38,22 @@ typedef struct mtd_info nand_info_t; extern int nand_curr_device; extern nand_info_t nand_info[]; -static inline int nand_read(nand_info_t *info, off_t ofs, size_t *len, u_char *buf) +static inline int nand_read(nand_info_t *info, loff_t ofs, size_t *len, u_char *buf) { return info->read(info, ofs, *len, (size_t *)len, buf); } -static inline int nand_write(nand_info_t *info, off_t ofs, size_t *len, u_char *buf) +static inline int nand_write(nand_info_t *info, loff_t ofs, size_t *len, u_char *buf) { return info->write(info, ofs, *len, (size_t *)len, buf); } -static inline int nand_block_isbad(nand_info_t *info, off_t ofs) +static inline int nand_block_isbad(nand_info_t *info, loff_t ofs) { return info->block_isbad(info, ofs); } -static inline int nand_erase(nand_info_t *info, off_t off, size_t size) +static inline int nand_erase(nand_info_t *info, loff_t off, size_t size) { struct erase_info instr; @@ -110,9 +110,9 @@ struct nand_erase_options { typedef struct nand_erase_options nand_erase_options_t; -int nand_read_skip_bad(nand_info_t *nand, size_t offset, size_t *length, +int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, u_char *buffer); -int nand_write_skip_bad(nand_info_t *nand, size_t offset, size_t *length, +int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, u_char *buffer); int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts); @@ -122,7 +122,7 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts); int nand_lock( nand_info_t *meminfo, int tight ); int nand_unlock( nand_info_t *meminfo, ulong start, ulong length ); -int nand_get_lock_status(nand_info_t *meminfo, ulong offset); +int nand_get_lock_status(nand_info_t *meminfo, loff_t offset); #ifdef CONFIG_SYS_NAND_SELECT_DEVICE void board_nand_select_device(struct nand_chip *nand, int chip); -- cgit From b74ab737369bbbe66c15cbe6c0d0b6a351b00c96 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Mon, 18 May 2009 16:07:22 +0200 Subject: nand_spl: read environment early, when booting from NAND using nand_spl Currently, when booting from NAND using nand_spl, in the beginning the default environment is used until later in boot process the dynamic environment is read out. This way environment variables that must be interpreted early, like the baudrate or "silent", cannot be modified dynamically and remain at their default values. Fix this problem by reading out main and redundand (if used) copies of the environment in the nand_spl code. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Scott Wood --- include/configs/smdk6400.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h index cac58cf325..018f576ef2 100644 --- a/include/configs/smdk6400.h +++ b/include/configs/smdk6400.h @@ -209,6 +209,9 @@ /* total memory available to uboot */ #define CONFIG_SYS_UBOOT_SIZE (1024 * 1024) +/* Put environment copies after the end of U-Boot owned RAM */ +#define CONFIG_NAND_ENV_DST (CONFIG_SYS_UBOOT_BASE + CONFIG_SYS_UBOOT_SIZE) + #ifdef CONFIG_ENABLE_MMU #define CONFIG_SYS_MAPPED_RAM_BASE 0xc0000000 #define CONFIG_BOOTCOMMAND "nand read 0xc0018000 0x60000 0x1c0000;" \ -- cgit