From 9c66ce662c076fc1f5e57c4e72126e41d56d0b80 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 6 Jan 2015 13:11:21 -0800 Subject: fsl-ch3/lowlevel: TZPC and TZASC programming to configure non-secure accesses This patch ensures that the TZPC (BP147) and TZASC-400 programming happens for LS2085A SoC only when the desired config flags are enabled and ensures that the TZPC programming is done to allow Non-secure (NS) + secure (S) transactions only for DCGF registers. The TZASC component is not present on LS2085A-Rev1, so the TZASC-400 config flag is turned OFF for now. Signed-off-by: Bhupesh Sharma Reviewed-by: York Sun --- include/configs/ls2085a_common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 6fe032c9ff..38984432b5 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -13,6 +13,7 @@ #define CONFIG_FSL_LSCH3 #define CONFIG_LS2085A #define CONFIG_GICV3 +#define CONFIG_FSL_TZPC_BP147 /* Link Definitions */ #define CONFIG_SYS_TEXT_BASE 0x30001000 -- cgit From 03e664d8f4065010ccb6c75648192200a832fd8b Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 6 Jan 2015 13:18:50 -0800 Subject: driver/ddr/fsl: Add support for multiple DDR clocks Controller number is passed for function calls to support individual DDR clock, depending on SoC implementation. It is backward compatible with exising platforms. Multiple clocks have been verifyed on LS2085A emulator. Signed-off-by: York Sun --- include/fsl_ddr.h | 15 +++++++++------ include/fsl_ddr_dimm_params.h | 2 +- 2 files changed, 10 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index 3286c95907..96fde91687 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -44,11 +44,12 @@ u32 fsl_ddr_get_version(void); * to this specific DDR technology. */ static __inline__ int -compute_dimm_parameters(const generic_spd_eeprom_t *spd, +compute_dimm_parameters(const unsigned int ctrl_num, + const generic_spd_eeprom_t *spd, dimm_params_t *pdimm, unsigned int dimm_number) { - return ddr_compute_dimm_parameters(spd, pdimm, dimm_number); + return ddr_compute_dimm_parameters(ctrl_num, spd, pdimm, dimm_number); } #endif @@ -92,13 +93,15 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, unsigned int size_only); const char *step_to_string(unsigned int step); -unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts, +unsigned int compute_fsl_memctl_config_regs(const unsigned int ctrl_num, + const memctl_options_t *popts, fsl_ddr_cfg_regs_t *ddr, const common_timing_params_t *common_dimm, const dimm_params_t *dimm_parameters, unsigned int dbw_capacity_adjust, unsigned int size_only); unsigned int compute_lowest_common_dimm_parameters( + const unsigned int ctrl_num, const dimm_params_t *dimm_params, common_timing_params_t *outpdimm, unsigned int number_of_dimms); @@ -108,9 +111,9 @@ unsigned int populate_memctl_options(int all_dimms_registered, unsigned int ctrl_num); void check_interleaving_options(fsl_ddr_info_t *pinfo); -unsigned int mclk_to_picos(unsigned int mclk); -unsigned int get_memory_clk_period_ps(void); -unsigned int picos_to_mclk(unsigned int picos); +unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk); +unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num); +unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos); void fsl_ddr_set_lawbar( const common_timing_params_t *memctl_common_params, unsigned int memctl_interleaved, diff --git a/include/fsl_ddr_dimm_params.h b/include/fsl_ddr_dimm_params.h index 09a67a6802..751e935117 100644 --- a/include/fsl_ddr_dimm_params.h +++ b/include/fsl_ddr_dimm_params.h @@ -112,7 +112,7 @@ typedef struct dimm_params_s { #endif } dimm_params_t; -extern unsigned int ddr_compute_dimm_parameters( +unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num, const generic_spd_eeprom_t *spd, dimm_params_t *pdimm, unsigned int dimm_number); -- cgit From 27f277fe33eb824308a4547d2e96bf511fb91d6b Mon Sep 17 00:00:00 2001 From: Kuldip Giroh Date: Tue, 6 Jan 2015 13:18:53 -0800 Subject: ARMv8/LS2085A: HugeTLB support is required by default in LS NADK LS NADK memory manager by default works on HugeTLB. Hence bootargs must include parameters default_hugepagesz (default hugepagesize, hugepagesz (hugepage size) and hugepages (number of hugepages to be reserved in kernel for the given size). Signed-off-by: Kuldip Giroh Reviewed-by: York Sun --- include/configs/ls2085a_common.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 38984432b5..55e7307cbc 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -274,7 +274,9 @@ "console=ttyAMA0,38400n8\0" #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ - "earlyprintk=uart8250-8bit,0x21c0600" + "earlyprintk=uart8250-8bit,0x21c0600 " \ + "default_hugepagesz=2m hugepagesz=2m " \ + "hugepages=16" #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ "$kernel_size && bootm $kernel_load" #define CONFIG_BOOTDELAY 1 -- cgit From 064d031ca6490d9641bbe308690b1f15b1f56077 Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 6 Jan 2015 13:18:54 -0800 Subject: ARMv8/LS2085A: Adjust system clock and DDR clock Set system clock to 100MHz and DDR clock to 133MHz. Signed-off-by: York Sun --- include/configs/ls2085a_common.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 55e7307cbc..387f904705 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -249,7 +249,8 @@ /* Physical Memory Map */ /* fixme: these need to be checked against the board */ #define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_SYS_CLK_FREQ 133333333 +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 133333333 #define CONFIG_NR_DRAM_BANKS 3 -- cgit From e32d59a2fa6446b64167bba31c0dd40eb023e8bb Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 6 Jan 2015 13:18:55 -0800 Subject: driver/ddr/fsl: Add sync of refresh Add sync of refresh for multiple DDR controllers. DDRC initialization needs to complete first. Code is re-ordered to keep refresh close. Signed-off-by: York Sun --- include/fsl_ddr.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index 96fde91687..feccef9c9c 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -118,6 +118,8 @@ void fsl_ddr_set_lawbar( const common_timing_params_t *memctl_common_params, unsigned int memctl_interleaved, unsigned int ctrl_num); +void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl, + unsigned int last_ctrl); int fsl_ddr_interactive_env_var_exists(void); unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set); -- cgit From 40e61f8e54f8262a6e85c127c5d9dc240253382a Mon Sep 17 00:00:00 2001 From: Arnab Basu Date: Tue, 6 Jan 2015 13:18:56 -0800 Subject: ARMv8/ls2085a: Switch to passing earlycon to kernel Since Linux v3.16-rc1 earlyprintk has been removed for arm64. Switch to using earlycon. Signed-off-by: Arnab Basu Signed-off-by: York Sun --- include/configs/ls2085a_common.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 387f904705..7e8d944dff 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -274,10 +274,10 @@ "kernel_size=0x1000000\0" \ "console=ttyAMA0,38400n8\0" -#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ - "earlyprintk=uart8250-8bit,0x21c0600 " \ - "default_hugepagesz=2m hugepagesz=2m " \ - "hugepages=16" +#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ + "earlycon=uart8250,mmio,0x21c0600,115200 " \ + "default_hugepagesz=2m hugepagesz=2m " \ + "hugepages=16" #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ "$kernel_size && bootm $kernel_load" #define CONFIG_BOOTDELAY 1 -- cgit From 052ddd5c812ad9f30e7cf9023e50fde882bd65da Mon Sep 17 00:00:00 2001 From: Stuart Yoder Date: Tue, 6 Jan 2015 13:18:57 -0800 Subject: ARMv8/ls2085a: Move kernel image load address Move the load address of the kernel image to get it away from the region of the uncompressed kernel. Signed-off-by: Stuart Yoder Reviewed-by: York Sun --- include/configs/ls2085a_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 7e8d944dff..befd4c7257 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -270,7 +270,7 @@ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_start=0x581200000\0" \ - "kernel_load=0x806f0000\0" \ + "kernel_load=0xa0000000\0" \ "kernel_size=0x1000000\0" \ "console=ttyAMA0,38400n8\0" -- cgit From bbeeb8bec084d9fff2cd16d2577ca285f8e66b72 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 6 Jan 2015 13:18:58 -0800 Subject: ls2085/configs: Ensure right banners are printed for EMU and SIMU This patch enusres that right banners are printed for LS2085A emulator and simulator platforms. Signed-off-by: Bhupesh Sharma Reviewed-by: York Sun --- include/configs/ls2085a_common.h | 3 --- include/configs/ls2085a_emu.h | 3 +++ include/configs/ls2085a_simu.h | 3 +++ 3 files changed, 6 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index befd4c7257..55f4c96360 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -27,9 +27,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_IDENT_STRING " LS2085A-EMU" -#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-EMU" - /* Flat Device Tree Definitions */ #define CONFIG_OF_LIBFDT #define CONFIG_OF_BOARD_SETUP diff --git a/include/configs/ls2085a_emu.h b/include/configs/ls2085a_emu.h index 487cd99c5d..2d2e1ea0bd 100644 --- a/include/configs/ls2085a_emu.h +++ b/include/configs/ls2085a_emu.h @@ -9,6 +9,9 @@ #include "ls2085a_common.h" +#define CONFIG_IDENT_STRING " LS2085A-EMU" +#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-EMU" + #define CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */ #define SPD_EEPROM_ADDRESS1 0x51 diff --git a/include/configs/ls2085a_simu.h b/include/configs/ls2085a_simu.h index 0f40b787b4..af34f3f95d 100644 --- a/include/configs/ls2085a_simu.h +++ b/include/configs/ls2085a_simu.h @@ -9,6 +9,9 @@ #include "ls2085a_common.h" +#define CONFIG_IDENT_STRING " LS2085A-SIMU" +#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-SIMU" + /* SMSC 91C111 ethernet configuration */ #define CONFIG_SMC91111 #define CONFIG_SMC91111_BASE (0x2210000) -- cgit From 4f2532c4a4a34f0241ef9bc921044772f19f928d Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 6 Jan 2015 13:19:01 -0800 Subject: armv8/ls2085a_emu: Enable sync of refresh Enable sync of DDR refresh for LS2085a platform. GPP DDR controllers stay in sync. DP-DDR has only one controller so it does no harm. Signed-off-by: York Sun --- include/configs/ls2085a_emu.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/ls2085a_emu.h b/include/configs/ls2085a_emu.h index 2d2e1ea0bd..a02d69450b 100644 --- a/include/configs/ls2085a_emu.h +++ b/include/configs/ls2085a_emu.h @@ -20,4 +20,5 @@ #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */ +#define CONFIG_FSL_DDR_SYNC_REFRESH #endif /* __LS2_EMU_H */ -- cgit From 7b3bd9a7988a8b4c8ba22a52b4927e8e59819b12 Mon Sep 17 00:00:00 2001 From: "J. German Rivera" Date: Tue, 6 Jan 2015 13:19:02 -0800 Subject: drivers/mc: Migrated MC Flibs to 0.5.2 Upgrade Manage Complex (MC) flib API to 0.5.2. Rename directory fsl_mc to fsl-mc. Change the fsl-mc node in Linux device tree from "fsl,dprcr" to "fsl-mc". Print MC version info when appropriate. Signed-off-by: J. German Rivera Signed-off-by: Lijun Pan Reviewed-by: York Sun --- include/configs/ls2085a_common.h | 4 +- include/fsl-mc/fsl_dpmng.h | 121 +++++++++++++++++++++++++++++++++++ include/fsl-mc/fsl_mc.h | 59 +++++++++++++++++ include/fsl-mc/fsl_mc_cmd.h | 132 +++++++++++++++++++++++++++++++++++++++ include/fsl-mc/fsl_mc_sys.h | 26 ++++++++ include/fsl_mc.h | 59 ----------------- 6 files changed, 339 insertions(+), 62 deletions(-) create mode 100644 include/fsl-mc/fsl_dpmng.h create mode 100644 include/fsl-mc/fsl_mc.h create mode 100644 include/fsl-mc/fsl_mc_cmd.h create mode 100644 include/fsl-mc/fsl_mc_sys.h delete mode 100644 include/fsl_mc.h (limited to 'include') diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 55f4c96360..17a1cde039 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -207,12 +207,10 @@ #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) #define CONFIG_SYS_LS_MC_FW_IN_NOR #define CONFIG_SYS_LS_MC_FW_ADDR 0x580200000ULL -/* TODO Actual FW length needs to be determined at runtime from FW header */ -#define CONFIG_SYS_LS_MC_FW_LENGTH (4U * 1024 * 1024) #define CONFIG_SYS_LS_MC_DPL_IN_NOR #define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ -#define CONFIG_SYS_LS_MC_DPL_LENGTH 4096 +#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH (256 * 1024) #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0xe00000 /* Carve the MC private DRAM block from the end of DRAM */ diff --git a/include/fsl-mc/fsl_dpmng.h b/include/fsl-mc/fsl_dpmng.h new file mode 100644 index 0000000000..c2e1ddd18b --- /dev/null +++ b/include/fsl-mc/fsl_dpmng.h @@ -0,0 +1,121 @@ +/* Copyright 2014 Freescale Semiconductor Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/*! + * @file fsl_dpmng.h + * @brief Management Complex General API + */ + +#ifndef __FSL_DPMNG_H +#define __FSL_DPMNG_H + +/*! + * @Group grp_dpmng Management Complex General API + * + * @brief Contains general API for the Management Complex firmware + * @{ + */ + +struct fsl_mc_io; + +/** + * @brief Management Complex firmware version information + */ +#define MC_VER_MAJOR 4 +#define MC_VER_MINOR 0 + +struct mc_version { + uint32_t major; + /*!< Major version number: incremented on API compatibility changes */ + uint32_t minor; + /*!< Minor version number: incremented on API additions (that are + * backward compatible); reset when major version is incremented + */ + uint32_t revision; + /*!< Internal revision number: incremented on implementation changes + * and/or bug fixes that have no impact on API + */ +}; + +/** + * @brief Retrieves the Management Complex firmware version information + * + * @param[in] mc_io Pointer to opaque I/O object + * @param[out] mc_ver_info Pointer to version information structure + * + * @returns '0' on Success; Error code otherwise. + */ +int mc_get_version(struct fsl_mc_io *mc_io, struct mc_version *mc_ver_info); + +/** + * @brief Resets an AIOP tile + * + * @param[in] mc_io Pointer to opaque I/O object + * @param[in] container_id AIOP container ID + * @param[in] aiop_tile_id AIOP tile ID to reset + * + * @returns '0' on Success; Error code otherwise. + */ +int dpmng_reset_aiop(struct fsl_mc_io *mc_io, + int container_id, + int aiop_tile_id); + +/** + * @brief Loads an image to AIOP tile + * + * @param[in] mc_io Pointer to opaque I/O object + * @param[in] container_id AIOP container ID + * @param[in] aiop_tile_id AIOP tile ID to reset + * @param[in] img_iova I/O virtual address of AIOP ELF image + * @param[in] img_size Size of AIOP ELF image in memory (in bytes) + * + * @returns '0' on Success; Error code otherwise. + */ +int dpmng_load_aiop(struct fsl_mc_io *mc_io, + int container_id, + int aiop_tile_id, + uint64_t img_iova, + uint32_t img_size); + +/** + * @brief AIOP run configuration + */ +struct dpmng_aiop_run_cfg { + uint32_t cores_mask; + /*!< Mask of AIOP cores to run (core 0 in most significant bit) */ + uint64_t options; + /*!< Execution options (currently none defined) */ +}; + +/** + * @brief Starts AIOP tile execution + * + * @param[in] mc_io Pointer to MC portal's I/O object + * @param[in] container_id AIOP container ID + * @param[in] aiop_tile_id AIOP tile ID to reset + * @param[in] cfg AIOP run configuration + * + * @returns '0' on Success; Error code otherwise. + */ +int dpmng_run_aiop(struct fsl_mc_io *mc_io, + int container_id, + int aiop_tile_id, + const struct dpmng_aiop_run_cfg *cfg); + +/** + * @brief Resets MC portal + * + * This function closes all object handles (tokens) that are currently + * open in the MC portal on which the command is submitted. This allows + * cleanup of stale handles that belong to non-functional user processes. + * + * @param[in] mc_io Pointer to MC portal's I/O object + * + * @returns '0' on Success; Error code otherwise. + */ +int dpmng_reset_mc_portal(struct fsl_mc_io *mc_io); + +/** @} */ + +#endif /* __FSL_DPMNG_H */ diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h new file mode 100644 index 0000000000..b9f089e5f3 --- /dev/null +++ b/include/fsl-mc/fsl_mc.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_MC_H__ +#define __FSL_MC_H__ + +#include + +#define MC_CCSR_BASE_ADDR \ + ((struct mc_ccsr_registers __iomem *)0x8340000) + +#define BIT(x) (1 << (x)) +#define GCR1_P1_STOP BIT(31) +#define GCR1_P2_STOP BIT(30) +#define GCR1_P1_DE_RST BIT(23) +#define GCR1_P2_DE_RST BIT(22) +#define GCR1_M1_DE_RST BIT(15) +#define GCR1_M2_DE_RST BIT(14) +#define GCR1_M_ALL_DE_RST (GCR1_M1_DE_RST | GCR1_M2_DE_RST) +#define GSR_FS_MASK 0x3fffffff +#define MCFAPR_PL_MASK (0x1 << 18) +#define MCFAPR_BMT_MASK (0x1 << 17) +#define MCFAPR_BYPASS_ICID_MASK \ + (MCFAPR_PL_MASK | MCFAPR_BMT_MASK) + +#define SOC_MC_PORTALS_BASE_ADDR ((void __iomem *)0x00080C000000) +#define SOC_MC_PORTAL_STRIDE 0x10000 + +#define SOC_MC_PORTAL_ADDR(_portal_id) \ + ((void __iomem *)((uintptr_t)SOC_MC_PORTALS_BASE_ADDR + \ + (_portal_id) * SOC_MC_PORTAL_STRIDE)) + +struct mc_ccsr_registers { + u32 reg_gcr1; + u32 reserved1; + u32 reg_gsr; + u32 reserved2; + u32 reg_sicbalr; + u32 reg_sicbahr; + u32 reg_sicapr; + u32 reserved3; + u32 reg_mcfbalr; + u32 reg_mcfbahr; + u32 reg_mcfapr; + u32 reserved4[0x2f1]; + u32 reg_psr; + u32 reserved5; + u32 reg_brr[2]; + u32 reserved6[0x80]; + u32 reg_error[]; +}; + +int mc_init(bd_t *bis); + +int get_mc_boot_status(void); +#endif diff --git a/include/fsl-mc/fsl_mc_cmd.h b/include/fsl-mc/fsl_mc_cmd.h new file mode 100644 index 0000000000..e7fcb5b142 --- /dev/null +++ b/include/fsl-mc/fsl_mc_cmd.h @@ -0,0 +1,132 @@ +/* Copyright 2014 Freescale Semiconductor Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __FSL_MC_CMD_H +#define __FSL_MC_CMD_H + +#define MC_CMD_NUM_OF_PARAMS 7 + +#define MAKE_UMASK64(_width) \ + ((uint64_t)((_width) < 64 ? ((uint64_t)1 << (_width)) - 1 : -1)) + +static inline uint64_t u64_enc(int lsoffset, int width, uint64_t val) +{ + return (uint64_t)(((uint64_t)val & MAKE_UMASK64(width)) << lsoffset); +} +static inline uint64_t u64_dec(uint64_t val, int lsoffset, int width) +{ + return (uint64_t)((val >> lsoffset) & MAKE_UMASK64(width)); +} + +struct mc_command { + uint64_t header; + uint64_t params[MC_CMD_NUM_OF_PARAMS]; +}; + +enum mc_cmd_status { + MC_CMD_STATUS_OK = 0x0, /*!< Completed successfully */ + MC_CMD_STATUS_READY = 0x1, /*!< Ready to be processed */ + MC_CMD_STATUS_AUTH_ERR = 0x3, /*!< Authentication error */ + MC_CMD_STATUS_NO_PRIVILEGE = 0x4, /*!< No privilege */ + MC_CMD_STATUS_DMA_ERR = 0x5, /*!< DMA or I/O error */ + MC_CMD_STATUS_CONFIG_ERR = 0x6, /*!< Configuration error */ + MC_CMD_STATUS_TIMEOUT = 0x7, /*!< Operation timed out */ + MC_CMD_STATUS_NO_RESOURCE = 0x8, /*!< No resources */ + MC_CMD_STATUS_NO_MEMORY = 0x9, /*!< No memory available */ + MC_CMD_STATUS_BUSY = 0xA, /*!< Device is busy */ + MC_CMD_STATUS_UNSUPPORTED_OP = 0xB, /*!< Unsupported operation */ + MC_CMD_STATUS_INVALID_STATE = 0xC /*!< Invalid state */ +}; + +#define MC_CMD_HDR_CMDID_O 52 /* Command ID field offset */ +#define MC_CMD_HDR_CMDID_S 12 /* Command ID field size */ +#define MC_CMD_HDR_AUTHID_O 38 /* Authentication ID field offset */ +#define MC_CMD_HDR_AUTHID_S 10 /* Authentication ID field size */ +#define MC_CMD_HDR_STATUS_O 16 /* Status field offset */ +#define MC_CMD_HDR_STATUS_S 8 /* Status field size*/ +#define MC_CMD_HDR_PRI_O 15 /* Priority field offset */ +#define MC_CMD_HDR_PRI_S 1 /* Priority field size */ + +#define MC_CMD_HDR_READ_STATUS(_hdr) \ + ((enum mc_cmd_status)u64_dec((_hdr), \ + MC_CMD_HDR_STATUS_O, MC_CMD_HDR_STATUS_S)) + +#define MC_CMD_HDR_READ_AUTHID(_hdr) \ + ((uint16_t)u64_dec((_hdr), MC_CMD_HDR_AUTHID_O, MC_CMD_HDR_AUTHID_S)) + +#define MC_CMD_PRI_LOW 0 /*!< Low Priority command indication */ +#define MC_CMD_PRI_HIGH 1 /*!< High Priority command indication */ + +#define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \ + ((_cmd).params[_param] |= u64_enc((_offset), (_width), _arg)) + +#define MC_RSP_OP(_cmd, _param, _offset, _width, _type, _arg) \ + (_arg = (_type)u64_dec(_cmd.params[_param], (_offset), (_width))) + +static inline uint64_t mc_encode_cmd_header(uint16_t cmd_id, + uint8_t priority, + uint16_t auth_id) +{ + uint64_t hdr; + + hdr = u64_enc(MC_CMD_HDR_CMDID_O, MC_CMD_HDR_CMDID_S, cmd_id); + hdr |= u64_enc(MC_CMD_HDR_AUTHID_O, MC_CMD_HDR_AUTHID_S, auth_id); + hdr |= u64_enc(MC_CMD_HDR_PRI_O, MC_CMD_HDR_PRI_S, priority); + hdr |= u64_enc(MC_CMD_HDR_STATUS_O, MC_CMD_HDR_STATUS_S, + MC_CMD_STATUS_READY); + + return hdr; +} + +/** + * mc_write_command - writes a command to a Management Complex (MC) portal + * + * @portal: pointer to an MC portal + * @cmd: pointer to a filled command + */ +static inline void mc_write_command(struct mc_command __iomem *portal, + struct mc_command *cmd) +{ + int i; + + /* copy command parameters into the portal */ + for (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++) + writeq(cmd->params[i], &portal->params[i]); + + /* submit the command by writing the header */ + writeq(cmd->header, &portal->header); +} + +/** + * mc_read_response - reads the response for the last MC command from a + * Management Complex (MC) portal + * + * @portal: pointer to an MC portal + * @resp: pointer to command response buffer + * + * Returns MC_CMD_STATUS_OK on Success; Error code otherwise. + */ +static inline enum mc_cmd_status mc_read_response( + struct mc_command __iomem *portal, + struct mc_command *resp) +{ + int i; + enum mc_cmd_status status; + + /* Copy command response header from MC portal: */ + resp->header = readq(&portal->header); + status = MC_CMD_HDR_READ_STATUS(resp->header); + if (status != MC_CMD_STATUS_OK) + return status; + + /* Copy command response data from MC portal: */ + for (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++) + resp->params[i] = readq(&portal->params[i]); + + return status; +} + +int mc_send_command(struct fsl_mc_io *mc_io, struct mc_command *cmd); + +#endif /* __FSL_MC_CMD_H */ diff --git a/include/fsl-mc/fsl_mc_sys.h b/include/fsl-mc/fsl_mc_sys.h new file mode 100644 index 0000000000..c0befe01d2 --- /dev/null +++ b/include/fsl-mc/fsl_mc_sys.h @@ -0,0 +1,26 @@ +/* + * Freescale Layerscape Management Complex (MC) Environment-specific code + * + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FSL_MC_SYS_H +#define _FSL_MC_SYS_H + +#include + +struct mc_command; + +/* + * struct mc_portal_wrapper - MC command portal wrapper object + */ +struct fsl_mc_io { + struct mc_command __iomem *mmio_regs; +}; + +int mc_send_command(struct fsl_mc_io *mc_io, + struct mc_command *cmd); + +#endif /* _FSL_MC_SYS_H */ diff --git a/include/fsl_mc.h b/include/fsl_mc.h deleted file mode 100644 index b9f089e5f3..0000000000 --- a/include/fsl_mc.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (C) 2014 Freescale Semiconductor - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __FSL_MC_H__ -#define __FSL_MC_H__ - -#include - -#define MC_CCSR_BASE_ADDR \ - ((struct mc_ccsr_registers __iomem *)0x8340000) - -#define BIT(x) (1 << (x)) -#define GCR1_P1_STOP BIT(31) -#define GCR1_P2_STOP BIT(30) -#define GCR1_P1_DE_RST BIT(23) -#define GCR1_P2_DE_RST BIT(22) -#define GCR1_M1_DE_RST BIT(15) -#define GCR1_M2_DE_RST BIT(14) -#define GCR1_M_ALL_DE_RST (GCR1_M1_DE_RST | GCR1_M2_DE_RST) -#define GSR_FS_MASK 0x3fffffff -#define MCFAPR_PL_MASK (0x1 << 18) -#define MCFAPR_BMT_MASK (0x1 << 17) -#define MCFAPR_BYPASS_ICID_MASK \ - (MCFAPR_PL_MASK | MCFAPR_BMT_MASK) - -#define SOC_MC_PORTALS_BASE_ADDR ((void __iomem *)0x00080C000000) -#define SOC_MC_PORTAL_STRIDE 0x10000 - -#define SOC_MC_PORTAL_ADDR(_portal_id) \ - ((void __iomem *)((uintptr_t)SOC_MC_PORTALS_BASE_ADDR + \ - (_portal_id) * SOC_MC_PORTAL_STRIDE)) - -struct mc_ccsr_registers { - u32 reg_gcr1; - u32 reserved1; - u32 reg_gsr; - u32 reserved2; - u32 reg_sicbalr; - u32 reg_sicbahr; - u32 reg_sicapr; - u32 reserved3; - u32 reg_mcfbalr; - u32 reg_mcfbahr; - u32 reg_mcfapr; - u32 reserved4[0x2f1]; - u32 reg_psr; - u32 reserved5; - u32 reg_brr[2]; - u32 reserved6[0x80]; - u32 reg_error[]; -}; - -int mc_init(bd_t *bis); - -int get_mc_boot_status(void); -#endif -- cgit From 180b8688dca2a7731a291a7660ae188e6eec84b8 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Wed, 21 Jan 2015 17:29:19 +0800 Subject: arm/ls1021a: add PCIe settings The patch enables and adds PCIe settings for boards LS1021AQDS and LS1021ATWR. Signed-off-by: Minghuan Lian Reviewed-by: York Sun --- include/configs/ls1021aqds.h | 24 ++++++++++++++++++++++++ include/configs/ls1021atwr.h | 24 ++++++++++++++++++++++++ 2 files changed, 48 insertions(+) (limited to 'include') diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 2874ccc6fa..3dc4da391b 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -510,6 +510,30 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" +#define CONFIG_SYS_PCI_64BIT + +#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 +#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ +#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 +#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ + +#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 +#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ + +#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 +#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 +#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ + +#ifdef CONFIG_PCI +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP +#define CONFIG_E1000 +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 0a0bb5f109..a13876b550 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -303,6 +303,30 @@ #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" +#define CONFIG_SYS_PCI_64BIT + +#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 +#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ +#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 +#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ + +#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 +#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ + +#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 +#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 +#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ + +#ifdef CONFIG_PCI +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP +#define CONFIG_E1000 +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII -- cgit From 0e1bf614d5045b060db8e1bf9e7f69afdf1c592f Mon Sep 17 00:00:00 2001 From: Volodymyr Riazantsev Date: Tue, 20 Jan 2015 10:16:44 -0500 Subject: mmc: fsl_esdhc: Add support for DDR mode Add support of the DDR mode for eSDHC driver. Enable it for i.MX6 SoC family only. Signed-off-by: Volodymyr Riazantsev Reviewed-by: York Sun --- include/configs/mx6_common.h | 2 ++ include/fsl_esdhc.h | 1 + 2 files changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index e0528ce4b9..29b72b2e9d 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -28,6 +28,8 @@ #define CONFIG_SYS_PL310_BASE L2_PL310_BASE #endif +#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE + #define CONFIG_MP #define CONFIG_MXC_GPT_HCLK diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index c1b6648591..313fa1e312 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -108,6 +108,7 @@ #define XFERTYP_RSPTYP_48_BUSY 0x00030000 #define XFERTYP_MSBSEL 0x00000020 #define XFERTYP_DTDSEL 0x00000010 +#define XFERTYP_DDREN 0x00000008 #define XFERTYP_AC12EN 0x00000004 #define XFERTYP_BCEN 0x00000002 #define XFERTYP_DMAEN 0x00000001 -- cgit From 94e3c8c4fd7bfe395fa467973cd647551d6d98c7 Mon Sep 17 00:00:00 2001 From: gaurav rana Date: Fri, 20 Feb 2015 12:51:46 +0530 Subject: crypto/fsl - Add progressive hashing support using hardware acceleration. Currently only normal hashing is supported using hardware acceleration. Added support for progressive hashing using hardware. Signed-off-by: Ruchika Gupta Signed-off-by: Gaurav Rana CC: Simon Glass Reviewed-by: Simon Glass Reviewed-by: York Sun --- include/fsl_sec.h | 26 ++++++++++++++++++++++++++ include/hw_sha.h | 41 ++++++++++++++++++++++++++++++++++++++++- 2 files changed, 66 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/fsl_sec.h b/include/fsl_sec.h index aa850a3bf1..b6e6f04a34 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -175,6 +175,32 @@ struct jr_regs { u32 jrcr; }; +/* + * Scatter Gather Entry - Specifies the the Scatter Gather Format + * related information + */ +struct sg_entry { +#ifdef CONFIG_SYS_FSL_SEC_LE + uint32_t addr_lo; /* Memory Address - lo */ + uint16_t addr_hi; /* Memory Address of start of buffer - hi */ + uint16_t reserved_zero; +#else + uint16_t reserved_zero; + uint16_t addr_hi; /* Memory Address of start of buffer - hi */ + uint32_t addr_lo; /* Memory Address - lo */ +#endif + + uint32_t len_flag; /* Length of the data in the frame */ +#define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF +#define SG_ENTRY_EXTENSION_BIT 0x80000000 +#define SG_ENTRY_FINAL_BIT 0x40000000 + uint32_t bpid_offset; +#define SG_ENTRY_BPID_MASK 0x00FF0000 +#define SG_ENTRY_BPID_SHIFT 16 +#define SG_ENTRY_OFFSET_MASK 0x00001FFF +#define SG_ENTRY_OFFSET_SHIFT 0 +}; + int sec_init(void); #endif diff --git a/include/hw_sha.h b/include/hw_sha.h index 783350d513..ab19a99188 100644 --- a/include/hw_sha.h +++ b/include/hw_sha.h @@ -7,7 +7,7 @@ */ #ifndef __HW_SHA_H #define __HW_SHA_H - +#include /** * Computes hash value of input pbuf using h/w acceleration @@ -34,4 +34,43 @@ void hw_sha256(const uchar * in_addr, uint buflen, */ void hw_sha1(const uchar * in_addr, uint buflen, uchar * out_addr, uint chunk_size); + +/* + * Create the context for sha progressive hashing using h/w acceleration + * + * @algo: Pointer to the hash_algo struct + * @ctxp: Pointer to the pointer of the context for hashing + * @return 0 if ok, -ve on error + */ +int hw_sha_init(struct hash_algo *algo, void **ctxp); + +/* + * Update buffer for sha progressive hashing using h/w acceleration + * + * The context is freed by this function if an error occurs. + * + * @algo: Pointer to the hash_algo struct + * @ctx: Pointer to the context for hashing + * @buf: Pointer to the buffer being hashed + * @size: Size of the buffer being hashed + * @is_last: 1 if this is the last update; 0 otherwise + * @return 0 if ok, -ve on error + */ +int hw_sha_update(struct hash_algo *algo, void *ctx, const void *buf, + unsigned int size, int is_last); + +/* + * Copy sha hash result at destination location + * + * The context is freed after completion of hash operation or after an error. + * + * @algo: Pointer to the hash_algo struct + * @ctx: Pointer to the context for hashing + * @dest_buf: Pointer to the destination buffer where hash is to be copied + * @size: Size of the buffer being hashed + * @return 0 if ok, -ve on error + */ +int hw_sha_finish(struct hash_algo *algo, void *ctx, void *dest_buf, + int size); + #endif -- cgit