From debb7354d1ea4f694154818df5e5b523f5c1cc1d Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 26 Apr 2006 17:58:56 -0500 Subject: Initial support for MPC8641 HPCN board. --- include/asm-ppc/processor.h | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) (limited to 'include/asm-ppc/processor.h') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 811378383d..1848aaf8cd 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -264,6 +264,7 @@ #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ #define SPRN_IMMR 0x27E /* Internal Memory Map Register */ +#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ #define SPRN_LR 0x008 /* Link Register */ #define SPRN_MBAR 0x137 /* System memory base address */ @@ -443,6 +444,11 @@ #define SPRN_MCSR 0x23c /* Machine Check Syndrome register */ #define ESR_ST 0x00800000 /* Store Operation */ +#if defined(CONFIG_MPC86xx) +#define SPRN_MSSCRO 0x3f6 +#endif + + /* Short-hand versions for a number of the above SPRNs */ #define CTR SPRN_CTR /* Counter Register */ @@ -501,10 +507,14 @@ #define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ #define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ #define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ +#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ #define L2CR SPRN_L2CR /* PPC 750 L2 control register */ #define LR SPRN_LR #define MBAR SPRN_MBAR /* System memory base address */ -#if defined(CONFIG_E500) +#if defined(CONFIG_MPC86xx) +#define MSSCR0 SPRN_MSSCRO +#endif +#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) #define PIR SPRN_PIR #endif #define SVR SPRN_SVR /* System-On-Chip Version Register */ @@ -538,7 +548,7 @@ #define CSRR0 SPRN_CSRR0 #define CSRR1 SPRN_CSRR1 #define IVPR SPRN_IVPR -#define USPRG0 SPRN_USPRG0 +#define USPRG0 SPRN_USPRG #define SPRG4R SPRN_SPRG4R #define SPRG5R SPRN_SPRG5R #define SPRG6R SPRN_SPRG6R @@ -755,6 +765,8 @@ #define PVR_85xx_REV1 (PVR_85xx | 0x0010) #define PVR_85xx_REV2 (PVR_85xx | 0x0020) +#define PVR_86xx 0x80040000 +#define PVR_86xx_REV1 (PVR_86xx | 0x0010) /* * For the 8xx processors, all of them report the same PVR family for @@ -808,6 +820,8 @@ #define SVR_8548 0x8031 #define SVR_8548_E 0x8039 +#define SVR_8641 0x8090 +#define SVR_8641D 0x8091 /* I am just adding a single entry for 8260 boards. I think we may be * able to combine mbx, fads, rpxlite, bseip, and classic into a single -- cgit From ae6241685cbcf0c79a3636530d2ceab1fb291a94 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 22 Aug 2006 18:07:00 -0500 Subject: Cleanup more poorly introduced whitespace. --- include/asm-ppc/processor.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'include/asm-ppc/processor.h') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 1848aaf8cd..0060cd030b 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -264,7 +264,7 @@ #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ #define SPRN_IMMR 0x27E /* Internal Memory Map Register */ -#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ +#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ #define SPRN_LR 0x008 /* Link Register */ #define SPRN_MBAR 0x137 /* System memory base address */ @@ -445,7 +445,7 @@ #define ESR_ST 0x00800000 /* Store Operation */ #if defined(CONFIG_MPC86xx) -#define SPRN_MSSCRO 0x3f6 +#define SPRN_MSSCRO 0x3f6 #endif @@ -507,12 +507,12 @@ #define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ #define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ #define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ -#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ +#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ #define L2CR SPRN_L2CR /* PPC 750 L2 control register */ #define LR SPRN_LR #define MBAR SPRN_MBAR /* System memory base address */ #if defined(CONFIG_MPC86xx) -#define MSSCR0 SPRN_MSSCRO +#define MSSCR0 SPRN_MSSCRO #endif #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) #define PIR SPRN_PIR @@ -548,7 +548,7 @@ #define CSRR0 SPRN_CSRR0 #define CSRR1 SPRN_CSRR1 #define IVPR SPRN_IVPR -#define USPRG0 SPRN_USPRG +#define USPRG0 SPRN_USPRG #define SPRG4R SPRN_SPRG4R #define SPRG5R SPRN_SPRG5R #define SPRG6R SPRN_SPRG6R -- cgit From d14ba6a798beb753e7a864500414fcc2d198b8bc Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 14 Sep 2006 08:40:36 -0500 Subject: Handle 86xx SVR values according to the new Reference Manual. Both 8641 and 8641D have SVR == 0x8090, and are distinguished by the byte in bits 16-23 instead. Thanks to Jason Jin for noticing. Signed-off-by: Jon Loeliger --- include/asm-ppc/processor.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'include/asm-ppc/processor.h') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 0060cd030b..553ef3d945 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -802,6 +802,8 @@ #define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */ +#define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */ + #define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */ #define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */ @@ -819,9 +821,8 @@ #define SVR_8541 0x807A #define SVR_8548 0x8031 #define SVR_8548_E 0x8039 - #define SVR_8641 0x8090 -#define SVR_8641D 0x8091 + /* I am just adding a single entry for 8260 boards. I think we may be * able to combine mbx, fads, rpxlite, bseip, and classic into a single -- cgit