From c0535c0ef0b7e7a3e4c1011266bf26baf94fd4a3 Mon Sep 17 00:00:00 2001 From: Vikas Manocha Date: Thu, 2 Jul 2015 18:29:43 -0700 Subject: spi: cadence_qspi: move the sram partition in init There is no need to re-configure sram partition for every read/write for better full use of sram for read or write. This patch divides the half sram for read & half for write once at initialization. Signed-off-by: Vikas Manocha Tested-by: Stefan Roese Reviewed-by: Jagannadh Teki --- drivers/spi/cadence_qspi_apb.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 00a115f3fb..fb78892f18 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -38,10 +38,7 @@ /* Controller sram size in word */ #define CQSPI_REG_SRAM_SIZE_WORD (128) -#define CQSPI_REG_SRAM_RESV_WORDS (2) -#define CQSPI_REG_SRAM_PARTITION_WR (1) -#define CQSPI_REG_SRAM_PARTITION_RD \ - (CQSPI_REG_SRAM_SIZE_WORD - CQSPI_REG_SRAM_RESV_WORDS) +#define CQSPI_REG_SRAM_PARTITION_RD (CQSPI_REG_SRAM_SIZE_WORD/2) #define CQSPI_REG_SRAM_THRESHOLD_WORDS (50) /* Transfer mode */ @@ -538,6 +535,10 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat) /* Configure the remap address register, no remap */ writel(0, plat->regbase + CQSPI_REG_REMAP); + /* Indirect mode configurations */ + writel(CQSPI_REG_SRAM_PARTITION_RD, + plat->regbase + CQSPI_REG_SRAMPARTITION); + /* Disable all interrupts */ writel(0, plat->regbase + CQSPI_REG_IRQMASK); @@ -700,10 +701,6 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), plat->regbase + CQSPI_REG_INDIRECTTRIGGER); - /* Configure SRAM partition for read. */ - writel(CQSPI_REG_SRAM_PARTITION_RD, plat->regbase + - CQSPI_REG_SRAMPARTITION); - /* Configure the opcode */ rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB; @@ -801,9 +798,6 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), plat->regbase + CQSPI_REG_INDIRECTTRIGGER); - writel(CQSPI_REG_SRAM_PARTITION_WR, - plat->regbase + CQSPI_REG_SRAMPARTITION); - /* Configure the opcode */ reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB; writel(reg, plat->regbase + CQSPI_REG_WR_INSTR); -- cgit From 90a2f7171182f3b96c28b2dcff67b02a3164cdb1 Mon Sep 17 00:00:00 2001 From: Vikas Manocha Date: Thu, 2 Jul 2015 18:29:44 -0700 Subject: spi: cadence_qspi: get sram size from device tree sram size could be different on different socs, e.g. on stv0991 it is 256 while on altera platform it is 128. It is better to receive it from device tree. Signed-off-by: Vikas Manocha Tested-by: Stefan Roese Reviewed-by: Jagannadh Teki --- drivers/spi/cadence_qspi.c | 1 + drivers/spi/cadence_qspi.h | 1 + drivers/spi/cadence_qspi_apb.c | 6 +----- 3 files changed, 3 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index a75fc46e95..34a0f46a1a 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -309,6 +309,7 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) plat->tsd2d_ns = fdtdec_get_int(blob, subnode, "tsd2d-ns", 255); plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20); plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20); + plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128); debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", __func__, plat->regbase, plat->ahbbase, plat->max_hz, diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index c9a6142e82..98e57aa5bc 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -25,6 +25,7 @@ struct cadence_spi_platdata { u32 tsd2d_ns; u32 tchsh_ns; u32 tslch_ns; + u32 sram_size; }; struct cadence_spi_priv { diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index fb78892f18..cbf0d428dd 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -36,9 +36,6 @@ #define CQSPI_FIFO_WIDTH (4) -/* Controller sram size in word */ -#define CQSPI_REG_SRAM_SIZE_WORD (128) -#define CQSPI_REG_SRAM_PARTITION_RD (CQSPI_REG_SRAM_SIZE_WORD/2) #define CQSPI_REG_SRAM_THRESHOLD_WORDS (50) /* Transfer mode */ @@ -536,8 +533,7 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat) writel(0, plat->regbase + CQSPI_REG_REMAP); /* Indirect mode configurations */ - writel(CQSPI_REG_SRAM_PARTITION_RD, - plat->regbase + CQSPI_REG_SRAMPARTITION); + writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION); /* Disable all interrupts */ writel(0, plat->regbase + CQSPI_REG_IRQMASK); -- cgit From 70bb2b141573afd75cbc4b448e430814f3990b28 Mon Sep 17 00:00:00 2001 From: Vikas Manocha Date: Thu, 2 Jul 2015 18:29:45 -0700 Subject: spi: cadence_qspi: support FIFO width other than 4 bytes This patch makes the code compatible with FIFO depths other than 4 bytes. It also simplify read/write FIFO loops. Signed-off-by: Vikas Manocha Tested-by: Stefan Roese Reviewed-by: Jagannadh Teki --- drivers/spi/cadence_qspi_apb.c | 46 +++++++++++++++++++++--------------------- 1 file changed, 23 insertions(+), 23 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index cbf0d428dd..d05340716e 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -200,18 +200,16 @@ static void cadence_qspi_apb_read_fifo_data(void *dest, unsigned int *dest_ptr = (unsigned int *)dest; unsigned int *src_ptr = (unsigned int *)src_ahb_addr; - while (remaining > 0) { - if (remaining >= CQSPI_FIFO_WIDTH) { - *dest_ptr = readl(src_ptr); - remaining -= CQSPI_FIFO_WIDTH; - } else { - /* dangling bytes */ - temp = readl(src_ptr); - memcpy(dest_ptr, &temp, remaining); - break; - } + while (remaining >= sizeof(dest_ptr)) { + *dest_ptr = readl(src_ptr); + remaining -= sizeof(src_ptr); dest_ptr++; } + if (remaining) { + /* dangling bytes */ + temp = readl(src_ptr); + memcpy(dest_ptr, &temp, remaining); + } return; } @@ -219,24 +217,26 @@ static void cadence_qspi_apb_read_fifo_data(void *dest, static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr, const void *src, unsigned int bytes) { - unsigned int temp; + unsigned int temp = 0; + int i; int remaining = bytes; unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr; unsigned int *src_ptr = (unsigned int *)src; - while (remaining > 0) { - if (remaining >= CQSPI_FIFO_WIDTH) { - writel(*src_ptr, dest_ptr); - remaining -= sizeof(unsigned int); - } else { - /* dangling bytes */ - memcpy(&temp, src_ptr, remaining); - writel(temp, dest_ptr); - break; - } - src_ptr++; + while (remaining >= CQSPI_FIFO_WIDTH) { + for (i = CQSPI_FIFO_WIDTH/sizeof(src_ptr) - 1; i >= 0; i--) + writel(*(src_ptr+i), dest_ptr+i); + src_ptr += CQSPI_FIFO_WIDTH/sizeof(src_ptr); + remaining -= CQSPI_FIFO_WIDTH; + } + if (remaining) { + /* dangling bytes */ + i = remaining/sizeof(dest_ptr); + memcpy(&temp, src_ptr+i, remaining % sizeof(dest_ptr)); + writel(temp, dest_ptr+i); + for (--i; i >= 0; i--) + writel(*(src_ptr+i), dest_ptr+i); } - return; } -- cgit From fa31377ef0fd1096fbeab9c240582a93c4da9f6d Mon Sep 17 00:00:00 2001 From: Tang Yuantian Date: Thu, 9 Jul 2015 14:37:30 +0800 Subject: ahci: Fix compiling warnings under 64bit platforms When compling under 64bit platforms, there are lots of warnings, like: drivers/block/ahci.c:114:18: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio; ^ drivers/block/ahci.c: In function ?.hci_host_init?. drivers/block/ahci.c:218:49: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); ...... Reviewed-by: Simon Glass Signed-off-by: Shaohui Xie Signed-off-by: Tang Yuantian --- drivers/block/ahci.c | 64 +++++++++++++++++++++++++--------------------- drivers/block/dwc_ahsata.c | 13 ++++++---- 2 files changed, 43 insertions(+), 34 deletions(-) (limited to 'drivers') diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 4fb846ad37..a57f674c52 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -43,13 +43,13 @@ u16 *ataid[AHCI_MAX_PORTS]; #define WAIT_MS_FLUSH 5000 #define WAIT_MS_LINKUP 200 -static inline u32 ahci_port_base(u32 base, u32 port) +static inline void __iomem *ahci_port_base(void __iomem *base, u32 port) { return base + 0x100 + (port * 0x80); } -static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, +static void ahci_setup_port(struct ahci_ioports *port, void __iomem *base, unsigned int port_idx) { base = ahci_port_base(base, port_idx); @@ -61,7 +61,7 @@ static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, #define msleep(a) udelay(a * 1000) -static void ahci_dcache_flush_range(unsigned begin, unsigned len) +static void ahci_dcache_flush_range(unsigned long begin, unsigned long len) { const unsigned long start = begin; const unsigned long end = start + len; @@ -75,7 +75,7 @@ static void ahci_dcache_flush_range(unsigned begin, unsigned len) * controller is invalidated from dcache; next access comes from * physical RAM. */ -static void ahci_dcache_invalidate_range(unsigned begin, unsigned len) +static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len) { const unsigned long start = begin; const unsigned long end = start + len; @@ -94,7 +94,7 @@ static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp) AHCI_PORT_PRIV_DMA_SZ); } -static int waiting_for_cmd_completed(volatile u8 *offset, +static int waiting_for_cmd_completed(void __iomem *offset, int timeout_msec, u32 sign) { @@ -111,7 +111,7 @@ int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port) { u32 tmp; int j = 0; - u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio; + void __iomem *port_mmio = probe_ent->port[port].port_mmio; /* * Bring up SATA link. @@ -131,7 +131,7 @@ int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port) #ifdef CONFIG_SUNXI_AHCI /* The sunxi AHCI controller requires this undocumented setup */ -static void sunxi_dma_init(volatile u8 *port_mmio) +static void sunxi_dma_init(void __iomem *port_mmio) { clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400); } @@ -171,10 +171,10 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) u16 tmp16; unsigned short vendor; #endif - volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; + void __iomem *mmio = probe_ent->mmio_base; u32 tmp, cap_save, cmd; int i, j, ret; - volatile u8 *port_mmio; + void __iomem *port_mmio; u32 port_map; debug("ahci_host_init: start\n"); @@ -215,9 +215,9 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) for (i = 0; i < probe_ent->n_ports; i++) { if (!(port_map & (1 << i))) continue; - probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); + probe_ent->port[i].port_mmio = ahci_port_base(mmio, i); port_mmio = (u8 *) probe_ent->port[i].port_mmio; - ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i); + ahci_setup_port(&probe_ent->port[i], mmio, i); /* make sure port is not active */ tmp = readl(port_mmio + PORT_CMD); @@ -329,7 +329,7 @@ static void ahci_print_info(struct ahci_probe_ent *probe_ent) pci_dev_t pdev = probe_ent->dev; u16 cc; #endif - volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; + void __iomem *mmio = probe_ent->mmio_base; u32 vers, cap, cap2, impl, speed; const char *speed_s; const char *scc_s; @@ -462,7 +462,7 @@ static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len) for (i = 0; i < sg_count; i++) { ahci_sg->addr = - cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT); + cpu_to_le32((unsigned long) buf + i * MAX_DATA_BYTE_COUNT); ahci_sg->addr_hi = 0; ahci_sg->flags_size = cpu_to_le32(0x3fffff & (buf_len < MAX_DATA_BYTE_COUNT @@ -480,8 +480,11 @@ static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) { pp->cmd_slot->opts = cpu_to_le32(opts); pp->cmd_slot->status = 0; - pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff); - pp->cmd_slot->tbl_addr_hi = 0; + pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff); +#ifdef CONFIG_PHYS_64BIT + pp->cmd_slot->tbl_addr_hi = + cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16)); +#endif } @@ -489,7 +492,7 @@ static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) static void ahci_set_feature(u8 port) { struct ahci_ioports *pp = &(probe_ent->port[port]); - volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; + void __iomem *port_mmio = pp->port_mmio; u32 cmd_fis_len = 5; /* five dwords */ u8 fis[20]; @@ -514,7 +517,7 @@ static void ahci_set_feature(u8 port) } #endif -static int wait_spinup(volatile u8 *port_mmio) +static int wait_spinup(void __iomem *port_mmio) { ulong start; u32 tf_data; @@ -532,9 +535,9 @@ static int wait_spinup(volatile u8 *port_mmio) static int ahci_port_start(u8 port) { struct ahci_ioports *pp = &(probe_ent->port[port]); - volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; + void __iomem *port_mmio = pp->port_mmio; u32 port_status; - u32 mem; + void __iomem *mem; debug("Enter start port: %d\n", port); port_status = readl(port_mmio + PORT_SCR_STAT); @@ -544,15 +547,16 @@ static int ahci_port_start(u8 port) return -1; } - mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); + mem = malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); if (!mem) { free(pp); printf("%s: No mem for table!\n", __func__); return -ENOMEM; } - mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */ - memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ); + /* Aligned to 2048-bytes */ + mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ); + memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); /* * First item in chunk of DMA memory: 32-slot command table, @@ -560,7 +564,7 @@ static int ahci_port_start(u8 port) */ pp->cmd_slot = (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem); - debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot); + debug("cmd_slot = %p\n", pp->cmd_slot); mem += (AHCI_CMD_SLOT_SZ + 224); /* @@ -574,13 +578,14 @@ static int ahci_port_start(u8 port) * and its scatter-gather table */ pp->cmd_tbl = virt_to_phys((void *)mem); - debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl); + debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl); mem += AHCI_CMD_TBL_HDR; pp->cmd_tbl_sg = (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem); - writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR); + writel_with_flush((unsigned long)pp->cmd_slot, + port_mmio + PORT_LST_ADDR); writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); @@ -607,7 +612,7 @@ static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf, { struct ahci_ioports *pp = &(probe_ent->port[port]); - volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; + void __iomem *port_mmio = pp->port_mmio; u32 opts; u32 port_status; int sg_count; @@ -632,7 +637,7 @@ static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf, ahci_fill_cmd_slot(pp, opts); ahci_dcache_flush_sata_cmd(pp); - ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len); + ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len); writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); @@ -642,7 +647,8 @@ static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf, return -1; } - ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len); + ahci_dcache_invalidate_range((unsigned long)buf, + (unsigned long)buf_len); debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status); return 0; @@ -1026,7 +1032,7 @@ static int ata_io_flush(u8 port) { u8 fis[20]; struct ahci_ioports *pp = &(probe_ent->port[port]); - volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; + void __iomem *port_mmio = pp->port_mmio; u32 cmd_fis_len = 5; /* five dwords */ /* Preset the FIS */ diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c index cf3ef6be62..bc072f335f 100644 --- a/drivers/block/dwc_ahsata.c +++ b/drivers/block/dwc_ahsata.c @@ -80,7 +80,7 @@ struct sata_host_regs { static int is_ready; -static inline u32 ahci_port_base(u32 base, u32 port) +static inline void __iomem *ahci_port_base(void __iomem *base, u32 port) { return base + 0x100 + (port * 0x80); } @@ -167,7 +167,7 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) for (i = 0; i < probe_ent->n_ports; i++) { probe_ent->port[i].port_mmio = - ahci_port_base((u32)host_mmio, i); + ahci_port_base(host_mmio, i); port_mmio = (struct sata_port_regs *)probe_ent->port[i].port_mmio; @@ -399,8 +399,11 @@ static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts) memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ); cmd_hdr->opts = cpu_to_le32(opts); cmd_hdr->status = 0; - cmd_hdr->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff); - cmd_hdr->tbl_addr_hi = 0; + pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff); +#ifdef CONFIG_PHYS_64BIT + pp->cmd_slot->tbl_addr_hi = + cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16)); +#endif } #define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0) @@ -520,7 +523,7 @@ static int ahci_port_start(struct ahci_probe_ent *probe_ent, * and its scatter-gather table */ pp->cmd_tbl = mem; - debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl); + debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl); mem += AHCI_CMD_TBL_HDR; -- cgit From 8fd3ec770c41115b95ca80f0f0ba344ac59dc293 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 2 Jul 2015 18:15:44 -0600 Subject: exynos: i2c: Correct bug in pinmux selection When driver model is not used the current code does not correctly select the pinmux for the I2C bus. This bug was introduced by this commit: 8dfcbaa dm: i2c: s3c24x0: adjust to dm-i2c api Signed-off-by: Simon Glass Acked-by: Heiko Schocher Reviewed-by: Przemyslaw Marczak Signed-off-by: Minkyu Kang --- drivers/i2c/s3c24x0_i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index c053e84cdb..9a04e48a0f 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -1035,7 +1035,7 @@ static void process_nodes(const void *blob, int node_list[], int count, CONFIG_SYS_I2C_S3C24X0_SPEED); bus->node = node; bus->bus_num = i; - exynos_pinmux_config(PERIPH_ID_I2C0 + bus->id, flags); + exynos_pinmux_config(bus->id, flags); /* Mark position as used */ node_list[i] = -1; -- cgit From 29905a451b7ecf86785a4404e926fb14a8daced3 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 29 Jun 2015 14:58:08 +0200 Subject: mmc: sdhci: Use timer based timeout detection in sdhci_send_command() The loop counter based timeout detection does not work on the Armada 38x based board (DB-88F6820-GP). At least with dcache enabled a timeout is detected. Without dcache enabled, the timeout does not occur. Increasing the loop counter solves this issue. But a better solution is to use a timer based timeout detection instead. This patch now implements this timer based detection. Signed-off-by: Stefan Roese Cc: Pantelis Antoniou Cc: Luka Perkov --- drivers/mmc/sdhci.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 75556a332d..f72536b2aa 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -133,8 +133,8 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, int trans_bytes = 0, is_aligned = 1; u32 mask, flags, mode; unsigned int time = 0, start_addr = 0; - unsigned int retry = 10000; int mmc_dev = mmc->block_dev.dev; + unsigned start = get_timer(0); /* Timeout unit - ms */ static unsigned int cmd_timeout = CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT; @@ -222,15 +222,15 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, flush_cache(start_addr, trans_bytes); #endif sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND); + start = get_timer(0); do { stat = sdhci_readl(host, SDHCI_INT_STATUS); if (stat & SDHCI_INT_ERROR) break; - if (--retry == 0) - break; - } while ((stat & mask) != mask); + } while (((stat & mask) != mask) && + (get_timer(start) < CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT)); - if (retry == 0) { + if (get_timer(start) >= CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT) { if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) return 0; else { -- cgit From 492d3223b076a9705b64897a061b60720f50d18b Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 29 Jun 2015 14:58:09 +0200 Subject: mmc: sdhci.c: Add config option to use a fixed buffer for transfers While implementing SDIO/MMC SPL booting for the Marvell Armada 38x, the following problem occured. The SPL runs in internal SRAM which is the L2 cache locked to memory. When the MMC buffers now are located on the stack (or bss), the SDIO controller (SDHCI) can't write into this L2 cache memory. This patch introduces a method to use a fixed buffer that will be used for all transfers by defining CONFIG_FIXED_SDHCI_ALIGNED_BUFFER. This way, the board can use this buffer address located in SDRAM for all transfers. This solves this SPL problem on the A38x and should only be used in the SPL U-Boot version. Tested for SPL booting on Marvell Armada 38x DB-88F6820-GP board. Signed-off-by: Stefan Roese Cc: Pantelis Antoniou Cc: Luka Perkov --- drivers/mmc/sdhci.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'drivers') diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index f72536b2aa..d89e302841 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -13,7 +13,11 @@ #include #include +#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) +void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER; +#else void *aligned_buffer; +#endif static void sdhci_reset(struct sdhci_host *host, u8 mask) { @@ -205,6 +209,17 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, memcpy(aligned_buffer, data->src, trans_bytes); } +#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) + /* + * Always use this bounce-buffer when + * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined + */ + is_aligned = 0; + start_addr = (unsigned long)aligned_buffer; + if (data->flags != MMC_DATA_READ) + memcpy(aligned_buffer, data->src, trans_bytes); +#endif + sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); mode |= SDHCI_TRNS_DMA; #endif -- cgit From 2cc1aa2e0010249fe671e38eb412d0cbefb0bf73 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 29 Jun 2015 14:58:12 +0200 Subject: block: ahci: Don't enable port interrupts This patch changes the initialization of the AHCI controller to not enable the default interrupts (DEF_PORT_IRQ). As interrupts are not used in U-Boot in general, this should not break the common AHCI driver operation. This change is needed to support the Marvell Armada 38x AHCI controller. With interrupts enabled, this results in timeouts in ahci_device_data_io(). Not enabling these interrupts fixes this problem and the common AHCI driver works fine. Signed-off-by: Stefan Roese Reviewed-by: Simon Glass Cc: Tom Rini Cc: Hans de Goede Cc: Luka Perkov --- drivers/block/ahci.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'drivers') diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 4fb846ad37..9bab0fce4e 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -299,9 +299,6 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) writel(1 << i, mmio + HOST_IRQ_STAT); - /* set irq mask (enables interrupts) */ - writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); - /* register linkup ports */ tmp = readl(port_mmio + PORT_SCR_STAT); debug("SATA port %d status: 0x%x\n", i, tmp); -- cgit From fe11ae2437e67509b0a0697d932bba10aa686756 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 29 Jun 2015 14:58:15 +0200 Subject: usb: Add EHCI support for Armada 38x (mvebu) This patch adds USB EHCI host support for the common mvebu platform. Including the Armada 38x. Tested on DB-88F6280-GP eval board. Signed-off-by: Stefan Roese Reviewed-by: Marek Vasut Cc: Luka Perkov --- drivers/usb/host/ehci-marvell.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'drivers') diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c index 1a5fd6eefc..03c489c014 100644 --- a/drivers/usb/host/ehci-marvell.c +++ b/drivers/usb/host/ehci-marvell.c @@ -10,6 +10,7 @@ #include #include #include "ehci.h" +#include #include #if defined(CONFIG_KIRKWOOD) @@ -30,6 +31,40 @@ DECLARE_GLOBAL_DATA_PTR; /* * USB 2.0 Bridge Address Decoding registers setup */ +#ifdef CONFIG_ARMADA_XP + +#define MVUSB0_BASE MVEBU_USB20_BASE + +/* + * Once all the older Marvell SoC's (Orion, Kirkwood) are converted + * to the common mvebu archticture including the mbus setup, this + * will be the only function needed to configure the access windows + */ +static void usb_brg_adrdec_setup(void) +{ + const struct mbus_dram_target_info *dram; + int i; + + dram = mvebu_mbus_dram_info(); + + for (i = 0; i < 4; i++) { + wrl(USB_WINDOW_CTRL(i), 0); + wrl(USB_WINDOW_BASE(i), 0); + } + + for (i = 0; i < dram->num_cs; i++) { + const struct mbus_dram_window *cs = dram->cs + i; + + /* Write size, attributes and target id to control register */ + wrl(USB_WINDOW_CTRL(i), + ((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | + (dram->mbus_dram_target_id << 4) | 1); + + /* Write base address to base register */ + wrl(USB_WINDOW_BASE(i), cs->base); + } +} +#else static void usb_brg_adrdec_setup(void) { int i; @@ -69,6 +104,7 @@ static void usb_brg_adrdec_setup(void) wrl(USB_WINDOW_BASE(i), base); } } +#endif /* * Create the appropriate control structures to manage -- cgit From f18d11163e4ea523aff489721db5de752fe062bf Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 1 Jul 2015 21:35:49 +0900 Subject: mtd: fix false positive "Offset exceeds device limit" error Since commit 09c3280754f8 (mtd, nand: Move common functions from cmd_nand.c to common place), NAND commands would not work at all on large devices. => nand read 80000000 10000 10000 NAND read: Offset exceeds device limit => nand erase 100000 100000 NAND erase: Offset exceeds device limit The type of the "size" of "struct mtd_info" is uint64_t, while mtd_arg_off_size() and mtd_arg_off() treat chipsize as int type. The chipsize is wrapped around if the argument is given with 2GB or larger. Acked-by: Heiko Schocher Acked-by: Scott Wood Signed-off-by: Masahiro Yamada --- drivers/mtd/mtd_uboot.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/mtd_uboot.c b/drivers/mtd/mtd_uboot.c index 7197007d41..c517b9c65d 100644 --- a/drivers/mtd/mtd_uboot.c +++ b/drivers/mtd/mtd_uboot.c @@ -43,7 +43,7 @@ static int get_part(const char *partname, int *idx, loff_t *off, loff_t *size, } int mtd_arg_off(const char *arg, int *idx, loff_t *off, loff_t *size, - loff_t *maxsize, int devtype, int chipsize) + loff_t *maxsize, int devtype, uint64_t chipsize) { if (!str2off(arg, off)) return get_part(arg, idx, off, size, maxsize, devtype); @@ -59,7 +59,8 @@ int mtd_arg_off(const char *arg, int *idx, loff_t *off, loff_t *size, } int mtd_arg_off_size(int argc, char *const argv[], int *idx, loff_t *off, - loff_t *size, loff_t *maxsize, int devtype, int chipsize) + loff_t *size, loff_t *maxsize, int devtype, + uint64_t chipsize) { int ret; -- cgit From 5d4a757ca5edb8782188c2bc2735f016e4b6c290 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 7 Jun 2015 08:50:33 -0600 Subject: dm: spi: Correct minor nits in ICH driver Tidy up three minor problems in this file. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Reviewed-by: Jagan Teki --- drivers/spi/ich.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 50354fdde1..6b6cfbf375 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -422,7 +422,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, int using_cmd = 0; int ret; - /* Ee don't support writing partial bytes. */ + /* We don't support writing partial bytes */ if (bitlen % 8) { debug("ICH SPI: Accessing partial bytes not supported\n"); return -EPROTONOSUPPORT; @@ -601,7 +601,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, return status; if (status & SPIS_FCERR) { - debug("ICH SPI: Data transaction error\n"); + debug("ICH SPI: Data transaction error %x\n", status); return -EIO; } @@ -619,7 +619,6 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, return 0; } - /* * This uses the SPI controller from the Intel Cougar Point and Panther Point * PCH to write-protect portions of the SPI flash until reboot. The changes -- cgit From 166c3984e6b1271c2e31ff0528ad65aadc913860 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 12 Jun 2015 14:52:18 +0800 Subject: dm: cpu: Fix undefined ENOSYS build error Include otherwise ENOSYS is undefined. Signed-off-by: Bin Meng Acked-by: Simon Glass --- drivers/cpu/cpu-uclass.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/cpu/cpu-uclass.c b/drivers/cpu/cpu-uclass.c index ab18ee2ea9..aa0267ca03 100644 --- a/drivers/cpu/cpu-uclass.c +++ b/drivers/cpu/cpu-uclass.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include -- cgit From cb5cbfd503d38bfe963ebd52da958563c636709d Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 12 Jun 2015 14:52:19 +0800 Subject: dm: cpu: Test against cpu_ops->get_info in cpu_get_info() In cpu_get_info() it wrongly tests against cpu_ops->get_desc to see if it is NULL. It should test against cpu_ops->get_info. Signed-off-by: Bin Meng --- drivers/cpu/cpu-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/cpu/cpu-uclass.c b/drivers/cpu/cpu-uclass.c index aa0267ca03..d6be9d4dcf 100644 --- a/drivers/cpu/cpu-uclass.c +++ b/drivers/cpu/cpu-uclass.c @@ -26,7 +26,7 @@ int cpu_get_info(struct udevice *dev, struct cpu_info *info) { struct cpu_ops *ops = cpu_get_ops(dev); - if (!ops->get_desc) + if (!ops->get_info) return -ENOSYS; return ops->get_info(dev, info); -- cgit From 780bfdd3c72a058ba24cda0df66ca75f0a7d8b18 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 17 Jun 2015 11:15:34 +0800 Subject: dm: cpu: Add a new get_count method to cpu uclass Introduce a new method 'get_count' in the UCLASS_CPU ops to get the number of CPUs in the system. Signed-off-by: Bin Meng Acked-by: Simon Glass --- drivers/cpu/cpu-uclass.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'drivers') diff --git a/drivers/cpu/cpu-uclass.c b/drivers/cpu/cpu-uclass.c index d6be9d4dcf..a2814a8dcf 100644 --- a/drivers/cpu/cpu-uclass.c +++ b/drivers/cpu/cpu-uclass.c @@ -32,6 +32,16 @@ int cpu_get_info(struct udevice *dev, struct cpu_info *info) return ops->get_info(dev, info); } +int cpu_get_count(struct udevice *dev) +{ + struct cpu_ops *ops = cpu_get_ops(dev); + + if (!ops->get_count) + return -ENOSYS; + + return ops->get_count(dev); +} + U_BOOT_DRIVER(cpu_bus) = { .name = "cpu_bus", .id = UCLASS_SIMPLE_BUS, -- cgit From 6e6f4ce4f82501e35301322872152fe28846d743 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 17 Jun 2015 11:15:36 +0800 Subject: x86: Move MP initialization codes into a common place Most of the MP initialization codes in arch/x86/cpu/baytrail/cpu.c is common to all x86 processors, except detect_num_cpus() which varies from cpu to cpu. Move these to arch/x86/cpu/cpu.c and implement the new 'get_count' method for baytrail and cpu_x86 drivers. Now we call cpu_get_count() in mp_init() to get the number of CPUs. Signed-off-by: Bin Meng Acked-by: Simon Glass --- drivers/cpu/cpu-uclass.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/cpu/cpu-uclass.c b/drivers/cpu/cpu-uclass.c index a2814a8dcf..7660f99ef5 100644 --- a/drivers/cpu/cpu-uclass.c +++ b/drivers/cpu/cpu-uclass.c @@ -12,6 +12,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + int cpu_get_desc(struct udevice *dev, char *buf, int size) { struct cpu_ops *ops = cpu_get_ops(dev); -- cgit From ed2ac0d564c4fac1178d36ea46a34b923c262d03 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Tue, 23 Jun 2015 12:18:41 +0800 Subject: dm: rtc: Support mc146818 driver in driver model Add driver model support to the mc146818 rtc driver. Also clean up the driver a little bit for coding convention issues. Signed-off-by: Bin Meng Acked-by: Simon Glass --- drivers/rtc/mc146818.c | 312 ++++++++++++++++++++++++++++++++----------------- 1 file changed, 204 insertions(+), 108 deletions(-) (limited to 'drivers') diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c index 44857a6e41..363ade33e3 100644 --- a/drivers/rtc/mc146818.c +++ b/drivers/rtc/mc146818.c @@ -9,10 +9,9 @@ * Date & Time support for the MC146818 (PIXX4) RTC */ -/*#define DEBUG*/ - #include #include +#include #include #if defined(__I386__) || defined(CONFIG_MALTA) @@ -24,9 +23,9 @@ #if defined(CONFIG_CMD_DATE) /* Set this to 1 to clear the CMOS RAM */ -#define CLEAR_CMOS 0 +#define CLEAR_CMOS 0 -#define RTC_PORT_MC146818 CONFIG_SYS_ISA_IO_BASE_ADDRESS + 0x70 +#define RTC_PORT_MC146818 CONFIG_SYS_ISA_IO_BASE_ADDRESS + 0x70 #define RTC_SECONDS 0x00 #define RTC_SECONDS_ALARM 0x01 #define RTC_MINUTES 0x02 @@ -37,10 +36,10 @@ #define RTC_DATE_OF_MONTH 0x07 #define RTC_MONTH 0x08 #define RTC_YEAR 0x09 -#define RTC_CONFIG_A 0x0A -#define RTC_CONFIG_B 0x0B -#define RTC_CONFIG_C 0x0C -#define RTC_CONFIG_D 0x0D +#define RTC_CONFIG_A 0x0a +#define RTC_CONFIG_B 0x0b +#define RTC_CONFIG_C 0x0c +#define RTC_CONFIG_D 0x0d #define RTC_REG_SIZE 0x80 #define RTC_CONFIG_A_REF_CLCK_32KHZ (1 << 5) @@ -50,89 +49,7 @@ #define RTC_CONFIG_D_VALID_RAM_AND_TIME 0x80 -/* ------------------------------------------------------------------------- */ - -int rtc_get (struct rtc_time *tmp) -{ - uchar sec, min, hour, mday, wday, mon, year; - /* here check if rtc can be accessed */ - while ((rtc_read8(RTC_CONFIG_A) & 0x80) == 0x80); - sec = rtc_read8(RTC_SECONDS); - min = rtc_read8(RTC_MINUTES); - hour = rtc_read8(RTC_HOURS); - mday = rtc_read8(RTC_DATE_OF_MONTH); - wday = rtc_read8(RTC_DAY_OF_WEEK); - mon = rtc_read8(RTC_MONTH); - year = rtc_read8(RTC_YEAR); -#ifdef RTC_DEBUG - printf ( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " - "hr: %02x min: %02x sec: %02x\n", - year, mon, mday, wday, - hour, min, sec ); - printf ( "Alarms: month: %02x hour: %02x min: %02x sec: %02x\n", - rtc_read8(RTC_CONFIG_D) & 0x3F, - rtc_read8(RTC_HOURS_ALARM), - rtc_read8(RTC_MINUTES_ALARM), - rtc_read8(RTC_SECONDS_ALARM)); -#endif - tmp->tm_sec = bcd2bin (sec & 0x7F); - tmp->tm_min = bcd2bin (min & 0x7F); - tmp->tm_hour = bcd2bin (hour & 0x3F); - tmp->tm_mday = bcd2bin (mday & 0x3F); - tmp->tm_mon = bcd2bin (mon & 0x1F); - tmp->tm_year = bcd2bin (year); - tmp->tm_wday = bcd2bin (wday & 0x07); - if(tmp->tm_year<70) - tmp->tm_year+=2000; - else - tmp->tm_year+=1900; - tmp->tm_yday = 0; - tmp->tm_isdst= 0; -#ifdef RTC_DEBUG - printf ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - - return 0; -} - -int rtc_set (struct rtc_time *tmp) -{ -#ifdef RTC_DEBUG - printf ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - rtc_write8(RTC_CONFIG_B, 0x82); /* disable the RTC to update the regs */ - - rtc_write8(RTC_YEAR, bin2bcd(tmp->tm_year % 100)); - rtc_write8(RTC_MONTH, bin2bcd(tmp->tm_mon)); - rtc_write8(RTC_DAY_OF_WEEK, bin2bcd(tmp->tm_wday)); - rtc_write8(RTC_DATE_OF_MONTH, bin2bcd(tmp->tm_mday)); - rtc_write8(RTC_HOURS, bin2bcd(tmp->tm_hour)); - rtc_write8(RTC_MINUTES, bin2bcd(tmp->tm_min)); - rtc_write8(RTC_SECONDS, bin2bcd(tmp->tm_sec)); - rtc_write8(RTC_CONFIG_B, 0x02); /* enable the RTC to update the regs */ - - return 0; -} - -void rtc_reset (void) -{ - rtc_write8(RTC_CONFIG_B, 0x82); /* disable the RTC to update the regs */ - rtc_write8(RTC_CONFIG_A, 0x20); /* Normal OP */ - rtc_write8(RTC_CONFIG_B, 0x00); - rtc_write8(RTC_CONFIG_B, 0x00); - rtc_write8(RTC_CONFIG_B, 0x02); /* enable the RTC to update the regs */ -} - -/* ------------------------------------------------------------------------- */ - -/* - * use direct memory access - */ -int rtc_read8(int reg) +static int mc146818_read8(int reg) { #ifdef CONFIG_SYS_RTC_REG_BASE_ADDR return in8(CONFIG_SYS_RTC_REG_BASE_ADDR + reg); @@ -149,7 +66,7 @@ int rtc_read8(int reg) #endif } -void rtc_write8(int reg, uchar val) +static void mc146818_write8(int reg, uchar val) { #ifdef CONFIG_SYS_RTC_REG_BASE_ADDR out8(CONFIG_SYS_RTC_REG_BASE_ADDR + reg, val); @@ -165,26 +82,93 @@ void rtc_write8(int reg, uchar val) #endif } -u32 rtc_read32(int reg) +static int mc146818_get(struct rtc_time *tmp) { - u32 value = 0; - int i; + uchar sec, min, hour, mday, wday, mon, year; - for (i = 0; i < sizeof(value); i++) - value |= rtc_read8(reg + i) << (i << 3); + /* here check if rtc can be accessed */ + while ((mc146818_read8(RTC_CONFIG_A) & 0x80) == 0x80) + ; + + sec = mc146818_read8(RTC_SECONDS); + min = mc146818_read8(RTC_MINUTES); + hour = mc146818_read8(RTC_HOURS); + mday = mc146818_read8(RTC_DATE_OF_MONTH); + wday = mc146818_read8(RTC_DAY_OF_WEEK); + mon = mc146818_read8(RTC_MONTH); + year = mc146818_read8(RTC_YEAR); +#ifdef RTC_DEBUG + printf("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x hr: %02x min: %02x sec: %02x\n", + year, mon, mday, wday, hour, min, sec); + printf("Alarms: month: %02x hour: %02x min: %02x sec: %02x\n", + mc146818_read8(RTC_CONFIG_D) & 0x3f, + mc146818_read8(RTC_HOURS_ALARM), + mc146818_read8(RTC_MINUTES_ALARM), + mc146818_read8(RTC_SECONDS_ALARM)); +#endif + tmp->tm_sec = bcd2bin(sec & 0x7f); + tmp->tm_min = bcd2bin(min & 0x7f); + tmp->tm_hour = bcd2bin(hour & 0x3f); + tmp->tm_mday = bcd2bin(mday & 0x3f); + tmp->tm_mon = bcd2bin(mon & 0x1f); + tmp->tm_year = bcd2bin(year); + tmp->tm_wday = bcd2bin(wday & 0x07); + + if (tmp->tm_year < 70) + tmp->tm_year += 2000; + else + tmp->tm_year += 1900; - return value; + tmp->tm_yday = 0; + tmp->tm_isdst = 0; +#ifdef RTC_DEBUG + printf("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +#endif + + return 0; } -void rtc_write32(int reg, u32 value) +static int mc146818_set(struct rtc_time *tmp) { - int i; +#ifdef RTC_DEBUG + printf("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +#endif + /* Disable the RTC to update the regs */ + mc146818_write8(RTC_CONFIG_B, 0x82); - for (i = 0; i < sizeof(value); i++) - rtc_write8(reg + i, (value >> (i << 3)) & 0xff); + mc146818_write8(RTC_YEAR, bin2bcd(tmp->tm_year % 100)); + mc146818_write8(RTC_MONTH, bin2bcd(tmp->tm_mon)); + mc146818_write8(RTC_DAY_OF_WEEK, bin2bcd(tmp->tm_wday)); + mc146818_write8(RTC_DATE_OF_MONTH, bin2bcd(tmp->tm_mday)); + mc146818_write8(RTC_HOURS, bin2bcd(tmp->tm_hour)); + mc146818_write8(RTC_MINUTES, bin2bcd(tmp->tm_min)); + mc146818_write8(RTC_SECONDS, bin2bcd(tmp->tm_sec)); + + /* Enable the RTC to update the regs */ + mc146818_write8(RTC_CONFIG_B, 0x02); + + return 0; } -void rtc_init(void) +static void mc146818_reset(void) +{ + /* Disable the RTC to update the regs */ + mc146818_write8(RTC_CONFIG_B, 0x82); + + /* Normal OP */ + mc146818_write8(RTC_CONFIG_A, 0x20); + mc146818_write8(RTC_CONFIG_B, 0x00); + mc146818_write8(RTC_CONFIG_B, 0x00); + + /* Enable the RTC to update the regs */ + mc146818_write8(RTC_CONFIG_B, 0x02); +} + +static void mc146818_init(void) { #if CLEAR_CMOS int i; @@ -198,14 +182,126 @@ void rtc_init(void) #endif /* Setup the real time clock */ - rtc_write8(RTC_CONFIG_B, RTC_CONFIG_B_24H); + mc146818_write8(RTC_CONFIG_B, RTC_CONFIG_B_24H); /* Setup the frequency it operates at */ - rtc_write8(RTC_CONFIG_A, RTC_CONFIG_A_REF_CLCK_32KHZ | - RTC_CONFIG_A_RATE_1024HZ); + mc146818_write8(RTC_CONFIG_A, RTC_CONFIG_A_REF_CLCK_32KHZ | + RTC_CONFIG_A_RATE_1024HZ); /* Ensure all reserved bits are 0 in register D */ - rtc_write8(RTC_CONFIG_D, RTC_CONFIG_D_VALID_RAM_AND_TIME); + mc146818_write8(RTC_CONFIG_D, RTC_CONFIG_D_VALID_RAM_AND_TIME); /* Clear any pending interrupts */ - rtc_read8(RTC_CONFIG_C); + mc146818_read8(RTC_CONFIG_C); } #endif + +#ifdef CONFIG_DM_RTC + +static int rtc_mc146818_get(struct udevice *dev, struct rtc_time *time) +{ + return mc146818_get(time); +} + +static int rtc_mc146818_set(struct udevice *dev, const struct rtc_time *time) +{ + return mc146818_set((struct rtc_time *)time); +} + +static int rtc_mc146818_reset(struct udevice *dev) +{ + mc146818_reset(); + + return 0; +} + +static int rtc_mc146818_read8(struct udevice *dev, unsigned int reg) +{ + return mc146818_read8(reg); +} + +static int rtc_mc146818_write8(struct udevice *dev, unsigned int reg, int val) +{ + mc146818_write8(reg, val); + + return 0; +} + +static int rtc_mc146818_bind(struct udevice *dev) +{ + mc146818_init(); + + return 0; +} + +static const struct rtc_ops rtc_mc146818_ops = { + .get = rtc_mc146818_get, + .set = rtc_mc146818_set, + .reset = rtc_mc146818_reset, + .read8 = rtc_mc146818_read8, + .write8 = rtc_mc146818_write8, +}; + +static const struct udevice_id rtc_mc146818_ids[] = { + { .compatible = "motorola,mc146818" }, + { } +}; + +U_BOOT_DRIVER(rtc_mc146818) = { + .name = "rtc_mc146818", + .id = UCLASS_RTC, + .of_match = rtc_mc146818_ids, + .bind = rtc_mc146818_bind, + .ops = &rtc_mc146818_ops, +}; + +#else /* !CONFIG_DM_RTC */ + +int rtc_get(struct rtc_time *tmp) +{ + return mc146818_get(tmp); +} + +int rtc_set(struct rtc_time *tmp) +{ + return mc146818_set(tmp); +} + +void rtc_reset(void) +{ + mc146818_reset(); +} + +int rtc_read8(int reg) +{ + return mc146818_read8(reg); +} + +void rtc_write8(int reg, uchar val) +{ + mc146818_write8(reg, val); +} + +u32 rtc_read32(int reg) +{ + u32 value = 0; + int i; + + for (i = 0; i < sizeof(value); i++) + value |= rtc_read8(reg + i) << (i << 3); + + return value; +} + +void rtc_write32(int reg, u32 value) +{ + int i; + + for (i = 0; i < sizeof(value); i++) + rtc_write8(reg + i, (value >> (i << 3)) & 0xff); +} + +void rtc_init(void) +{ + mc146818_init(); +} + +#endif /* CONFIG_DM_RTC */ -- cgit From aec241dfb45e7763716c1cbc98942cb01a3a77fd Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 7 Jun 2015 08:50:40 -0600 Subject: dm: pci: Use the correct hose when configuring devices Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass --- drivers/pci/pci-uclass.c | 6 +++++- drivers/pci/pci_common.c | 6 ++++++ 2 files changed, 11 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index de87505466..41d19cb37a 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -296,6 +296,7 @@ int pci_auto_config_devices(struct udevice *bus) !ret && dev; ret = device_find_next_child(&dev)) { struct pci_child_platdata *pplat; + struct pci_controller *ctlr_hose; pplat = dev_get_parent_platdata(dev); unsigned int max_bus; @@ -303,7 +304,10 @@ int pci_auto_config_devices(struct udevice *bus) bdf = PCI_ADD_BUS(bus->seq, pplat->devfn); debug("%s: device %s\n", __func__, dev->name); - max_bus = pciauto_config_device(hose, bdf); + + /* The root controller has the region information */ + ctlr_hose = hose->ctlr->uclass_priv; + max_bus = pciauto_config_device(ctlr_hose, bdf); sub_bus = max(sub_bus, max_bus); } debug("%s: done\n", __func__); diff --git a/drivers/pci/pci_common.c b/drivers/pci/pci_common.c index b9ff23f35b..f67c9c7b2f 100644 --- a/drivers/pci/pci_common.c +++ b/drivers/pci/pci_common.c @@ -11,6 +11,7 @@ */ #include +#include #include #include #include @@ -221,6 +222,11 @@ phys_addr_t pci_hose_bus_to_phys(struct pci_controller *hose, return phys_addr; } +#ifdef CONFIG_DM_PCI + /* The root controller has the region information */ + hose = hose->ctlr->uclass_priv; +#endif + /* * if PCI_REGION_MEM is set we do a two pass search with preference * on matches that don't have PCI_REGION_SYS_MEMORY set -- cgit From 5afeb4bb456de129a88f38fae1573564cd53fc41 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 7 Jun 2015 08:50:41 -0600 Subject: dm: pci: Correct bus number when scanning sub-buses The sub-bus passed to pciauto_prescan_setup_bridge() is incorrect. Fix it so that sub-buses are numbered correctly. Signed-off-by: Simon Glass --- drivers/pci/pci-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 41d19cb37a..edec93f9a4 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -334,7 +334,7 @@ int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf) sub_bus = pci_get_bus_max() + 1; debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name); - pciauto_prescan_setup_bridge(hose, bdf, bus->seq); + pciauto_prescan_setup_bridge(hose, bdf, sub_bus); ret = device_probe(bus); if (ret) { -- cgit From b018a8c71602d53d5d5ebac859f33327b97e9cec Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 6 Jul 2015 16:31:26 +0800 Subject: video: vesa_fb: Look up VGA device by class instead of id Per PCI spec, VGA device reports its class as standard 030000h in its configuration space, so we can use it to determine if we need run option rom instead of testing the supported vendor/device ids. Signed-off-by: Bin Meng Acked-by: Simon Glass --- drivers/video/vesa_fb.c | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/video/vesa_fb.c b/drivers/video/vesa_fb.c index 47f824a726..909f8e8091 100644 --- a/drivers/video/vesa_fb.c +++ b/drivers/video/vesa_fb.c @@ -1,6 +1,5 @@ /* - * - * Vesa frame buffer driver for x86 + * VESA frame buffer driver * * Copyright (C) 2014 Google, Inc * @@ -17,16 +16,6 @@ */ GraphicDevice ctfb; -/* Devices to allow - only the last one works fully */ -struct pci_device_id vesa_video_ids[] = { - { .vendor = 0x102b, .device = 0x0525 }, - { .vendor = 0x1002, .device = 0x5159 }, - { .vendor = 0x1002, .device = 0x4752 }, - { .vendor = 0x1002, .device = 0x5452 }, - { .vendor = 0x8086, .device = 0x0f31 }, - {}, -}; - void *video_hw_init(void) { GraphicDevice *gdev = &ctfb; @@ -36,8 +25,7 @@ void *video_hw_init(void) printf("Video: "); if (vbe_get_video_info(gdev)) { - /* TODO: Should we look these up by class? */ - dev = pci_find_devices(vesa_video_ids, 0); + dev = pci_find_class(PCI_CLASS_DISPLAY_VGA << 8, 0); if (dev == -1) { printf("no card detected\n"); return NULL; -- cgit From 0e98a1473a85f2d8590f97653a36f90f55267732 Mon Sep 17 00:00:00 2001 From: Jian Luo Date: Mon, 6 Jul 2015 16:31:29 +0800 Subject: video: Add 32-bit color depth support for VBE The TunnelCreek IGD VBE reports 32-bit color depth regardless 24-bit color depth is configured. Since 24-bit mode already uses 4 bytes internally, it should be OK to just add this option in switch case. Signed-off-by: Jian Luo Acked-by: Simon Glass Tested-by: Bin Meng --- drivers/pci/pci_rom.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 37450c8e31..0a644a9bc5 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -203,6 +203,7 @@ int vbe_get_video_info(struct graphic_device *gdev) gdev->gdfBytesPP = vesa->bits_per_pixel / 8; switch (vesa->bits_per_pixel) { + case 32: case 24: gdev->gdfIndex = GDF_32BIT_X888RGB; break; -- cgit From 786a08e0dd3d0505e10cc93622ce5db696c627e9 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 6 Jul 2015 16:31:33 +0800 Subject: x86: Move VGA option rom macros to Kconfig Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on HAVE_VGA_BIOS. The new names are consistent with other x86 binary blob options like HAVE_FSP/FSP_FILE/FSP_ADDR. Signed-off-by: Bin Meng Acked-by: Simon Glass --- drivers/pci/pci_rom.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 0a644a9bc5..dd7fd953ca 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -79,8 +79,8 @@ static int pci_rom_probe(pci_dev_t dev, uint class, if (vendev != mapped_vendev) debug("Device ID mapped to %#08x\n", mapped_vendev); -#ifdef CONFIG_X86_OPTION_ROM_ADDR - rom_address = CONFIG_X86_OPTION_ROM_ADDR; +#ifdef CONFIG_VGA_BIOS_ADDR + rom_address = CONFIG_VGA_BIOS_ADDR; #else if (pciauto_setup_rom(pci_bus_to_hose(PCI_BUS(dev)), dev)) { -- cgit From a452002259e172c93277dbe5752817e0732afe78 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 6 Jul 2015 16:31:36 +0800 Subject: x86: Configure VESA parameters before loading Linux kernel Store VESA parameters to Linux setup header so that vesafb driver in the kernel could work. Signed-off-by: Bin Meng Acked-by: Simon Glass Tested-by: Jian Luo --- drivers/pci/pci_rom.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'drivers') diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index dd7fd953ca..e7f995971c 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -31,6 +31,7 @@ #include #include #include +#include #ifdef CONFIG_HAVE_ACPI_RESUME #include @@ -230,6 +231,33 @@ int vbe_get_video_info(struct graphic_device *gdev) #endif } +void setup_video(struct screen_info *screen_info) +{ +#ifdef CONFIG_FRAMEBUFFER_SET_VESA_MODE + struct vesa_mode_info *vesa = &mode_info.vesa; + + screen_info->orig_video_isVGA = VIDEO_TYPE_VLFB; + + screen_info->lfb_width = vesa->x_resolution; + screen_info->lfb_height = vesa->y_resolution; + screen_info->lfb_depth = vesa->bits_per_pixel; + screen_info->lfb_linelength = vesa->bytes_per_scanline; + screen_info->lfb_base = vesa->phys_base_ptr; + screen_info->lfb_size = + ALIGN(screen_info->lfb_linelength * screen_info->lfb_height, + 65536); + screen_info->lfb_size >>= 16; + screen_info->red_size = vesa->red_mask_size; + screen_info->red_pos = vesa->red_mask_pos; + screen_info->green_size = vesa->green_mask_size; + screen_info->green_pos = vesa->green_mask_pos; + screen_info->blue_size = vesa->blue_mask_size; + screen_info->blue_pos = vesa->blue_mask_pos; + screen_info->rsvd_size = vesa->reserved_mask_size; + screen_info->rsvd_pos = vesa->reserved_mask_pos; +#endif +} + int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), int exec_method) { struct pci_rom_header *rom, *ram; -- cgit From e1e332c8f2e5cac70566998a0ba0ccfdea437f10 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 3 Jul 2015 18:28:21 -0600 Subject: dm: spi: Correct status register access width The status register on ICH9 is a single byte, so use byte access when writing to it, to avoid updating the control register also. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Reviewed-by: Jagan Teki --- drivers/spi/ich.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 6b6cfbf375..66a5cbaaa1 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -411,6 +411,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { struct udevice *bus = dev_get_parent(dev); + struct ich_spi_platdata *plat = dev_get_platdata(bus); struct ich_spi_priv *ctlr = dev_get_priv(bus); uint16_t control; int16_t opcode_index; @@ -477,7 +478,10 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, if (ret < 0) return ret; - ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); + if (plat->ich_version == 7) + ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); + else + ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); spi_setup_type(trans, using_cmd ? bytes : 0); opcode_index = spi_setup_opcode(ctlr, trans); -- cgit From 507879280750fc4af5e5fd0c4387147d286ff6f7 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 3 Jul 2015 18:28:22 -0600 Subject: dm: spi: Correct BIOS protection logic for ICH9 The logic is incorrect and currently has no effect. Fix it so that we can write to SPI flash, since by default it is write-protected. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Andrew Bradford --- drivers/spi/ich.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 66a5cbaaa1..2e388e7ad9 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -40,6 +40,7 @@ struct ich_spi_priv { int status; int control; int bbar; + int bcr; uint32_t *pr; /* only for ich9 */ int speed; /* pointer to speed control */ ulong max_speed; /* Maximum bus speed in MHz */ @@ -239,6 +240,7 @@ static int ich_init_controller(struct ich_spi_platdata *plat, ctlr->speed = ctlr->control + 2; ctlr->bbar = offsetof(struct ich9_spi_regs, bbar); ctlr->preop = offsetof(struct ich9_spi_regs, preop); + ctlr->bcr = offsetof(struct ich9_spi_regs, bcr); ctlr->pr = &ich9_spi->pr[0]; ctlr->base = ich9_spi; } else { @@ -688,13 +690,10 @@ static int ich_spi_probe(struct udevice *bus) * v9, deassert SMM BIOS Write Protect Disable. */ if (plat->use_sbase) { - struct ich9_spi_regs *ich9_spi; - - ich9_spi = priv->base; - bios_cntl = ich_readb(priv, ich9_spi->bcr); + bios_cntl = ich_readb(priv, priv->bcr); bios_cntl &= ~(1 << 5); /* clear Enable InSMM_STS (EISS) */ bios_cntl |= 1; /* Write Protect Disable (WPD) */ - ich_writeb(priv, bios_cntl, ich9_spi->bcr); + ich_writeb(priv, bios_cntl, priv->bcr); } else { pci_read_config_byte(plat->dev, 0xdc, &bios_cntl); if (plat->ich_version == 9) -- cgit From 945cae79e1b547d6edcce53aae68be2e3679a364 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 3 Jul 2015 18:28:25 -0600 Subject: x86: pci: Tidy up the generic x86 PCI driver This driver should use the x86 PCI configuration functions. Also adjust its compatible string to something generic (i.e. without a vendor name). Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/pci/pci_x86.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/pci/pci_x86.c b/drivers/pci/pci_x86.c index 901bdcacce..89e8c119b7 100644 --- a/drivers/pci/pci_x86.c +++ b/drivers/pci/pci_x86.c @@ -7,18 +7,21 @@ #include #include #include +#include -static const struct dm_pci_ops x86_pci_ops = { +static const struct dm_pci_ops pci_x86_ops = { + .read_config = pci_x86_read_config, + .write_config = pci_x86_write_config, }; -static const struct udevice_id x86_pci_ids[] = { - { .compatible = "x86,pci" }, +static const struct udevice_id pci_x86_ids[] = { + { .compatible = "pci-x86" }, { } }; U_BOOT_DRIVER(pci_x86) = { .name = "pci_x86", .id = UCLASS_PCI, - .of_match = x86_pci_ids, - .ops = &x86_pci_ops, + .of_match = pci_x86_ids, + .ops = &pci_x86_ops, }; -- cgit From b9da5086b88a1565c7aede14e68bef2456c44475 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 3 Jul 2015 18:28:27 -0600 Subject: dm: x86: baytrail: Correct PCI region 3 when driver model is used Commit afbbd413a fixed this for non-driver-model. Make sure that the driver model code handles this also. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/pci/pci-uclass.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index edec93f9a4..5b91fe3dce 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -444,6 +444,7 @@ static int decode_regions(struct pci_controller *hose, const void *blob, { int pci_addr_cells, addr_cells, size_cells; int cells_per_record; + phys_addr_t addr; const u32 *prop; int len; int i; @@ -494,8 +495,11 @@ static int decode_regions(struct pci_controller *hose, const void *blob, } /* Add a region for our local memory */ - pci_set_region(hose->regions + hose->region_count++, 0, 0, - gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + addr = gd->ram_size; + if (gd->pci_ram_top && gd->pci_ram_top < addr) + addr = gd->pci_ram_top; + pci_set_region(hose->regions + hose->region_count++, 0, 0, addr, + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); return 0; } -- cgit From e1783b5ba3d32c0471a2b963ebec54e7e7cde264 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sat, 16 May 2015 09:33:16 +0800 Subject: drivers: block: Remove the ata_piix driver This driver was originally added to support the native IDE mode for Intel chipset, however it has some bugs like not supporting ATAPI devices, endianness issue, or even broken build when CONFIG_LAB48. Given no board is using this driver as of today, rather than fixing all these issues we just remove it from the source tree. Signed-off-by: Bin Meng Acked-by: Simon Glass --- drivers/block/Makefile | 1 - drivers/block/ata_piix.c | 717 ----------------------------------------------- drivers/block/ata_piix.h | 71 ----- 3 files changed, 789 deletions(-) delete mode 100644 drivers/block/ata_piix.c delete mode 100644 drivers/block/ata_piix.h (limited to 'drivers') diff --git a/drivers/block/Makefile b/drivers/block/Makefile index 8697da4262..f161c01c67 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -6,7 +6,6 @@ # obj-$(CONFIG_SCSI_AHCI) += ahci.o -obj-$(CONFIG_ATA_PIIX) += ata_piix.o obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o obj-$(CONFIG_FSL_SATA) += fsl_sata.o obj-$(CONFIG_IDE_FTIDE020) += ftide020.o diff --git a/drivers/block/ata_piix.c b/drivers/block/ata_piix.c deleted file mode 100644 index 30426842cc..0000000000 --- a/drivers/block/ata_piix.c +++ /dev/null @@ -1,717 +0,0 @@ -/* - * Copyright (C) Procsys. All rights reserved. - * Author: Mushtaq Khan - * - * - * SPDX-License-Identifier: GPL-2.0+ - * - * with the reference to ata_piix driver in kernel 2.4.32 - */ - -/* - * This file contains SATA controller and SATA drive initialization functions - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define DEBUG_SATA 0 /* For debug prints set DEBUG_SATA to 1 */ - -#define SATA_DECL -#define DRV_DECL /* For file specific declarations */ -#include "ata_piix.h" - -/* Macros realted to PCI */ -#define PCI_SATA_BUS 0x00 -#define PCI_SATA_DEV 0x1f -#define PCI_SATA_FUNC 0x02 - -#define PCI_SATA_BASE1 0x10 -#define PCI_SATA_BASE2 0x14 -#define PCI_SATA_BASE3 0x18 -#define PCI_SATA_BASE4 0x1c -#define PCI_SATA_BASE5 0x20 -#define PCI_PMR 0x90 -#define PCI_PI 0x09 -#define PCI_PCS 0x92 -#define PCI_DMA_CTL 0x48 - -#define PORT_PRESENT (1<<0) -#define PORT_ENABLED (1<<4) - -u32 bdf; -u32 iobase1; /* Primary cmd block */ -u32 iobase2; /* Primary ctl block */ -u32 iobase3; /* Sec cmd block */ -u32 iobase4; /* sec ctl block */ -u32 iobase5; /* BMDMA*/ - -int pci_sata_init(void) -{ - u32 bus = PCI_SATA_BUS; - u32 dev = PCI_SATA_DEV; - u32 fun = PCI_SATA_FUNC; - u16 cmd = 0; - u8 lat = 0, pcibios_max_latency = 0xff; - u8 pmr; /* Port mapping reg */ - u8 pi; /* Prgming Interface reg */ - - bdf = PCI_BDF(bus, dev, fun); - pci_read_config_dword(bdf, PCI_SATA_BASE1, &iobase1); - pci_read_config_dword(bdf, PCI_SATA_BASE2, &iobase2); - pci_read_config_dword(bdf, PCI_SATA_BASE3, &iobase3); - pci_read_config_dword(bdf, PCI_SATA_BASE4, &iobase4); - pci_read_config_dword(bdf, PCI_SATA_BASE5, &iobase5); - - if ((iobase1 == 0xFFFFFFFF) || (iobase2 == 0xFFFFFFFF) || - (iobase3 == 0xFFFFFFFF) || (iobase4 == 0xFFFFFFFF) || - (iobase5 == 0xFFFFFFFF)) { - /* ERROR */ - printf("error no base addr for SATA controller\n"); - return 1; - } - - iobase1 &= 0xFFFFFFFE; - iobase2 &= 0xFFFFFFFE; - iobase3 &= 0xFFFFFFFE; - iobase4 &= 0xFFFFFFFE; - iobase5 &= 0xFFFFFFFE; - - /* check for mode */ - pci_read_config_byte(bdf, PCI_PMR, &pmr); - if (pmr > 1) { - puts("combined mode not supported\n"); - return 1; - } - - pci_read_config_byte(bdf, PCI_PI, &pi); - if ((pi & 0x05) != 0x05) { - puts("Sata is in Legacy mode\n"); - return 1; - } else - puts("sata is in Native mode\n"); - - /* MASTER CFG AND IO CFG */ - pci_read_config_word(bdf, PCI_COMMAND, &cmd); - cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO; - pci_write_config_word(bdf, PCI_COMMAND, cmd); - pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); - - if (lat < 16) - lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; - else if (lat > pcibios_max_latency) - lat = pcibios_max_latency; - pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); - - return 0; -} - -int sata_bus_probe(int port_no) -{ - int orig_mask, mask; - u16 pcs; - - mask = (PORT_PRESENT << port_no); - pci_read_config_word(bdf, PCI_PCS, &pcs); - orig_mask = (int) pcs & 0xff; - if ((orig_mask & mask) != mask) - return 0; - else - return 1; -} - -int init_sata(int dev) -{ - static int done; - u8 i, rv = 0; - - if (!done) - done = 1; - else - return 0; - - rv = pci_sata_init(); - if (rv == 1) { - puts("pci initialization failed\n"); - return 1; - } - - port[0].port_no = 0; - port[0].ioaddr.cmd_addr = iobase1; - port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr = - iobase2 | ATA_PCI_CTL_OFS; - port[0].ioaddr.bmdma_addr = iobase5; - - port[1].port_no = 1; - port[1].ioaddr.cmd_addr = iobase3; - port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr = - iobase4 | ATA_PCI_CTL_OFS; - port[1].ioaddr.bmdma_addr = iobase5 + 0x8; - - for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) - sata_port(&port[i].ioaddr); - - for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) { - if (!(sata_bus_probe(i))) { - port[i].port_state = 0; - printf("SATA#%d port is not present\n", i); - } else { - printf("SATA#%d port is present\n", i); - if (sata_bus_softreset(i)) - port[i].port_state = 0; - else - port[i].port_state = 1; - } - } - - for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) { - u8 j, devno; - - if (port[i].port_state == 0) - continue; - for (j = 0; j < CONFIG_SYS_SATA_DEVS_PER_BUS; j++) { - sata_identify(i, j); - set_Feature_cmd(i, j); - devno = i * CONFIG_SYS_SATA_DEVS_PER_BUS + j; - if ((sata_dev_desc[devno].lba > 0) && - (sata_dev_desc[devno].blksz > 0)) { - dev_print(&sata_dev_desc[devno]); - /* initialize partition type */ - init_part(&sata_dev_desc[devno]); - } - } - } - return 0; -} - -int reset_sata(int dev) -{ - return 0; -} - -static inline u8 sata_inb(unsigned long ioaddr) -{ - return inb(ioaddr); -} - -static inline void sata_outb(unsigned char val, unsigned long ioaddr) -{ - outb(val, ioaddr); -} - -static void output_data(struct sata_ioports *ioaddr, ulong * sect_buf, - int words) -{ - outsw(ioaddr->data_addr, sect_buf, words << 1); -} - -static int input_data(struct sata_ioports *ioaddr, ulong * sect_buf, int words) -{ - insw(ioaddr->data_addr, sect_buf, words << 1); - return 0; -} - -static void sata_cpy(unsigned char *dst, unsigned char *src, unsigned int len) -{ - unsigned char *end, *last; - - last = dst; - end = src + len - 1; - - /* reserve space for '\0' */ - if (len < 2) - goto OUT; - - /* skip leading white space */ - while ((*src) && (src < end) && (*src == ' ')) - ++src; - - /* copy string, omitting trailing white space */ - while ((*src) && (src < end)) { - *dst++ = *src; - if (*src++ != ' ') - last = dst; - } -OUT: - *last = '\0'; -} - -int sata_bus_softreset(int num) -{ - u8 dev = 0, status = 0, i; - - port[num].dev_mask = 0; - - for (i = 0; i < CONFIG_SYS_SATA_DEVS_PER_BUS; i++) { - if (!(sata_devchk(&port[num].ioaddr, i))) { - debug("dev_chk failed for dev#%d\n", i); - } else { - port[num].dev_mask |= (1 << i); - debug("dev_chk passed for dev#%d\n", i); - } - } - - if (!(port[num].dev_mask)) { - printf("no devices on port%d\n", num); - return 1; - } - - dev_select(&port[num].ioaddr, dev); - - port[num].ctl_reg = 0x08; /* Default value of control reg */ - sata_outb(port[num].ctl_reg, port[num].ioaddr.ctl_addr); - udelay(10); - sata_outb(port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr); - udelay(10); - sata_outb(port[num].ctl_reg, port[num].ioaddr.ctl_addr); - - /* - * spec mandates ">= 2ms" before checking status. - * We wait 150ms, because that was the magic delay used for - * ATAPI devices in Hale Landis's ATADRVR, for the period of time - * between when the ATA command register is written, and then - * status is checked. Because waiting for "a while" before - * checking status is fine, post SRST, we perform this magic - * delay here as well. - */ - mdelay(150); - status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 300); - while ((status & ATA_BUSY)) { - mdelay(100); - status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 3); - } - - if (status & ATA_BUSY) - printf("ata%u is slow to respond,plz be patient\n", num); - - while ((status & ATA_BUSY)) { - mdelay(100); - status = sata_chk_status(&port[num].ioaddr); - } - - if (status & ATA_BUSY) { - printf("ata%u failed to respond : bus reset failed\n", num); - return 1; - } - return 0; -} - -void sata_identify(int num, int dev) -{ - u8 cmd = 0, status = 0; - u8 devno = num * CONFIG_SYS_SATA_DEVS_PER_BUS + dev; - u16 iobuf[ATA_SECT_SIZE]; - u64 n_sectors = 0; - u8 mask = 0; - - memset(iobuf, 0, sizeof(iobuf)); - hd_driveid_t *iop = (hd_driveid_t *) iobuf; - - if (dev == 0) - mask = 0x01; - else - mask = 0x02; - - if (!(port[num].dev_mask & mask)) { - printf("dev%d is not present on port#%d\n", dev, num); - return; - } - - printf("port=%d dev=%d\n", num, dev); - - dev_select(&port[num].ioaddr, dev); - - status = 0; - cmd = ATA_CMD_IDENT; /* Device Identify Command */ - sata_outb(cmd, port[num].ioaddr.command_addr); - sata_inb(port[num].ioaddr.altstatus_addr); - udelay(10); - - status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 1000); - if (status & ATA_ERR) { - puts("\ndevice not responding\n"); - port[num].dev_mask &= ~mask; - return; - } - - input_data(&port[num].ioaddr, (ulong *) iobuf, ATA_SECTORWORDS); - - debug("\nata%u: dev %u cfg 49:%04x 82:%04x 83:%04x 84:%04x85:%04x" - "86:%04x" "87:%04x 88:%04x\n", num, dev, iobuf[49], - iobuf[82], iobuf[83], iobuf[84], iobuf[85], iobuf[86], - iobuf[87], iobuf[88]); - - /* we require LBA and DMA support (bits 8 & 9 of word 49) */ - if (!ata_id_has_dma(iobuf) || !ata_id_has_lba(iobuf)) - debug("ata%u: no dma/lba\n", num); - ata_dump_id(iobuf); - - if (ata_id_has_lba48(iobuf)) - n_sectors = ata_id_u64(iobuf, 100); - else - n_sectors = ata_id_u32(iobuf, 60); - debug("no. of sectors %u\n", ata_id_u64(iobuf, 100)); - debug("no. of sectors %u\n", ata_id_u32(iobuf, 60)); - - if (n_sectors == 0) { - port[num].dev_mask &= ~mask; - return; - } - - sata_cpy((unsigned char *)sata_dev_desc[devno].revision, iop->fw_rev, - sizeof(sata_dev_desc[devno].revision)); - sata_cpy((unsigned char *)sata_dev_desc[devno].vendor, iop->model, - sizeof(sata_dev_desc[devno].vendor)); - sata_cpy((unsigned char *)sata_dev_desc[devno].product, iop->serial_no, - sizeof(sata_dev_desc[devno].product)); - strswab(sata_dev_desc[devno].revision); - strswab(sata_dev_desc[devno].vendor); - - if ((iop->config & 0x0080) == 0x0080) - sata_dev_desc[devno].removable = 1; - else - sata_dev_desc[devno].removable = 0; - - sata_dev_desc[devno].lba = iop->lba_capacity; - debug("lba=0x%x", sata_dev_desc[devno].lba); - -#ifdef CONFIG_LBA48 - if (iop->command_set_2 & 0x0400) { - sata_dev_desc[devno].lba48 = 1; - lba = (unsigned long long) iop->lba48_capacity[0] | - ((unsigned long long) iop->lba48_capacity[1] << 16) | - ((unsigned long long) iop->lba48_capacity[2] << 32) | - ((unsigned long long) iop->lba48_capacity[3] << 48); - } else { - sata_dev_desc[devno].lba48 = 0; - } -#endif - - /* assuming HD */ - sata_dev_desc[devno].type = DEV_TYPE_HARDDISK; - sata_dev_desc[devno].blksz = ATA_BLOCKSIZE; - sata_dev_desc[devno].log2blksz = LOG2(sata_dev_desc[devno].blksz); - sata_dev_desc[devno].lun = 0; /* just to fill something in... */ -} - -void set_Feature_cmd(int num, int dev) -{ - u8 mask = 0x00, status = 0; - - if (dev == 0) - mask = 0x01; - else - mask = 0x02; - - if (!(port[num].dev_mask & mask)) { - debug("dev%d is not present on port#%d\n", dev, num); - return; - } - - dev_select(&port[num].ioaddr, dev); - - sata_outb(SETFEATURES_XFER, port[num].ioaddr.feature_addr); - sata_outb(XFER_PIO_4, port[num].ioaddr.nsect_addr); - sata_outb(0, port[num].ioaddr.lbal_addr); - sata_outb(0, port[num].ioaddr.lbam_addr); - sata_outb(0, port[num].ioaddr.lbah_addr); - - sata_outb(ATA_DEVICE_OBS, port[num].ioaddr.device_addr); - sata_outb(ATA_CMD_SETF, port[num].ioaddr.command_addr); - - udelay(50); - mdelay(150); - - status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 5000); - if ((status & (ATA_STAT_BUSY | ATA_STAT_ERR))) { - printf("Error : status 0x%02x\n", status); - port[num].dev_mask &= ~mask; - } -} - -void sata_port(struct sata_ioports *ioport) -{ - ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA; - ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR; - ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE; - ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT; - ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL; - ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM; - ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH; - ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE; - ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS; - ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD; -} - -int sata_devchk(struct sata_ioports *ioaddr, int dev) -{ - u8 nsect, lbal; - - dev_select(ioaddr, dev); - - sata_outb(0x55, ioaddr->nsect_addr); - sata_outb(0xaa, ioaddr->lbal_addr); - - sata_outb(0xaa, ioaddr->nsect_addr); - sata_outb(0x55, ioaddr->lbal_addr); - - sata_outb(0x55, ioaddr->nsect_addr); - sata_outb(0xaa, ioaddr->lbal_addr); - - nsect = sata_inb(ioaddr->nsect_addr); - lbal = sata_inb(ioaddr->lbal_addr); - - if ((nsect == 0x55) && (lbal == 0xaa)) - return 1; /* we found a device */ - else - return 0; /* nothing found */ -} - -void dev_select(struct sata_ioports *ioaddr, int dev) -{ - u8 tmp = 0; - - if (dev == 0) - tmp = ATA_DEVICE_OBS; - else - tmp = ATA_DEVICE_OBS | ATA_DEV1; - - sata_outb(tmp, ioaddr->device_addr); - sata_inb(ioaddr->altstatus_addr); - udelay(5); -} - -u8 sata_busy_wait(struct sata_ioports *ioaddr, int bits, unsigned int max) -{ - u8 status; - - do { - udelay(1000); - status = sata_chk_status(ioaddr); - max--; - } while ((status & bits) && (max > 0)); - - return status; -} - -u8 sata_chk_status(struct sata_ioports *ioaddr) -{ - return sata_inb(ioaddr->status_addr); -} - - -ulong sata_read(int device, ulong blknr, lbaint_t blkcnt, void *buff) -{ - ulong n = 0, *buffer = (ulong *)buff; - u8 dev = 0, num = 0, mask = 0, status = 0; - -#ifdef CONFIG_LBA48 - unsigned char lba48 = 0; - - if (blknr & 0x0000fffff0000000) { - if (!sata_dev_desc[devno].lba48) { - printf("Drive doesn't support 48-bit addressing\n"); - return 0; - } - /* more than 28 bits used, use 48bit mode */ - lba48 = 1; - } -#endif - /* Port Number */ - num = device / CONFIG_SYS_SATA_DEVS_PER_BUS; - /* dev on the port */ - if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS) - dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS; - else - dev = device; - - if (dev == 0) - mask = 0x01; - else - mask = 0x02; - - if (!(port[num].dev_mask & mask)) { - printf("dev%d is not present on port#%d\n", dev, num); - return 0; - } - - /* Select device */ - dev_select(&port[num].ioaddr, dev); - - status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500); - if (status & ATA_BUSY) { - printf("ata%u failed to respond\n", port[num].port_no); - return n; - } - while (blkcnt-- > 0) { - status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500); - if (status & ATA_BUSY) { - printf("ata%u failed to respond\n", 0); - return n; - } -#ifdef CONFIG_LBA48 - if (lba48) { - /* write high bits */ - sata_outb(0, port[num].ioaddr.nsect_addr); - sata_outb((blknr >> 24) & 0xFF, - port[num].ioaddr.lbal_addr); - sata_outb((blknr >> 32) & 0xFF, - port[num].ioaddr.lbam_addr); - sata_outb((blknr >> 40) & 0xFF, - port[num].ioaddr.lbah_addr); - } -#endif - sata_outb(1, port[num].ioaddr.nsect_addr); - sata_outb(((blknr) >> 0) & 0xFF, - port[num].ioaddr.lbal_addr); - sata_outb((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr); - sata_outb((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr); - -#ifdef CONFIG_LBA48 - if (lba48) { - sata_outb(ATA_LBA, port[num].ioaddr.device_addr); - sata_outb(ATA_CMD_READ_EXT, - port[num].ioaddr.command_addr); - } else -#endif - { - sata_outb(ATA_LBA | ((blknr >> 24) & 0xF), - port[num].ioaddr.device_addr); - sata_outb(ATA_CMD_READ, - port[num].ioaddr.command_addr); - } - - mdelay(50); - /* may take up to 4 sec */ - status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 4000); - - if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) - != ATA_STAT_DRQ) { - u8 err = 0; - - printf("Error no DRQ dev %d blk %ld: sts 0x%02x\n", - device, (ulong) blknr, status); - err = sata_inb(port[num].ioaddr.error_addr); - printf("Error reg = 0x%x\n", err); - return n; - } - input_data(&port[num].ioaddr, buffer, ATA_SECTORWORDS); - sata_inb(port[num].ioaddr.altstatus_addr); - udelay(50); - - ++n; - ++blknr; - buffer += ATA_SECTORWORDS; - } - return n; -} - -ulong sata_write(int device, ulong blknr, lbaint_t blkcnt, const void *buff) -{ - ulong n = 0, *buffer = (ulong *)buff; - unsigned char status = 0, num = 0, dev = 0, mask = 0; - -#ifdef CONFIG_LBA48 - unsigned char lba48 = 0; - - if (blknr & 0x0000fffff0000000) { - if (!sata_dev_desc[devno].lba48) { - printf("Drive doesn't support 48-bit addressing\n"); - return 0; - } - /* more than 28 bits used, use 48bit mode */ - lba48 = 1; - } -#endif - /* Port Number */ - num = device / CONFIG_SYS_SATA_DEVS_PER_BUS; - /* dev on the Port */ - if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS) - dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS; - else - dev = device; - - if (dev == 0) - mask = 0x01; - else - mask = 0x02; - - /* Select device */ - dev_select(&port[num].ioaddr, dev); - - status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500); - if (status & ATA_BUSY) { - printf("ata%u failed to respond\n", port[num].port_no); - return n; - } - - while (blkcnt-- > 0) { - status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500); - if (status & ATA_BUSY) { - printf("ata%u failed to respond\n", - port[num].port_no); - return n; - } -#ifdef CONFIG_LBA48 - if (lba48) { - /* write high bits */ - sata_outb(0, port[num].ioaddr.nsect_addr); - sata_outb((blknr >> 24) & 0xFF, - port[num].ioaddr.lbal_addr); - sata_outb((blknr >> 32) & 0xFF, - port[num].ioaddr.lbam_addr); - sata_outb((blknr >> 40) & 0xFF, - port[num].ioaddr.lbah_addr); - } -#endif - sata_outb(1, port[num].ioaddr.nsect_addr); - sata_outb((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr); - sata_outb((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr); - sata_outb((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr); -#ifdef CONFIG_LBA48 - if (lba48) { - sata_outb(ATA_LBA, port[num].ioaddr.device_addr); - sata_outb(ATA_CMD_WRITE_EXT, - port[num].ioaddr.command_addr); - } else -#endif - { - sata_outb(ATA_LBA | ((blknr >> 24) & 0xF), - port[num].ioaddr.device_addr); - sata_outb(ATA_CMD_WRITE, - port[num].ioaddr.command_addr); - } - - mdelay(50); - /* may take up to 4 sec */ - status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 4000); - if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) - != ATA_STAT_DRQ) { - printf("Error no DRQ dev %d blk %ld: sts 0x%02x\n", - device, (ulong) blknr, status); - return n; - } - - output_data(&port[num].ioaddr, buffer, ATA_SECTORWORDS); - sata_inb(port[num].ioaddr.altstatus_addr); - udelay(50); - - ++n; - ++blknr; - buffer += ATA_SECTORWORDS; - } - return n; -} - -int scan_sata(int dev) -{ - return 0; -} diff --git a/drivers/block/ata_piix.h b/drivers/block/ata_piix.h deleted file mode 100644 index 6c68ea2f01..0000000000 --- a/drivers/block/ata_piix.h +++ /dev/null @@ -1,71 +0,0 @@ -#ifndef __ATA_PIIX_H__ -#define __ATA_PIIX_H__ - -struct sata_ioports { - unsigned long cmd_addr; - unsigned long data_addr; - unsigned long error_addr; - unsigned long feature_addr; - unsigned long nsect_addr; - unsigned long lbal_addr; - unsigned long lbam_addr; - unsigned long lbah_addr; - unsigned long device_addr; - unsigned long status_addr; - unsigned long command_addr; - unsigned long altstatus_addr; - unsigned long ctl_addr; - unsigned long bmdma_addr; - unsigned long scr_addr; -}; - -struct sata_port { - unsigned char port_no; /* primary=0, secondary=1 */ - struct sata_ioports ioaddr; /* ATA cmd/ctl/dma reg blks */ - unsigned char ctl_reg; - unsigned char last_ctl; - unsigned char port_state; /* 1-port is available and */ - /* 0-port is not available */ - unsigned char dev_mask; -}; - -/***********SATA LIBRARY SPECIFIC DEFINITIONS AND DECLARATIONS**************/ -#ifdef SATA_DECL /* SATA library specific declarations */ -inline void ata_dump_id(u16 *id) -{ - debug("49 = 0x%04x " - "53 = 0x%04x " - "63 = 0x%04x " - "64 = 0x%04x " - "75 = 0x%04x\n", id[49], id[53], id[63], id[64], id[75]); - debug("80 = 0x%04x " - "81 = 0x%04x " - "82 = 0x%04x " - "83 = 0x%04x " - "84 = 0x%04x\n", id[80], id[81], id[82], id[83], id[84]); - debug("88 = 0x%04x " "93 = 0x%04x\n", id[88], id[93]); -} -#endif - -#ifdef SATA_DECL /*SATA library specific declarations */ -int sata_bus_softreset(int num); -void sata_identify(int num, int dev); -void sata_port(struct sata_ioports *ioport); -void set_Feature_cmd(int num, int dev); -int sata_devchk(struct sata_ioports *ioaddr, int dev); -void dev_select(struct sata_ioports *ioaddr, int dev); -u8 sata_busy_wait(struct sata_ioports *ioaddr, int bits, unsigned int max); -u8 sata_chk_status(struct sata_ioports *ioaddr); -#endif - -/************DRIVER SPECIFIC DEFINITIONS AND DECLARATIONS**************/ - -#ifdef DRV_DECL /* Driver specific declaration */ -int init_sata(int dev); -#endif - -#ifdef DRV_DECL /* Defines Driver Specific variables */ -struct sata_port port[CONFIG_SYS_SATA_MAXBUS]; -#endif - -#endif /* __ATA_PIIX_H__ */ -- cgit From 6c89663cb152bb49f7618f283d999c417fd85746 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 8 Jul 2015 13:06:40 +0800 Subject: pci: Configure expansion ROM during auto config process Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng Reviewed-by: Simon Glass Tested-by: Simon Glass Acked-by: Simon Glass --- drivers/pci/pci_auto.c | 48 ++++++++++++++++++++++-------------------------- drivers/pci/pci_rom.c | 5 ----- 2 files changed, 22 insertions(+), 31 deletions(-) (limited to 'drivers') diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index 7c109832f6..e034ed1715 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -87,6 +87,8 @@ void pciauto_setup_device(struct pci_controller *hose, pci_size_t bar_size; u16 cmdstat = 0; int bar, bar_nr = 0; + u8 header_type; + int rom_addr; #ifndef CONFIG_PCI_ENUM_ONLY pci_addr_t bar_value; struct pci_region *bar_res; @@ -182,38 +184,32 @@ void pciauto_setup_device(struct pci_controller *hose, bar_nr++; } + /* Configure the expansion ROM address */ + pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type); + if (header_type != PCI_HEADER_TYPE_CARDBUS) { + rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ? + PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1; + pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe); + pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response); + if (bar_response) { + bar_size = -(bar_response & ~1); + DEBUGF("PCI Autoconfig: ROM, size=%#x, ", bar_size); + if (pciauto_region_allocate(mem, bar_size, + &bar_value) == 0) { + pci_hose_write_config_dword(hose, dev, rom_addr, + bar_value); + } + cmdstat |= PCI_COMMAND_MEMORY; + DEBUGF("\n"); + } + } + pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat); pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, CONFIG_SYS_PCI_CACHE_LINE_SIZE); pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); } -int pciauto_setup_rom(struct pci_controller *hose, pci_dev_t dev) -{ - pci_addr_t bar_value; - pci_size_t bar_size; - u32 bar_response; - u16 cmdstat = 0; - - pci_hose_write_config_dword(hose, dev, PCI_ROM_ADDRESS, 0xfffffffe); - pci_hose_read_config_dword(hose, dev, PCI_ROM_ADDRESS, &bar_response); - if (!bar_response) - return -ENOENT; - - bar_size = -(bar_response & ~1); - DEBUGF("PCI Autoconfig: ROM, size=%#x, ", bar_size); - if (pciauto_region_allocate(hose->pci_mem, bar_size, &bar_value) == 0) { - pci_hose_write_config_dword(hose, dev, PCI_ROM_ADDRESS, - bar_value); - } - DEBUGF("\n"); - pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat); - cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; - pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat); - - return 0; -} - void pciauto_prescan_setup_bridge(struct pci_controller *hose, pci_dev_t dev, int sub_bus) { diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index e7f995971c..aa06767d2a 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -84,11 +84,6 @@ static int pci_rom_probe(pci_dev_t dev, uint class, rom_address = CONFIG_VGA_BIOS_ADDR; #else - if (pciauto_setup_rom(pci_bus_to_hose(PCI_BUS(dev)), dev)) { - debug("Cannot find option ROM\n"); - return -ENOENT; - } - pci_read_config_dword(dev, PCI_ROM_ADDRESS, &rom_address); if (rom_address == 0x00000000 || rom_address == 0xffffffff) { debug("%s: rom_address=%x\n", __func__, rom_address); -- cgit From f110da9984c0aa0aba9e1c4178b67b7abecf7e8d Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 8 Jul 2015 13:06:41 +0800 Subject: pci: Disable expansion ROM address decoding when signature check fails We should not leave the expansion ROM address window open when there is not a valid ROM. Suggested-by: Matt Porter Signed-off-by: Bin Meng Tested-by: Simon Glass Acked-by: Simon Glass --- drivers/pci/pci_rom.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index aa06767d2a..a33efae263 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -104,6 +104,10 @@ static int pci_rom_probe(pci_dev_t dev, uint class, if (le16_to_cpu(rom_header->signature) != PCI_ROM_HDR) { printf("Incorrect expansion ROM header signature %04x\n", le16_to_cpu(rom_header->signature)); +#ifndef CONFIG_VGA_BIOS_ADDR + /* Disable expansion ROM address decoding */ + pci_write_config_dword(dev, PCI_ROM_ADDRESS, rom_address); +#endif return -EINVAL; } -- cgit