From f0b5f23f32adfb790293c4f1722042026fa98416 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Fri, 4 Dec 2015 12:32:48 -0700 Subject: ARM: imx: fsl_esdhc: fix usage of low 4 bits of sysctl register The low four bits of the SYSCTL register are reserved on the USDHC controller on i.MX6 and i.MX7 processors, but are used for clocking operations on earlier models. Guard against their usage by hiding the bit mask macros on those processors. These bits are used to prevent glitches when changing clocks on i.MX35 et al. Use the RSTA bit instead for i.MX6 and i.MX7. >From the i.MX6DQ RM: To prevent possible glitch on the card clock, clear the FRC_SDCLK_ON bit when changing clock divisor value(SDCLKFS or DVS in System Control Register) or setting RSTA bit. Signed-off-by: Eric Nelson Reviewed-by: Fabio Estevam Reviewed-by: Stefano Babic Reviewed-by: Hector Palacios --- drivers/mmc/fsl_esdhc.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index c5054d66bd..1ccc576c34 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -502,15 +502,22 @@ static void set_sysctl(struct mmc *mmc, uint clock) clk = (pre_div << 8) | (div << 4); +#ifdef CONFIG_FSL_USDHC + esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); +#else esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); +#endif esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); udelay(10000); - clk = SYSCTL_PEREN | SYSCTL_CKEN; +#ifdef CONFIG_FSL_USDHC + esdhc_clrbits32(®s->sysctl, SYSCTL_RSTA); +#else + esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); +#endif - esdhc_setbits32(®s->sysctl, clk); } #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK @@ -585,7 +592,9 @@ static int esdhc_init(struct mmc *mmc) esdhc_write32(®s->scr, 0x00000040); #endif +#ifndef CONFIG_FSL_USDHC esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); +#endif /* Set the initial clock speed */ mmc_set_clock(mmc, 400000); @@ -657,8 +666,10 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) /* First reset the eSDHC controller */ esdhc_reset(regs); +#ifndef CONFIG_FSL_USDHC esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN | SYSCTL_IPGEN | SYSCTL_CKEN); +#endif writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); memset(&cfg->cfg, 0, sizeof(cfg->cfg)); -- cgit From 434afa809e91bbf67e003df8daf0e2f39c48ce59 Mon Sep 17 00:00:00 2001 From: Maximilian Schwerin Date: Wed, 25 Nov 2015 14:08:00 +0100 Subject: serial_mxc: Fix setup of UARTx_UFCR register This patch writes the default values for TXTL and RXTL to UARTx_UFCR. Without this patch some older kernel versions crash as UARTx_UFCR was not always correctly initialized. Signed-off-by: Maximilian Schwerin --- drivers/serial/serial_mxc.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index d6cf1d874a..51485c0d09 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -75,6 +75,7 @@ #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ +#define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */ #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ #define USR1_RTSS (1<<14) /* RTS pin status */ @@ -135,6 +136,10 @@ DECLARE_GLOBAL_DATA_PTR; +#define TXTL 2 /* reset default */ +#define RXTL 1 /* reset default */ +#define RFDIV 4 /* divide input clock by 2 */ + static void mxc_serial_setbrg(void) { u32 clk = imx_get_uartclk(); @@ -142,7 +147,9 @@ static void mxc_serial_setbrg(void) if (!gd->baudrate) gd->baudrate = CONFIG_BAUDRATE; - __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */ + __REG(UART_PHYS + UFCR) = (RFDIV << UFCR_RFDIV_SHF) + | (TXTL << UFCR_TXTL_SHF) + | (RXTL << UFCR_RXTL_SHF); __REG(UART_PHYS + UBIR) = 0xf; __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); -- cgit From 843a3e5893a713a3df752d30d31861d5b03ad75c Mon Sep 17 00:00:00 2001 From: Måns Rullgård Date: Tue, 8 Dec 2015 15:38:45 +0000 Subject: net: fec_mxc: configure MDIO hold time If the host clock frequency is higher than 100 MHz, the MDIO hold time needs to be increased from its current setting of one cycle in order to meet the specified minium of 10 ns. Writing an appropriate value to the HOLDTIME field of the MII_SPEED register achieves this. Comment copied from Linux kernel. Signed-off-by: Mans Rullgard Reviewed-by: Eric Nelson --- drivers/net/fec_mxc.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 79f6737e8e..798cc165dd 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -131,13 +131,25 @@ static void fec_mii_setspeed(struct ethernet_regs *eth) /* * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock * and do not drop the Preamble. + * + * The i.MX28 and i.MX6 types have another field in the MSCR (aka + * MII_SPEED) register that defines the MDIO output hold time. Earlier + * versions are RAZ there, so just ignore the difference and write the + * register always. + * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. + * HOLDTIME + 1 is the number of clk cycles the fec is holding the + * output. + * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). + * Given that ceil(clkrate / 5000000) <= 64, the calculation for + * holdtime cannot result in a value greater than 3. */ - register u32 speed = DIV_ROUND_UP(imx_get_fecclk(), 5000000); + u32 pclk = imx_get_fecclk(); + u32 speed = DIV_ROUND_UP(pclk, 5000000); + u32 hold = DIV_ROUND_UP(pclk, 100000000) - 1; #ifdef FEC_QUIRK_ENET_MAC speed--; #endif - speed <<= 1; - writel(speed, ð->mii_speed); + writel(speed << 1 | hold << 8, ð->mii_speed); debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed)); } -- cgit From 845a57b4de972aefb21bf7f13b23d472bccb6afb Mon Sep 17 00:00:00 2001 From: Måns Rullgård Date: Tue, 8 Dec 2015 15:38:46 +0000 Subject: net: fec_mxc: unregister mdio bus on probe error If fecmxc_initialize_multi() fails, it frees but does not unregister the mdio bus, causing subsequent uses of the "mii" command to crash. Fix this by adding mdio_unregister() calls where needed. Signed-off-by: Mans Rullgard Reviewed-by: Eric Nelson --- drivers/net/fec_mxc.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 798cc165dd..3340dd256f 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -1109,6 +1109,7 @@ int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) #ifdef CONFIG_PHYLIB phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII); if (!phydev) { + mdio_unregister(bus); free(bus); return -ENOMEM; } @@ -1120,6 +1121,7 @@ int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) #ifdef CONFIG_PHYLIB free(phydev); #endif + mdio_unregister(bus); free(bus); } return ret; -- cgit From aee3fddb677d86a131d9ac7bac2251f9a6ab2975 Mon Sep 17 00:00:00 2001 From: Gong Qianyu Date: Fri, 18 Dec 2015 17:38:01 +0800 Subject: i2c: mxc: add a condition in case the parameter is NULL This could avoid executing the code that only applies to i.MX platforms. The bus_i2c_init() is called before relocation and will assgin value to a static variable. If U-Boot is then still running in a flash device, it's theoretically not allowed to write data to flash without an erasing operation. For i.MX platforms, the U-Boot is always running in DDR. Actually it causes asynchronous error when the ARM64 system error report is enabled and the flash write protect is set. Signed-off-by: Gong Qianyu Reviewed-by: Heiko Schocher --- drivers/i2c/mxc_i2c.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index fa4c82f1a2..b2d15c9b6a 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -581,8 +581,16 @@ void bus_i2c_init(int index, int speed, int unused, return; } - mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn; - mxc_i2c_buses[index].idle_bus_data = idle_bus_data; + /* + * Warning: Be careful to allow the assignment to a static + * variable here. This function could be called while U-Boot is + * still running in flash memory. So such assignment is equal + * to write data to flash without erasing. + */ + if (idle_bus_fn) + mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn; + if (idle_bus_data) + mxc_i2c_buses[index].idle_bus_data = idle_bus_data; ret = enable_i2c_clk(1, index); if (ret < 0) { -- cgit