From 3a5648259014abba09ea7f243b244b60660d4358 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Wed, 14 May 2014 16:58:03 -0700 Subject: serial_mxc: disable new features of autobaud detection Bit 7 of UCR3 is described in the i.MX3x/i.MX5x/i.MX6x reference manuals as follows: Autobaud Detection Not Improved-. Disables new features of autobaud detection (See Baud Rate Automatic Detection Protocol, for more details). 0 Autobaud detection new features selected 1 Keep old autobaud detection mechanism On at least i.MX6DQ, i.MX6DLS and i.MX53, the "new features" occasionally cause the receiver to get out of sync and continuously produce received characters of '\xff'. This patch disables the "new feature" on all boards, since there's no support for auto-baud in U-Boot on any of them. More details are available in this post on i.MX Community: https://community.freescale.com/message/403254 Signed-off-by: Eric Nelson Tested-by: Fabio Estevam Acked-by: Stefano Babic --- drivers/serial/serial_mxc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index 56bee55208..313d560afc 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -77,7 +77,7 @@ #define UCR3_DSR (1<<10) /* Data set ready */ #define UCR3_DCD (1<<9) /* Data carrier detect */ #define UCR3_RI (1<<8) /* Ring indicator */ -#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ +#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ @@ -186,7 +186,7 @@ static int mxc_serial_init(void) while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST)); - __REG(UART_PHYS + UCR3) = 0x0704; + __REG(UART_PHYS + UCR3) = 0x0704 | UCR3_ADNIMP; __REG(UART_PHYS + UCR4) = 0x8000; __REG(UART_PHYS + UESC) = 0x002b; __REG(UART_PHYS + UTIM) = 0x0; -- cgit From 73210dccdb41b6164a715c363c1a0e28fed1be49 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 2 Jun 2014 16:13:18 -0700 Subject: spl: nand: add support for mxs nand This utilizes existing mxs_nand support layer to provide a method to load an image off nand for SPL. The flash device will be detected in order to support multiple flash devices instead of having layout hard coded at build time. Cc: Stefan Roese Cc: Otavio Salvador Cc: Andy Ng Cc: Eric Nelson Cc: Tapani Utriainen Cc: Tom Rini Cc: Scott Wood Signed-off-by: Tim Harvey --- drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/mxs_nand_spl.c | 231 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 232 insertions(+) create mode 100644 drivers/mtd/nand/mxs_nand_spl.c (limited to 'drivers') diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 4eb354da93..bf1312a373 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -68,5 +68,6 @@ else # minimal SPL drivers obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o obj-$(CONFIG_NAND_MXC) += mxc_nand_spl.o +obj-$(CONFIG_NAND_MXS) += mxs_nand_spl.o mxs_nand.o endif # drivers diff --git a/drivers/mtd/nand/mxs_nand_spl.c b/drivers/mtd/nand/mxs_nand_spl.c new file mode 100644 index 0000000000..0e7c364a22 --- /dev/null +++ b/drivers/mtd/nand/mxs_nand_spl.c @@ -0,0 +1,231 @@ +/* + * Copyright (C) 2014 Gateworks Corporation + * Author: Tim Harvey + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include + +static nand_info_t mtd; +static struct nand_chip nand_chip; + +static void mxs_nand_command(struct mtd_info *mtd, unsigned int command, + int column, int page_addr) +{ + register struct nand_chip *chip = mtd->priv; + u32 timeo, time_start; + + /* write out the command to the device */ + chip->cmd_ctrl(mtd, command, NAND_CLE); + + /* Serially input address */ + if (column != -1) { + chip->cmd_ctrl(mtd, column, NAND_ALE); + chip->cmd_ctrl(mtd, column >> 8, NAND_ALE); + } + if (page_addr != -1) { + chip->cmd_ctrl(mtd, page_addr, NAND_ALE); + chip->cmd_ctrl(mtd, page_addr >> 8, NAND_ALE); + /* One more address cycle for devices > 128MiB */ + if (chip->chipsize > (128 << 20)) + chip->cmd_ctrl(mtd, page_addr >> 16, NAND_ALE); + } + chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0); + + if (command == NAND_CMD_READ0) { + chip->cmd_ctrl(mtd, NAND_CMD_READSTART, NAND_CLE); + chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0); + } + + /* wait for nand ready */ + ndelay(100); + timeo = (CONFIG_SYS_HZ * 20) / 1000; + time_start = get_timer(0); + while (get_timer(time_start) < timeo) { + if (chip->dev_ready(mtd)) + break; + } +} + +static int mxs_flash_ident(struct mtd_info *mtd) +{ + register struct nand_chip *chip = mtd->priv; + int i; + u8 mfg_id, dev_id; + u8 id_data[8]; + struct nand_onfi_params *p = &chip->onfi_params; + + /* Reset the chip */ + chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + + /* Send the command for reading device ID */ + chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); + + /* Read manufacturer and device IDs */ + mfg_id = chip->read_byte(mtd); + dev_id = chip->read_byte(mtd); + + /* Try again to make sure */ + chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); + for (i = 0; i < 8; i++) + id_data[i] = chip->read_byte(mtd); + if (id_data[0] != mfg_id || id_data[1] != dev_id) { + printf("second ID read did not match"); + return -1; + } + debug("0x%02x:0x%02x ", mfg_id, dev_id); + + /* read ONFI */ + chip->onfi_version = 0; + chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1); + if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' || + chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I') { + return -2; + } + + /* we have ONFI, probe it */ + chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); + chip->read_buf(mtd, (uint8_t *)p, sizeof(*p)); + mtd->name = p->model; + mtd->writesize = le32_to_cpu(p->byte_per_page); + mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize; + mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); + chip->chipsize = le32_to_cpu(p->blocks_per_lun); + chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; + /* Calculate the address shift from the page size */ + chip->page_shift = ffs(mtd->writesize) - 1; + chip->phys_erase_shift = ffs(mtd->erasesize) - 1; + /* Convert chipsize to number of pages per chip -1 */ + chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; + chip->badblockbits = 8; + + debug("erasesize=%d (>>%d)\n", mtd->erasesize, chip->phys_erase_shift); + debug("writesize=%d (>>%d)\n", mtd->writesize, chip->page_shift); + debug("oobsize=%d\n", mtd->oobsize); + debug("chipsize=%lld\n", chip->chipsize); + + return 0; +} + +static int mxs_read_page_ecc(struct mtd_info *mtd, void *buf, unsigned int page) +{ + register struct nand_chip *chip = mtd->priv; + int ret; + + chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page); + ret = nand_chip.ecc.read_page(mtd, chip, buf, 1, page); + if (ret < 0) { + printf("read_page failed %d\n", ret); + return -1; + } + return 0; +} + +static int is_badblock(struct mtd_info *mtd, loff_t offs, int allowbbt) +{ + register struct nand_chip *chip = mtd->priv; + unsigned int block = offs >> chip->phys_erase_shift; + unsigned int page = offs >> chip->page_shift; + + debug("%s offs=0x%08x block:%d page:%d\n", __func__, (int)offs, block, + page); + chip->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page); + memset(chip->oob_poi, 0, mtd->oobsize); + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); + + return chip->oob_poi[0] != 0xff; +} + +/* setup mtd and nand structs and init mxs_nand driver */ +static int mxs_nand_init(void) +{ + /* return if already initalized */ + if (nand_chip.numchips) + return 0; + + /* init mxs nand driver */ + board_nand_init(&nand_chip); + mtd.priv = &nand_chip; + /* set mtd functions */ + nand_chip.cmdfunc = mxs_nand_command; + nand_chip.numchips = 1; + + /* identify flash device */ + puts("NAND : "); + if (mxs_flash_ident(&mtd)) { + printf("Failed to identify\n"); + return -1; + } + + /* allocate and initialize buffers */ + nand_chip.buffers = memalign(ARCH_DMA_MINALIGN, + sizeof(*nand_chip.buffers)); + nand_chip.oob_poi = nand_chip.buffers->databuf + mtd.writesize; + /* setup flash layout (does not scan as we override that) */ + mtd.size = nand_chip.chipsize; + nand_chip.scan_bbt(&mtd); + + printf("%llu MiB\n", (mtd.size / (1024 * 1024))); + return 0; +} + +int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf) +{ + struct nand_chip *chip; + unsigned int page; + unsigned int nand_page_per_block; + unsigned int sz = 0; + + if (mxs_nand_init()) + return -ENODEV; + chip = mtd.priv; + page = offs >> chip->page_shift; + nand_page_per_block = mtd.erasesize / mtd.writesize; + + debug("%s offset:0x%08x len:%d page:%d\n", __func__, offs, size, page); + + size = roundup(size, mtd.writesize); + while (sz < size) { + if (mxs_read_page_ecc(&mtd, buf, page) < 0) + return -1; + sz += mtd.writesize; + offs += mtd.writesize; + page++; + buf += mtd.writesize; + + /* + * Check if we have crossed a block boundary, and if so + * check for bad block. + */ + if (!(page % nand_page_per_block)) { + /* + * Yes, new block. See if this block is good. If not, + * loop until we find a good block. + */ + while (is_badblock(&mtd, offs, 1)) { + page = page + nand_page_per_block; + /* Check i we've reached the end of flash. */ + if (page >= mtd.size >> chip->page_shift) + return -ENOMEM; + } + } + } + + return 0; +} + +int nand_default_bbt(struct mtd_info *mtd) +{ + return 0; +} + +void nand_init(void) +{ +} + +void nand_deselect(void) +{ +} + -- cgit From ca84d72d1cfd7629118abce15c0b24cd7413692c Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Wed, 7 May 2014 22:23:35 -0700 Subject: dwc_ahsata: return failure for MX6 if not IMX6Q/IMX6D The IMX6QUAD/DUAL have SATA, but the IMX6SOLO/DL do not. Return failure instead of attempting a memory access that results in a data abort and reset. Signed-off-by: Tim Harvey --- drivers/block/dwc_ahsata.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers') diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c index 3569214297..15d65d77f3 100644 --- a/drivers/block/dwc_ahsata.c +++ b/drivers/block/dwc_ahsata.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "dwc_ahsata.h" struct sata_port_regs { @@ -558,6 +559,10 @@ int init_sata(int dev) u32 linkmap; struct ahci_probe_ent *probe_ent = NULL; +#if defined(CONFIG_MX6) + if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D)) + return 1; +#endif if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { printf("The sata index %d is out of ranges\n\r", dev); return -1; -- cgit