From 40ed88529c6ad73c20908c2c5cdbdcc01da3d476 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Wed, 27 May 2020 13:31:29 +1200 Subject: mv_ddr: ddr3: Use correct bitmask for read sample delay In the Armada 385 functional spec (MV-S109094-00 Rev. C) the read sample delay fields are 5 bits wide. Use the correct bitmask of 0x1f when extracting the value. Signed-off-by: Chris Packham [upstream https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/22] Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c index df832ac6dc..ce9a47fc2c 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c @@ -11,7 +11,7 @@ #define VREF_MAX_INDEX 7 #define MAX_VALUE (1024 - 1) #define MIN_VALUE (-MAX_VALUE) -#define GET_RD_SAMPLE_DELAY(data, cs) ((data >> rd_sample_mask[cs]) & 0xf) +#define GET_RD_SAMPLE_DELAY(data, cs) ((data >> rd_sample_mask[cs]) & 0x1f) u32 ca_delay; int ddr3_tip_centr_skip_min_win_check = 0; -- cgit From 485dbd3f1088c091c32138845f2f645d51d00667 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Wed, 27 May 2020 13:31:30 +1200 Subject: mv_ddr: ddr3: Update {min,max}_read_sample calculation Measurements on actual hardware shown that the read ODT is early by 3 clocks. Adjust the calculation to avoid this. Signed-off-by: Chris Packham [upstream https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/22] Signed-off-by: Chris Packham Tested-by: Baruch Siach Reviewed-by: Stefan Roese --- drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c index ce9a47fc2c..58ffb20507 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c @@ -91,8 +91,8 @@ int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id) min_read_sample = read_sample[cs_num]; } - min_read_sample = min_read_sample - 1; - max_read_sample = max_read_sample + 4 + (max_phase + 1) / 2 + 1; + min_read_sample = min_read_sample + 2; + max_read_sample = max_read_sample + 7 + (max_phase + 1) / 2 + 1; if (min_read_sample >= 0xf) min_read_sample = 0xf; if (max_read_sample >= 0x1f) -- cgit From 3078e03516934c016ef3ea15f8bce19df3948dfe Mon Sep 17 00:00:00 2001 From: Sven Auhagen Date: Wed, 1 Jul 2020 17:43:43 +0200 Subject: net: mvpp2: fix second cp110 initialization Since the mdio code got upstreamed it is not possible to activate network ports on CP110 Master and Slave. The problem is in mvpp2_base_probe which is called for each CP110 and it initializes the buffer area for descs and rx_buffers. This should only happen once though and the bd space is actually set to 0 after the first run of the function. This leads to an error when the second CP110 tries the initialization again and disables all network ports on this CP110. This patch adds a static variable to check if the buffer area is initialized only once globally. Signed-off-by: Sven Auhagen Reviewed-by: Stefan Roese --- drivers/net/mvpp2.c | 63 +++++++++++++++++++++++++++++------------------------ 1 file changed, 34 insertions(+), 29 deletions(-) (limited to 'drivers') diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 19b9375ee2..a5747a25ab 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -1263,6 +1263,7 @@ struct buffer_location { * can be enabled at once */ static struct buffer_location buffer_loc; +static int buffer_loc_init; /* * Page table entries are set to 1MB, or multiples of 1MB @@ -5247,40 +5248,44 @@ static int mvpp2_base_probe(struct udevice *dev) * be active. Make this area DMA-safe by disabling the D-cache */ - /* Align buffer area for descs and rx_buffers to 1MiB */ - bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); - mmu_set_region_dcache_behaviour((unsigned long)bd_space, - BD_SPACE, DCACHE_OFF); - - buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space; - size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE; - - buffer_loc.tx_descs = - (struct mvpp2_tx_desc *)((unsigned long)bd_space + size); - size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE; + if (!buffer_loc_init) { + /* Align buffer area for descs and rx_buffers to 1MiB */ + bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); + mmu_set_region_dcache_behaviour((unsigned long)bd_space, + BD_SPACE, DCACHE_OFF); + + buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space; + size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE; + + buffer_loc.tx_descs = + (struct mvpp2_tx_desc *)((unsigned long)bd_space + size); + size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE; + + buffer_loc.rx_descs = + (struct mvpp2_rx_desc *)((unsigned long)bd_space + size); + size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE; + + for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { + buffer_loc.bm_pool[i] = + (unsigned long *)((unsigned long)bd_space + size); + if (priv->hw_version == MVPP21) + size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32); + else + size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64); + } - buffer_loc.rx_descs = - (struct mvpp2_rx_desc *)((unsigned long)bd_space + size); - size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE; + for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) { + buffer_loc.rx_buffer[i] = + (unsigned long *)((unsigned long)bd_space + size); + size += RX_BUFFER_SIZE; + } - for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { - buffer_loc.bm_pool[i] = - (unsigned long *)((unsigned long)bd_space + size); - if (priv->hw_version == MVPP21) - size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32); - else - size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64); - } + /* Clear the complete area so that all descriptors are cleared */ + memset(bd_space, 0, size); - for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) { - buffer_loc.rx_buffer[i] = - (unsigned long *)((unsigned long)bd_space + size); - size += RX_BUFFER_SIZE; + buffer_loc_init = 1; } - /* Clear the complete area so that all descriptors are cleared */ - memset(bd_space, 0, size); - /* Save base addresses for later use */ priv->base = (void *)devfdt_get_addr_index(dev, 0); if (IS_ERR(priv->base)) -- cgit