From 70ad375ee444645001d3ca78bb17790b50232999 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 21 Mar 2014 12:28:58 -0600 Subject: ARM: tegra: Tegra20 pinmux cleanup This renames all the Tegra20 pinmux pins and functions so they have a prefix which matches the type name. The entries in tegra20_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. Signed-off-by: Stephen Warren Acked-by: Simon Glass Signed-off-by: Tom Warren --- drivers/spi/tegra20_sflash.c | 6 +++--- drivers/video/tegra.c | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c index 603c024bcc..b5d561be34 100644 --- a/drivers/spi/tegra20_sflash.c +++ b/drivers/spi/tegra20_sflash.c @@ -208,9 +208,9 @@ int tegra20_spi_claim_bus(struct spi_slave *slave) * SPI pins on Tegra20 are muxed - change pinmux later due to UART * issue. */ - pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH); - pinmux_tristate_disable(PINGRP_LSPI); - pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH); + pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH); + pinmux_tristate_disable(PMUX_PINGRP_LSPI); + pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH); return 0; } diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c index c047e6e785..57cb0074e2 100644 --- a/drivers/video/tegra.c +++ b/drivers/video/tegra.c @@ -229,8 +229,8 @@ static int handle_stage(const void *blob) break; case STAGE_PWM: /* Enable PWM at 15/16 high, 32768 Hz with divider 1 */ - pinmux_set_func(PINGRP_GPU, PMUX_FUNC_PWM); - pinmux_tristate_disable(PINGRP_GPU); + pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM); + pinmux_tristate_disable(PMUX_PINGRP_GPU); pwm_enable(config.pwm_channel, 32768, 0xdf, 1); break; -- cgit From b03f4b3742a728c13a89f3fbf8a9a2ec43061025 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Sun, 2 Mar 2014 19:46:48 +0100 Subject: usb: tegra: fix USB2 powerdown for Tegra30 and later Clear the forced powerdown bit in the UTMIP_PLL_CFG2_0 register which brings USB2 in UTMI mode to work. This was clearly missing since the forced powerdown bit is set in reset by default for all USB ports. Acked-by: Stephen Warren Signed-off-by: Stefan Agner Tested-by: Stephen Warren Signed-off-by: Tom Warren --- drivers/usb/host/ehci-tegra.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index 0b42aa5b38..20e9297d9c 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -461,6 +461,9 @@ static int init_utmi_usb_controller(struct fdt_usb *config) if (config->periph_id == PERIPH_ID_USBD) clrbits_le32(&clkrst->crc_utmip_pll_cfg2, UTMIP_FORCE_PD_SAMP_A_POWERDOWN); + if (config->periph_id == PERIPH_ID_USB2) + clrbits_le32(&clkrst->crc_utmip_pll_cfg2, + UTMIP_FORCE_PD_SAMP_B_POWERDOWN); if (config->periph_id == PERIPH_ID_USB3) clrbits_le32(&clkrst->crc_utmip_pll_cfg2, UTMIP_FORCE_PD_SAMP_C_POWERDOWN); -- cgit From b1d615f3f10294c016cc424ef05e938f49af8117 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Sun, 2 Mar 2014 19:46:49 +0100 Subject: usb: tegra: fix PHY configuration On Tegra30 and later, the PTS (parallel transceiver select) and STS (serial transceiver select) are part of the HOSTPC1_DEVLC_0 register rather than PORTSC1_0 register. Since the reset configuration usually matches the intended configuration, this error did not show up on Tegra30 devices. Also use the slightly different bit fields of first USB, (USBD) on Tegra20 and move those definitions to the Tegra20 specific header file. Reviewed-by: Stephen Warren Signed-off-by: Stefan Agner Signed-off-by: Tom Warren --- drivers/usb/host/ehci-tegra.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index 20e9297d9c..c6b64b299e 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -486,9 +486,21 @@ static int init_utmi_usb_controller(struct fdt_usb *config) clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); /* Select UTMI parallel interface */ - clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, +#if defined(CONFIG_TEGRA20) + if (config->periph_id == PERIPH_ID_USBD) { + clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK, + PTS_UTMI << PTS1_SHIFT); + clrbits_le32(&usbctlr->port_sc1, STS1); + } else { + clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, + PTS_UTMI << PTS_SHIFT); + clrbits_le32(&usbctlr->port_sc1, STS); + } +#else + clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, PTS_UTMI << PTS_SHIFT); - clrbits_le32(&usbctlr->port_sc1, STS); + clrbits_le32(&usbctlr->hostpc1_devlc, STS); +#endif /* Deassert power down state */ clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | @@ -546,7 +558,13 @@ static int init_ulpi_usb_controller(struct fdt_usb *config) ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP); /* Select ULPI parallel interface */ - clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT); +#if defined(CONFIG_TEGRA20) + clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, + PTS_ULPI << PTS_SHIFT); +#else + clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, + PTS_ULPI << PTS_SHIFT); +#endif /* enable ULPI transceiver */ setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB); -- cgit From 8f9fd6caafb838bdb0d6a1c0a7e96997aec27b90 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Sun, 2 Mar 2014 19:46:50 +0100 Subject: usb: tegra: combine header file Combine the Tegra USB header file into one header file for all SoCs. Use ifdef to account for the difference, especially Tegra20 is quite different from newer SoCs. This avoids duplication, mainly for Tegra30 and newer devices. Reviewed-by: Stephen Warren Signed-off-by: Stefan Agner Signed-off-by: Tom Warren --- drivers/usb/host/ehci-tegra.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index c6b64b299e..38db18e2c9 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include -- cgit From 6dd3b566893a99629771e076dca1ce8db7b77dc1 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 28 Mar 2014 12:03:36 -0400 Subject: mtd: Add a CONFIG_SPL_MTD_SUPPORT for a more full NAND subsystem in SPL This mainly converts the am335x_spl_bch driver to the "normal" format which means a slight change to nand_info within the driver. Acked-by: Scott Wood Signed-off-by: Tom Rini --- drivers/mtd/nand/am335x_spl_bch.c | 54 +++++++++++++++++++-------------------- 1 file changed, 27 insertions(+), 27 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/am335x_spl_bch.c b/drivers/mtd/nand/am335x_spl_bch.c index c84851bab5..bd89b067d5 100644 --- a/drivers/mtd/nand/am335x_spl_bch.c +++ b/drivers/mtd/nand/am335x_spl_bch.c @@ -16,7 +16,7 @@ #include static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS; -static nand_info_t mtd; +nand_info_t nand_info[1]; static struct nand_chip nand_chip; #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ @@ -30,12 +30,12 @@ static struct nand_chip nand_chip; static int nand_command(int block, int page, uint32_t offs, u8 cmd) { - struct nand_chip *this = mtd.priv; + struct nand_chip *this = nand_info[0].priv; int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; void (*hwctrl)(struct mtd_info *mtd, int cmd, unsigned int ctrl) = this->cmd_ctrl; - while (!this->dev_ready(&mtd)) + while (!this->dev_ready(&nand_info[0])) ; /* Emulate NAND_CMD_READOOB */ @@ -45,11 +45,11 @@ static int nand_command(int block, int page, uint32_t offs, } /* Begin command latch cycle */ - hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); + hwctrl(&nand_info[0], cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); if (cmd == NAND_CMD_RESET) { - hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); - while (!this->dev_ready(&mtd)) + hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + while (!this->dev_ready(&nand_info[0])) ; return 0; } @@ -60,35 +60,35 @@ static int nand_command(int block, int page, uint32_t offs, /* Set ALE and clear CLE to start address cycle */ /* Column address */ - hwctrl(&mtd, offs & 0xff, + hwctrl(&nand_info[0], offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */ - hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */ + hwctrl(&nand_info[0], (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */ /* Row address */ - hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */ - hwctrl(&mtd, ((page_addr >> 8) & 0xff), + hwctrl(&nand_info[0], (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */ + hwctrl(&nand_info[0], ((page_addr >> 8) & 0xff), NAND_CTRL_ALE); /* A[27:20] */ #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE /* One more address cycle for devices > 128MiB */ - hwctrl(&mtd, (page_addr >> 16) & 0x0f, + hwctrl(&nand_info[0], (page_addr >> 16) & 0x0f, NAND_CTRL_ALE); /* A[31:28] */ #endif - hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); if (cmd == NAND_CMD_READ0) { /* Latch in address */ - hwctrl(&mtd, NAND_CMD_READSTART, + hwctrl(&nand_info[0], NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE); - hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); /* * Wait a while for the data to be ready */ - while (!this->dev_ready(&mtd)) + while (!this->dev_ready(&nand_info[0])) ; } else if (cmd == NAND_CMD_RNDOUT) { - hwctrl(&mtd, NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE | + hwctrl(&nand_info[0], NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE); - hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); } return 0; @@ -96,7 +96,7 @@ static int nand_command(int block, int page, uint32_t offs, static int nand_is_bad_block(int block) { - struct nand_chip *this = mtd.priv; + struct nand_chip *this = nand_info[0].priv; nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB); @@ -117,7 +117,7 @@ static int nand_is_bad_block(int block) static int nand_read_page(int block, int page, void *dst) { - struct nand_chip *this = mtd.priv; + struct nand_chip *this = nand_info[0].priv; u_char ecc_calc[ECCTOTAL]; u_char ecc_code[ECCTOTAL]; u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; @@ -133,15 +133,15 @@ static int nand_read_page(int block, int page, void *dst) nand_command(block, page, 0, NAND_CMD_READ0); for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { - this->ecc.hwctl(&mtd, NAND_ECC_READ); + this->ecc.hwctl(&nand_info[0], NAND_ECC_READ); nand_command(block, page, data_pos, NAND_CMD_RNDOUT); - this->read_buf(&mtd, p, eccsize); + this->read_buf(&nand_info[0], p, eccsize); nand_command(block, page, oob_pos, NAND_CMD_RNDOUT); - this->read_buf(&mtd, oob, eccbytes); - this->ecc.calculate(&mtd, p, &ecc_calc[i]); + this->read_buf(&nand_info[0], oob, eccbytes); + this->ecc.calculate(&nand_info[0], p, &ecc_calc[i]); data_pos += eccsize; oob_pos += eccbytes; @@ -160,7 +160,7 @@ static int nand_read_page(int block, int page, void *dst) * from correct_data(). We just hope that all possible errors * are corrected by this routine. */ - this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]); + this->ecc.correct(&nand_info[0], p, &ecc_code[i], &ecc_calc[i]); } return 0; @@ -206,13 +206,13 @@ void nand_init(void) /* * Init board specific nand support */ - mtd.priv = &nand_chip; + nand_info[0].priv = &nand_chip; nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE; board_nand_init(&nand_chip); if (nand_chip.select_chip) - nand_chip.select_chip(&mtd, 0); + nand_chip.select_chip(&nand_info[0], 0); /* NAND chip may require reset after power-on */ nand_command(0, 0, 0, NAND_CMD_RESET); @@ -222,5 +222,5 @@ void nand_init(void) void nand_deselect(void) { if (nand_chip.select_chip) - nand_chip.select_chip(&mtd, -1); + nand_chip.select_chip(&nand_info[0], -1); } -- cgit From db605806496cea6d6a82032b2f9ae1628ae7778d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 28 Mar 2014 12:03:37 -0400 Subject: mtd: Build nand_util.o for CONFIG_ENV_IS_IN_NAND in SPL Acked-by: Scott Wood Signed-off-by: Tom Rini --- drivers/mtd/nand/Makefile | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 02b149cacc..4eb354da93 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -18,6 +18,9 @@ obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o obj-$(CONFIG_SPL_NAND_INIT) += nand.o +ifeq ($(CONFIG_SPL_ENV_SUPPORT),y) +obj-$(CONFIG_ENV_IS_IN_NAND) += nand_util.o +endif else # not spl -- cgit From b545a98f5dc5635d55b5b3878cbb44142e863017 Mon Sep 17 00:00:00 2001 From: "Poddar, Sourav" Date: Thu, 3 Apr 2014 07:52:54 -0400 Subject: spi: ti_qspi: Add delay for successful bulk erase. Bulk erase is not happening properly on dra7 due to erase timing constraints, add a delay so that erase timing constraints are properly met. Signed-off-by: Sourav Poddar Tested-by: Yebio Mesfin --- drivers/spi/ti_qspi.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index dfa5d0ca21..c5d2245e44 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -314,6 +314,9 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, qslave->cmd |= QSPI_RD_SNGL; debug("rx cmd %08x dc %08x\n", qslave->cmd, qslave->dc); + #ifdef CONFIG_DRA7XX + udelay(500); + #endif writel(qslave->cmd, &qslave->base->cmd); status = readl(&qslave->base->status); timeout = QSPI_TIMEOUT; -- cgit From fa1a73fa87bfd204f56224d3ef7ab1ab486ca95f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 3 Apr 2014 07:52:55 -0400 Subject: SPL:SPI: Add Falcon Mode support Signed-off-by: Tom Rini --- drivers/mtd/spi/spi_spl_load.c | 46 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 40 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/spi/spi_spl_load.c b/drivers/mtd/spi/spi_spl_load.c index 29355307f3..1954b7e886 100644 --- a/drivers/mtd/spi/spi_spl_load.c +++ b/drivers/mtd/spi/spi_spl_load.c @@ -13,6 +13,35 @@ #include #include +#ifdef CONFIG_SPL_OS_BOOT +/* + * Load the kernel, check for a valid header we can parse, and if found load + * the kernel and then device tree. + */ +static int spi_load_image_os(struct spi_flash *flash, + struct image_header *header) +{ + /* Read for a header, parse or error out. */ + spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, 0x40, + (void *)header); + + if (image_get_magic(header) != IH_MAGIC) + return -1; + + spl_parse_image_header(header); + + spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, + spl_image.size, (void *)spl_image.load_addr); + + /* Read device tree. */ + spi_flash_read(flash, CONFIG_SYS_SPI_ARGS_OFFS, + CONFIG_SYS_SPI_ARGS_SIZE, + (void *)CONFIG_SYS_SPL_ARGS_ADDR); + + return 0; +} +#endif + /* * The main entry for SPI booting. It's necessary that SDRAM is already * configured and available since this code loads the main U-Boot image @@ -37,10 +66,15 @@ void spl_spi_load_image(void) /* use CONFIG_SYS_TEXT_BASE as temporary storage area */ header = (struct image_header *)(CONFIG_SYS_TEXT_BASE); - /* Load u-boot, mkimage header is 64 bytes. */ - spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40, - (void *)header); - spl_parse_image_header(header); - spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS, - spl_image.size, (void *)spl_image.load_addr); +#ifdef CONFIG_SPL_OS_BOOT + if (spl_start_uboot() || spi_load_image_os(flash, header)) +#endif + { + /* Load u-boot, mkimage header is 64 bytes. */ + spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40, + (void *)header); + spl_parse_image_header(header); + spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS, + spl_image.size, (void *)spl_image.load_addr); + } } -- cgit From 999d7d326de45c014077cda9904e9ac25166c3f2 Mon Sep 17 00:00:00 2001 From: "Karicheri, Muralidharan" Date: Fri, 4 Apr 2014 13:16:50 -0400 Subject: NAND: DaVinci: allow forced disable of subpage writes This patch introduces a configurable mechanism to disable subpage writes in the DaVinci NAND driver. Signed-off-by: Vitaly Andrianov Signed-off-by: Murali Karicheri Acked-by: Tom Rini --- drivers/mtd/nand/davinci_nand.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index 5b17d7be8b..75b03a74b6 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -609,6 +609,9 @@ void davinci_nand_init(struct nand_chip *nand) #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT nand->bbt_options |= NAND_BBT_USE_FLASH; #endif +#ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE + nand->options |= NAND_NO_SUBPAGE_WRITE; +#endif #ifdef CONFIG_SYS_NAND_HW_ECC nand->ecc.mode = NAND_ECC_HW; nand->ecc.size = 512; -- cgit From 356d15ebb2b0bb2adde2ca4fe4cccb87f75531a0 Mon Sep 17 00:00:00 2001 From: "Karicheri, Muralidharan" Date: Fri, 4 Apr 2014 13:16:51 -0400 Subject: i2c, davinci: move i2c_defs.h to the drivers/i2c directory This patch moves the davinci i2c_defs.h file to drivers.i2c directory. It will allow to reuse the davinci_i2c driver for TI Keystone2 SOCs. Not used "git mv" command to move the file because small part of it with definitions specific for Davinci SOCs has to remain in the arch/arm/include/asm/arch-davinci. Signed-off-by: Vitaly Andrianov Signed-off-by: Murali Karicheri Acked-by: Tom Rini --- drivers/i2c/davinci_i2c.c | 1 + drivers/i2c/davinci_i2c.h | 75 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 76 insertions(+) create mode 100644 drivers/i2c/davinci_i2c.h (limited to 'drivers') diff --git a/drivers/i2c/davinci_i2c.c b/drivers/i2c/davinci_i2c.c index e56fe75b15..6e5260c482 100644 --- a/drivers/i2c/davinci_i2c.c +++ b/drivers/i2c/davinci_i2c.c @@ -12,6 +12,7 @@ #include #include #include +#include "davinci_i2c.h" #define CHECK_NACK() \ do {\ diff --git a/drivers/i2c/davinci_i2c.h b/drivers/i2c/davinci_i2c.h new file mode 100644 index 0000000000..79ff7a3d67 --- /dev/null +++ b/drivers/i2c/davinci_i2c.h @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2004-2014 + * Texas Instruments, + * + * Some changes copyright (C) 2007 Sergey Kubushyn + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _DAVINCI_I2C_H_ +#define _DAVINCI_I2C_H_ + +#define I2C_WRITE 0 +#define I2C_READ 1 + +#define I2C_OA (I2C_BASE + 0x00) +#define I2C_IE (I2C_BASE + 0x04) +#define I2C_STAT (I2C_BASE + 0x08) +#define I2C_SCLL (I2C_BASE + 0x0c) +#define I2C_SCLH (I2C_BASE + 0x10) +#define I2C_CNT (I2C_BASE + 0x14) +#define I2C_DRR (I2C_BASE + 0x18) +#define I2C_SA (I2C_BASE + 0x1c) +#define I2C_DXR (I2C_BASE + 0x20) +#define I2C_CON (I2C_BASE + 0x24) +#define I2C_IV (I2C_BASE + 0x28) +#define I2C_PSC (I2C_BASE + 0x30) + +/* I2C masks */ + +/* I2C Interrupt Enable Register (I2C_IE): */ +#define I2C_IE_SCD_IE (1 << 5) /* Stop condition detect interrupt enable */ +#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ +#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ +#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ +#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ + +/* I2C Status Register (I2C_STAT): */ + +#define I2C_STAT_BB (1 << 12) /* Bus busy */ +#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ +#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ +#define I2C_STAT_AAS (1 << 9) /* Address as slave */ +#define I2C_STAT_SCD (1 << 5) /* Stop condition detect */ +#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ +#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ +#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ +#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ + +/* I2C Interrupt Code Register (I2C_INTCODE): */ + +#define I2C_INTCODE_MASK 7 +#define I2C_INTCODE_NONE 0 +#define I2C_INTCODE_AL 1 /* Arbitration lost */ +#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ +#define I2C_INTCODE_ARDY 3 /* Register access ready */ +#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ +#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ +#define I2C_INTCODE_SCD 6 /* Stop condition detect */ + +/* I2C Configuration Register (I2C_CON): */ + +#define I2C_CON_EN (1 << 5) /* I2C module enable */ +#define I2C_CON_STB (1 << 4) /* Start byte mode (master mode only) */ +#define I2C_CON_MST (1 << 10) /* Master/slave mode */ +#define I2C_CON_TRX (1 << 9) /* Tx/Rx mode (master mode only) */ +#define I2C_CON_XA (1 << 8) /* Expand address */ +#define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */ +#define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */ +#define I2C_CON_FREE (1 << 14) /* Free run on emulation */ + +#define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */ + +#endif -- cgit From e8459dcc33c3f3fc5a98b7b69bb3ddd7ad77f632 Mon Sep 17 00:00:00 2001 From: Vitaly Andrianov Date: Fri, 4 Apr 2014 13:16:52 -0400 Subject: i2c, davinci: convert driver to new mutlibus/mutliadapter framework - add davinci driver to new multibus/multiadpater support - adapted all config files, which uses this driver Signed-off-by: Vitaly Andrianov Signed-off-by: Murali Karicheri Acked-by: Heiko Schocher --- drivers/i2c/Makefile | 2 +- drivers/i2c/davinci_i2c.c | 401 +++++++++++++++++++++++++++------------------- drivers/i2c/davinci_i2c.h | 27 ++-- 3 files changed, 250 insertions(+), 180 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 36d5e5f1a2..e33586d8a6 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -6,7 +6,6 @@ # obj-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o -obj-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o obj-$(CONFIG_DW_I2C) += designware_i2c.o obj-$(CONFIG_I2C_MVTWSI) += mvtwsi.o obj-$(CONFIG_I2C_MV) += mv_i2c.o @@ -16,6 +15,7 @@ obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o obj-$(CONFIG_U8500_I2C) += u8500_i2c.o obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o obj-$(CONFIG_SYS_I2C) += i2c_core.o +obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o diff --git a/drivers/i2c/davinci_i2c.c b/drivers/i2c/davinci_i2c.c index 6e5260c482..9ca99c4abd 100644 --- a/drivers/i2c/davinci_i2c.c +++ b/drivers/i2c/davinci_i2c.c @@ -1,8 +1,9 @@ /* * TI DaVinci (TMS320DM644x) I2C driver. * - * Copyright (C) 2007 Sergey Kubushyn - * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * (C) Copyright 2007 Sergey Kubushyn * -------------------------------------------------------- * * SPDX-License-Identifier: GPL-2.0+ @@ -12,306 +13,372 @@ #include #include #include +#include #include "davinci_i2c.h" #define CHECK_NACK() \ do {\ if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\ - REG(I2C_CON) = 0;\ - return(1);\ - }\ + REG(&(i2c_base->i2c_con)) = 0;\ + return 1;\ + } \ } while (0) +static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap); -static int wait_for_bus(void) +static int wait_for_bus(struct i2c_adapter *adap) { + struct i2c_regs *i2c_base = davinci_get_base(adap); int stat, timeout; - REG(I2C_STAT) = 0xffff; + REG(&(i2c_base->i2c_stat)) = 0xffff; for (timeout = 0; timeout < 10; timeout++) { - if (!((stat = REG(I2C_STAT)) & I2C_STAT_BB)) { - REG(I2C_STAT) = 0xffff; - return(0); + stat = REG(&(i2c_base->i2c_stat)); + if (!((stat) & I2C_STAT_BB)) { + REG(&(i2c_base->i2c_stat)) = 0xffff; + return 0; } - REG(I2C_STAT) = stat; + REG(&(i2c_base->i2c_stat)) = stat; udelay(50000); } - REG(I2C_STAT) = 0xffff; - return(1); + REG(&(i2c_base->i2c_stat)) = 0xffff; + return 1; } -static int poll_i2c_irq(int mask) +static int poll_i2c_irq(struct i2c_adapter *adap, int mask) { + struct i2c_regs *i2c_base = davinci_get_base(adap); int stat, timeout; for (timeout = 0; timeout < 10; timeout++) { udelay(1000); - stat = REG(I2C_STAT); - if (stat & mask) { - return(stat); - } + stat = REG(&(i2c_base->i2c_stat)); + if (stat & mask) + return stat; } - REG(I2C_STAT) = 0xffff; - return(stat | I2C_TIMEOUT); + REG(&(i2c_base->i2c_stat)) = 0xffff; + return stat | I2C_TIMEOUT; } - -void flush_rx(void) +static void flush_rx(struct i2c_adapter *adap) { + struct i2c_regs *i2c_base = davinci_get_base(adap); + while (1) { - if (!(REG(I2C_STAT) & I2C_STAT_RRDY)) + if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_RRDY)) break; - REG(I2C_DRR); - REG(I2C_STAT) = I2C_STAT_RRDY; + REG(&(i2c_base->i2c_drr)); + REG(&(i2c_base->i2c_stat)) = I2C_STAT_RRDY; udelay(1000); } } +static uint davinci_i2c_setspeed(struct i2c_adapter *adap, uint speed) +{ + struct i2c_regs *i2c_base = davinci_get_base(adap); + uint32_t div, psc; + + psc = 2; + /* SCLL + SCLH */ + div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; + REG(&(i2c_base->i2c_psc)) = psc; /* 27MHz / (2 + 1) = 9MHz */ + REG(&(i2c_base->i2c_scll)) = (div * 50) / 100; /* 50% Duty */ + REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll)); + + adap->speed = speed; + return 0; +} -void i2c_init(int speed, int slaveadd) +static void davinci_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) { - u_int32_t div, psc; + struct i2c_regs *i2c_base = davinci_get_base(adap); - if (REG(I2C_CON) & I2C_CON_EN) { - REG(I2C_CON) = 0; - udelay (50000); + if (REG(&(i2c_base->i2c_con)) & I2C_CON_EN) { + REG(&(i2c_base->i2c_con)) = 0; + udelay(50000); } - psc = 2; - div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; /* SCLL + SCLH */ - REG(I2C_PSC) = psc; /* 27MHz / (2 + 1) = 9MHz */ - REG(I2C_SCLL) = (div * 50) / 100; /* 50% Duty */ - REG(I2C_SCLH) = div - REG(I2C_SCLL); + davinci_i2c_setspeed(adap, speed); - REG(I2C_OA) = slaveadd; - REG(I2C_CNT) = 0; + REG(&(i2c_base->i2c_oa)) = slaveadd; + REG(&(i2c_base->i2c_cnt)) = 0; /* Interrupts must be enabled or I2C module won't work */ - REG(I2C_IE) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE | + REG(&(i2c_base->i2c_ie)) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE; /* Now enable I2C controller (get it out of reset) */ - REG(I2C_CON) = I2C_CON_EN; + REG(&(i2c_base->i2c_con)) = I2C_CON_EN; udelay(1000); } -int i2c_set_bus_speed(unsigned int speed) -{ - i2c_init(speed, CONFIG_SYS_I2C_SLAVE); - return 0; -} - -int i2c_probe(u_int8_t chip) +static int davinci_i2c_probe(struct i2c_adapter *adap, uint8_t chip) { + struct i2c_regs *i2c_base = davinci_get_base(adap); int rc = 1; - if (chip == REG(I2C_OA)) { - return(rc); - } + if (chip == REG(&(i2c_base->i2c_oa))) + return rc; - REG(I2C_CON) = 0; - if (wait_for_bus()) {return(1);} + REG(&(i2c_base->i2c_con)) = 0; + if (wait_for_bus(adap)) + return 1; /* try to read one byte from current (or only) address */ - REG(I2C_CNT) = 1; - REG(I2C_SA) = chip; - REG(I2C_CON) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP); - udelay (50000); + REG(&(i2c_base->i2c_cnt)) = 1; + REG(&(i2c_base->i2c_sa)) = chip; + REG(&(i2c_base->i2c_con)) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | + I2C_CON_STP); + udelay(50000); - if (!(REG(I2C_STAT) & I2C_STAT_NACK)) { + if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_NACK)) { rc = 0; - flush_rx(); - REG(I2C_STAT) = 0xffff; + flush_rx(adap); + REG(&(i2c_base->i2c_stat)) = 0xffff; } else { - REG(I2C_STAT) = 0xffff; - REG(I2C_CON) |= I2C_CON_STP; + REG(&(i2c_base->i2c_stat)) = 0xffff; + REG(&(i2c_base->i2c_con)) |= I2C_CON_STP; udelay(20000); - if (wait_for_bus()) {return(1);} + if (wait_for_bus(adap)) + return 1; } - flush_rx(); - REG(I2C_STAT) = 0xffff; - REG(I2C_CNT) = 0; - return(rc); + flush_rx(adap); + REG(&(i2c_base->i2c_stat)) = 0xffff; + REG(&(i2c_base->i2c_cnt)) = 0; + return rc; } - -int i2c_read(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) +static int davinci_i2c_read(struct i2c_adapter *adap, uint8_t chip, + uint32_t addr, int alen, uint8_t *buf, int len) { - u_int32_t tmp; + struct i2c_regs *i2c_base = davinci_get_base(adap); + uint32_t tmp; int i; if ((alen < 0) || (alen > 2)) { - printf("%s(): bogus address length %x\n", __FUNCTION__, alen); - return(1); + printf("%s(): bogus address length %x\n", __func__, alen); + return 1; } - if (wait_for_bus()) {return(1);} + if (wait_for_bus(adap)) + return 1; if (alen != 0) { /* Start address phase */ tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX; - REG(I2C_CNT) = alen; - REG(I2C_SA) = chip; - REG(I2C_CON) = tmp; + REG(&(i2c_base->i2c_cnt)) = alen; + REG(&(i2c_base->i2c_sa)) = chip; + REG(&(i2c_base->i2c_con)) = tmp; - tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK); CHECK_NACK(); switch (alen) { - case 2: - /* Send address MSByte */ - if (tmp & I2C_STAT_XRDY) { - REG(I2C_DXR) = (addr >> 8) & 0xff; - } else { - REG(I2C_CON) = 0; - return(1); - } - - tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); - - CHECK_NACK(); - /* No break, fall through */ - case 1: - /* Send address LSByte */ - if (tmp & I2C_STAT_XRDY) { - REG(I2C_DXR) = addr & 0xff; - } else { - REG(I2C_CON) = 0; - return(1); - } - - tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK | I2C_STAT_ARDY); - - CHECK_NACK(); - - if (!(tmp & I2C_STAT_ARDY)) { - REG(I2C_CON) = 0; - return(1); - } + case 2: + /* Send address MSByte */ + if (tmp & I2C_STAT_XRDY) { + REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff; + } else { + REG(&(i2c_base->i2c_con)) = 0; + return 1; + } + + tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK); + + CHECK_NACK(); + /* No break, fall through */ + case 1: + /* Send address LSByte */ + if (tmp & I2C_STAT_XRDY) { + REG(&(i2c_base->i2c_dxr)) = addr & 0xff; + } else { + REG(&(i2c_base->i2c_con)) = 0; + return 1; + } + + tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | + I2C_STAT_NACK | I2C_STAT_ARDY); + + CHECK_NACK(); + + if (!(tmp & I2C_STAT_ARDY)) { + REG(&(i2c_base->i2c_con)) = 0; + return 1; + } } } /* Address phase is over, now read 'len' bytes and stop */ tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP; - REG(I2C_CNT) = len & 0xffff; - REG(I2C_SA) = chip; - REG(I2C_CON) = tmp; + REG(&(i2c_base->i2c_cnt)) = len & 0xffff; + REG(&(i2c_base->i2c_sa)) = chip; + REG(&(i2c_base->i2c_con)) = tmp; for (i = 0; i < len; i++) { - tmp = poll_i2c_irq(I2C_STAT_RRDY | I2C_STAT_NACK | I2C_STAT_ROVR); + tmp = poll_i2c_irq(adap, I2C_STAT_RRDY | I2C_STAT_NACK | + I2C_STAT_ROVR); CHECK_NACK(); if (tmp & I2C_STAT_RRDY) { - buf[i] = REG(I2C_DRR); + buf[i] = REG(&(i2c_base->i2c_drr)); } else { - REG(I2C_CON) = 0; - return(1); + REG(&(i2c_base->i2c_con)) = 0; + return 1; } } - tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK); + tmp = poll_i2c_irq(adap, I2C_STAT_SCD | I2C_STAT_NACK); CHECK_NACK(); if (!(tmp & I2C_STAT_SCD)) { - REG(I2C_CON) = 0; - return(1); + REG(&(i2c_base->i2c_con)) = 0; + return 1; } - flush_rx(); - REG(I2C_STAT) = 0xffff; - REG(I2C_CNT) = 0; - REG(I2C_CON) = 0; + flush_rx(adap); + REG(&(i2c_base->i2c_stat)) = 0xffff; + REG(&(i2c_base->i2c_cnt)) = 0; + REG(&(i2c_base->i2c_con)) = 0; - return(0); + return 0; } - -int i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) +static int davinci_i2c_write(struct i2c_adapter *adap, uint8_t chip, + uint32_t addr, int alen, uint8_t *buf, int len) { - u_int32_t tmp; + struct i2c_regs *i2c_base = davinci_get_base(adap); + uint32_t tmp; int i; if ((alen < 0) || (alen > 2)) { - printf("%s(): bogus address length %x\n", __FUNCTION__, alen); - return(1); + printf("%s(): bogus address length %x\n", __func__, alen); + return 1; } if (len < 0) { - printf("%s(): bogus length %x\n", __FUNCTION__, len); - return(1); + printf("%s(): bogus length %x\n", __func__, len); + return 1; } - if (wait_for_bus()) {return(1);} + if (wait_for_bus(adap)) + return 1; /* Start address phase */ - tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP; - REG(I2C_CNT) = (alen == 0) ? len & 0xffff : (len & 0xffff) + alen; - REG(I2C_SA) = chip; - REG(I2C_CON) = tmp; + tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | + I2C_CON_TRX | I2C_CON_STP; + REG(&(i2c_base->i2c_cnt)) = (alen == 0) ? + len & 0xffff : (len & 0xffff) + alen; + REG(&(i2c_base->i2c_sa)) = chip; + REG(&(i2c_base->i2c_con)) = tmp; switch (alen) { - case 2: - /* Send address MSByte */ - tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + case 2: + /* Send address MSByte */ + tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK); - CHECK_NACK(); + CHECK_NACK(); - if (tmp & I2C_STAT_XRDY) { - REG(I2C_DXR) = (addr >> 8) & 0xff; - } else { - REG(I2C_CON) = 0; - return(1); - } - /* No break, fall through */ - case 1: - /* Send address LSByte */ - tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + if (tmp & I2C_STAT_XRDY) { + REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff; + } else { + REG(&(i2c_base->i2c_con)) = 0; + return 1; + } + /* No break, fall through */ + case 1: + /* Send address LSByte */ + tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK); - CHECK_NACK(); + CHECK_NACK(); - if (tmp & I2C_STAT_XRDY) { - REG(I2C_DXR) = addr & 0xff; - } else { - REG(I2C_CON) = 0; - return(1); - } + if (tmp & I2C_STAT_XRDY) { + REG(&(i2c_base->i2c_dxr)) = addr & 0xff; + } else { + REG(&(i2c_base->i2c_con)) = 0; + return 1; + } } for (i = 0; i < len; i++) { - tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK); CHECK_NACK(); - if (tmp & I2C_STAT_XRDY) { - REG(I2C_DXR) = buf[i]; - } else { - return(1); - } + if (tmp & I2C_STAT_XRDY) + REG(&(i2c_base->i2c_dxr)) = buf[i]; + else + return 1; } - tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK); + tmp = poll_i2c_irq(adap, I2C_STAT_SCD | I2C_STAT_NACK); CHECK_NACK(); if (!(tmp & I2C_STAT_SCD)) { - REG(I2C_CON) = 0; - return(1); + REG(&(i2c_base->i2c_con)) = 0; + return 1; } - flush_rx(); - REG(I2C_STAT) = 0xffff; - REG(I2C_CNT) = 0; - REG(I2C_CON) = 0; + flush_rx(adap); + REG(&(i2c_base->i2c_stat)) = 0xffff; + REG(&(i2c_base->i2c_cnt)) = 0; + REG(&(i2c_base->i2c_con)) = 0; + + return 0; +} + +static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap) +{ + switch (adap->hwadapnr) { +#if I2C_BUS_MAX >= 3 + case 2: + return (struct i2c_regs *)I2C2_BASE; +#endif +#if I2C_BUS_MAX >= 2 + case 1: + return (struct i2c_regs *)I2C1_BASE; +#endif + case 0: + return (struct i2c_regs *)I2C_BASE; + + default: + printf("wrong hwadapnr: %d\n", adap->hwadapnr); + } - return(0); + return NULL; } + +U_BOOT_I2C_ADAP_COMPLETE(davinci_0, davinci_i2c_init, davinci_i2c_probe, + davinci_i2c_read, davinci_i2c_write, + davinci_i2c_setspeed, + CONFIG_SYS_DAVINCI_I2C_SPEED, + CONFIG_SYS_DAVINCI_I2C_SLAVE, + 0) + +#if I2C_BUS_MAX >= 2 +U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe, + davinci_i2c_read, davinci_i2c_write, + davinci_i2c_setspeed, + CONFIG_SYS_DAVINCI_I2C_SPEED1, + CONFIG_SYS_DAVINCI_I2C_SLAVE1, + 1) +#endif + +#if I2C_BUS_MAX >= 3 +U_BOOT_I2C_ADAP_COMPLETE(davinci_2, davinci_i2c_init, davinci_i2c_probe, + davinci_i2c_read, davinci_i2c_write, + davinci_i2c_setspeed, + CONFIG_SYS_DAVINCI_I2C_SPEED2, + CONFIG_SYS_DAVINCI_I2C_SLAVE2, + 2) +#endif diff --git a/drivers/i2c/davinci_i2c.h b/drivers/i2c/davinci_i2c.h index 79ff7a3d67..20d43424b9 100644 --- a/drivers/i2c/davinci_i2c.h +++ b/drivers/i2c/davinci_i2c.h @@ -12,18 +12,21 @@ #define I2C_WRITE 0 #define I2C_READ 1 -#define I2C_OA (I2C_BASE + 0x00) -#define I2C_IE (I2C_BASE + 0x04) -#define I2C_STAT (I2C_BASE + 0x08) -#define I2C_SCLL (I2C_BASE + 0x0c) -#define I2C_SCLH (I2C_BASE + 0x10) -#define I2C_CNT (I2C_BASE + 0x14) -#define I2C_DRR (I2C_BASE + 0x18) -#define I2C_SA (I2C_BASE + 0x1c) -#define I2C_DXR (I2C_BASE + 0x20) -#define I2C_CON (I2C_BASE + 0x24) -#define I2C_IV (I2C_BASE + 0x28) -#define I2C_PSC (I2C_BASE + 0x30) +struct i2c_regs { + u32 i2c_oa; + u32 i2c_ie; + u32 i2c_stat; + u32 i2c_scll; + u32 i2c_sclh; + u32 i2c_cnt; + u32 i2c_drr; + u32 i2c_sa; + u32 i2c_dxr; + u32 i2c_con; + u32 i2c_iv; + u32 res_2c; + u32 i2c_psc; +}; /* I2C masks */ -- cgit From ef509b9063fb702ce69d1a64ff293698a04075d6 Mon Sep 17 00:00:00 2001 From: Vitaly Andrianov Date: Fri, 4 Apr 2014 13:16:53 -0400 Subject: k2hk: add support for k2hk SOC and EVM k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please refer the ti/k2hk_evm/README for details on the board, build and other information. This patch add support for keystone architecture and k2hk evm. Signed-off-by: Vitaly Andrianov Signed-off-by: Murali Karicheri Signed-off-by: WingMan Kwok Signed-off-by: Sandeep Nair --- drivers/serial/ns16550.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers') diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index fbc37b27e8..8a13454943 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -30,6 +30,11 @@ #define serial_in(y) readb(y) #endif +#if defined(CONFIG_K2HK_EVM) +#define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0 +#define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0)) +#endif + #ifndef CONFIG_SYS_NS16550_IER #define CONFIG_SYS_NS16550_IER 0x00 #endif /* CONFIG_SYS_NS16550_IER */ @@ -77,6 +82,9 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) /* /16 is proper to hit 115200 with 48MHz */ serial_out(0, &com_port->mdr1); #endif /* CONFIG_OMAP */ +#if defined(CONFIG_K2HK_EVM) + serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC); +#endif } #ifndef CONFIG_NS16550_MIN_FUNCTIONS -- cgit From 2bcdf84d5820320724932199fddeed32d2d49e4a Mon Sep 17 00:00:00 2001 From: "Karicheri, Muralidharan" Date: Fri, 4 Apr 2014 13:16:54 -0400 Subject: spi: davinci: add support for multiple bus and chip select Currently davinci spi driver supports only bus 0 cs 0. This patch allows driver to support bus 1 and bus 2 with configurable number of chip selects. Also defaults are selected in a way to avoid regression on other platforms that uses davinci spi driver and has only one spi bus. Signed-off-by: Rex Chang Signed-off-by: Murali Karicheri Reviewed-by: Jagannadha Sutradharudu Teki --- drivers/spi/davinci_spi.c | 49 ++++++++++++++++++++++++++++++++++++++++++++--- drivers/spi/davinci_spi.h | 33 +++++++++++++++++++++++++++++++ 2 files changed, 79 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index e3fb3212aa..28fb3a2e9f 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -32,7 +32,27 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!ds) return NULL; - ds->regs = (struct davinci_spi_regs *)CONFIG_SYS_SPI_BASE; + ds->slave.bus = bus; + ds->slave.cs = cs; + + switch (bus) { + case SPI0_BUS: + ds->regs = (struct davinci_spi_regs *)SPI0_BASE; + break; +#ifdef CONFIG_SYS_SPI1 + case SPI1_BUS: + ds->regs = (struct davinci_spi_regs *)SPI0_BASE; + break; +#endif +#ifdef CONFIG_SYS_SPI2 + case SPI2_BUS: + ds->regs = (struct davinci_spi_regs *)SPI2_BASE; + break; +#endif + default: /* Invalid bus number */ + return NULL; + } + ds->freq = max_hz; return &ds->slave; @@ -59,7 +79,7 @@ int spi_claim_bus(struct spi_slave *slave) writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1); /* CS, CLK, SIMO and SOMI are functional pins */ - writel((SPIPC0_EN0FUN_MASK | SPIPC0_CLKFUN_MASK | + writel(((1 << slave->cs) | SPIPC0_CLKFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0); /* setup format */ @@ -264,7 +284,30 @@ out: int spi_cs_is_valid(unsigned int bus, unsigned int cs) { - return bus == 0 && cs == 0; + int ret = 0; + + switch (bus) { + case SPI0_BUS: + if (cs < SPI0_NUM_CS) + ret = 1; + break; +#ifdef CONFIG_SYS_SPI1 + case SPI1_BUS: + if (cs < SPI1_NUM_CS) + ret = 1; + break; +#endif +#ifdef CONFIG_SYS_SPI2 + case SPI2_BUS: + if (cs < SPI2_NUM_CS) + ret = 1; + break; +#endif + default: + /* Invalid bus number. Do nothing */ + break; + } + return ret; } void spi_cs_activate(struct spi_slave *slave) diff --git a/drivers/spi/davinci_spi.h b/drivers/spi/davinci_spi.h index 33f69b5ca9..d4612d3527 100644 --- a/drivers/spi/davinci_spi.h +++ b/drivers/spi/davinci_spi.h @@ -74,6 +74,39 @@ struct davinci_spi_regs { /* SPIDEF */ #define SPIDEF_CSDEF0_MASK BIT(0) +#define SPI0_BUS 0 +#define SPI0_BASE CONFIG_SYS_SPI_BASE +/* + * Define default SPI0_NUM_CS as 1 for existing platforms that uses this + * driver. Platform can configure number of CS using CONFIG_SYS_SPI0_NUM_CS + * if more than one CS is supported and by defining CONFIG_SYS_SPI0. + */ +#ifndef CONFIG_SYS_SPI0 +#define SPI0_NUM_CS 1 +#else +#define SPI0_NUM_CS CONFIG_SYS_SPI0_NUM_CS +#endif + +/* + * define CONFIG_SYS_SPI1 when platform has spi-1 device (bus #1) and + * CONFIG_SYS_SPI1_NUM_CS defines number of CS on this bus + */ +#ifdef CONFIG_SYS_SPI1 +#define SPI1_BUS 1 +#define SPI1_NUM_CS CONFIG_SYS_SPI1_NUM_CS +#define SPI1_BASE CONFIG_SYS_SPI1_BASE +#endif + +/* + * define CONFIG_SYS_SPI2 when platform has spi-2 device (bus #2) and + * CONFIG_SYS_SPI2_NUM_CS defines number of CS on this bus + */ +#ifdef CONFIG_SYS_SPI2 +#define SPI2_BUS 2 +#define SPI2_NUM_CS CONFIG_SYS_SPI2_NUM_CS +#define SPI2_BASE CONFIG_SYS_SPI2_BASE +#endif + struct davinci_spi_slave { struct spi_slave slave; struct davinci_spi_regs *regs; -- cgit From fc9a8e8d40e770b00383c2433c843fe68e38dad3 Mon Sep 17 00:00:00 2001 From: "Karicheri, Muralidharan" Date: Tue, 1 Apr 2014 15:01:13 -0400 Subject: keystone2: net: add keystone ethernet driver Ethernet driver configures the CPSW, SGMI and Phy and uses the the Navigator APIs. The driver supports 4 Ethernet ports and can work with only one port at a time. Port configurations are defined in board.c. Signed-off-by: Vitaly Andrianov Signed-off-by: Murali Karicheri Signed-off-by: WingMan Kwok --- drivers/net/Makefile | 1 + drivers/net/keystone_net.c | 716 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 717 insertions(+) create mode 100644 drivers/net/keystone_net.c (limited to 'drivers') diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 7f9ce90a6d..6005f7e413 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_FTMAC110) += ftmac110.o obj-$(CONFIG_FTMAC100) += ftmac100.o obj-$(CONFIG_GRETH) += greth.o obj-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o +obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o obj-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o obj-$(CONFIG_LAN91C96) += lan91c96.o diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c new file mode 100644 index 0000000000..f95c928076 --- /dev/null +++ b/drivers/net/keystone_net.c @@ -0,0 +1,716 @@ +/* + * Ethernet driver for TI K2HK EVM. + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include + +#include +#include +#include +#include +#include +#include + +unsigned int emac_dbg; + +unsigned int emac_open; +static unsigned int sys_has_mdio = 1; + +#ifdef KEYSTONE2_EMAC_GIG_ENABLE +#define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x) +#else +#define emac_gigabit_enable(x) /* no gigabit to enable */ +#endif + +#define RX_BUFF_NUMS 24 +#define RX_BUFF_LEN 1520 +#define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN + +static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16); + +struct rx_buff_desc net_rx_buffs = { + .buff_ptr = rx_buffs, + .num_buffs = RX_BUFF_NUMS, + .buff_len = RX_BUFF_LEN, + .rx_flow = 22, +}; + +static void keystone2_eth_mdio_enable(void); + +static int gen_get_link_speed(int phy_addr); + +/* EMAC Addresses */ +static volatile struct emac_regs *adap_emac = + (struct emac_regs *)EMAC_EMACSL_BASE_ADDR; +static volatile struct mdio_regs *adap_mdio = + (struct mdio_regs *)EMAC_MDIO_BASE_ADDR; + +int keystone2_eth_read_mac_addr(struct eth_device *dev) +{ + struct eth_priv_t *eth_priv; + u32 maca = 0; + u32 macb = 0; + + eth_priv = (struct eth_priv_t *)dev->priv; + + /* Read the e-fuse mac address */ + if (eth_priv->slave_port == 1) { + maca = __raw_readl(MAC_ID_BASE_ADDR); + macb = __raw_readl(MAC_ID_BASE_ADDR + 4); + } + + dev->enetaddr[0] = (macb >> 8) & 0xff; + dev->enetaddr[1] = (macb >> 0) & 0xff; + dev->enetaddr[2] = (maca >> 24) & 0xff; + dev->enetaddr[3] = (maca >> 16) & 0xff; + dev->enetaddr[4] = (maca >> 8) & 0xff; + dev->enetaddr[5] = (maca >> 0) & 0xff; + + return 0; +} + +static void keystone2_eth_mdio_enable(void) +{ + u_int32_t clkdiv; + + clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; + + writel((clkdiv & 0xffff) | + MDIO_CONTROL_ENABLE | + MDIO_CONTROL_FAULT | + MDIO_CONTROL_FAULT_ENABLE, + &adap_mdio->control); + + while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE) + ; +} + +/* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */ +int keystone2_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) +{ + int tmp; + + while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) + ; + + writel(MDIO_USERACCESS0_GO | + MDIO_USERACCESS0_WRITE_READ | + ((reg_num & 0x1f) << 21) | + ((phy_addr & 0x1f) << 16), + &adap_mdio->useraccess0); + + /* Wait for command to complete */ + while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO) + ; + + if (tmp & MDIO_USERACCESS0_ACK) { + *data = tmp & 0xffff; + return 0; + } + + *data = -1; + return -1; +} + +/* + * Write to a PHY register via MDIO inteface. + * Blocks until operation is complete. + */ +int keystone2_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data) +{ + while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) + ; + + writel(MDIO_USERACCESS0_GO | + MDIO_USERACCESS0_WRITE_WRITE | + ((reg_num & 0x1f) << 21) | + ((phy_addr & 0x1f) << 16) | + (data & 0xffff), + &adap_mdio->useraccess0); + + /* Wait for command to complete */ + while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) + ; + + return 0; +} + +/* PHY functions for a generic PHY */ +static int gen_get_link_speed(int phy_addr) +{ + u_int16_t tmp; + + if ((!keystone2_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp)) && + (tmp & 0x04)) { + return 0; + } + + return -1; +} + +static void __attribute__((unused)) + keystone2_eth_gigabit_enable(struct eth_device *dev) +{ + u_int16_t data; + struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; + + if (sys_has_mdio) { + if (keystone2_eth_phy_read(eth_priv->phy_addr, 0, &data) || + !(data & (1 << 6))) /* speed selection MSB */ + return; + } + + /* + * Check if link detected is giga-bit + * If Gigabit mode detected, enable gigbit in MAC + */ + writel(readl(&(adap_emac[eth_priv->slave_port - 1].maccontrol)) | + EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE, + &(adap_emac[eth_priv->slave_port - 1].maccontrol)) + ; +} + +int keystone_sgmii_link_status(int port) +{ + u32 status = 0; + + status = __raw_readl(SGMII_STATUS_REG(port)); + + return status & SGMII_REG_STATUS_LINK; +} + + +int keystone_get_link_status(struct eth_device *dev) +{ + struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; + int sgmii_link; + int link_state = 0; +#if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1 + int j; + + for (j = 0; (j < CONFIG_GET_LINK_STATUS_ATTEMPTS) && (link_state == 0); + j++) { +#endif + sgmii_link = + keystone_sgmii_link_status(eth_priv->slave_port - 1); + + if (sgmii_link) { + link_state = 1; + + if (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) + if (gen_get_link_speed(eth_priv->phy_addr)) + link_state = 0; + } +#if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1 + } +#endif + return link_state; +} + +int keystone_sgmii_config(int port, int interface) +{ + unsigned int i, status, mask; + unsigned int mr_adv_ability, control; + + switch (interface) { + case SGMII_LINK_MAC_MAC_AUTONEG: + mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE | + SGMII_REG_MR_ADV_LINK | + SGMII_REG_MR_ADV_FULL_DUPLEX | + SGMII_REG_MR_ADV_GIG_MODE); + control = (SGMII_REG_CONTROL_MASTER | + SGMII_REG_CONTROL_AUTONEG); + + break; + case SGMII_LINK_MAC_PHY: + case SGMII_LINK_MAC_PHY_FORCED: + mr_adv_ability = SGMII_REG_MR_ADV_ENABLE; + control = SGMII_REG_CONTROL_AUTONEG; + + break; + case SGMII_LINK_MAC_MAC_FORCED: + mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE | + SGMII_REG_MR_ADV_LINK | + SGMII_REG_MR_ADV_FULL_DUPLEX | + SGMII_REG_MR_ADV_GIG_MODE); + control = SGMII_REG_CONTROL_MASTER; + + break; + case SGMII_LINK_MAC_FIBER: + mr_adv_ability = 0x20; + control = SGMII_REG_CONTROL_AUTONEG; + + break; + default: + mr_adv_ability = SGMII_REG_MR_ADV_ENABLE; + control = SGMII_REG_CONTROL_AUTONEG; + } + + __raw_writel(0, SGMII_CTL_REG(port)); + + /* + * Wait for the SerDes pll to lock, + * but don't trap if lock is never read + */ + for (i = 0; i < 1000; i++) { + udelay(2000); + status = __raw_readl(SGMII_STATUS_REG(port)); + if ((status & SGMII_REG_STATUS_LOCK) != 0) + break; + } + + __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port)); + __raw_writel(control, SGMII_CTL_REG(port)); + + + mask = SGMII_REG_STATUS_LINK; + + if (control & SGMII_REG_CONTROL_AUTONEG) + mask |= SGMII_REG_STATUS_AUTONEG; + + for (i = 0; i < 1000; i++) { + status = __raw_readl(SGMII_STATUS_REG(port)); + if ((status & mask) == mask) + break; + } + + return 0; +} + +int mac_sl_reset(u32 port) +{ + u32 i, v; + + if (port >= DEVICE_N_GMACSL_PORTS) + return GMACSL_RET_INVALID_PORT; + + /* Set the soft reset bit */ + DEVICE_REG32_W(DEVICE_EMACSL_BASE(port) + + CPGMACSL_REG_RESET, CPGMAC_REG_RESET_VAL_RESET); + + /* Wait for the bit to clear */ + for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) { + v = DEVICE_REG32_R(DEVICE_EMACSL_BASE(port) + + CPGMACSL_REG_RESET); + if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) != + CPGMAC_REG_RESET_VAL_RESET) + return GMACSL_RET_OK; + } + + /* Timeout on the reset */ + return GMACSL_RET_WARN_RESET_INCOMPLETE; +} + +int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg) +{ + u32 v, i; + int ret = GMACSL_RET_OK; + + if (port >= DEVICE_N_GMACSL_PORTS) + return GMACSL_RET_INVALID_PORT; + + if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) { + cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN; + ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG; + } + + /* Must wait if the device is undergoing reset */ + for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) { + v = DEVICE_REG32_R(DEVICE_EMACSL_BASE(port) + + CPGMACSL_REG_RESET); + if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) != + CPGMAC_REG_RESET_VAL_RESET) + break; + } + + if (i == DEVICE_EMACSL_RESET_POLL_COUNT) + return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE; + + DEVICE_REG32_W(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN, + cfg->max_rx_len); + + DEVICE_REG32_W(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL, + cfg->ctl); + + return ret; +} + +int ethss_config(u32 ctl, u32 max_pkt_size) +{ + u32 i; + + /* Max length register */ + DEVICE_REG32_W(DEVICE_CPSW_BASE + CPSW_REG_MAXLEN, max_pkt_size); + + /* Control register */ + DEVICE_REG32_W(DEVICE_CPSW_BASE + CPSW_REG_CTL, ctl); + + /* All statistics enabled by default */ + DEVICE_REG32_W(DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN, + CPSW_REG_VAL_STAT_ENABLE_ALL); + + /* Reset and enable the ALE */ + DEVICE_REG32_W(DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL, + CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE | + CPSW_REG_VAL_ALE_CTL_BYPASS); + + /* All ports put into forward mode */ + for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++) + DEVICE_REG32_W(DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i), + CPSW_REG_VAL_PORTCTL_FORWARD_MODE); + + return 0; +} + +int ethss_start(void) +{ + int i; + struct mac_sl_cfg cfg; + + cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER; + cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL; + + for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) { + mac_sl_reset(i); + mac_sl_config(i, &cfg); + } + + return 0; +} + +int ethss_stop(void) +{ + int i; + + for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) + mac_sl_reset(i); + + return 0; +} + +int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num) +{ + if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE) + num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE; + + return netcp_send(buffer, num_bytes, (slave_port_num) << 16); +} + +/* Eth device open */ +static int keystone2_eth_open(struct eth_device *dev, bd_t *bis) +{ + u_int32_t clkdiv; + int link; + struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; + + debug("+ emac_open\n"); + + net_rx_buffs.rx_flow = eth_priv->rx_flow; + + sys_has_mdio = + (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0; + + psc_enable_module(KS2_LPSC_PA); + psc_enable_module(KS2_LPSC_CPGMAC); + + sgmii_serdes_setup_156p25mhz(); + + if (sys_has_mdio) + keystone2_eth_mdio_enable(); + + keystone_sgmii_config(eth_priv->slave_port - 1, + eth_priv->sgmii_link_type); + + udelay(10000); + + /* On chip switch configuration */ + ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE); + + /* TODO: add error handling code */ + if (qm_init()) { + printf("ERROR: qm_init()\n"); + return -1; + } + if (netcp_init(&net_rx_buffs)) { + qm_close(); + printf("ERROR: netcp_init()\n"); + return -1; + } + + /* + * Streaming switch configuration. If not present this + * statement is defined to void in target.h. + * If present this is usually defined to a series of register writes + */ + hw_config_streaming_switch(); + + if (sys_has_mdio) { + /* Init MDIO & get link state */ + clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; + writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | + MDIO_CONTROL_FAULT, &adap_mdio->control) + ; + + /* We need to wait for MDIO to start */ + udelay(1000); + + link = keystone_get_link_status(dev); + if (link == 0) { + netcp_close(); + qm_close(); + return -1; + } + } + + emac_gigabit_enable(dev); + + ethss_start(); + + debug("- emac_open\n"); + + emac_open = 1; + + return 0; +} + +/* Eth device close */ +void keystone2_eth_close(struct eth_device *dev) +{ + debug("+ emac_close\n"); + + if (!emac_open) + return; + + ethss_stop(); + + netcp_close(); + qm_close(); + + emac_open = 0; + + debug("- emac_close\n"); +} + +static int tx_send_loop; + +/* + * This function sends a single packet on the network and returns + * positive number (number of bytes transmitted) or negative for error + */ +static int keystone2_eth_send_packet(struct eth_device *dev, + void *packet, int length) +{ + int ret_status = -1; + struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; + + tx_send_loop = 0; + + if (keystone_get_link_status(dev) == 0) + return -1; + + emac_gigabit_enable(dev); + + if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0) + return ret_status; + + if (keystone_get_link_status(dev) == 0) + return -1; + + emac_gigabit_enable(dev); + + return length; +} + +/* + * This function handles receipt of a packet from the network + */ +static int keystone2_eth_rcv_packet(struct eth_device *dev) +{ + void *hd; + int pkt_size; + u32 *pkt; + + hd = netcp_recv(&pkt, &pkt_size); + if (hd == NULL) + return 0; + + NetReceive((uchar *)pkt, pkt_size); + + netcp_release_rxhd(hd); + + return pkt_size; +} + +/* + * This function initializes the EMAC hardware. + */ +int keystone2_emac_initialize(struct eth_priv_t *eth_priv) +{ + struct eth_device *dev; + + dev = malloc(sizeof(struct eth_device)); + if (dev == NULL) + return -1; + + memset(dev, 0, sizeof(struct eth_device)); + + strcpy(dev->name, eth_priv->int_name); + dev->priv = eth_priv; + + keystone2_eth_read_mac_addr(dev); + + dev->iobase = 0; + dev->init = keystone2_eth_open; + dev->halt = keystone2_eth_close; + dev->send = keystone2_eth_send_packet; + dev->recv = keystone2_eth_rcv_packet; + + eth_register(dev); + + return 0; +} + +void sgmii_serdes_setup_156p25mhz(void) +{ + unsigned int cnt; + + /* + * configure Serializer/Deserializer (SerDes) hardware. SerDes IP + * hardware vendor published only register addresses and their values + * to be used for configuring SerDes. So had to use hardcoded values + * below. + */ + clrsetbits_le32(0x0232a000, 0xffff0000, 0x00800000); + clrsetbits_le32(0x0232a014, 0x0000ffff, 0x00008282); + clrsetbits_le32(0x0232a060, 0x00ffffff, 0x00142438); + clrsetbits_le32(0x0232a064, 0x00ffff00, 0x00c3c700); + clrsetbits_le32(0x0232a078, 0x0000ff00, 0x0000c000); + + clrsetbits_le32(0x0232a204, 0xff0000ff, 0x38000080); + clrsetbits_le32(0x0232a208, 0x000000ff, 0x00000000); + clrsetbits_le32(0x0232a20c, 0xff000000, 0x02000000); + clrsetbits_le32(0x0232a210, 0xff000000, 0x1b000000); + clrsetbits_le32(0x0232a214, 0x0000ffff, 0x00006fb8); + clrsetbits_le32(0x0232a218, 0xffff00ff, 0x758000e4); + clrsetbits_le32(0x0232a2ac, 0x0000ff00, 0x00004400); + clrsetbits_le32(0x0232a22c, 0x00ffff00, 0x00200800); + clrsetbits_le32(0x0232a280, 0x00ff00ff, 0x00820082); + clrsetbits_le32(0x0232a284, 0xffffffff, 0x1d0f0385); + + clrsetbits_le32(0x0232a404, 0xff0000ff, 0x38000080); + clrsetbits_le32(0x0232a408, 0x000000ff, 0x00000000); + clrsetbits_le32(0x0232a40c, 0xff000000, 0x02000000); + clrsetbits_le32(0x0232a410, 0xff000000, 0x1b000000); + clrsetbits_le32(0x0232a414, 0x0000ffff, 0x00006fb8); + clrsetbits_le32(0x0232a418, 0xffff00ff, 0x758000e4); + clrsetbits_le32(0x0232a4ac, 0x0000ff00, 0x00004400); + clrsetbits_le32(0x0232a42c, 0x00ffff00, 0x00200800); + clrsetbits_le32(0x0232a480, 0x00ff00ff, 0x00820082); + clrsetbits_le32(0x0232a484, 0xffffffff, 0x1d0f0385); + + clrsetbits_le32(0x0232a604, 0xff0000ff, 0x38000080); + clrsetbits_le32(0x0232a608, 0x000000ff, 0x00000000); + clrsetbits_le32(0x0232a60c, 0xff000000, 0x02000000); + clrsetbits_le32(0x0232a610, 0xff000000, 0x1b000000); + clrsetbits_le32(0x0232a614, 0x0000ffff, 0x00006fb8); + clrsetbits_le32(0x0232a618, 0xffff00ff, 0x758000e4); + clrsetbits_le32(0x0232a6ac, 0x0000ff00, 0x00004400); + clrsetbits_le32(0x0232a62c, 0x00ffff00, 0x00200800); + clrsetbits_le32(0x0232a680, 0x00ff00ff, 0x00820082); + clrsetbits_le32(0x0232a684, 0xffffffff, 0x1d0f0385); + + clrsetbits_le32(0x0232a804, 0xff0000ff, 0x38000080); + clrsetbits_le32(0x0232a808, 0x000000ff, 0x00000000); + clrsetbits_le32(0x0232a80c, 0xff000000, 0x02000000); + clrsetbits_le32(0x0232a810, 0xff000000, 0x1b000000); + clrsetbits_le32(0x0232a814, 0x0000ffff, 0x00006fb8); + clrsetbits_le32(0x0232a818, 0xffff00ff, 0x758000e4); + clrsetbits_le32(0x0232a8ac, 0x0000ff00, 0x00004400); + clrsetbits_le32(0x0232a82c, 0x00ffff00, 0x00200800); + clrsetbits_le32(0x0232a880, 0x00ff00ff, 0x00820082); + clrsetbits_le32(0x0232a884, 0xffffffff, 0x1d0f0385); + + clrsetbits_le32(0x0232aa00, 0x0000ff00, 0x00000800); + clrsetbits_le32(0x0232aa08, 0xffff0000, 0x38a20000); + clrsetbits_le32(0x0232aa30, 0x00ffff00, 0x008a8a00); + clrsetbits_le32(0x0232aa84, 0x0000ff00, 0x00000600); + clrsetbits_le32(0x0232aa94, 0xff000000, 0x10000000); + clrsetbits_le32(0x0232aaa0, 0xff000000, 0x81000000); + clrsetbits_le32(0x0232aabc, 0xff000000, 0xff000000); + clrsetbits_le32(0x0232aac0, 0x000000ff, 0x0000008b); + clrsetbits_le32(0x0232ab08, 0xffff0000, 0x583f0000); + clrsetbits_le32(0x0232ab0c, 0x000000ff, 0x0000004e); + clrsetbits_le32(0x0232a000, 0x000000ff, 0x00000003); + clrsetbits_le32(0x0232aa00, 0x000000ff, 0x0000005f); + + clrsetbits_le32(0x0232aa48, 0x00ffff00, 0x00fd8c00); + clrsetbits_le32(0x0232aa54, 0x00ffffff, 0x002fec72); + clrsetbits_le32(0x0232aa58, 0xffffff00, 0x00f92100); + clrsetbits_le32(0x0232aa5c, 0xffffffff, 0x00040060); + clrsetbits_le32(0x0232aa60, 0xffffffff, 0x00008000); + clrsetbits_le32(0x0232aa64, 0xffffffff, 0x0c581220); + clrsetbits_le32(0x0232aa68, 0xffffffff, 0xe13b0602); + clrsetbits_le32(0x0232aa6c, 0xffffffff, 0xb8074cc1); + clrsetbits_le32(0x0232aa70, 0xffffffff, 0x3f02e989); + clrsetbits_le32(0x0232aa74, 0x000000ff, 0x00000001); + clrsetbits_le32(0x0232ab20, 0x00ff0000, 0x00370000); + clrsetbits_le32(0x0232ab1c, 0xff000000, 0x37000000); + clrsetbits_le32(0x0232ab20, 0x000000ff, 0x0000005d); + + /*Bring SerDes out of Reset if SerDes is Shutdown & is in Reset Mode*/ + clrbits_le32(0x0232a010, 1 << 28); + + /* Enable TX and RX via the LANExCTL_STS 0x0000 + x*4 */ + clrbits_le32(0x0232a228, 1 << 29); + writel(0xF800F8C0, 0x0232bfe0); + clrbits_le32(0x0232a428, 1 << 29); + writel(0xF800F8C0, 0x0232bfe4); + clrbits_le32(0x0232a628, 1 << 29); + writel(0xF800F8C0, 0x0232bfe8); + clrbits_le32(0x0232a828, 1 << 29); + writel(0xF800F8C0, 0x0232bfec); + + /*Enable pll via the pll_ctrl 0x0014*/ + writel(0xe0000000, 0x0232bff4) + ; + + /*Waiting for SGMII Serdes PLL lock.*/ + for (cnt = 10000; cnt > 0 && ((readl(0x02090114) & 0x10) == 0); cnt--) + ; + + for (cnt = 10000; cnt > 0 && ((readl(0x02090214) & 0x10) == 0); cnt--) + ; + + for (cnt = 10000; cnt > 0 && ((readl(0x02090414) & 0x10) == 0); cnt--) + ; + + for (cnt = 10000; cnt > 0 && ((readl(0x02090514) & 0x10) == 0); cnt--) + ; + + udelay(45000); +} + +void sgmii_serdes_shutdown(void) +{ + /* + * shutdown SerDes hardware. SerDes hardware vendor published only + * register addresses and their values. So had to use hardcoded + * values below. + */ + clrbits_le32(0x0232bfe0, 3 << 29 | 3 << 13); + setbits_le32(0x02320228, 1 << 29); + clrbits_le32(0x0232bfe4, 3 << 29 | 3 << 13); + setbits_le32(0x02320428, 1 << 29); + clrbits_le32(0x0232bfe8, 3 << 29 | 3 << 13); + setbits_le32(0x02320628, 1 << 29); + clrbits_le32(0x0232bfec, 3 << 29 | 3 << 13); + setbits_le32(0x02320828, 1 << 29); + + clrbits_le32(0x02320034, 3 << 29); + setbits_le32(0x02320010, 1 << 28); +} -- cgit From a69214dc719862b8433608d7e914e51464dfd14c Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Tue, 29 Apr 2014 14:37:56 -0700 Subject: video: mxc_ipuv3_fb: stash frame buffer pointer in global data. This patch updates the i.MX video driver to store the frame-buffer address in the fb_base field of the global data structure *gd. By doing this, you can find the frame buffer address using the 'bdinfo' command: U-Boot > bdinfo arch_number = 0x00000EB9 ... FB base = 0x4F35F1C0 This is very useful when debugging display connections. Signed-off-by: Eric Nelson Acked-by: Otavio Salvador Acked-by: Marek Vasut --- drivers/video/mxc_ipuv3_fb.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers') diff --git a/drivers/video/mxc_ipuv3_fb.c b/drivers/video/mxc_ipuv3_fb.c index 3e21fb2306..f75d77064e 100644 --- a/drivers/video/mxc_ipuv3_fb.c +++ b/drivers/video/mxc_ipuv3_fb.c @@ -13,6 +13,7 @@ #include #include +#include #include #include #include @@ -24,6 +25,8 @@ #include "mxcfb.h" #include "ipu_regs.h" +DECLARE_GLOBAL_DATA_PTR; + static int mxcfb_map_video_memory(struct fb_info *fbi); static int mxcfb_unmap_video_memory(struct fb_info *fbi); @@ -415,6 +418,8 @@ static int mxcfb_map_video_memory(struct fb_info *fbi) fbi->screen_size = fbi->fix.smem_len; + gd->fb_base = fbi->fix.smem_start; + /* Clear the screen */ memset((char *)fbi->screen_base, 0, fbi->fix.smem_len); -- cgit From 1161f98db687a1cb263cbacdc7eb548a0354218d Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Mon, 10 Mar 2014 16:40:41 +0800 Subject: at91: video: atmel_hlcdfb.c: fix bad timing configuration The right correspondance between LCD margins and LCD timings is: * upper margin -> vertical back porch * lower margin -> vertical front porch * left margin -> horizontal back porch * right margin -> horizontal front porch Signed-off-by: Josh Wu --- drivers/video/atmel_hlcdfb.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c index 853303b5e5..bb4d7d8c14 100644 --- a/drivers/video/atmel_hlcdfb.c +++ b/drivers/video/atmel_hlcdfb.c @@ -128,12 +128,12 @@ void lcd_ctrl_init(void *lcdbase) value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1); lcdc_writel(®s->lcdc_lcdcfg1, value); - value = LCDC_LCDCFG2_VBPW(panel_info.vl_lower_margin); - value |= LCDC_LCDCFG2_VFPW(panel_info.vl_upper_margin - 1); + value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin); + value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1); lcdc_writel(®s->lcdc_lcdcfg2, value); - value = LCDC_LCDCFG3_HBPW(panel_info.vl_right_margin - 1); - value |= LCDC_LCDCFG3_HFPW(panel_info.vl_left_margin - 1); + value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1); + value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1); lcdc_writel(®s->lcdc_lcdcfg3, value); /* Display size */ -- cgit From 5146fc2b37a3098f0973b2f2339e069adfc7d272 Mon Sep 17 00:00:00 2001 From: "Jesper B. Christensen" Date: Fri, 25 Apr 2014 15:46:17 +0200 Subject: i2c: zynq: Fixed compilation errors when using DEBUG Signed-off-by: Jesper B. Christensen Signed-off-by: Michal Simek --- drivers/i2c/zynq_i2c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/zynq_i2c.c b/drivers/i2c/zynq_i2c.c index f1f65131a2..b3264af452 100644 --- a/drivers/i2c/zynq_i2c.c +++ b/drivers/i2c/zynq_i2c.c @@ -142,7 +142,7 @@ static u32 zynq_i2c_wait(struct zynq_i2c_registers *zynq_i2c, u32 mask) break; } #ifdef DEBUG - zynq_i2c_debug_status(zynq_i2c)); + zynq_i2c_debug_status(zynq_i2c); #endif /* Clear interrupt status flags */ writel(int_status & mask, &zynq_i2c->interrupt_status); @@ -235,7 +235,7 @@ static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); #ifdef DEBUG - zynq_i2c_debug_status(); + zynq_i2c_debug_status(zynq_i2c); #endif return 0; } -- cgit From 8e2615752ee6d5daf8ce2e1e599a0512750f24b9 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 4 Apr 2014 20:09:58 +0900 Subject: bd_info: remove bi_barudrate member from struct bd_info gd->bd->bi_baudrate is a copy of gd->baudrate. Since baudrate is a common feature for all architectures, keep gd->baudrate only. It is true that bi_baudrate was passed to the kernel in that structure but it was a long time ago. Signed-off-by: Masahiro Yamada Cc: Tom Rini Cc: Simon Glass Cc: Wolfgang Denk Cc: Heiko Schocher Acked-by: Michal Simek (For microblaze) --- drivers/serial/serial.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index c4fb59cfb3..fd61a5e545 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -74,9 +74,6 @@ static int on_baudrate(const char *name, const char *value, enum env_op op, } gd->baudrate = baudrate; -#if defined(CONFIG_PPC) || defined(CONFIG_MCF52x2) - gd->bd->bi_baudrate = baudrate; -#endif serial_setbrg(); @@ -502,12 +499,11 @@ int uart_post_test(int flags) unsigned char c; int ret, saved_baud, b; struct serial_device *saved_dev, *s; - bd_t *bd = gd->bd; /* Save current serial state */ ret = 0; saved_dev = serial_current; - saved_baud = bd->bi_baudrate; + saved_baud = gd->baudrate; for (s = serial_devices; s; s = s->next) { /* If this driver doesn't support loop back, skip it */ @@ -530,7 +526,7 @@ int uart_post_test(int flags) /* Test every available baud rate */ for (b = 0; b < ARRAY_SIZE(bauds); ++b) { - bd->bi_baudrate = bauds[b]; + gd->baudrate = bauds[b]; serial_setbrg(); /* @@ -572,7 +568,7 @@ int uart_post_test(int flags) done: /* Restore previous serial state */ serial_current = saved_dev; - bd->bi_baudrate = saved_baud; + gd->baudrate = saved_baud; serial_reinit_all(); serial_setbrg(); -- cgit From d57dee5787ad96d2c80bf36f443276592d39ee21 Mon Sep 17 00:00:00 2001 From: "Karicheri, Muralidharan" Date: Wed, 9 Apr 2014 15:38:46 -0400 Subject: serial: nsl16550: add hw flow control support keystone serial hw support hw flow control. This patch enables hw flow control for keystone EVMs as an optional feature based on CONFIG_SERIAL_HW_FLOW_CONTROL. Signed-off-by: Murali Karicheri --- drivers/serial/ns16550.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers') diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 8a13454943..f26979dbe1 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -33,6 +33,12 @@ #if defined(CONFIG_K2HK_EVM) #define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0 #define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0)) +#undef UART_MCRVAL +#ifdef CONFIG_SERIAL_HW_FLOW_CONTROL +#define UART_MCRVAL (UART_MCR_RTS | UART_MCR_AFE) +#else +#define UART_MCRVAL (UART_MCR_RTS) +#endif #endif #ifndef CONFIG_SYS_NS16550_IER -- cgit From 02aa4c538838edc918ff4e7e9e4121259552ef70 Mon Sep 17 00:00:00 2001 From: Xiaobo Xie Date: Fri, 11 Apr 2014 16:03:11 +0800 Subject: AR8035/phy: Enable autonegotiation function for ar8035 Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before, but used "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8035 to enable autonegotiation. Then removed the genphy_config_aneg() function. Signed-off-by: Xie Xiaobo --- drivers/net/phy/atheros.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index abd4e5b463..d509e30d35 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -31,9 +31,7 @@ static int ar8035_config(struct phy_device *phydev) regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100)); - genphy_config_aneg(phydev); - - phy_reset(phydev); + phydev->supported = phydev->drv->features; return 0; } -- cgit From 597fe041a85fe3b1bf6044adf5e132f7a5457000 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 11 Apr 2014 16:14:17 +0800 Subject: net/phy: enable get_phy_id redefinable As some PHYs have non-standard PHY ID registers, PHY Id can't be read correctly by current get_phy_id function, so we enable get_phy_id redefinable to permit specific PHY driver having own specific get_phy_id function. Signed-off-by: Shengzhou Liu --- drivers/net/phy/phy.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index c691fbbbc6..230ed97dd1 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -18,6 +18,7 @@ #include #include #include +#include /* Generic PHY support and helper functions */ @@ -577,7 +578,7 @@ static struct phy_device *phy_device_create(struct mii_dev *bus, int addr, * Description: Reads the ID registers of the PHY at @addr on the * @bus, stores it in @phy_id and returns zero on success. */ -static int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id) +int __weak get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id) { int phy_reg; -- cgit From da384a9d7628c77140023e7c095f79ecfe5a4e2d Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 18 Apr 2014 19:09:48 +0900 Subject: net: rename and refactor eth_rand_ethaddr() function Some functions in include/net.h are ported from include/linux/etherdevice.h of Linux Kernel. For ex. is_zero_ether_addr() is_multicast_ether_addr() is_broadcast_ether_addr() is_valid_ether_addr(); So, we should use the same function name as that of Linux Kernel, eth_rand_addr(), for consistency. Besides, eth_rand_addr() has been implemented as an inline function. So it should not be surrounded by #ifdef CONFIG_RANDOM_MACADDR. Signed-off-by: Masahiro Yamada Acked-by: Joe Hershberger --- drivers/net/dm9000x.c | 2 +- drivers/net/ftmac110.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index b68d808c74..4de9d41642 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -345,7 +345,7 @@ static int dm9000_init(struct eth_device *dev, bd_t *bd) if (!is_valid_ether_addr(dev->enetaddr)) { #ifdef CONFIG_RANDOM_MACADDR printf("Bad MAC address (uninitialized EEPROM?), randomizing\n"); - eth_random_enetaddr(dev->enetaddr); + eth_random_addr(dev->enetaddr); printf("MAC: %pM\n", dev->enetaddr); #else printf("WARNING: Bad MAC address (uninitialized EEPROM?)\n"); diff --git a/drivers/net/ftmac110.c b/drivers/net/ftmac110.c index 8eee272cf1..98c4f09629 100644 --- a/drivers/net/ftmac110.c +++ b/drivers/net/ftmac110.c @@ -425,7 +425,7 @@ int ftmac110_initialize(bd_t *bis) dev->recv = ftmac110_recv; if (!eth_getenv_enetaddr_by_index("eth", card_nr, dev->enetaddr)) - eth_random_enetaddr(dev->enetaddr); + eth_random_addr(dev->enetaddr); /* allocate tx descriptors (it must be 16 bytes aligned) */ chip->txd = dma_alloc_coherent( -- cgit From bafd67d3d0f39a19c1e32146cde8b1f4ccd6d666 Mon Sep 17 00:00:00 2001 From: Manish Badarkhe Date: Thu, 24 Apr 2014 08:55:07 +0530 Subject: tps6586x: staticize funtions Make funtions static which are locally used in file. Signed-off-by: Manish Badarkhe --- drivers/power/tps6586x.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/power/tps6586x.c b/drivers/power/tps6586x.c index 704c2439b1..d29d969533 100644 --- a/drivers/power/tps6586x.c +++ b/drivers/power/tps6586x.c @@ -32,7 +32,7 @@ enum { }; #define MAX_I2C_RETRY 3 -int tps6586x_read(int reg) +static int tps6586x_read(int reg) { int i; uchar data; @@ -61,7 +61,7 @@ exit: return retval; } -int tps6586x_write(int reg, uchar *data, uint len) +static int tps6586x_write(int reg, uchar *data, uint len) { int i; int retval = -1; -- cgit From 15e82e5309ed706fa2878aed3b225aa48ae960c7 Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Mon, 28 Apr 2014 20:14:05 +0100 Subject: net/designware: call phy_connect_dev() to properly setup phylib device This sets up the linkage from the phydev back to the ethernet device. This symptom of not doing this which I noticed was: Waiting for PHY auto negotiation to complete.... rather than: dwmac.1c50000 Waiting for PHY auto negotiation to complete.... Signed-off-by: Ian Campbell Cc: Alexey Brodkin --- drivers/net/designware.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/net/designware.c b/drivers/net/designware.c index c45593bcc0..78751b2600 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -390,6 +390,8 @@ static int dw_phy_init(struct eth_device *dev) if (!phydev) return -1; + phy_connect_dev(phydev, dev); + phydev->supported &= PHY_GBIT_FEATURES; phydev->advertising = phydev->supported; -- cgit From b625b9aef383be4366670e8d22b13d48ef8aa870 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 13 Mar 2014 11:23:43 +0100 Subject: fpga: spartan2: Avoid CamelCase No functional changes. Signed-off-by: Michal Simek --- drivers/fpga/spartan2.c | 40 ++++++++++++++++++++-------------------- drivers/fpga/xilinx.c | 14 +++++++------- 2 files changed, 27 insertions(+), 27 deletions(-) (limited to 'drivers') diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index 6eab1b51e5..bd317095c6 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -31,29 +31,29 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif -static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int Spartan2_sp_info(Xilinx_desc *desc ); */ +static int spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan2_sp_info(Xilinx_desc *desc ); */ -static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int Spartan2_ss_info(Xilinx_desc *desc ); */ +static int spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan2_ss_info(Xilinx_desc *desc ); */ /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int Spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); - ret_val = Spartan2_ss_load (desc, buf, bsize); + ret_val = spartan2_ss_load(desc, buf, bsize); break; case slave_parallel: PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); - ret_val = Spartan2_sp_load (desc, buf, bsize); + ret_val = spartan2_sp_load(desc, buf, bsize); break; default: @@ -64,19 +64,19 @@ int Spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +int spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__); - ret_val = Spartan2_ss_dump (desc, buf, bsize); + ret_val = spartan2_ss_dump(desc, buf, bsize); break; case slave_parallel: PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__); - ret_val = Spartan2_sp_dump (desc, buf, bsize); + ret_val = spartan2_sp_dump(desc, buf, bsize); break; default: @@ -87,7 +87,7 @@ int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Spartan2_info( Xilinx_desc *desc ) +int spartan2_info(Xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -96,10 +96,10 @@ int Spartan2_info( Xilinx_desc *desc ) /* ------------------------------------------------------------------------- */ /* Spartan-II Slave Parallel Generic Implementation */ -static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns; + xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns; PRINTF ("%s: start with interface functions @ 0x%p\n", __FUNCTION__, fn); @@ -248,10 +248,10 @@ static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns; + xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns; if (fn) { unsigned char *data = (unsigned char *) buf; @@ -296,10 +296,10 @@ static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) /* ------------------------------------------------------------------------- */ -static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan2_Slave_Serial_fns *fn = desc->iface_fns; + xilinx_spartan2_slave_serial_fns *fn = desc->iface_fns; int i; unsigned char val; @@ -439,7 +439,7 @@ static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 2e0db535d4..47bbf39514 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -149,11 +149,11 @@ int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize) printf ("%s: Invalid device descriptor\n", __FUNCTION__); } else switch (desc->family) { - case Xilinx_Spartan2: + case xilinx_spartan2: #if defined(CONFIG_FPGA_SPARTAN2) PRINTF ("%s: Launching the Spartan-II Loader...\n", __FUNCTION__); - ret_val = Spartan2_load (desc, buf, bsize); + ret_val = spartan2_load(desc, buf, bsize); #else printf ("%s: No support for Spartan-II devices.\n", __FUNCTION__); @@ -206,11 +206,11 @@ int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize) printf ("%s: Invalid device descriptor\n", __FUNCTION__); } else switch (desc->family) { - case Xilinx_Spartan2: + case xilinx_spartan2: #if defined(CONFIG_FPGA_SPARTAN2) PRINTF ("%s: Launching the Spartan-II Reader...\n", __FUNCTION__); - ret_val = Spartan2_dump (desc, buf, bsize); + ret_val = spartan2_dump(desc, buf, bsize); #else printf ("%s: No support for Spartan-II devices.\n", __FUNCTION__); @@ -262,7 +262,7 @@ int xilinx_info (Xilinx_desc * desc) if (xilinx_validate (desc, (char *)__FUNCTION__)) { printf ("Family: \t"); switch (desc->family) { - case Xilinx_Spartan2: + case xilinx_spartan2: printf ("Spartan-II\n"); break; case Xilinx_Spartan3: @@ -316,9 +316,9 @@ int xilinx_info (Xilinx_desc * desc) if (desc->iface_fns) { printf ("Device Function Table @ 0x%p\n", desc->iface_fns); switch (desc->family) { - case Xilinx_Spartan2: + case xilinx_spartan2: #if defined(CONFIG_FPGA_SPARTAN2) - Spartan2_info (desc); + spartan2_info(desc); #else /* just in case */ printf ("%s: No support for Spartan-II devices.\n", -- cgit From 2a6e3869f25093cd4032a3cd64ee455afbd668bf Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 13 Mar 2014 11:28:42 +0100 Subject: fpga: spartan3: Avoid CamelCase No functional changes. Signed-off-by: Michal Simek --- drivers/fpga/spartan3.c | 40 ++++++++++++++++++++-------------------- drivers/fpga/xilinx.c | 14 +++++++------- 2 files changed, 27 insertions(+), 27 deletions(-) (limited to 'drivers') diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 3edc5c2c66..e40abbfb94 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -35,29 +35,29 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif -static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int Spartan3_sp_info(Xilinx_desc *desc ); */ +static int spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan3_sp_info(Xilinx_desc *desc ); */ -static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int Spartan3_ss_info(Xilinx_desc *desc); */ +static int spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan3_ss_info(Xilinx_desc *desc); */ /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int Spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); - ret_val = Spartan3_ss_load (desc, buf, bsize); + ret_val = spartan3_ss_load(desc, buf, bsize); break; case slave_parallel: PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); - ret_val = Spartan3_sp_load (desc, buf, bsize); + ret_val = spartan3_sp_load(desc, buf, bsize); break; default: @@ -68,19 +68,19 @@ int Spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +int spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__); - ret_val = Spartan3_ss_dump (desc, buf, bsize); + ret_val = spartan3_ss_dump(desc, buf, bsize); break; case slave_parallel: PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__); - ret_val = Spartan3_sp_dump (desc, buf, bsize); + ret_val = spartan3_sp_dump(desc, buf, bsize); break; default: @@ -91,7 +91,7 @@ int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Spartan3_info( Xilinx_desc *desc ) +int spartan3_info(Xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -100,10 +100,10 @@ int Spartan3_info( Xilinx_desc *desc ) /* ------------------------------------------------------------------------- */ /* Spartan-II Slave Parallel Generic Implementation */ -static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns; + xilinx_spartan3_slave_parallel_fns *fn = desc->iface_fns; PRINTF ("%s: start with interface functions @ 0x%p\n", __FUNCTION__, fn); @@ -254,10 +254,10 @@ static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns; + xilinx_spartan3_slave_parallel_fns *fn = desc->iface_fns; if (fn) { unsigned char *data = (unsigned char *) buf; @@ -302,10 +302,10 @@ static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) /* ------------------------------------------------------------------------- */ -static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns; + xilinx_spartan3_slave_serial_fns *fn = desc->iface_fns; int i; unsigned char val; @@ -457,7 +457,7 @@ static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 47bbf39514..7d93d641f6 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -159,11 +159,11 @@ int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize) __FUNCTION__); #endif break; - case Xilinx_Spartan3: + case xilinx_spartan3: #if defined(CONFIG_FPGA_SPARTAN3) PRINTF ("%s: Launching the Spartan-III Loader...\n", __FUNCTION__); - ret_val = Spartan3_load (desc, buf, bsize); + ret_val = spartan3_load(desc, buf, bsize); #else printf ("%s: No support for Spartan-III devices.\n", __FUNCTION__); @@ -216,11 +216,11 @@ int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize) __FUNCTION__); #endif break; - case Xilinx_Spartan3: + case xilinx_spartan3: #if defined(CONFIG_FPGA_SPARTAN3) PRINTF ("%s: Launching the Spartan-III Reader...\n", __FUNCTION__); - ret_val = Spartan3_dump (desc, buf, bsize); + ret_val = spartan3_dump(desc, buf, bsize); #else printf ("%s: No support for Spartan-III devices.\n", __FUNCTION__); @@ -265,7 +265,7 @@ int xilinx_info (Xilinx_desc * desc) case xilinx_spartan2: printf ("Spartan-II\n"); break; - case Xilinx_Spartan3: + case xilinx_spartan3: printf ("Spartan-III\n"); break; case Xilinx_Virtex2: @@ -325,9 +325,9 @@ int xilinx_info (Xilinx_desc * desc) __FUNCTION__); #endif break; - case Xilinx_Spartan3: + case xilinx_spartan3: #if defined(CONFIG_FPGA_SPARTAN3) - Spartan3_info (desc); + spartan3_info(desc); #else /* just in case */ printf ("%s: No support for Spartan-III devices.\n", -- cgit From d9071ce0a8cd684589c9c35e4d7c604a9cbd7d62 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 13 Mar 2014 11:33:36 +0100 Subject: fpga: virtex2: Avoid CamelCase No functional changes. Signed-off-by: Michal Simek --- drivers/fpga/virtex2.c | 34 +++++++++++++++++----------------- drivers/fpga/xilinx.c | 14 +++++++------- 2 files changed, 24 insertions(+), 24 deletions(-) (limited to 'drivers') diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index b5a895d41a..1cd9046a24 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -84,25 +84,25 @@ #define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */ #endif -static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); - ret_val = Virtex2_ss_load (desc, buf, bsize); + ret_val = virtex2_ss_load(desc, buf, bsize); break; case slave_selectmap: PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); - ret_val = Virtex2_ssm_load (desc, buf, bsize); + ret_val = virtex2_ssm_load(desc, buf, bsize); break; default: @@ -112,19 +112,19 @@ int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +int virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__); - ret_val = Virtex2_ss_dump (desc, buf, bsize); + ret_val = virtex2_ss_dump(desc, buf, bsize); break; case slave_parallel: PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__); - ret_val = Virtex2_ssm_dump (desc, buf, bsize); + ret_val = virtex2_ssm_dump(desc, buf, bsize); break; default: @@ -134,7 +134,7 @@ int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Virtex2_info (Xilinx_desc * desc) +int virtex2_info(Xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -153,10 +153,10 @@ int Virtex2_info (Xilinx_desc * desc) * INIT_B and DONE lines. If both are high, configuration has * succeeded. Congratulations! */ -static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; - Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns; + xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns; PRINTF ("%s:%d: Start with interface functions @ 0x%p\n", __FUNCTION__, __LINE__, fn); @@ -352,10 +352,10 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) /* * Read the FPGA configuration data */ -static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; - Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns; + xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns; if (fn) { unsigned char *data = (unsigned char *) buf; @@ -404,13 +404,13 @@ static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) { printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__); return FPGA_FAIL; } -static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__); return FPGA_FAIL; diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 7d93d641f6..6953535f08 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -169,11 +169,11 @@ int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize) __FUNCTION__); #endif break; - case Xilinx_Virtex2: + case xilinx_virtex2: #if defined(CONFIG_FPGA_VIRTEX2) PRINTF ("%s: Launching the Virtex-II Loader...\n", __FUNCTION__); - ret_val = Virtex2_load (desc, buf, bsize); + ret_val = virtex2_load(desc, buf, bsize); #else printf ("%s: No support for Virtex-II devices.\n", __FUNCTION__); @@ -226,11 +226,11 @@ int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize) __FUNCTION__); #endif break; - case Xilinx_Virtex2: + case xilinx_virtex2: #if defined( CONFIG_FPGA_VIRTEX2) PRINTF ("%s: Launching the Virtex-II Reader...\n", __FUNCTION__); - ret_val = Virtex2_dump (desc, buf, bsize); + ret_val = virtex2_dump(desc, buf, bsize); #else printf ("%s: No support for Virtex-II devices.\n", __FUNCTION__); @@ -268,7 +268,7 @@ int xilinx_info (Xilinx_desc * desc) case xilinx_spartan3: printf ("Spartan-III\n"); break; - case Xilinx_Virtex2: + case xilinx_virtex2: printf ("Virtex-II\n"); break; case xilinx_zynq: @@ -334,9 +334,9 @@ int xilinx_info (Xilinx_desc * desc) __FUNCTION__); #endif break; - case Xilinx_Virtex2: + case xilinx_virtex2: #if defined(CONFIG_FPGA_VIRTEX2) - Virtex2_info (desc); + virtex2_info(desc); #else /* just in case */ printf ("%s: No support for Virtex-II devices.\n", -- cgit From f8c1be9816a60d1f627954fe202b502917c69863 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 13 Mar 2014 12:49:21 +0100 Subject: fpga: xilinx: Avoid CamelCase for in Xilinx_desc No functional changes. Signed-off-by: Michal Simek --- drivers/fpga/spartan2.c | 26 +++++++++++++------------- drivers/fpga/spartan3.c | 26 +++++++++++++------------- drivers/fpga/virtex2.c | 22 +++++++++++----------- drivers/fpga/xilinx.c | 14 +++++++------- drivers/fpga/zynqpl.c | 6 +++--- 5 files changed, 47 insertions(+), 47 deletions(-) (limited to 'drivers') diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index bd317095c6..0796729436 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -31,17 +31,17 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif -static int spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int spartan2_sp_info(Xilinx_desc *desc ); */ +static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan2_sp_info(xilinx_desc *desc ); */ -static int spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int spartan2_ss_info(Xilinx_desc *desc ); */ +static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan2_ss_info(xilinx_desc *desc ); */ /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -64,7 +64,7 @@ int spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -87,7 +87,7 @@ int spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int spartan2_info(Xilinx_desc *desc) +int spartan2_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -96,7 +96,7 @@ int spartan2_info(Xilinx_desc *desc) /* ------------------------------------------------------------------------- */ /* Spartan-II Slave Parallel Generic Implementation */ -static int spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns; @@ -248,7 +248,7 @@ static int spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns; @@ -296,7 +296,7 @@ static int spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) /* ------------------------------------------------------------------------- */ -static int spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ xilinx_spartan2_slave_serial_fns *fn = desc->iface_fns; @@ -439,7 +439,7 @@ static int spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index e40abbfb94..1304b4c646 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -35,17 +35,17 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif -static int spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int spartan3_sp_info(Xilinx_desc *desc ); */ +static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan3_sp_info(xilinx_desc *desc ); */ -static int spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int spartan3_ss_info(Xilinx_desc *desc); */ +static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan3_ss_info(xilinx_desc *desc); */ /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -68,7 +68,7 @@ int spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -91,7 +91,7 @@ int spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int spartan3_info(Xilinx_desc *desc) +int spartan3_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -100,7 +100,7 @@ int spartan3_info(Xilinx_desc *desc) /* ------------------------------------------------------------------------- */ /* Spartan-II Slave Parallel Generic Implementation */ -static int spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ xilinx_spartan3_slave_parallel_fns *fn = desc->iface_fns; @@ -254,7 +254,7 @@ static int spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ xilinx_spartan3_slave_parallel_fns *fn = desc->iface_fns; @@ -302,7 +302,7 @@ static int spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) /* ------------------------------------------------------------------------- */ -static int spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ xilinx_spartan3_slave_serial_fns *fn = desc->iface_fns; @@ -457,7 +457,7 @@ static int spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index 1cd9046a24..a582bf2d79 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -84,13 +84,13 @@ #define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */ #endif -static int virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize); -static int virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); -int virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -112,7 +112,7 @@ int virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -134,7 +134,7 @@ int virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int virtex2_info(Xilinx_desc *desc) +int virtex2_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -153,7 +153,7 @@ int virtex2_info(Xilinx_desc *desc) * INIT_B and DONE lines. If both are high, configuration has * succeeded. Congratulations! */ -static int virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns; @@ -352,7 +352,7 @@ static int virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) /* * Read the FPGA configuration data */ -static int virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns; @@ -404,13 +404,13 @@ static int virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) { printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__); return FPGA_FAIL; } -static int virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) { printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__); return FPGA_FAIL; diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 6953535f08..b0e9cb35a3 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -31,7 +31,7 @@ #endif /* Local Static Functions */ -static int xilinx_validate (Xilinx_desc * desc, char *fn); +static int xilinx_validate(xilinx_desc *desc, char *fn); /* ------------------------------------------------------------------------- */ @@ -43,7 +43,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size) unsigned char *dataptr; unsigned int i; const fpga_desc *desc; - Xilinx_desc *xdesc; + xilinx_desc *xdesc; dataptr = (unsigned char *)fpgadata; /* Find out fpga_description */ @@ -94,7 +94,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size) return FPGA_FAIL; } } else { - printf("%s: Please fill correct device ID to Xilinx_desc\n", + printf("%s: Please fill correct device ID to xilinx_desc\n", __func__); } printf(" part number = \"%s\"\n", buffer); @@ -141,7 +141,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size) return fpga_load(devnum, dataptr, swapsize); } -int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume a failure */ @@ -198,7 +198,7 @@ int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume a failure */ @@ -255,7 +255,7 @@ int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int xilinx_info (Xilinx_desc * desc) +int xilinx_info(xilinx_desc *desc) { int ret_val = FPGA_FAIL; @@ -369,7 +369,7 @@ int xilinx_info (Xilinx_desc * desc) /* ------------------------------------------------------------------------- */ -static int xilinx_validate (Xilinx_desc * desc, char *fn) +static int xilinx_validate(xilinx_desc *desc, char *fn) { int ret_val = false; diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 923a1586d8..b4d0e2278c 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -36,7 +36,7 @@ #define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */ #endif -int zynq_info(Xilinx_desc *desc) +int zynq_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -153,7 +153,7 @@ static void *check_data(u8 *buf, size_t bsize, u32 *swap) } -int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) { unsigned long ts; /* Timestamp */ u32 partialbit = 0; @@ -358,7 +358,7 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) return FPGA_SUCCESS; } -int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize) { return FPGA_FAIL; } -- cgit From 14cfc4f3735d9704cb6a630ef302be596d380684 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 13 Mar 2014 13:07:57 +0100 Subject: fpga: xilinx: Simplify load/dump/info function handling Connect FPGA version with appropriate operations to remove huge switch-cases for every FPGA family. Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test. Signed-off-by: Michal Simek --- drivers/fpga/spartan2.c | 12 +++- drivers/fpga/spartan3.c | 12 +++- drivers/fpga/virtex2.c | 12 +++- drivers/fpga/xilinx.c | 159 +++--------------------------------------------- drivers/fpga/zynqpl.c | 13 ++-- 5 files changed, 43 insertions(+), 165 deletions(-) (limited to 'drivers') diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index 0796729436..7054056140 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -41,7 +41,7 @@ static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -64,7 +64,7 @@ int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -87,7 +87,7 @@ int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int spartan2_info(xilinx_desc *desc) +static int spartan2_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -447,3 +447,9 @@ static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) __FUNCTION__); return FPGA_FAIL; } + +struct xilinx_fpga_op spartan2_op = { + .load = spartan2_load, + .dump = spartan2_dump, + .info = spartan2_info, +}; diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 1304b4c646..5c9412c2f6 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -45,7 +45,7 @@ static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -68,7 +68,7 @@ int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -91,7 +91,7 @@ int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int spartan3_info(xilinx_desc *desc) +static int spartan3_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -465,3 +465,9 @@ static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) __FUNCTION__); return FPGA_FAIL; } + +struct xilinx_fpga_op spartan3_op = { + .load = spartan3_load, + .dump = spartan3_dump, + .info = spartan3_info, +}; diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index a582bf2d79..e092147edd 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -90,7 +90,7 @@ static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize); static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize); static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); -int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -112,7 +112,7 @@ int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -134,7 +134,7 @@ int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int virtex2_info(xilinx_desc *desc) +static int virtex2_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -417,3 +417,9 @@ static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) } /* vim: set ts=4 tw=78: */ + +struct xilinx_fpga_op virtex2_op = { + .load = virtex2_load, + .dump = virtex2_dump, + .info = virtex2_info, +}; diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index b0e9cb35a3..8837f5c122 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -19,17 +19,6 @@ #include #include -#if 0 -#define FPGA_DEBUG -#endif - -/* Define FPGA_DEBUG to get debug printf's */ -#ifdef FPGA_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - /* Local Static Functions */ static int xilinx_validate(xilinx_desc *desc, char *fn); @@ -143,116 +132,22 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size) int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize) { - int ret_val = FPGA_FAIL; /* assume a failure */ - if (!xilinx_validate (desc, (char *)__FUNCTION__)) { printf ("%s: Invalid device descriptor\n", __FUNCTION__); - } else - switch (desc->family) { - case xilinx_spartan2: -#if defined(CONFIG_FPGA_SPARTAN2) - PRINTF ("%s: Launching the Spartan-II Loader...\n", - __FUNCTION__); - ret_val = spartan2_load(desc, buf, bsize); -#else - printf ("%s: No support for Spartan-II devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_spartan3: -#if defined(CONFIG_FPGA_SPARTAN3) - PRINTF ("%s: Launching the Spartan-III Loader...\n", - __FUNCTION__); - ret_val = spartan3_load(desc, buf, bsize); -#else - printf ("%s: No support for Spartan-III devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_virtex2: -#if defined(CONFIG_FPGA_VIRTEX2) - PRINTF ("%s: Launching the Virtex-II Loader...\n", - __FUNCTION__); - ret_val = virtex2_load(desc, buf, bsize); -#else - printf ("%s: No support for Virtex-II devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_zynq: -#if defined(CONFIG_FPGA_ZYNQPL) - PRINTF("%s: Launching the Zynq PL Loader...\n", - __func__); - ret_val = zynq_load(desc, buf, bsize); -#else - printf("%s: No support for Zynq devices.\n", - __func__); -#endif - break; - - default: - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); - } + return FPGA_FAIL; + } - return ret_val; + return desc->operations->load(desc, buf, bsize); } int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize) { - int ret_val = FPGA_FAIL; /* assume a failure */ - if (!xilinx_validate (desc, (char *)__FUNCTION__)) { printf ("%s: Invalid device descriptor\n", __FUNCTION__); - } else - switch (desc->family) { - case xilinx_spartan2: -#if defined(CONFIG_FPGA_SPARTAN2) - PRINTF ("%s: Launching the Spartan-II Reader...\n", - __FUNCTION__); - ret_val = spartan2_dump(desc, buf, bsize); -#else - printf ("%s: No support for Spartan-II devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_spartan3: -#if defined(CONFIG_FPGA_SPARTAN3) - PRINTF ("%s: Launching the Spartan-III Reader...\n", - __FUNCTION__); - ret_val = spartan3_dump(desc, buf, bsize); -#else - printf ("%s: No support for Spartan-III devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_virtex2: -#if defined( CONFIG_FPGA_VIRTEX2) - PRINTF ("%s: Launching the Virtex-II Reader...\n", - __FUNCTION__); - ret_val = virtex2_dump(desc, buf, bsize); -#else - printf ("%s: No support for Virtex-II devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_zynq: -#if defined(CONFIG_FPGA_ZYNQPL) - PRINTF("%s: Launching the Zynq PL Reader...\n", - __func__); - ret_val = zynq_dump(desc, buf, bsize); -#else - printf("%s: No support for Zynq devices.\n", - __func__); -#endif - break; - - default: - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); - } + return FPGA_FAIL; + } - return ret_val; + return desc->operations->dump(desc, buf, bsize); } int xilinx_info(xilinx_desc *desc) @@ -315,47 +210,7 @@ int xilinx_info(xilinx_desc *desc) if (desc->iface_fns) { printf ("Device Function Table @ 0x%p\n", desc->iface_fns); - switch (desc->family) { - case xilinx_spartan2: -#if defined(CONFIG_FPGA_SPARTAN2) - spartan2_info(desc); -#else - /* just in case */ - printf ("%s: No support for Spartan-II devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_spartan3: -#if defined(CONFIG_FPGA_SPARTAN3) - spartan3_info(desc); -#else - /* just in case */ - printf ("%s: No support for Spartan-III devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_virtex2: -#if defined(CONFIG_FPGA_VIRTEX2) - virtex2_info(desc); -#else - /* just in case */ - printf ("%s: No support for Virtex-II devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_zynq: -#if defined(CONFIG_FPGA_ZYNQPL) - zynq_info(desc); -#else - /* just in case */ - printf("%s: No support for Zynq devices.\n", - __func__); -#endif - /* Add new family types here */ - default: - /* we don't need a message here - we give one up above */ - ; - } + desc->operations->info(desc); } else printf ("No Device Function Table.\n"); diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index b4d0e2278c..dcd34951ad 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -36,7 +36,7 @@ #define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */ #endif -int zynq_info(xilinx_desc *desc) +static int zynq_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -152,8 +152,7 @@ static void *check_data(u8 *buf, size_t bsize, u32 *swap) return 0; } - -int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) +static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) { unsigned long ts; /* Timestamp */ u32 partialbit = 0; @@ -358,7 +357,13 @@ int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) return FPGA_SUCCESS; } -int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize) +static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize) { return FPGA_FAIL; } + +struct xilinx_fpga_op zynq_op = { + .load = zynq_load, + .dump = zynq_dump, + .info = zynq_info, +}; -- cgit From 42a74a08eb4ef976f3b29a0b2bdefe0e509af8f5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 25 Apr 2014 13:51:58 +0200 Subject: fpga: zynq: Remove sparse warnings Warnings: drivers/fpga/zynqpl.c:150:32: warning: Using plain integer as NULL pointer drivers/fpga/zynqpl.c:152:16: warning: Using plain integer as NULL pointer Signed-off-by: Michal Simek --- drivers/fpga/zynqpl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index dcd34951ad..0a134e524c 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -147,9 +147,9 @@ static void *check_data(u8 *buf, size_t bsize, u32 *swap) } /* Loop can be huge - support CTRL + C */ if (ctrlc()) - return 0; + return NULL; } - return 0; + return NULL; } static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) -- cgit From a0735a34f8ab2d7060b6f8c16d3cccf78b137283 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Wed, 12 Mar 2014 17:09:26 +0530 Subject: fpga: zynq: Use helper functions for zynq dma Use zynq_dma_xfer_init, zynq_align_dma_buffer, zynq_dma_transfer helper function performing dma transfers so that the code can be reused easily for different cases of dma transfer. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- drivers/fpga/zynqpl.c | 201 +++++++++++++++++++++++++++++--------------------- 1 file changed, 115 insertions(+), 86 deletions(-) (limited to 'drivers') diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 0a134e524c..ef6d1caca4 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -152,70 +152,52 @@ static void *check_data(u8 *buf, size_t bsize, u32 *swap) return NULL; } -static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) +static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen) { - unsigned long ts; /* Timestamp */ - u32 partialbit = 0; - u32 i, control, isr_status, status, swap, diff; - u32 *buf_start; + unsigned long ts; + u32 isr_status; - /* Detect if we are going working with partial or full bitstream */ - if (bsize != desc->size) { - printf("%s: Working with partial bitstream\n", __func__); - partialbit = 1; - } - - buf_start = check_data((u8 *)buf, bsize, &swap); - if (!buf_start) - return FPGA_FAIL; - - /* Check if data is postpone from start */ - diff = (u32)buf_start - (u32)buf; - if (diff) { - printf("%s: Bitstream is not validated yet (diff %x)\n", - __func__, diff); - return FPGA_FAIL; - } + /* Set up the transfer */ + writel((u32)srcbuf, &devcfg_base->dma_src_addr); + writel(dstbuf, &devcfg_base->dma_dst_addr); + writel(srclen, &devcfg_base->dma_src_len); + writel(dstlen, &devcfg_base->dma_dst_len); - if ((u32)buf < SZ_1M) { - printf("%s: Bitstream has to be placed up to 1MB (%x)\n", - __func__, (u32)buf); - return FPGA_FAIL; - } + isr_status = readl(&devcfg_base->int_sts); - if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) { - u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN); + /* Polling the PCAP_INIT status for Set */ + ts = get_timer(0); + while (!(isr_status & DEVCFG_ISR_DMA_DONE)) { + if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) { + debug("%s: Error: isr = 0x%08X\n", __func__, + isr_status); + debug("%s: Write count = 0x%08X\n", __func__, + readl(&devcfg_base->write_count)); + debug("%s: Read count = 0x%08X\n", __func__, + readl(&devcfg_base->read_count)); - /* - * This might be dangerous but permits to flash if - * ARCH_DMA_MINALIGN is greater than header size - */ - if (new_buf > buf_start) { - debug("%s: Aligned buffer is after buffer start\n", - __func__); - new_buf -= ARCH_DMA_MINALIGN; + return FPGA_FAIL; } + if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) { + printf("%s: Timeout wait for DMA to complete\n", + __func__); + return FPGA_FAIL; + } + isr_status = readl(&devcfg_base->int_sts); + } - printf("%s: Align buffer at %x to %x(swap %d)\n", __func__, - (u32)buf_start, (u32)new_buf, swap); - - for (i = 0; i < (bsize/4); i++) - new_buf[i] = load_word(&buf_start[i], swap); - - swap = SWAP_DONE; - buf = new_buf; - } else if (swap != SWAP_DONE) { - /* For bitstream which are aligned */ - u32 *new_buf = (u32 *)buf; + debug("%s: DMA transfer is done\n", __func__); - printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__, - swap); + /* Clear out the DMA status */ + writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts); - for (i = 0; i < (bsize/4); i++) - new_buf[i] = load_word(&buf_start[i], swap); + return FPGA_SUCCESS; +} - swap = SWAP_DONE; - } +static int zynq_dma_xfer_init(u32 partialbit) +{ + u32 status, control, isr_status; + unsigned long ts; /* Clear loopback bit */ clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK); @@ -297,6 +279,83 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status); } + return FPGA_SUCCESS; +} + +static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap) +{ + u32 *new_buf; + u32 i; + + if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) { + new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN); + + /* + * This might be dangerous but permits to flash if + * ARCH_DMA_MINALIGN is greater than header size + */ + if (new_buf > buf) { + debug("%s: Aligned buffer is after buffer start\n", + __func__); + new_buf -= ARCH_DMA_MINALIGN; + } + printf("%s: Align buffer at %x to %x(swap %d)\n", __func__, + (u32)buf, (u32)new_buf, swap); + + for (i = 0; i < (len/4); i++) + new_buf[i] = load_word(&buf[i], swap); + + buf = new_buf; + } else if (swap != SWAP_DONE) { + /* For bitstream which are aligned */ + u32 *new_buf = (u32 *)buf; + + printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__, + swap); + + for (i = 0; i < (len/4); i++) + new_buf[i] = load_word(&buf[i], swap); + } + + return buf; +} + +static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) +{ + unsigned long ts; /* Timestamp */ + u32 partialbit = 0; + u32 isr_status, swap, diff; + u32 *buf_start; + + /* Detect if we are going working with partial or full bitstream */ + if (bsize != desc->size) { + printf("%s: Working with partial bitstream\n", __func__); + partialbit = 1; + } + + buf_start = check_data((u8 *)buf, bsize, &swap); + if (!buf_start) + return FPGA_FAIL; + + /* Check if data is postpone from start */ + diff = (u32)buf_start - (u32)buf; + if (diff) { + printf("%s: Bitstream is not validated yet (diff %x)\n", + __func__, diff); + return FPGA_FAIL; + } + + if ((u32)buf < SZ_1M) { + printf("%s: Bitstream has to be placed up to 1MB (%x)\n", + __func__, (u32)buf); + return FPGA_FAIL; + } + + if (zynq_dma_xfer_init(partialbit)) + return FPGA_FAIL; + + buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap); + debug("%s: Source = 0x%08X\n", __func__, (u32)buf); debug("%s: Size = %zu\n", __func__, bsize); @@ -304,37 +363,10 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) flush_dcache_range((u32)buf, (u32)buf + roundup(bsize, ARCH_DMA_MINALIGN)); - /* Set up the transfer */ - writel((u32)buf | 1, &devcfg_base->dma_src_addr); - writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr); - writel(bsize >> 2, &devcfg_base->dma_src_len); - writel(0, &devcfg_base->dma_dst_len); + if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0)) + return FPGA_FAIL; isr_status = readl(&devcfg_base->int_sts); - - /* Polling the PCAP_INIT status for Set */ - ts = get_timer(0); - while (!(isr_status & DEVCFG_ISR_DMA_DONE)) { - if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) { - debug("%s: Error: isr = 0x%08X\n", __func__, - isr_status); - debug("%s: Write count = 0x%08X\n", __func__, - readl(&devcfg_base->write_count)); - debug("%s: Read count = 0x%08X\n", __func__, - readl(&devcfg_base->read_count)); - - return FPGA_FAIL; - } - if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) { - printf("%s: Timeout wait for DMA to complete\n", - __func__); - return FPGA_FAIL; - } - isr_status = readl(&devcfg_base->int_sts); - } - - debug("%s: DMA transfer is done\n", __func__); - /* Check FPGA configuration completion */ ts = get_timer(0); while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { @@ -348,9 +380,6 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) debug("%s: FPGA config done\n", __func__); - /* Clear out the DMA status */ - writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts); - if (!partialbit) zynq_slcr_devcfg_enable(); -- cgit From 31081859855e606ca06131c3a14e099e043d39f0 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Thu, 13 Mar 2014 11:57:34 +0530 Subject: fpga: zynq: Use helper function zynq_validate_bitstream Use helper function zynq_validate_bitstream so that the code can be reused easily for different cases of dma transfer. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- drivers/fpga/zynqpl.c | 32 +++++++++++++++++++++++++------- 1 file changed, 25 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index ef6d1caca4..c066f21d79 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -320,20 +320,20 @@ static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap) return buf; } -static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) +static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf, + size_t bsize, u32 blocksize, u32 *swap, + u32 *partialbit) { - unsigned long ts; /* Timestamp */ - u32 partialbit = 0; - u32 isr_status, swap, diff; u32 *buf_start; + u32 diff; /* Detect if we are going working with partial or full bitstream */ if (bsize != desc->size) { printf("%s: Working with partial bitstream\n", __func__); - partialbit = 1; + *partialbit = 1; } + buf_start = check_data((u8 *)buf, blocksize, swap); - buf_start = check_data((u8 *)buf, bsize, &swap); if (!buf_start) return FPGA_FAIL; @@ -351,7 +351,25 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) return FPGA_FAIL; } - if (zynq_dma_xfer_init(partialbit)) + if (zynq_dma_xfer_init(*partialbit)) + return FPGA_FAIL; + + return 0; +} + + +static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) +{ + unsigned long ts; /* Timestamp */ + u32 partialbit = 0; + u32 isr_status, swap; + + /* + * send bsize inplace of blocksize as it was not a bitstream + * in chunks + */ + if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap, + &partialbit)) return FPGA_FAIL; buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap); -- cgit From 0b2e13d9ccbe56e32dc674cf896b2fb55684368c Mon Sep 17 00:00:00 2001 From: Chunhe Lan Date: Mon, 14 Apr 2014 18:42:06 +0800 Subject: powerpc/85xx: Add T4240RDB board support T4240RDB board Specification ---------------------------- Memory subsystem: 6GB DDR3 128MB NOR flash 2GB NAND flash Ethernet: Eight 1G SGMII ports Four 10Gbps SFP+ ports PCIe: Two PCIe slots USB: Two USB2.0 Type A ports SDHC: One SD-card port SATA: One SATA port UART: Dual RJ45 ports Signed-off-by: Chunhe Lan [York Sun: fix CONFIG_SYS_QE_FMAN_FW_ADDR in T4240RDB.h] --- drivers/mmc/fsl_esdhc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 4c3b93d413..50cba64d99 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -96,7 +96,7 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) else if (cmd->resp_type & MMC_RSP_PRESENT) xfertyp |= XFERTYP_RSPTYP_48; -#if defined(CONFIG_MX53) || defined(CONFIG_T4240QDS) +#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) xfertyp |= XFERTYP_CMDTYP_ABORT; #endif -- cgit From 3a7ed5aa232da1d2836b5d3962e59e685307122e Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Tue, 22 Apr 2014 18:21:37 +0800 Subject: powerpc/fman/memac: use default MDIO_HOLD value Current driver uses a Maximum value for MDIO_HOLD when doing 10G MDIO access, this is due to an errata A-006260 on T4 rev1.0 which is fixed on rev2.0, so remove the maximum value to use the default value for rev2.0. Signed-off-by: Shaohui Xie --- drivers/net/fm/memac_phy.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c index 2f4bc11a6c..de9c0e9cd2 100644 --- a/drivers/net/fm/memac_phy.c +++ b/drivers/net/fm/memac_phy.c @@ -29,10 +29,8 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, c45 = 0; /* clause 22 */ dev_addr = regnum & 0x1f; clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC); - } else { + } else setbits_be32(®s->mdio_stat, MDIO_STAT_ENC); - setbits_be32(®s->mdio_stat, MDIO_STAT_HOLD_15_CLK); - } /* Wait till the bus is free */ while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) @@ -76,10 +74,8 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, c45 = 0; /* clause 22 */ dev_addr = regnum & 0x1f; clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC); - } else { + } else setbits_be32(®s->mdio_stat, MDIO_STAT_ENC); - setbits_be32(®s->mdio_stat, MDIO_STAT_HOLD_15_CLK); - } /* Wait till the bus is free */ while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) -- cgit From 5122dfae5d3cd68e0b6e5e08597df91ba79770aa Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 25 Apr 2014 16:31:22 +0800 Subject: powerpc/85xx: add T4080 SoC support The T4080 SoC is a low-power version of the T4160. T4080 combines 4 dual-threaded Power Architecture e6500 cores with single cluster and two memory complexes. Signed-off-by: Shengzhou Liu --- drivers/net/fm/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile index ee5d768937..5ae3b167a9 100644 --- a/drivers/net/fm/Makefile +++ b/drivers/net/fm/Makefile @@ -32,5 +32,6 @@ obj-$(CONFIG_PPC_T2080) += t2080.o obj-$(CONFIG_PPC_T2081) += t2080.o obj-$(CONFIG_PPC_T4240) += t4240.o obj-$(CONFIG_PPC_T4160) += t4240.o +obj-$(CONFIG_PPC_T4080) += t4240.o obj-$(CONFIG_PPC_B4420) += b4860.o obj-$(CONFIG_PPC_B4860) += b4860.o -- cgit From ca721fb292c0d17c586caf1993a22a10f6fffd9c Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Wed, 30 Apr 2014 16:45:31 +0800 Subject: qe: disable qe when qe-ucode fails to be uploaded for "deep sleep" when qe-ucode fails to be uploaded, "deep sleep" will hang. if there is no qe-ucode, disable qe module for platforms which support "deep sleep" Signed-off-by: Zhao Qiang --- drivers/qe/qe.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index b1da75ec4d..9c5fbd1d69 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -14,6 +14,8 @@ #include "asm/immap_qe.h" #include "qe.h" +#define MPC85xx_DEVDISR_QE_DISABLE 0x1 + qe_map_t *qe_immr = NULL; static qe_snum_t snums[QE_NUM_OF_SNUM]; @@ -317,7 +319,9 @@ int qe_upload_firmware(const struct qe_firmware *firmware) size_t calc_size = sizeof(struct qe_firmware); size_t length; const struct qe_header *hdr; - +#ifdef CONFIG_DEEP_SLEEP + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif if (!firmware) { printf("Invalid address\n"); return -EINVAL; @@ -330,6 +334,9 @@ int qe_upload_firmware(const struct qe_firmware *firmware) if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || (hdr->magic[2] != 'F')) { printf("Not a microcode\n"); +#ifdef CONFIG_DEEP_SLEEP + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE); +#endif return -EPERM; } -- cgit From fab356a0b87d57d474d6e87408f1ede98a503150 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 3 May 2014 17:46:26 +0200 Subject: mvtwsi: Fix clock programming The TWSI_FREQUENCY macro was wrong in 2 ways: 1) It was casting the result of the calculations to an u8, while i2c clk rates are often >= 100Khz which won't fit in a u8, drop the cast. 2) It had an extra factor of 2 in the divider which neither the datasheet nor the Linux driver have. The comment for the default value was wrongly saying that m lives in bits 4-7, while in reality it is in bits 3-6, as can be seen from the correct shift by 3 used in i2c_init(). While at it remove the unused twsi_actual_speed variable. Signed-off-by: Hans de Goede --- drivers/i2c/mvtwsi.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index 90c8387918..b44944378a 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -216,7 +216,7 @@ static int twsi_stop(int status) */ #define TWSI_FREQUENCY(m, n) \ - ((u8) (CONFIG_SYS_TCLK / (10 * (m + 1) * 2 * (1 << n)))) + (CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n))) /* * These are required to be reprogrammed before enabling the controller @@ -225,10 +225,8 @@ static int twsi_stop(int status) * twsi_slave_address left uninitialized lest checkpatch.pl complains. */ -/* Baudrate generator: m (bits 7..4) =4, n (bits 3..0) =4 */ +/* Baudrate generator: m (bits 6..3) = 8, n (bits 2..0) = 4 */ static u8 twsi_baud_rate = 0x44; /* baudrate at controller reset */ -/* Default frequency corresponding to default m=4, n=4 */ -static u8 twsi_actual_speed = TWSI_FREQUENCY(4, 4); /* Default slave address is 0 (so is an uninitialized static) */ static u8 twsi_slave_address; @@ -279,7 +277,6 @@ void i2c_init(int requested_speed, int slaveadd) } /* save baud rate and slave for later calls to twsi_reset */ twsi_baud_rate = baud; - twsi_actual_speed = highest_speed; twsi_slave_address = slaveadd; /* reset controller */ twsi_reset(); -- cgit From 2072e7262965bb48d7fffb1e283101e6ed8b21a8 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 3 May 2014 17:46:27 +0200 Subject: mvtwsi: Remove unnecessary twsi_baud_rate and twsi_slave_address globals These are used only once, so their is no need to have them global. This also stops mvtwsi from using any bss vars making it easier to use before dram init (to talk to the pmic to set the dram voltage). Signed-off-by: Hans de Goede --- drivers/i2c/mvtwsi.c | 23 ++++------------------- 1 file changed, 4 insertions(+), 19 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index b44944378a..5ba0e03862 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -218,25 +218,13 @@ static int twsi_stop(int status) #define TWSI_FREQUENCY(m, n) \ (CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n))) -/* - * These are required to be reprogrammed before enabling the controller - * because a reset loses them. - * Default values come from the spec, but a twsi_reset will change them. - * twsi_slave_address left uninitialized lest checkpatch.pl complains. - */ - -/* Baudrate generator: m (bits 6..3) = 8, n (bits 2..0) = 4 */ -static u8 twsi_baud_rate = 0x44; /* baudrate at controller reset */ -/* Default slave address is 0 (so is an uninitialized static) */ -static u8 twsi_slave_address; - /* * Reset controller. * Called at end of i2c_init unsuccessful i2c transactions. * Controller reset also resets the baud rate and slave address, so * re-establish them. */ -static void twsi_reset(void) +static void twsi_reset(u8 baud_rate, u8 slave_address) { /* ensure controller will be enabled by any twsi*() function */ twsi_control_flags = MVTWSI_CONTROL_TWSIEN; @@ -245,9 +233,9 @@ static void twsi_reset(void) /* wait 2 ms -- this is what the Marvell LSP does */ udelay(20000); /* set baud rate */ - writel(twsi_baud_rate, &twsi->baudrate); + writel(baud_rate, &twsi->baudrate); /* set slave address even though we don't use it */ - writel(twsi_slave_address, &twsi->slave_address); + writel(slave_address, &twsi->slave_address); writel(0, &twsi->xtnd_slave_addr); /* assert STOP but don't care for the result */ (void) twsi_stop(0); @@ -275,11 +263,8 @@ void i2c_init(int requested_speed, int slaveadd) } } } - /* save baud rate and slave for later calls to twsi_reset */ - twsi_baud_rate = baud; - twsi_slave_address = slaveadd; /* reset controller */ - twsi_reset(); + twsi_reset(baud, slaveadd); } /* -- cgit