From 616f03dabacb6c500e8a7ceb920cd08554c9fcae Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 4 May 2020 22:08:50 +0800 Subject: mtd: gpmi: change the BCH layout setting for large oob NAND MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The code change updated the NAND driver BCH ECC layout algorithm to support large oob size NAND chips(oob > 1024 bytes) and proposed a new way to set ECC layout. Current implementation requires each chunk size larger than oob size so the bad block marker (BBM) can be guaranteed located in data chunk. The ECC layout always using the unbalanced layout(Ecc for both meta and Data0 chunk), but for the NAND chips with oob larger than 1k, the driver cannot support because BCH doesn’t support GF 15 for 2K chunk. The change keeps the data chunk no larger than 1k and adjust the ECC strength or ECC layout to locate the BBM in data chunk. General idea for large oob NAND chips is 1.Try all ECC strength from the minimum value required by NAND spec to the maximum one that works, any ECC makes the BBM locate in data chunk can be chosen. 2.If none of them works, using separate ECC for meta, which will add one extra ecc with the same ECC strength as other data chunks. This extra ECC can guarantee BBM located in data chunk, of course, we need to check if oob can afford it. Previous code has two methods for ECC layout setting, the legacy_calc_ecc_layout and calc_ecc_layout_by_info, the difference between these two methods is, legacy_calc_ecc_layout set the chunk size larger chan oob size and then set the maximum ECC strength that oob can afford. While the calc_ecc_layout_by_info set chunk size and ECC strength according to NAND spec. It has been proved that the first method cannot provide safe ECC strength for some modern NAND chips, so in current code, 1. Driver read NAND parameters first and then chose the proper ECC layout setting method. 2. If the oob is large or NAND required data chunk larger than oob size, chose calc_ecc_for_large_oob, otherwise use calc_ecc_layout_by_info 3. legacy_calc_ecc_layout only used for some NAND chips does not contains necessary information. So this is only a backup plan, it is NOT recommended to use these NAND chips. Signed-off-by: Han Xu Signed-off-by: Ye Li Signed-off-by: Peng Fan --- drivers/mtd/nand/raw/mxs_nand.c | 205 ++++++++++++++++++++++++++-------------- 1 file changed, 136 insertions(+), 69 deletions(-) (limited to 'drivers/mtd') diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index fe8097c146..8da59e39c0 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -112,53 +112,32 @@ static uint32_t mxs_nand_aux_status_offset(void) return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3; } -static inline int mxs_nand_calc_mark_offset(struct bch_geometry *geo, - uint32_t page_data_size) +static inline bool mxs_nand_bbm_in_data_chunk(struct bch_geometry *geo, struct mtd_info *mtd, + unsigned int *chunk_num) { - uint32_t chunk_data_size_in_bits = geo->ecc_chunk_size * 8; - uint32_t chunk_ecc_size_in_bits = geo->ecc_strength * geo->gf_len; - uint32_t chunk_total_size_in_bits; - uint32_t block_mark_chunk_number; - uint32_t block_mark_chunk_bit_offset; - uint32_t block_mark_bit_offset; + unsigned int i, j; - chunk_total_size_in_bits = - chunk_data_size_in_bits + chunk_ecc_size_in_bits; - - /* Compute the bit offset of the block mark within the physical page. */ - block_mark_bit_offset = page_data_size * 8; - - /* Subtract the metadata bits. */ - block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8; - - /* - * Compute the chunk number (starting at zero) in which the block mark - * appears. - */ - block_mark_chunk_number = - block_mark_bit_offset / chunk_total_size_in_bits; - - /* - * Compute the bit offset of the block mark within its chunk, and - * validate it. - */ - block_mark_chunk_bit_offset = block_mark_bit_offset - - (block_mark_chunk_number * chunk_total_size_in_bits); + if (geo->ecc_chunk0_size != geo->ecc_chunkn_size) { + dev_err(this->dev, "The size of chunk0 must equal to chunkn\n"); + return false; + } - if (block_mark_chunk_bit_offset > chunk_data_size_in_bits) - return -EINVAL; + i = (mtd->writesize * 8 - MXS_NAND_METADATA_SIZE * 8) / + (geo->gf_len * geo->ecc_strength + + geo->ecc_chunkn_size * 8); - /* - * Now that we know the chunk number in which the block mark appears, - * we can subtract all the ECC bits that appear before it. - */ - block_mark_bit_offset -= - block_mark_chunk_number * chunk_ecc_size_in_bits; + j = (mtd->writesize * 8 - MXS_NAND_METADATA_SIZE * 8) - + (geo->gf_len * geo->ecc_strength + + geo->ecc_chunkn_size * 8) * i; - geo->block_mark_byte_offset = block_mark_bit_offset >> 3; - geo->block_mark_bit_offset = block_mark_bit_offset & 0x7; + if (j < geo->ecc_chunkn_size * 8) { + *chunk_num = i + 1; + dev_dbg(this->dev, "Set ecc to %d and bbm in chunk %d\n", + geo->ecc_strength, *chunk_num); + return true; + } - return 0; + return false; } static inline int mxs_nand_calc_ecc_layout_by_info(struct bch_geometry *geo, @@ -168,6 +147,7 @@ static inline int mxs_nand_calc_ecc_layout_by_info(struct bch_geometry *geo, { struct nand_chip *chip = mtd_to_nand(mtd); struct mxs_nand_info *nand_info = nand_get_controller_data(chip); + unsigned int block_mark_bit_offset; switch (ecc_step) { case SZ_512: @@ -180,45 +160,51 @@ static inline int mxs_nand_calc_ecc_layout_by_info(struct bch_geometry *geo, return -EINVAL; } - geo->ecc_chunk_size = ecc_step; + geo->ecc_chunk0_size = ecc_step; + geo->ecc_chunkn_size = ecc_step; geo->ecc_strength = round_up(ecc_strength, 2); /* Keep the C >= O */ - if (geo->ecc_chunk_size < mtd->oobsize) + if (geo->ecc_chunkn_size < mtd->oobsize) return -EINVAL; if (geo->ecc_strength > nand_info->max_ecc_strength_supported) return -EINVAL; - geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size; + geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunkn_size; + + /* For bit swap. */ + block_mark_bit_offset = mtd->writesize * 8 - + (geo->ecc_strength * geo->gf_len * (geo->ecc_chunk_count - 1) + + MXS_NAND_METADATA_SIZE * 8); + + geo->block_mark_byte_offset = block_mark_bit_offset / 8; + geo->block_mark_bit_offset = block_mark_bit_offset % 8; return 0; } -static inline int mxs_nand_calc_ecc_layout(struct bch_geometry *geo, +static inline int mxs_nand_legacy_calc_ecc_layout(struct bch_geometry *geo, struct mtd_info *mtd) { struct nand_chip *chip = mtd_to_nand(mtd); struct mxs_nand_info *nand_info = nand_get_controller_data(chip); + unsigned int block_mark_bit_offset; /* The default for the length of Galois Field. */ geo->gf_len = 13; /* The default for chunk size. */ - geo->ecc_chunk_size = 512; + geo->ecc_chunk0_size = 512; + geo->ecc_chunkn_size = 512; - if (geo->ecc_chunk_size < mtd->oobsize) { + if (geo->ecc_chunkn_size < mtd->oobsize) { geo->gf_len = 14; - geo->ecc_chunk_size *= 2; + geo->ecc_chunk0_size *= 2; + geo->ecc_chunkn_size *= 2; } - if (mtd->oobsize > geo->ecc_chunk_size) { - printf("Not support the NAND chips whose oob size is larger then %d bytes!\n", - geo->ecc_chunk_size); - return -EINVAL; - } - - geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size; + geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunkn_size; /* * Determine the ECC layout with the formula: @@ -234,6 +220,84 @@ static inline int mxs_nand_calc_ecc_layout(struct bch_geometry *geo, geo->ecc_strength = min(round_down(geo->ecc_strength, 2), nand_info->max_ecc_strength_supported); + block_mark_bit_offset = mtd->writesize * 8 - + (geo->ecc_strength * geo->gf_len * (geo->ecc_chunk_count - 1) + + MXS_NAND_METADATA_SIZE * 8); + + geo->block_mark_byte_offset = block_mark_bit_offset / 8; + geo->block_mark_bit_offset = block_mark_bit_offset % 8; + + return 0; +} + +static inline int mxs_nand_calc_ecc_for_large_oob(struct bch_geometry *geo, + struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct mxs_nand_info *nand_info = nand_get_controller_data(chip); + unsigned int block_mark_bit_offset; + unsigned int max_ecc; + unsigned int bbm_chunk; + unsigned int i; + + /* sanity check for the minimum ecc nand required */ + if (!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0)) + return -EINVAL; + geo->ecc_strength = chip->ecc_strength_ds; + + /* calculate the maximum ecc platform can support*/ + geo->gf_len = 14; + geo->ecc_chunk0_size = 1024; + geo->ecc_chunkn_size = 1024; + geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunkn_size; + max_ecc = ((mtd->oobsize - MXS_NAND_METADATA_SIZE) * 8) + / (geo->gf_len * geo->ecc_chunk_count); + max_ecc = min(round_down(max_ecc, 2), + nand_info->max_ecc_strength_supported); + + + /* search a supported ecc strength that makes bbm */ + /* located in data chunk */ + geo->ecc_strength = chip->ecc_strength_ds; + while (!(geo->ecc_strength > max_ecc)) { + if (mxs_nand_bbm_in_data_chunk(geo, mtd, &bbm_chunk)) + break; + geo->ecc_strength += 2; + } + + /* if none of them works, keep using the minimum ecc */ + /* nand required but changing ecc page layout */ + if (geo->ecc_strength > max_ecc) { + geo->ecc_strength = chip->ecc_strength_ds; + /* add extra ecc for meta data */ + geo->ecc_chunk0_size = 0; + geo->ecc_chunk_count = (mtd->writesize / geo->ecc_chunkn_size) + 1; + geo->ecc_for_meta = 1; + /* check if oob can afford this extra ecc chunk */ + if (mtd->oobsize * 8 < MXS_NAND_METADATA_SIZE * 8 + + geo->gf_len * geo->ecc_strength + * geo->ecc_chunk_count) { + printf("unsupported NAND chip with new layout\n"); + return -EINVAL; + } + + /* calculate in which chunk bbm located */ + bbm_chunk = (mtd->writesize * 8 - MXS_NAND_METADATA_SIZE * 8 - + geo->gf_len * geo->ecc_strength) / + (geo->gf_len * geo->ecc_strength + + geo->ecc_chunkn_size * 8) + 1; + } + + /* calculate the number of ecc chunk behind the bbm */ + i = (mtd->writesize / geo->ecc_chunkn_size) - bbm_chunk + 1; + + block_mark_bit_offset = mtd->writesize * 8 - + (geo->ecc_strength * geo->gf_len * (geo->ecc_chunk_count - i) + + MXS_NAND_METADATA_SIZE * 8); + + geo->block_mark_byte_offset = block_mark_bit_offset / 8; + geo->block_mark_bit_offset = block_mark_bit_offset % 8; + return 0; } @@ -983,18 +1047,23 @@ static int mxs_nand_set_geometry(struct mtd_info *mtd, struct bch_geometry *geo) struct nand_chip *nand = mtd_to_nand(mtd); struct mxs_nand_info *nand_info = nand_get_controller_data(nand); - if (chip->ecc.strength > 0 && chip->ecc.size > 0) - return mxs_nand_calc_ecc_layout_by_info(geo, mtd, - chip->ecc.strength, chip->ecc.size); + if (chip->ecc_strength_ds > nand_info->max_ecc_strength_supported) { + printf("unsupported NAND chip, minimum ecc required %d\n" + , chip->ecc_strength_ds); + return -EINVAL; + } + + if (!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0) && + (mtd->oobsize < 1024)) { + dev_warn(this->dev, "use legacy bch geometry\n"); + return mxs_nand_legacy_calc_ecc_layout(geo, mtd); + } - if (nand_info->use_minimum_ecc || - mxs_nand_calc_ecc_layout(geo, mtd)) { - if (!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0)) - return -EINVAL; + if (mtd->oobsize > 1024 || chip->ecc_step_ds < mtd->oobsize) + return mxs_nand_calc_ecc_for_large_oob(geo, mtd); - return mxs_nand_calc_ecc_layout_by_info(geo, mtd, + return mxs_nand_calc_ecc_layout_by_info(geo, mtd, chip->ecc_strength_ds, chip->ecc_step_ds); - } return 0; } @@ -1025,8 +1094,6 @@ int mxs_nand_setup_ecc(struct mtd_info *mtd) if (ret) return ret; - mxs_nand_calc_mark_offset(geo, mtd->writesize); - /* Configure BCH and set NFC geometry */ mxs_reset_block(&bch_regs->hw_bch_ctrl_reg); @@ -1034,7 +1101,7 @@ int mxs_nand_setup_ecc(struct mtd_info *mtd) tmp = (geo->ecc_chunk_count - 1) << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET; tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET; tmp |= (geo->ecc_strength >> 1) << BCH_FLASHLAYOUT0_ECC0_OFFSET; - tmp |= geo->ecc_chunk_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT; + tmp |= geo->ecc_chunk0_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT; tmp |= (geo->gf_len == 14 ? 1 : 0) << BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET; writel(tmp, &bch_regs->hw_bch_flash0layout0); @@ -1043,7 +1110,7 @@ int mxs_nand_setup_ecc(struct mtd_info *mtd) tmp = (mtd->writesize + mtd->oobsize) << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET; tmp |= (geo->ecc_strength >> 1) << BCH_FLASHLAYOUT1_ECCN_OFFSET; - tmp |= geo->ecc_chunk_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT; + tmp |= geo->ecc_chunkn_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT; tmp |= (geo->gf_len == 14 ? 1 : 0) << BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET; writel(tmp, &bch_regs->hw_bch_flash0layout1); @@ -1268,7 +1335,7 @@ int mxs_nand_init_ctrl(struct mxs_nand_info *nand_info) nand->ecc.layout = &fake_ecc_layout; nand->ecc.mode = NAND_ECC_HW; - nand->ecc.size = nand_info->bch_geometry.ecc_chunk_size; + nand->ecc.size = nand_info->bch_geometry.ecc_chunkn_size; nand->ecc.strength = nand_info->bch_geometry.ecc_strength; /* second phase scan */ -- cgit From 51cdf83eea45861f9932019db2a1b3a0a6a3af52 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 4 May 2020 22:08:51 +0800 Subject: mtd: gpmi: provide the option to use legacy bch geometry Provide an option in DT to use legacy bch geometry, which compatible with the 3.10 kernel bch setting. To enable the feature, adding "fsl,legacy-bch-geometry" under gpmi-nand node. NOTICE: The feature must be enabled/disabled in both u-boot and kernel. Signed-off-by: Han Xu Signed-off-by: Ye Li Signed-off-by: Peng Fan --- drivers/mtd/nand/raw/mxs_nand.c | 4 ++-- drivers/mtd/nand/raw/mxs_nand_dt.c | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/mtd') diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index 8da59e39c0..3247064c3f 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -1053,8 +1053,8 @@ static int mxs_nand_set_geometry(struct mtd_info *mtd, struct bch_geometry *geo) return -EINVAL; } - if (!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0) && - (mtd->oobsize < 1024)) { + if ((!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0) && + mtd->oobsize < 1024) || nand_info->legacy_bch_geometry) { dev_warn(this->dev, "use legacy bch geometry\n"); return mxs_nand_legacy_calc_ecc_layout(geo, mtd); } diff --git a/drivers/mtd/nand/raw/mxs_nand_dt.c b/drivers/mtd/nand/raw/mxs_nand_dt.c index 8ad7d618c6..7a32b284f7 100644 --- a/drivers/mtd/nand/raw/mxs_nand_dt.c +++ b/drivers/mtd/nand/raw/mxs_nand_dt.c @@ -69,6 +69,8 @@ static int mxs_nand_dt_probe(struct udevice *dev) info->use_minimum_ecc = dev_read_bool(dev, "fsl,use-minimum-ecc"); + info->legacy_bch_geometry = dev_read_bool(dev, "fsl,legacy-bch-geometry"); + return mxs_nand_init_ctrl(info); } -- cgit From 552c88273ef9c5ebe269d47e7610a39ef5bfa5cc Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 4 May 2020 22:08:52 +0800 Subject: nand: mxs: fix the bitflips for erased page when uncorrectable error This patch is porting from linux: http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/ ?h=imx_4.1.15_1.0.0_ga&id=3d42fcece496224fde59f9343763fb2dfc5b0768 " We may meet the bitflips in reading an erased page(contains all 0xFF), this may causes the UBIFS corrupt, please see the log from Elie: ----------------------------------------------------------------- [ 3.831323] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry [ 3.845026] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry [ 3.858710] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry [ 3.872408] UBI error: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read 16384 bytes ... [ 4.011529] UBIFS error (pid 36): ubifs_recover_leb: corrupt empty space LEB 27:237568, corruption starts at 9815 [ 4.021897] UBIFS error (pid 36): ubifs_scanned_corruption: corruption at LEB 27:247383 [ 4.030000] UBIFS error (pid 36): ubifs_scanned_corruption: first 6569 bytes from LEB 27:247383 ----------------------------------------------------------------- This patch does a check for the uncorrectable failure in the following steps: [0] set the threshold. The threshold is set based on the truth: "A single 0 bit will lead to gf_len(13 or 14) bits 0 after the BCH do the ECC." For the sake of safe, we will set the threshold with half the gf_len, and do not make it bigger the ECC strength. [1] count the bitflips of the current ECC chunk, assume it is N. [2] if the (N <= threshold) is true, we continue to read out the page with ECC disabled. and we count the bitflips again, assume it is N2. (We read out the whole page, not just a chunk, this makes the check more strictly, and make the code more simple.) [3] if the (N2 <= threshold) is true again, we can regard this is a erased page. This is because a real erased page is full of 0xFF(maybe also has several bitflips), while a page contains the 0xFF data will definitely has many bitflips in the ECC parity areas. [4] if the [3] fails, we can regard this is a page filled with the '0xFF' data. " Signed-off-by: Peng Fan --- drivers/mtd/nand/raw/mxs_nand.c | 44 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'drivers/mtd') diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index 3247064c3f..55d24cd062 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -612,6 +612,45 @@ static uint8_t mxs_nand_read_byte(struct mtd_info *mtd) return buf; } +static bool mxs_nand_erased_page(struct mtd_info *mtd, struct nand_chip *nand, + u8 *buf, int chunk, int page) +{ + struct mxs_nand_info *nand_info = nand_get_controller_data(nand); + struct bch_geometry *geo = &nand_info->bch_geometry; + unsigned int flip_bits = 0, flip_bits_noecc = 0; + unsigned int threshold; + unsigned int base = geo->ecc_chunkn_size * chunk; + u32 *dma_buf = (u32 *)buf; + int i; + + threshold = geo->gf_len / 2; + if (threshold > geo->ecc_strength) + threshold = geo->ecc_strength; + + for (i = 0; i < geo->ecc_chunkn_size; i++) { + flip_bits += hweight8(~buf[base + i]); + if (flip_bits > threshold) + return false; + } + + nand->cmdfunc(mtd, NAND_CMD_READ0, 0, page); + nand->read_buf(mtd, buf, mtd->writesize); + + for (i = 0; i < mtd->writesize / 4; i++) { + flip_bits_noecc += hweight32(~dma_buf[i]); + if (flip_bits_noecc > threshold) + return false; + } + + mtd->ecc_stats.corrected += flip_bits; + + memset(buf, 0xff, mtd->writesize); + + printf("The page(%d) is an erased page(%d,%d,%d,%d).\n", page, chunk, threshold, flip_bits, flip_bits_noecc); + + return true; +} + /* * Read a page from NAND. */ @@ -715,6 +754,8 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, goto rtn; } + mxs_nand_return_dma_descs(nand_info); + /* Invalidate caches */ mxs_nand_inval_data_buf(nand_info); @@ -731,6 +772,9 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, continue; if (status[i] == 0xfe) { + if (mxs_nand_erased_page(mtd, nand, + nand_info->data_buf, i, page)) + break; failed++; continue; } -- cgit From 29f40c07e7a649c6fc44a3a44449dce1ee733816 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 4 May 2020 22:08:53 +0800 Subject: nand: mxs: correct bitflip for erased NAND page This patch is a porting of http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/ commit/?h=imx_4.1.15_1.0.0_ga&id=e4dacc44d22e9474ec456cb330df525cd805ea38 " i.MX6QP and i.MX7D BCH module integrated a new feature to detect the bitflip number for erased NAND page. So for these two platform, set the erase threshold to gf/2 and if bitflip detected, GPMI driver will correct the data to all 0xFF. Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q with the one for i.MX6QP. " In this patch, i.MX6UL is added and threshold changed to use ecc_strength. Signed-off-by: Peng Fan --- drivers/mtd/nand/raw/mxs_nand.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) (limited to 'drivers/mtd') diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index 55d24cd062..2ac06a5730 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -10,6 +10,7 @@ * * Copyright (C) 2010 Freescale Semiconductor, Inc. * Copyright (C) 2008 Embedded Alley Solutions, Inc. + * Copyright 2017-2019 NXP */ #include @@ -660,11 +661,13 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, { struct mxs_nand_info *nand_info = nand_get_controller_data(nand); struct bch_geometry *geo = &nand_info->bch_geometry; + struct mxs_bch_regs *bch_regs = nand_info->bch_regs; struct mxs_dma_desc *d; uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; uint32_t corrected = 0, failed = 0; uint8_t *status; int i, ret; + int flag = 0; /* Compile the DMA descriptor - wait for ready. */ d = mxs_nand_get_dma_desc(nand_info); @@ -768,8 +771,13 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, if (status[i] == 0x00) continue; - if (status[i] == 0xff) + if (status[i] == 0xff) { + if (is_mx6dqp() || is_mx7() || + is_mx6ul()) + if (readl(&bch_regs->hw_bch_debug1)) + flag = 1; continue; + } if (status[i] == 0xfe) { if (mxs_nand_erased_page(mtd, nand, @@ -801,6 +809,8 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, memcpy(buf, nand_info->data_buf, mtd->writesize); + if (flag) + memset(buf, 0xff, mtd->writesize); rtn: mxs_nand_return_dma_descs(nand_info); @@ -1160,6 +1170,12 @@ int mxs_nand_setup_ecc(struct mtd_info *mtd) writel(tmp, &bch_regs->hw_bch_flash0layout1); nand_info->bch_flash0layout1 = tmp; + /* Set erase threshold to ecc strength for mx6ul, mx6qp and mx7 */ + if (is_mx6dqp() || is_mx7() || + is_mx6ul()) + writel(BCH_MODE_ERASE_THRESHOLD(geo->ecc_strength), + &bch_regs->hw_bch_mode); + /* Set *all* chip selects to use layout 0 */ writel(0, &bch_regs->hw_bch_layoutselect); -- cgit From ff99041b3b6dccc1649d0c8512303a5240fb8785 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 4 May 2020 22:08:54 +0800 Subject: mxs_nand: Add support for i.MX8M Update the gpmi/apbh_dma/bch drivers and relevant registers for i.MX8M. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- drivers/mtd/nand/raw/Kconfig | 6 +++--- drivers/mtd/nand/raw/mxs_nand.c | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) (limited to 'drivers/mtd') diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 23201ca720..c46fec3d32 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -259,12 +259,12 @@ config NAND_MXC config NAND_MXS bool "MXS NAND support" - depends on MX23 || MX28 || MX6 || MX7 + depends on MX23 || MX28 || MX6 || MX7 || IMX8M select SYS_NAND_SELF_INIT imply CMD_NAND select APBH_DMA - select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 - select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 + select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8M + select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8M help This enables NAND driver for the NAND flash controller on the MXS processors. diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index 2ac06a5730..facedf92c5 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -31,7 +31,7 @@ #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4 -#if (defined(CONFIG_MX6) || defined(CONFIG_MX7)) +#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M)) #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2 #else #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0 @@ -773,7 +773,7 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, if (status[i] == 0xff) { if (is_mx6dqp() || is_mx7() || - is_mx6ul()) + is_mx6ul() || is_imx8m()) if (readl(&bch_regs->hw_bch_debug1)) flag = 1; continue; @@ -1172,7 +1172,7 @@ int mxs_nand_setup_ecc(struct mtd_info *mtd) /* Set erase threshold to ecc strength for mx6ul, mx6qp and mx7 */ if (is_mx6dqp() || is_mx7() || - is_mx6ul()) + is_mx6ul() || is_imx8m()) writel(BCH_MODE_ERASE_THRESHOLD(geo->ecc_strength), &bch_regs->hw_bch_mode); @@ -1311,7 +1311,7 @@ int mxs_nand_init_spl(struct nand_chip *nand) nand_info->gpmi_regs = (struct mxs_gpmi_regs *)MXS_GPMI_BASE; nand_info->bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE; - if (is_mx6sx() || is_mx7()) + if (is_mx6sx() || is_mx7() || is_imx8m()) nand_info->max_ecc_strength_supported = 62; else nand_info->max_ecc_strength_supported = 40; -- cgit From b209635c7a7f66e97d23de3b8c7f87d08c26b1ee Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 4 May 2020 22:08:55 +0800 Subject: nand: Update SPL MXS NAND mini driver Update the mini driver to add support for getting ecc info from ONFI and support read image data from page unaligned NAND address. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- drivers/mtd/nand/raw/mxs_nand_spl.c | 41 ++++++++++++++++++++++++++++++------- 1 file changed, 34 insertions(+), 7 deletions(-) (limited to 'drivers/mtd') diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c index a653dfa5ed..ae50cc37b5 100644 --- a/drivers/mtd/nand/raw/mxs_nand_spl.c +++ b/drivers/mtd/nand/raw/mxs_nand_spl.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2014 Gateworks Corporation + * Copyright 2019 NXP * Author: Tim Harvey */ #include @@ -38,6 +39,12 @@ static void mxs_nand_command(struct mtd_info *mtd, unsigned int command, if (command == NAND_CMD_READ0) { chip->cmd_ctrl(mtd, NAND_CMD_READSTART, NAND_CLE); chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0); + } else if (command == NAND_CMD_RNDOUT) { + /* No ready / busy check necessary */ + chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, + NAND_NCE | NAND_CLE); + chip->cmd_ctrl(mtd, NAND_CMD_NONE, + NAND_NCE); } /* wait for nand ready */ @@ -212,23 +219,39 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf) unsigned int page; unsigned int nand_page_per_block; unsigned int sz = 0; + u8 *page_buf = NULL; + u32 page_off; chip = mtd_to_nand(mtd); if (!chip->numchips) return -ENODEV; + + page_buf = malloc(mtd->writesize); + if (!page_buf) + return -ENOMEM; + page = offs >> chip->page_shift; + page_off = offs & (mtd->writesize - 1); nand_page_per_block = mtd->erasesize / mtd->writesize; - debug("%s offset:0x%08x len:%d page:%d\n", __func__, offs, size, page); + debug("%s offset:0x%08x len:%d page:%x\n", __func__, offs, size, page); - size = roundup(size, mtd->writesize); - while (sz < size) { - if (mxs_read_page_ecc(mtd, buf, page) < 0) + while (size) { + if (mxs_read_page_ecc(mtd, page_buf, page) < 0) return -1; - sz += mtd->writesize; + + if (size > (mtd->writesize - page_off)) + sz = (mtd->writesize - page_off); + else + sz = size; + + memcpy(buf, page_buf + page_off, sz); + offs += mtd->writesize; page++; - buf += mtd->writesize; + buf += (mtd->writesize - page_off); + page_off = 0; + size -= sz; /* * Check if we have crossed a block boundary, and if so @@ -242,12 +265,16 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf) while (is_badblock(mtd, offs, 1)) { page = page + nand_page_per_block; /* Check i we've reached the end of flash. */ - if (page >= mtd->size >> chip->page_shift) + if (page >= mtd->size >> chip->page_shift) { + free(page_buf); return -ENOMEM; + } } } } + free(page_buf); + return 0; } -- cgit From e551ee2deac2f63bc5f84ea0dc3ad3a3b74a107f Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 4 May 2020 22:08:56 +0800 Subject: mxs_nand: Update compatible string for i.MX6SX The iMX6SX uses compatible string "fsl,imx6sx-gpmi-nand" for gpmi node in DTS, so update the driver for the string Signed-off-by: Ye Li Signed-off-by: Peng Fan --- drivers/mtd/nand/raw/mxs_nand_dt.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers/mtd') diff --git a/drivers/mtd/nand/raw/mxs_nand_dt.c b/drivers/mtd/nand/raw/mxs_nand_dt.c index 7a32b284f7..7efc9684db 100644 --- a/drivers/mtd/nand/raw/mxs_nand_dt.c +++ b/drivers/mtd/nand/raw/mxs_nand_dt.c @@ -25,6 +25,10 @@ static const struct mxs_nand_dt_data mxs_nand_imx6q_data = { .max_ecc_strength_supported = 40, }; +static const struct mxs_nand_dt_data mxs_nand_imx6sx_data = { + .max_ecc_strength_supported = 62, +}; + static const struct mxs_nand_dt_data mxs_nand_imx7d_data = { .max_ecc_strength_supported = 62, }; @@ -34,6 +38,10 @@ static const struct udevice_id mxs_nand_dt_ids[] = { .compatible = "fsl,imx6q-gpmi-nand", .data = (unsigned long)&mxs_nand_imx6q_data, }, + { + .compatible = "fsl,imx6sx-gpmi-nand", + .data = (unsigned long)&mxs_nand_imx6sx_data, + }, { .compatible = "fsl,imx7d-gpmi-nand", .data = (unsigned long)&mxs_nand_imx7d_data, -- cgit From 9fdb5f0a0c3af60375831eeb1988c6934698ad22 Mon Sep 17 00:00:00 2001 From: Han Xu Date: Mon, 4 May 2020 22:08:57 +0800 Subject: mtd: nand: mxs_nand: add i.MX6QP compatible string add the dedicate compatible string for i.MX6QP Signed-off-by: Han Xu Signed-off-by: Peng Fan --- drivers/mtd/nand/raw/mxs_nand_dt.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/mtd') diff --git a/drivers/mtd/nand/raw/mxs_nand_dt.c b/drivers/mtd/nand/raw/mxs_nand_dt.c index 7efc9684db..bd429e0d62 100644 --- a/drivers/mtd/nand/raw/mxs_nand_dt.c +++ b/drivers/mtd/nand/raw/mxs_nand_dt.c @@ -38,6 +38,10 @@ static const struct udevice_id mxs_nand_dt_ids[] = { .compatible = "fsl,imx6q-gpmi-nand", .data = (unsigned long)&mxs_nand_imx6q_data, }, + { + .compatible = "fsl,imx6qp-gpmi-nand", + .data = (unsigned long)&mxs_nand_imx6q_data, + }, { .compatible = "fsl,imx6sx-gpmi-nand", .data = (unsigned long)&mxs_nand_imx6sx_data, -- cgit From 17282f45abba6f10842adafdd47c0f24cae6b0ef Mon Sep 17 00:00:00 2001 From: Han Xu Date: Mon, 4 May 2020 22:08:58 +0800 Subject: mtd: mxs_nand: fix the gf_13/14 definition issue gf_13/14 mask was not set correctly in register definition. Signed-off-by: Han Xu Signed-off-by: Peng Fan --- drivers/mtd/nand/raw/mxs_nand.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/mtd') diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index facedf92c5..1b66636a4f 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -1474,6 +1474,8 @@ void mxs_nand_get_layout(struct mtd_info *mtd, struct mxs_nand_layout *l) BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET); l->eccn = (tmp & BCH_FLASHLAYOUT1_ECCN_MASK) >> BCH_FLASHLAYOUT1_ECCN_OFFSET; + l->gf_len = (tmp & BCH_FLASHLAYOUT1_GF13_0_GF14_1_MASK) >> + BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET; } /* -- cgit From f290fe0a4291a6251358aaca7a3f25964f0e12da Mon Sep 17 00:00:00 2001 From: Alice Guo Date: Mon, 4 May 2020 22:08:59 +0800 Subject: nand: mxs_nand: make imx8mm can use hardware BCH and randomizer imx8mm needs to BCH encode and set NAND page number needed to be randomized modify conditional compilation Use CONFIG_IMX8M, so it apply to imx8mq/mm/mn Signed-off-by: Alice Guo Signed-off-by: Peng Fan --- drivers/mtd/nand/raw/mxs_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/mtd') diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index 1b66636a4f..3bf5ab2d8c 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -859,7 +859,7 @@ static int mxs_nand_ecc_write_page(struct mtd_info *mtd, d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf; d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf; - if (is_mx7() && nand_info->en_randomizer) { + if ((is_mx7() || is_imx8m()) && nand_info->en_randomizer) { d->cmd.pio_words[2] |= GPMI_ECCCTRL_RANDOMIZER_ENABLE | GPMI_ECCCTRL_RANDOMIZER_TYPE2; /* -- cgit From 39320e7256412ed4b6eee9fc09f7d30f0e4ddee4 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 4 May 2020 22:09:00 +0800 Subject: mtd: nand: support GPMI NAND driver for i.MX8 enable the GPMI NAND driver for i.MX8, i.MX8 use similar controller as i.MX8M - register definition for i.mx8 - DMA structure must be 32bit address Signed-off-by: Peng Fan --- drivers/mtd/nand/raw/Kconfig | 6 +++--- drivers/mtd/nand/raw/mxs_nand.c | 15 ++++++++------- drivers/mtd/nand/raw/mxs_nand_dt.c | 8 ++++++++ 3 files changed, 19 insertions(+), 10 deletions(-) (limited to 'drivers/mtd') diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index c46fec3d32..c4d9d31388 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -259,12 +259,12 @@ config NAND_MXC config NAND_MXS bool "MXS NAND support" - depends on MX23 || MX28 || MX6 || MX7 || IMX8M + depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M select SYS_NAND_SELF_INIT imply CMD_NAND select APBH_DMA - select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8M - select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8M + select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M + select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M help This enables NAND driver for the NAND flash controller on the MXS processors. diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index 3bf5ab2d8c..b6e65c616d 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -31,7 +31,8 @@ #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4 -#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M)) +#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || \ + defined(CONFIG_IMX8M) #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2 #else #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0 @@ -55,21 +56,21 @@ struct nand_ecclayout fake_ecc_layout; #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) static void mxs_nand_flush_data_buf(struct mxs_nand_info *info) { - uint32_t addr = (uint32_t)info->data_buf; + uint32_t addr = (uintptr_t)info->data_buf; flush_dcache_range(addr, addr + info->data_buf_size); } static void mxs_nand_inval_data_buf(struct mxs_nand_info *info) { - uint32_t addr = (uint32_t)info->data_buf; + uint32_t addr = (uintptr_t)info->data_buf; invalidate_dcache_range(addr, addr + info->data_buf_size); } static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) { - uint32_t addr = (uint32_t)info->cmd_buf; + uint32_t addr = (uintptr_t)info->cmd_buf; flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE); } @@ -773,7 +774,7 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, if (status[i] == 0xff) { if (is_mx6dqp() || is_mx7() || - is_mx6ul() || is_imx8m()) + is_mx6ul() || is_imx8() || is_imx8m()) if (readl(&bch_regs->hw_bch_debug1)) flag = 1; continue; @@ -1172,7 +1173,7 @@ int mxs_nand_setup_ecc(struct mtd_info *mtd) /* Set erase threshold to ecc strength for mx6ul, mx6qp and mx7 */ if (is_mx6dqp() || is_mx7() || - is_mx6ul() || is_imx8m()) + is_mx6ul() || is_imx8() || is_imx8m()) writel(BCH_MODE_ERASE_THRESHOLD(geo->ecc_strength), &bch_regs->hw_bch_mode); @@ -1311,7 +1312,7 @@ int mxs_nand_init_spl(struct nand_chip *nand) nand_info->gpmi_regs = (struct mxs_gpmi_regs *)MXS_GPMI_BASE; nand_info->bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE; - if (is_mx6sx() || is_mx7() || is_imx8m()) + if (is_mx6sx() || is_mx7() || is_imx8() || is_imx8m()) nand_info->max_ecc_strength_supported = 62; else nand_info->max_ecc_strength_supported = 40; diff --git a/drivers/mtd/nand/raw/mxs_nand_dt.c b/drivers/mtd/nand/raw/mxs_nand_dt.c index bd429e0d62..c4dc0bb1dd 100644 --- a/drivers/mtd/nand/raw/mxs_nand_dt.c +++ b/drivers/mtd/nand/raw/mxs_nand_dt.c @@ -33,6 +33,10 @@ static const struct mxs_nand_dt_data mxs_nand_imx7d_data = { .max_ecc_strength_supported = 62, }; +static const struct mxs_nand_dt_data mxs_nand_imx8qxp_data = { + .max_ecc_strength_supported = 62, +}; + static const struct udevice_id mxs_nand_dt_ids[] = { { .compatible = "fsl,imx6q-gpmi-nand", @@ -50,6 +54,10 @@ static const struct udevice_id mxs_nand_dt_ids[] = { .compatible = "fsl,imx7d-gpmi-nand", .data = (unsigned long)&mxs_nand_imx7d_data, }, + { + .compatible = "fsl,imx8qxp-gpmi-nand", + .data = (unsigned long)&mxs_nand_imx8qxp_data, + }, { /* sentinel */ } }; -- cgit From a59691280dacae478183c95a93c5f00f4717d49c Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 4 May 2020 22:09:01 +0800 Subject: MXS_NAND: Add clock support for iMX8 Since iMX8 has enabled clock uclass, we can parse the clocks from DTB and enable them in GPMI driver. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- drivers/mtd/nand/raw/mxs_nand_dt.c | 69 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) (limited to 'drivers/mtd') diff --git a/drivers/mtd/nand/raw/mxs_nand_dt.c b/drivers/mtd/nand/raw/mxs_nand_dt.c index c4dc0bb1dd..43dbe9e66e 100644 --- a/drivers/mtd/nand/raw/mxs_nand_dt.c +++ b/drivers/mtd/nand/raw/mxs_nand_dt.c @@ -2,6 +2,8 @@ * NXP GPMI NAND flash driver (DT initialization) * * Copyright (C) 2018 Toradex + * Copyright 2019 NXP + * * Authors: * Stefan Agner * @@ -14,6 +16,7 @@ #include #include #include +#include #include @@ -91,6 +94,72 @@ static int mxs_nand_dt_probe(struct udevice *dev) info->legacy_bch_geometry = dev_read_bool(dev, "fsl,legacy-bch-geometry"); + if (IS_ENABLED(CONFIG_CLK) && IS_ENABLED(CONFIG_IMX8)) { + /* Assigned clock already set clock */ + struct clk gpmi_clk; + + ret = clk_get_by_name(dev, "gpmi_io", &gpmi_clk); + if (ret < 0) { + debug("Can't get gpmi io clk: %d\n", ret); + return ret; + } + + ret = clk_enable(&gpmi_clk); + if (ret < 0) { + debug("Can't enable gpmi io clk: %d\n", ret); + return ret; + } + + ret = clk_get_by_name(dev, "gpmi_apb", &gpmi_clk); + if (ret < 0) { + debug("Can't get gpmi_apb clk: %d\n", ret); + return ret; + } + + ret = clk_enable(&gpmi_clk); + if (ret < 0) { + debug("Can't enable gpmi_apb clk: %d\n", ret); + return ret; + } + + ret = clk_get_by_name(dev, "gpmi_bch", &gpmi_clk); + if (ret < 0) { + debug("Can't get gpmi_bch clk: %d\n", ret); + return ret; + } + + ret = clk_enable(&gpmi_clk); + if (ret < 0) { + debug("Can't enable gpmi_bch clk: %d\n", ret); + return ret; + } + + ret = clk_get_by_name(dev, "gpmi_apb_bch", &gpmi_clk); + if (ret < 0) { + debug("Can't get gpmi_apb_bch clk: %d\n", ret); + return ret; + } + + ret = clk_enable(&gpmi_clk); + if (ret < 0) { + debug("Can't enable gpmi_apb_bch clk: %d\n", ret); + return ret; + } + + /* this clock is used for apbh_dma, since the apbh dma does not support DM, + * we optionally enable it here + */ + ret = clk_get_by_name(dev, "gpmi_apbh_dma", &gpmi_clk); + if (ret < 0) { + debug("Can't get gpmi_apbh_dma clk: %d\n", ret); + } else { + ret = clk_enable(&gpmi_clk); + if (ret < 0) { + debug("Can't enable gpmi_apbh_dma clk: %d\n", ret); + } + } + } + return mxs_nand_init_ctrl(info); } -- cgit From f7bb012ab7e19d3ede6c0e9a39edd6a37bd598ff Mon Sep 17 00:00:00 2001 From: Han Xu Date: Mon, 4 May 2020 22:09:02 +0800 Subject: mxs_nand: don't check zero count when ECC reading with randomizer When enabled randomizer during ECC reading, the controller reported it's erased page. Checking zero count will cause data get modified to all 0xFF. Stop checking during randomizer to workaround this issue. Signed-off-by: Han Xu Signed-off-by: Peng Fan --- drivers/mtd/nand/raw/mxs_nand.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/mtd') diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index b6e65c616d..3fd21e51f2 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -773,8 +773,9 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, continue; if (status[i] == 0xff) { - if (is_mx6dqp() || is_mx7() || - is_mx6ul() || is_imx8() || is_imx8m()) + if (!nand_info->en_randomizer && + (is_mx6dqp() || is_mx7() || is_mx6ul() || + is_imx8() || is_imx8m())) if (readl(&bch_regs->hw_bch_debug1)) flag = 1; continue; -- cgit From fe04bcd7e86ba2b9ccbcf83b5afc278e69115756 Mon Sep 17 00:00:00 2001 From: Alice Guo Date: Mon, 4 May 2020 22:09:03 +0800 Subject: nand: enable the Randomizer module for i.mx7 and i.mx8 To enable the Randomizer module, set GPMI_ECCCTRL[RANDOMIZER_ENABLE] to 1, then set GPMI_ECCCOUNT[RANDOMIZER_PAGE] to select randomizer page number needed to be randomized. Signed-off-by: Alice Guo Signed-off-by: Peng Fan --- drivers/mtd/nand/raw/mxs_nand.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'drivers/mtd') diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index 3fd21e51f2..c3191feca8 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -710,6 +710,12 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf; d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf; + if ((is_mx7() || is_imx8m()) && nand_info->en_randomizer) { + d->cmd.pio_words[2] |= GPMI_ECCCTRL_RANDOMIZER_ENABLE | + GPMI_ECCCTRL_RANDOMIZER_TYPE2; + d->cmd.pio_words[3] |= (page % 256) << 16; + } + mxs_dma_desc_append(channel, d); /* Compile the DMA descriptor - disable the BCH block. */ @@ -871,7 +877,7 @@ static int mxs_nand_ecc_write_page(struct mtd_info *mtd, * The value is between 0-255. For additional details * check 9.6.6.4 of i.MX7D Applications Processor reference */ - d->cmd.pio_words[3] |= (page % 255) << 16; + d->cmd.pio_words[3] |= (page % 256) << 16; } mxs_dma_desc_append(channel, d); -- cgit From bf9382addf94c9b90033a1eac5522afae9b7a0d7 Mon Sep 17 00:00:00 2001 From: Han Xu Date: Wed, 6 May 2020 20:59:19 +0800 Subject: mtd: nand: raw: mxs_nand changes for nandbcb Add more BCH setting mode and remove the unnecessary platform constrain Signed-off-by: Han Xu Signed-off-by: Peng Fan --- drivers/mtd/nand/raw/mxs_nand.c | 43 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 40 insertions(+), 3 deletions(-) (limited to 'drivers/mtd') diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index c3191feca8..e3516cd141 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -710,7 +710,7 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf; d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf; - if ((is_mx7() || is_imx8m()) && nand_info->en_randomizer) { + if (nand_info->en_randomizer) { d->cmd.pio_words[2] |= GPMI_ECCCTRL_RANDOMIZER_ENABLE | GPMI_ECCCTRL_RANDOMIZER_TYPE2; d->cmd.pio_words[3] |= (page % 256) << 16; @@ -867,7 +867,7 @@ static int mxs_nand_ecc_write_page(struct mtd_info *mtd, d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf; d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf; - if ((is_mx7() || is_imx8m()) && nand_info->en_randomizer) { + if (nand_info->en_randomizer) { d->cmd.pio_words[2] |= GPMI_ECCCTRL_RANDOMIZER_ENABLE | GPMI_ECCCTRL_RANDOMIZER_TYPE2; /* @@ -1489,7 +1489,7 @@ void mxs_nand_get_layout(struct mtd_info *mtd, struct mxs_nand_layout *l) /* * Set BCH to specific layout used by ROM bootloader to read FCB. */ -void mxs_nand_mode_fcb(struct mtd_info *mtd) +void mxs_nand_mode_fcb_62bit(struct mtd_info *mtd) { u32 tmp; struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE; @@ -1522,6 +1522,43 @@ void mxs_nand_mode_fcb(struct mtd_info *mtd) writel(tmp, &bch_regs->hw_bch_flash0layout1); } +/* + * Set BCH to specific layout used by ROM bootloader to read FCB. + */ +void mxs_nand_mode_fcb_40bit(struct mtd_info *mtd) +{ + u32 tmp; + struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE; + struct nand_chip *nand = mtd_to_nand(mtd); + struct mxs_nand_info *nand_info = nand_get_controller_data(nand); + + /* no randomizer in this setting*/ + nand_info->en_randomizer = 0; + + mtd->writesize = 1024; + mtd->oobsize = 1576 - 1024; + + /* 8 ecc_chunks_*/ + tmp = 7 << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET; + /* 32 bytes for metadata */ + tmp |= 32 << BCH_FLASHLAYOUT0_META_SIZE_OFFSET; + /* using ECC40 level to be performed */ + tmp |= 0x14 << BCH_FLASHLAYOUT0_ECC0_OFFSET; + /* 0x20 * 4 bytes of the data0 block */ + tmp |= 0x20 << BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET; + tmp |= 0 << BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET; + writel(tmp, &bch_regs->hw_bch_flash0layout0); + + /* 1024 for data + 552 for OOB */ + tmp = 1576 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET; + /* using ECC40 level to be performed */ + tmp |= 0x14 << BCH_FLASHLAYOUT1_ECCN_OFFSET; + /* 0x20 * 4 bytes of the data0 block */ + tmp |= 0x20 << BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET; + tmp |= 0 << BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET; + writel(tmp, &bch_regs->hw_bch_flash0layout1); +} + /* * Restore BCH to normal settings. */ -- cgit