From 69ffb5577a0fa4d47e34a7684861d88e556f1d48 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 9 Mar 2020 14:59:22 +0100 Subject: clk: stm32mp1: correct CKSELR masks Correct three masks used to access on the RCC register RCC_QSPICKSELR, RCC_FMCCKSELR and RCC_ADCCKSELR: only 3 bits. Signed-off-by: Patrick Delaunay Acked-by: Patrice Chotard --- drivers/clk/clk_stm32mp1.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index fd8c821e48..42f9ef4e46 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -621,13 +621,13 @@ static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7, sdmmc3_parents), STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents), - STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents), - STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents), + STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0x3, qspi_parents), + STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0x3, fmc_parents), STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents), STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents), STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents), STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents), - STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents), + STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x3, adc_parents), STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents), STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT, (RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT), -- cgit From 0c90e0cf63531bfdfb09a54acbd28c53d4c261ea Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 9 Mar 2020 14:59:23 +0100 Subject: clk: stm32mp1: add SPI5_K support Add clock support for SPI5, as this instance is available on extension connector of ST board. Signed-off-by: Patrick Delaunay Acked-by: Patrice Chotard --- drivers/clk/clk_stm32mp1.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 42f9ef4e46..52bd8e96f3 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -95,6 +95,7 @@ DECLARE_GLOBAL_DATA_PTR; #define RCC_I2C12CKSELR 0x8C0 #define RCC_I2C35CKSELR 0x8C4 #define RCC_SPI2S1CKSELR 0x8D8 +#define RCC_SPI45CKSELR 0x8E0 #define RCC_UART6CKSELR 0x8E4 #define RCC_UART24CKSELR 0x8E8 #define RCC_UART35CKSELR 0x8EC @@ -304,6 +305,7 @@ enum stm32mp1_parent_sel { _DSI_SEL, _ADC12_SEL, _SPI1_SEL, + _SPI45_SEL, _RTC_SEL, _PARENT_SEL_NB, _UNKNOWN_SEL = 0xff, @@ -527,6 +529,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 8, SPI1_K, _SPI1_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 10, SPI5_K, _SPI45_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3), @@ -603,6 +606,8 @@ static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P}; static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q}; static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER, _PLL3_R}; +static const u8 spi45_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, + _HSE_KER}; static const u8 rtc_parents[] = {_UNKNOWN_ID, _LSE, _LSI, _HSE}; static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { @@ -629,6 +634,7 @@ static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents), STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x3, adc_parents), STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents), + STM32MP1_CLK_PARENT(_SPI45_SEL, RCC_SPI45CKSELR, 0, 0x7, spi45_parents), STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT, (RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT), rtc_parents), @@ -747,6 +753,7 @@ char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = { [_DSI_SEL] = "DSI", [_ADC12_SEL] = "ADC12", [_SPI1_SEL] = "SPI1", + [_SPI45_SEL] = "SPI45", [_RTC_SEL] = "RTC", }; -- cgit From 87a8f9675949da859ed24fe49c3f5250064a13bf Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sat, 15 Feb 2020 21:10:54 +0100 Subject: clk: meson-g12a: missing break Add missing break for CLKID_PCIE_PLL in switch statement. Reported by CppCheck. Cc: Neil Armstrong Fixes: 08e09c263fdf ("clk: meson-g12a: Add PCIE PLL support") Signed-off-by: Heinrich Schuchardt Reviewed-by: Lukasz Majewski Acked-by: Neil Armstrong Signed-off-by: Neil Armstrong --- drivers/clk/meson/g12a.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk') diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 686d94ebfe..cada80e6b5 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -804,6 +804,7 @@ static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id) break; case CLKID_PCIE_PLL: rate = meson_pcie_pll_get_rate(clk); + break; case CLKID_VPU_0: rate = meson_div_get_rate(clk, CLKID_VPU_0_DIV); break; -- cgit From b3d69aa596599c7c940f7ad463c04b693589ff9a Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Thu, 5 Mar 2020 12:12:37 +0100 Subject: clk: meson: reset mmc clock on probe On some SoCs, depending on the boot device, the MMC clock block may be left in a weird state by the ROM code, in which no decent clock may be provided. Reset the related register to make sure a sane MMC clock is ready for the controller. Reviewed-by: Neil Armstrong Tested-by: Anand Moon Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong --- drivers/clk/meson/axg.c | 7 +++++++ drivers/clk/meson/g12a.c | 7 +++++++ drivers/clk/meson/gxbb.c | 7 +++++++ 3 files changed, 21 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 7035b59a13..4b0028d04b 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -291,6 +291,13 @@ static int meson_clk_probe(struct udevice *dev) if (IS_ERR(priv->map)) return PTR_ERR(priv->map); + /* + * Depending on the boot src, the state of the MMC clock might + * be different. Reset it to make sure we won't get stuck + */ + regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0); + regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0); + debug("meson-clk-axg: probed\n"); return 0; diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index cada80e6b5..c1976aa1ef 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -978,6 +978,13 @@ static int meson_clk_probe(struct udevice *dev) if (IS_ERR(priv->map)) return PTR_ERR(priv->map); + /* + * Depending on the boot src, the state of the MMC clock might + * be different. Reset it to make sure we won't get stuck + */ + regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0); + regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0); + debug("meson-clk-g12a: probed\n"); return 0; diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index e781e08d9d..5ef4dd794d 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -887,6 +887,13 @@ static int meson_clk_probe(struct udevice *dev) if (IS_ERR(priv->map)) return PTR_ERR(priv->map); + /* + * Depending on the boot src, the state of the MMC clock might + * be different. Reset it to make sure we won't get stuck + */ + regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0); + regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0); + debug("meson-clk: probed\n"); return 0; -- cgit