From 87e29878caba758ed3e09e9912ac8eb6dfc55f39 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Wed, 4 Nov 2015 15:48:32 -0600 Subject: mpc85xx: Add support for the Varisys Cyrus board This board runs a P5020 or P5040 chip, and utilizes an EEPROM with similar formatting to the Freescale P5020DS. Large amounts of this code were developed by Adrian Cox Signed-off-by: Andy Fleming Reviewed-by: York Sun --- board/varisys/cyrus/Kconfig | 12 +++ board/varisys/cyrus/MAINTAINERS | 7 ++ board/varisys/cyrus/Makefile | 8 ++ board/varisys/cyrus/README | 19 ++++ board/varisys/cyrus/cyrus.c | 116 +++++++++++++++++++++ board/varisys/cyrus/cyrus.h | 11 ++ board/varisys/cyrus/ddr.c | 188 +++++++++++++++++++++++++++++++++++ board/varisys/cyrus/eth.c | 100 +++++++++++++++++++ board/varisys/cyrus/law.c | 27 +++++ board/varisys/cyrus/pbi.cfg | 35 +++++++ board/varisys/cyrus/pci.c | 23 +++++ board/varisys/cyrus/rcw_p5020_v2.cfg | 11 ++ board/varisys/cyrus/rcw_p5040.cfg | 11 ++ board/varisys/cyrus/tlb.c | 106 ++++++++++++++++++++ 14 files changed, 674 insertions(+) create mode 100644 board/varisys/cyrus/Kconfig create mode 100644 board/varisys/cyrus/MAINTAINERS create mode 100644 board/varisys/cyrus/Makefile create mode 100644 board/varisys/cyrus/README create mode 100644 board/varisys/cyrus/cyrus.c create mode 100644 board/varisys/cyrus/cyrus.h create mode 100644 board/varisys/cyrus/ddr.c create mode 100644 board/varisys/cyrus/eth.c create mode 100644 board/varisys/cyrus/law.c create mode 100644 board/varisys/cyrus/pbi.cfg create mode 100644 board/varisys/cyrus/pci.c create mode 100644 board/varisys/cyrus/rcw_p5020_v2.cfg create mode 100644 board/varisys/cyrus/rcw_p5040.cfg create mode 100644 board/varisys/cyrus/tlb.c (limited to 'board/varisys/cyrus') diff --git a/board/varisys/cyrus/Kconfig b/board/varisys/cyrus/Kconfig new file mode 100644 index 0000000000..d9ea7ef89c --- /dev/null +++ b/board/varisys/cyrus/Kconfig @@ -0,0 +1,12 @@ +if TARGET_CYRUS + +config SYS_BOARD + default "cyrus" + +config SYS_VENDOR + default "varisys" + +config SYS_CONFIG_NAME + default "cyrus" + +endif diff --git a/board/varisys/cyrus/MAINTAINERS b/board/varisys/cyrus/MAINTAINERS new file mode 100644 index 0000000000..53b4a886bd --- /dev/null +++ b/board/varisys/cyrus/MAINTAINERS @@ -0,0 +1,7 @@ +Cyrus BOARD +M: Andy Fleming +S: Maintained +F: board/varisys/cyrus/ +F: include/configs/cyrus.h +F: configs/Cyrus_P5020_defconfig +F: configs/Cyrus_P5040_defconfig diff --git a/board/varisys/cyrus/Makefile b/board/varisys/cyrus/Makefile new file mode 100644 index 0000000000..303fc422af --- /dev/null +++ b/board/varisys/cyrus/Makefile @@ -0,0 +1,8 @@ +# + +obj-y += $(BOARD).o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o +obj-y += eth.o +obj-$(CONFIG_PCI) += pci.o diff --git a/board/varisys/cyrus/README b/board/varisys/cyrus/README new file mode 100644 index 0000000000..9595dcb7cc --- /dev/null +++ b/board/varisys/cyrus/README @@ -0,0 +1,19 @@ +Rebuilding u-boot for Cyrus + +The Cyrus defconfigs are Cyrus_P5020_defconfig and Cyrus_P5040_defconfig. + +They currently disable size optimization in order to avoid a relocation +bug in some versions of GCC. As the output size is a constant, the size +optimization is not currently important. + +Cyrus boots off a microSD card in a slot on the motherboard. This requires +that the u-boot is built for the Pre-Boot Loader on the P5020/P5040. +In order to reflash u-boot, you must download u-boot.pbl, then write it +onto the card. To do that from u-boot: + +> tftp 1000000 u-boot.pbl +> mmc write 1000000 8 672 + +If you want to do this via a card reader in linux: + +> dd if=u-boot.pbl of=/dev/sdX bs=512 oseek=8 diff --git a/board/varisys/cyrus/cyrus.c b/board/varisys/cyrus/cyrus.c new file mode 100644 index 0000000000..79c363cf84 --- /dev/null +++ b/board/varisys/cyrus/cyrus.c @@ -0,0 +1,116 @@ +/* + * Based on corenet_ds.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cyrus.h" +#include "../common/eeprom.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define GPIO_OPENDRAIN 0x30000000 +#define GPIO_DIR 0x3c000004 +#define GPIO_INITIAL 0x30000000 +#define GPIO_VGA_SWITCH 0x00001000 + +int checkboard(void) +{ + printf("Board: CYRUS\n"); + + return 0; +} + +int board_early_init_f(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + + /* + * Only use DDR1_MCK0/3 and DDR2_MCK0/3 + * disable DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce + * the noise introduced by these unterminated and unused clock pairs. + */ + setbits_be32(&gur->ddrclkdr, 0x001B001B); + + /* Set GPIO reset lines to open-drain, tristate */ + setbits_be32(&pgpio->gpdat, GPIO_INITIAL); + setbits_be32(&pgpio->gpodr, GPIO_OPENDRAIN); + + /* Set GPIO Direction */ + setbits_be32(&pgpio->gpdir, GPIO_DIR); + + return 0; +} + +int board_early_init_r(void) +{ + fsl_lbc_t *lbc = LBC_BASE_ADDR; + + out_be32(&lbc->lbcr, 0); + /* 1 clock LALE cycle */ + out_be32(&lbc->lcrr, 0x80000000 | CONFIG_SYS_LBC_LCRR); + + set_liodns(); + +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + print_lbc_regs(); + return 0; +} + +int misc_init_r(void) +{ + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + fdt_fixup_dr_usb(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); +#endif + + return 0; +} + +int mac_read_from_eeprom(void) +{ + init_eeprom(CONFIG_SYS_EEPROM_BUS_NUM, + CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN); + + return mac_read_from_eeprom_common(); +} diff --git a/board/varisys/cyrus/cyrus.h b/board/varisys/cyrus/cyrus.h new file mode 100644 index 0000000000..8cd52ba3c5 --- /dev/null +++ b/board/varisys/cyrus/cyrus.h @@ -0,0 +1,11 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CYRUS_H +#define __CYRUS_H + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, bd_t *bd); + +#endif diff --git a/board/varisys/cyrus/ddr.c b/board/varisys/cyrus/ddr.c new file mode 100644 index 0000000000..bb1d29a94c --- /dev/null +++ b/board/varisys/cyrus/ddr.c @@ -0,0 +1,188 @@ +/* + * Based on corenet_ds ddr code + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 clk_adjust; + u32 wrlvl_start; + u32 cpo; + u32 write_data_delay; + u32 force_2t; +}; + +/* + * This table contains all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| clk| wrlvl | cpo |wrdata|2T + * ranks| mhz|adjst| start | |delay | + */ + {4, 850, 4, 6, 0xff, 2, 0}, + {4, 950, 5, 7, 0xff, 2, 0}, + {4, 1050, 5, 8, 0xff, 2, 0}, + {4, 1250, 5, 10, 0xff, 2, 0}, + {4, 1350, 5, 11, 0xff, 2, 0}, + {4, 1666, 5, 12, 0xff, 2, 0}, + {2, 850, 5, 6, 0xff, 2, 0}, + {2, 1050, 5, 7, 0xff, 2, 0}, + {2, 1250, 4, 6, 0xff, 2, 0}, + {2, 1350, 5, 7, 0xff, 2, 0}, + {2, 1666, 5, 8, 0xff, 2, 0}, + {1, 1250, 4, 6, 0xff, 2, 0}, + {1, 1335, 4, 7, 0xff, 2, 0}, + {1, 1666, 4, 8, 0xff, 2, 0}, + {} +}; + +/* + * The two slots have slightly different timing. The center values are good + * for both slots. We use identical speed tables for them. In future use, if + * DIMMs have fewer center values that require two separated tables, copy the + * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start. + */ +static const struct board_specific_parameters *udimms[] = { + udimm0, + udimm0, +}; + +static const struct board_specific_parameters rdimm0[] = { + /* + * memory controller 0 + * num| hi| clk| wrlvl | cpo |wrdata|2T + * ranks| mhz|adjst| start | |delay | + */ + {4, 850, 4, 6, 0xff, 2, 0}, + {4, 950, 5, 7, 0xff, 2, 0}, + {4, 1050, 5, 8, 0xff, 2, 0}, + {4, 1250, 5, 10, 0xff, 2, 0}, + {4, 1350, 5, 11, 0xff, 2, 0}, + {4, 1666, 5, 12, 0xff, 2, 0}, + {2, 850, 4, 6, 0xff, 2, 0}, + {2, 1050, 4, 7, 0xff, 2, 0}, + {2, 1666, 4, 8, 0xff, 2, 0}, + {1, 850, 4, 5, 0xff, 2, 0}, + {1, 950, 4, 7, 0xff, 2, 0}, + {1, 1666, 4, 8, 0xff, 2, 0}, + {} +}; + +/* + * The two slots have slightly different timing. See comments above. + */ +static const struct board_specific_parameters *rdimms[] = { + rdimm0, + rdimm0, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 1) { + printf("Wrong parameter for controller number %d", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + if (popts->registered_dimm_en) + pbsp = rdimms[ctrl_num]; + else + pbsp = udimms[ctrl_num]; + + + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = + pbsp->write_data_delay; + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->twot_en = pbsp->force_2t; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for data rate %lu MT/s!\nTrying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->cpo_override = pbsp_highest->cpo; + popts->write_data_delay = pbsp_highest->write_data_delay; + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->twot_en = pbsp_highest->force_2t; + } else { + panic("DIMM is not supported by this board"); + } +found: + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 60 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN; +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + + puts("Initializing...."); + + if (!fsl_use_spd()) + panic("Cyrus only supports using SPD for DRAM\n"); + + puts("using SPD\n"); + dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + debug(" DDR: "); + return dram_size; +} diff --git a/board/varisys/cyrus/eth.c b/board/varisys/cyrus/eth.c new file mode 100644 index 0000000000..bcadc67794 --- /dev/null +++ b/board/varisys/cyrus/eth.c @@ -0,0 +1,100 @@ +/* + * Author Adrian Cox + * Based somewhat on board/freescale/corenet_ds/eth_hydra.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_FMAN_ENET + +#define FIRST_PORT_ADDR 3 +#define SECOND_PORT_ADDR 7 + +#ifdef CONFIG_PPC_P5040 +#define FIRST_PORT FM1_DTSEC5 +#define SECOND_PORT FM2_DTSEC5 +#else +#define FIRST_PORT FM1_DTSEC4 +#define SECOND_PORT FM1_DTSEC5 +#endif + +#define IS_VALID_PORT(p) ((p) == FIRST_PORT || (p) == SECOND_PORT) + +static void cyrus_phy_tuning(int phy) +{ + /* + * Enable RGMII delay on Tx and Rx for CPU port + */ + printf("Tuning PHY @ %d\n", phy); + + /* sets address 0x104 or reg 260 for writing */ + miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8104); + /* Sets RXC/TXC to +0.96ns and TX_CTL/RX_CTL to -0.84ns */ + miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0xf0f0); + /* sets address 0x105 or reg 261 for writing */ + miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8105); + /* writes to address 0x105 , RXD[3..0] to -0. */ + miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0x0000); + /* sets address 0x106 or reg 261 for writing */ + miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8106); + /* writes to address 0x106 , TXD[3..0] to -0.84ns */ + miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0x0000); + /* force re-negotiation */ + miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0x0, 0x1340); +} +#endif + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct fsl_pq_mdio_info dtsec_mdio_info; + unsigned int i; + + printf("Initializing Fman\n"); + + + /* Register the real 1G MDIO bus */ + dtsec_mdio_info.regs = + (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + fsl_pq_mdio_init(bis, &dtsec_mdio_info); + + + fm_info_set_phy_address(FIRST_PORT, FIRST_PORT_ADDR); + fm_info_set_mdio(FIRST_PORT, + miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); + fm_info_set_phy_address(SECOND_PORT, SECOND_PORT_ADDR); + fm_info_set_mdio(SECOND_PORT, + miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); + + /* Never disable DTSEC1 - it controls MDIO */ + for (i = FM1_DTSEC2; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + if (!IS_VALID_PORT(i)) + fm_disable_port(i); + } + +#ifdef CONFIG_PPC_P5040 + for (i = FM2_DTSEC2; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { + if (!IS_VALID_PORT(i)) + fm_disable_port(i); + } +#endif + + cpu_eth_init(bis); + + cyrus_phy_tuning(FIRST_PORT_ADDR); + cyrus_phy_tuning(SECOND_PORT_ADDR); +#endif + + return pci_eth_init(bis); +} diff --git a/board/varisys/cyrus/law.c b/board/varisys/cyrus/law.c new file mode 100644 index 0000000000..91e1d85246 --- /dev/null +++ b/board/varisys/cyrus/law.c @@ -0,0 +1,27 @@ +/* + * Author: Adrian Cox + * Based on corenet_ds law files. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_LBC0_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_LBC1_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + /* Limit DCSR to 32M to access NPC Trace Buffer */ + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/varisys/cyrus/pbi.cfg b/board/varisys/cyrus/pbi.cfg new file mode 100644 index 0000000000..9b330ddcc4 --- /dev/null +++ b/board/varisys/cyrus/pbi.cfg @@ -0,0 +1,35 @@ +# +# Copyright 2012 Freescale Semiconductor, Inc. +# +# Refer docs/README.pblimage for more details about how-to configure +# and create PBL boot image +# +# SPDX-License-Identifier: GPL-2.0+ +# + +#PBI commands +#Initialize CPC1 as 1MB SRAM +09010000 00200400 +09138000 00000000 +091380c0 00000100 +09010100 00000000 +09010104 fff0000b +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff00000 +09000d08 81000013 +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Initialize eSPI controller, default configuration is slow for eSPI to +#load data, this configuration comes from u-boot eSPI driver. +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +09138000 00000000 +091380c0 00000000 diff --git a/board/varisys/cyrus/pci.c b/board/varisys/cyrus/pci.c new file mode 100644 index 0000000000..4780e8c147 --- /dev/null +++ b/board/varisys/cyrus/pci.c @@ -0,0 +1,23 @@ +/* + * Copyright 2007-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/varisys/cyrus/rcw_p5020_v2.cfg b/board/varisys/cyrus/rcw_p5020_v2.cfg new file mode 100644 index 0000000000..9188080605 --- /dev/null +++ b/board/varisys/cyrus/rcw_p5020_v2.cfg @@ -0,0 +1,11 @@ +# +# Default RCW for Cyrus P5020 +# + +#PBL preamble and RCW header +aa55aa55 010e0100 +#64 bytes RCW data +0c540000 00000000 1e1e0000 00000000 +44808c00 ff002000 68000000 45000000 +00000000 00000000 00000000 0003000f +a0000000 00000000 00000000 00000000 diff --git a/board/varisys/cyrus/rcw_p5040.cfg b/board/varisys/cyrus/rcw_p5040.cfg new file mode 100644 index 0000000000..5284481568 --- /dev/null +++ b/board/varisys/cyrus/rcw_p5040.cfg @@ -0,0 +1,11 @@ +# +# Default RCW for Cyrus P5040 +# + +#PBL preamble and RCW header +aa55aa55 010e0100 +#64 bytes RCW data +90e00000 00000000 acac9800 00440000 +44808c00 ff29a000 68000000 61000000 +00000000 00000000 00000000 0003000f +a0000000 00000000 00000000 00000000 diff --git a/board/varisys/cyrus/tlb.c b/board/varisys/cyrus/tlb.c new file mode 100644 index 0000000000..3fa58644bb --- /dev/null +++ b/board/varisys/cyrus/tlb.c @@ -0,0 +1,106 @@ +/* + * Author: Adrian Cox + * Based on corenet_ds tlb code + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* Local Bus */ + SET_TLB_ENTRY(1, CONFIG_SYS_LBC0_BASE, CONFIG_SYS_LBC0_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_64K, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_LBC1_BASE, CONFIG_SYS_LBC1_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_1M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SW|MAS3_SR, 0, + 0, 11, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_1M, 1), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 13, BOOKE_PAGESZ_4M, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); -- cgit