From 9e9771a6105785189828706418945748d4db89a1 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:11 +0800 Subject: dm: powerpc: T1023/T1024: add i2c DM support This supports i2c DM for SoC T1023/T1024 Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- board/freescale/t102xqds/t102xqds.c | 95 ++++++++++++++++++++++++++++++++++++- board/freescale/t102xqds/t102xqds.h | 3 +- board/freescale/t102xrdb/t102xrdb.c | 71 +++++++++++++++++++++++++-- 3 files changed, 162 insertions(+), 7 deletions(-) (limited to 'board/freescale') diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c index e42337e47a..32b4780376 100644 --- a/board/freescale/t102xqds/t102xqds.c +++ b/board/freescale/t102xqds/t102xqds.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #include @@ -75,11 +76,24 @@ int checkboard(void) return 0; } -int select_i2c_ch_pca9547(u8 ch) +int select_i2c_ch_pca9547(u8 ch, int bus_num) { int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + + ret = dm_i2c_write(dev, 0, &ch, 1); +#else ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -191,6 +205,82 @@ void board_retimer_ds125df111_init(void) { u8 reg; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret, bus_num = 0; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, + 1, &dev); + if (ret) + goto failed; + + /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */ + reg = I2C_MUX_CH7; + dm_i2c_write(dev, 0, ®, 1); + + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC, + 1, &dev); + if (ret) + goto failed; + + reg = I2C_MUX_CH5; + dm_i2c_write(dev, 0, ®, 1); + + /* Access to Control/Shared register */ + ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR, + 1, &dev); + if (ret) + goto failed; + reg = 0x0; + dm_i2c_write(dev, 0xff, ®, 1); + + /* Read device revision and ID */ + dm_i2c_read(dev, 1, ®, 1); + debug("Retimer version id = 0x%x\n", reg); + + /* Enable Broadcast */ + reg = 0x0c; + dm_i2c_write(dev, 0xff, ®, 1); + + /* Reset Channel Registers */ + dm_i2c_read(dev, 0, ®, 1); + reg |= 0x4; + dm_i2c_write(dev, 0, ®, 1); + + /* Enable override divider select and Enable Override Output Mux */ + dm_i2c_read(dev, 9, ®, 1); + reg |= 0x24; + dm_i2c_write(dev, 9, ®, 1); + + /* Select VCO Divider to full rate (000) */ + dm_i2c_read(dev, 0x18, ®, 1); + reg &= 0x8f; + dm_i2c_write(dev, 0x18, ®, 1); + + /* Select active PFD MUX input as re-timed data (001) */ + dm_i2c_read(dev, 0x1e, ®, 1); + reg &= 0x3f; + reg |= 0x20; + dm_i2c_write(dev, 0x1e, ®, 1); + + /* Set data rate as 10.3125 Gbps */ + reg = 0x0; + dm_i2c_write(dev, 0x60, ®, 1); + reg = 0xb2; + dm_i2c_write(dev, 0x61, ®, 1); + reg = 0x90; + dm_i2c_write(dev, 0x62, ®, 1); + reg = 0xb3; + dm_i2c_write(dev, 0x63, ®, 1); + reg = 0xcd; + dm_i2c_write(dev, 0x64, ®, 1); + return; + +failed: + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return; +#else /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */ reg = I2C_MUX_CH7; i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1); @@ -241,6 +331,7 @@ void board_retimer_ds125df111_init(void) i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); reg = 0xcd; i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); +#endif } int board_early_init_f(void) @@ -281,7 +372,7 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); #endif - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); board_mux_lane_to_slot(); board_retimer_ds125df111_init(); diff --git a/board/freescale/t102xqds/t102xqds.h b/board/freescale/t102xqds/t102xqds.h index 15de132598..d327b5edb9 100644 --- a/board/freescale/t102xqds/t102xqds.h +++ b/board/freescale/t102xqds/t102xqds.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #ifndef __T102x_QDS_H__ @@ -8,6 +9,6 @@ void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, bd_t *bd); -int select_i2c_ch_pca9547(u8 ch); +int select_i2c_ch_pca9547(u8 ch, int bus_num); #endif diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index eee09a5701..a34490c8bd 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #include @@ -250,8 +251,69 @@ static u32 t1023rdb_ctrl(u32 ctrl_type) { ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 val, orig_bus = i2c_get_bus_num(); + u32 val; u8 tmp; + int bus_num = I2C_PCA6408_BUS_NUM; + +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA6408_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + switch (ctrl_type) { + case GPIO1_SD_SEL: + val = in_be32(&pgpio->gpdat); + val |= GPIO1_SD_SEL; + out_be32(&pgpio->gpdat, val); + setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL); + break; + case GPIO1_EMMC_SEL: + val = in_be32(&pgpio->gpdat); + val &= ~GPIO1_SD_SEL; + out_be32(&pgpio->gpdat, val); + setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL); + break; + case GPIO3_GET_VERSION: + pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + + GPIO3_OFFSET); + val = in_be32(&pgpio->gpdat); + val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3; + if (val == 0x3) /* GPIO3_4/5 not used on RevB */ + val = 0; + return val; + case I2C_GET_BANK: + dm_i2c_read(dev, 0, &tmp, 1); + tmp &= 0x7; + tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2); + return tmp; + case I2C_SET_BANK0: + tmp = 0x0; + dm_i2c_write(dev, 1, &tmp, 1); + tmp = 0xf8; + dm_i2c_write(dev, 3, &tmp, 1); + /* asserting HRESET_REQ */ + out_be32(&gur->rstcr, 0x2); + break; + case I2C_SET_BANK4: + tmp = 0x1; + dm_i2c_write(dev, 1, &tmp, 1); + tmp = 0xf8; + dm_i2c_write(dev, 3, &tmp, 1); + out_be32(&gur->rstcr, 0x2); + break; + default: + break; + } +#else + u32 orig_bus; + + orig_bus = i2c_get_bus_num(); switch (ctrl_type) { case GPIO1_SD_SEL: @@ -275,14 +337,14 @@ static u32 t1023rdb_ctrl(u32 ctrl_type) val = 0; return val; case I2C_GET_BANK: - i2c_set_bus_num(I2C_PCA6408_BUS_NUM); + i2c_set_bus_num(bus_num); i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1); tmp &= 0x7; tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2); i2c_set_bus_num(orig_bus); return tmp; case I2C_SET_BANK0: - i2c_set_bus_num(I2C_PCA6408_BUS_NUM); + i2c_set_bus_num(bus_num); tmp = 0x0; i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1); tmp = 0xf8; @@ -291,7 +353,7 @@ static u32 t1023rdb_ctrl(u32 ctrl_type) out_be32(&gur->rstcr, 0x2); break; case I2C_SET_BANK4: - i2c_set_bus_num(I2C_PCA6408_BUS_NUM); + i2c_set_bus_num(bus_num); tmp = 0x1; i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1); tmp = 0xf8; @@ -301,6 +363,7 @@ static u32 t1023rdb_ctrl(u32 ctrl_type) default: break; } +#endif return 0; } -- cgit