From 9c1563e3fd24ca7161c089dfd999d031f95094de Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 15 May 2019 09:56:59 +0000 Subject: mx7ulp: Select the SCG1 APLL PFD as a system clock source Due to the APLL out glitch issue, the APLLCFG PLLS bit must be set to select SCG1 APLL PFD for generating system clock to align with the design. Signed-off-by: Ye Li Acked-by: Peng Fan --- board/freescale/mx7ulp_evk/plugin.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board/freescale/mx7ulp_evk/plugin.S') diff --git a/board/freescale/mx7ulp_evk/plugin.S b/board/freescale/mx7ulp_evk/plugin.S index ccd2fc03a4..55dfecc751 100644 --- a/board/freescale/mx7ulp_evk/plugin.S +++ b/board/freescale/mx7ulp_evk/plugin.S @@ -18,7 +18,7 @@ ldr r3, =0x80808080 str r3, [r2, #0x50c] - ldr r3, =0x00160000 + ldr r3, =0x00160002 str r3, [r2, #0x508] ldr r3, =0x00000002 str r3, [r2, #0x510] -- cgit