From 64a0a4995e79ef9813bb51d5f1ff35ae5dabfc7e Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sat, 24 Apr 2010 00:05:37 +1000 Subject: x86: Fix MMCR Access Change sc520 MMCR Access to use memory accessor functions Signed-off-by: Graeme Russ --- board/eNET/eNET.c | 86 +++++++++++++++++++++++++++---------------------------- 1 file changed, 43 insertions(+), 43 deletions(-) (limited to 'board/eNET') diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index 6d0b15a0fa..f794bebc25 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -46,7 +46,7 @@ unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN; void init_sc520_enet (void) { /* Set CPU Speed to 100MHz */ - sc520_mmcr->cpuctl = 0x01; + writeb(0x01, &sc520_mmcr->cpuctl); /* wait at least one millisecond */ asm("movl $0x2000,%%ecx\n" @@ -55,7 +55,7 @@ void init_sc520_enet (void) "loop 0b\n": : : "ecx"); /* turn on the SDRAM write buffer */ - sc520_mmcr->dbctl = 0x11; + writeb(0x11, &sc520_mmcr->dbctl); /* turn on the cache and disable write through */ asm("movl %%cr0, %%eax\n" @@ -70,51 +70,51 @@ int board_early_init_f(void) { init_sc520_enet(); - sc520_mmcr->gpcsrt = 0x01; /* GP Chip Select Recovery Time */ - sc520_mmcr->gpcspw = 0x07; /* GP Chip Select Pulse Width */ - sc520_mmcr->gpcsoff = 0x00; /* GP Chip Select Offset */ - sc520_mmcr->gprdw = 0x05; /* GP Read pulse width */ - sc520_mmcr->gprdoff = 0x01; /* GP Read offset */ - sc520_mmcr->gpwrw = 0x05; /* GP Write pulse width */ - sc520_mmcr->gpwroff = 0x01; /* GP Write offset */ - - sc520_mmcr->piodata15_0 = 0x0630; /* PIO15_PIO0 Data */ - sc520_mmcr->piodata31_16 = 0x2000; /* PIO31_PIO16 Data */ - sc520_mmcr->piodir31_16 = 0x2000; /* GPIO Direction */ - sc520_mmcr->piodir15_0 = 0x87b5; /* GPIO Direction */ - sc520_mmcr->piopfs31_16 = 0x0dfe; /* GPIO pin function 31-16 reg */ - sc520_mmcr->piopfs15_0 = 0x200a; /* GPIO pin function 15-0 reg */ - sc520_mmcr->cspfs = 0x00f8; /* Chip Select Pin Function Select */ - - sc520_mmcr->par[2] = 0x200713f8; /* Uart A (GPCS0, 0x013f8, 8 Bytes) */ - sc520_mmcr->par[3] = 0x2c0712f8; /* Uart B (GPCS3, 0x012f8, 8 Bytes) */ - sc520_mmcr->par[4] = 0x300711f8; /* Uart C (GPCS4, 0x011f8, 8 Bytes) */ - sc520_mmcr->par[5] = 0x340710f8; /* Uart D (GPCS5, 0x010f8, 8 Bytes) */ - sc520_mmcr->par[6] = 0xe3ffc000; /* SDRAM (0x00000000, 128MB) */ - sc520_mmcr->par[7] = 0xaa3fd000; /* StrataFlash (ROMCS1, 0x10000000, 16MB) */ - sc520_mmcr->par[8] = 0xca3fd100; /* StrataFlash (ROMCS2, 0x11000000, 16MB) */ - sc520_mmcr->par[9] = 0x4203d900; /* SRAM (GPCS0, 0x19000000, 1MB) */ - sc520_mmcr->par[10] = 0x4e03d910; /* SRAM (GPCS3, 0x19100000, 1MB) */ - sc520_mmcr->par[11] = 0x50018100; /* DP-RAM (GPCS4, 0x18100000, 4kB) */ - sc520_mmcr->par[12] = 0x54020000; /* CFLASH1 (0x200000000, 4kB) */ - sc520_mmcr->par[13] = 0x5c020001; /* CFLASH2 (0x200010000, 4kB) */ -/* sc520_mmcr->par14 = 0x8bfff800; */ /* BOOTCS at 0x18000000 */ -/* sc520_mmcr->par15 = 0x38201000; */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */ + writeb(0x01, &sc520_mmcr->gpcsrt); /* GP Chip Select Recovery Time */ + writeb(0x07, &sc520_mmcr->gpcspw); /* GP Chip Select Pulse Width */ + writeb(0x00, &sc520_mmcr->gpcsoff); /* GP Chip Select Offset */ + writeb(0x05, &sc520_mmcr->gprdw); /* GP Read pulse width */ + writeb(0x01, &sc520_mmcr->gprdoff); /* GP Read offset */ + writeb(0x05, &sc520_mmcr->gpwrw); /* GP Write pulse width */ + writeb(0x01, &sc520_mmcr->gpwroff); /* GP Write offset */ + + writew(0x0630, &sc520_mmcr->piodata15_0); /* PIO15_PIO0 Data */ + writew(0x2000, &sc520_mmcr->piodata31_16); /* PIO31_PIO16 Data */ + writew(0x2000, &sc520_mmcr->piodir31_16); /* GPIO Direction */ + writew(0x87b5, &sc520_mmcr->piodir15_0); /* GPIO Direction */ + writew(0x0dfe, &sc520_mmcr->piopfs31_16); /* GPIO pin function 31-16 reg */ + writew(0x200a, &sc520_mmcr->piopfs15_0); /* GPIO pin function 15-0 reg */ + writeb(0xf8, &sc520_mmcr->cspfs); /* Chip Select Pin Function Select */ + + writel(0x200713f8, &sc520_mmcr->par[2]); /* Uart A (GPCS0, 0x013f8, 8 Bytes) */ + writel(0x2c0712f8, &sc520_mmcr->par[3]); /* Uart B (GPCS3, 0x012f8, 8 Bytes) */ + writel(0x300711f8, &sc520_mmcr->par[4]); /* Uart C (GPCS4, 0x011f8, 8 Bytes) */ + writel(0x340710f8, &sc520_mmcr->par[5]); /* Uart D (GPCS5, 0x010f8, 8 Bytes) */ + writel(0xe3ffc000, &sc520_mmcr->par[6]); /* SDRAM (0x00000000, 128MB) */ + writel(0xaa3fd000, &sc520_mmcr->par[7]); /* StrataFlash (ROMCS1, 0x10000000, 16MB) */ + writel(0xca3fd100, &sc520_mmcr->par[8]); /* StrataFlash (ROMCS2, 0x11000000, 16MB) */ + writel(0x4203d900, &sc520_mmcr->par[9]); /* SRAM (GPCS0, 0x19000000, 1MB) */ + writel(0x4e03d910, &sc520_mmcr->par[10]); /* SRAM (GPCS3, 0x19100000, 1MB) */ + writel(0x50018100, &sc520_mmcr->par[11]); /* DP-RAM (GPCS4, 0x18100000, 4kB) */ + writel(0x54020000, &sc520_mmcr->par[12]); /* CFLASH1 (0x200000000, 4kB) */ + writel(0x5c020001, &sc520_mmcr->par[13]); /* CFLASH2 (0x200010000, 4kB) */ +/* writel(0x8bfff800, &sc520_mmcr->par14); */ /* BOOTCS at 0x18000000 */ +/* writel(0x38201000, &sc520_mmcr->par15); */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */ /* Disable Watchdog */ - sc520_mmcr->wdtmrctl = 0x3333; - sc520_mmcr->wdtmrctl = 0xcccc; - sc520_mmcr->wdtmrctl = 0x0000; + writew(0x3333, &sc520_mmcr->wdtmrctl); + writew(0xcccc, &sc520_mmcr->wdtmrctl); + writew(0x0000, &sc520_mmcr->wdtmrctl); /* Chip Select Configuration */ - sc520_mmcr->bootcsctl = 0x0033; - sc520_mmcr->romcs1ctl = 0x0615; - sc520_mmcr->romcs2ctl = 0x0615; - - sc520_mmcr->adddecctl = 0x02; - sc520_mmcr->uart1ctl = 0x07; - sc520_mmcr->sysarbctl = 0x06; - sc520_mmcr->sysarbmenb = 0x0003; + writew(0x0033, &sc520_mmcr->bootcsctl); + writew(0x0615, &sc520_mmcr->romcs1ctl); + writew(0x0615, &sc520_mmcr->romcs2ctl); + + writeb(0x02, &sc520_mmcr->adddecctl); + writeb(0x07, &sc520_mmcr->uart1ctl); + writeb(0x06, &sc520_mmcr->sysarbctl); + writew(0x0003, &sc520_mmcr->sysarbmenb); return 0; } -- cgit From 077e1958ca4afe12d88043b123ded058c51b89f7 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sat, 24 Apr 2010 00:05:42 +1000 Subject: x86: Add RAM bootstrap functionality Add a parameter to the 32-bit entry to indicate if entry is from Real Mode or not. If entry is from Real Mode, execute the destructive 'sizer' routine to determine memory size as we are booting cold and running in Flash. If not entering from Real Mode, we are executing a U-Boot image from RAM and therefore the memory size is already known (and running 'sizer' will destroy the running image) There are now two 32-bit entry points. The first is the 'in RAM' entry point which exists at the start of the U-Boot binary image. As such, you can load u-boot.bin in RAM and jump directly to the load address without needing to calculate any offsets. The second entry point is used by the real-to-protected mode switch This patch also changes TEXT_BASE to 0x6000000 (in RAM). You can load the resulting image at 0x6000000 and simple go 0x6000000 from the u-boot prompt Hopefully a later patch will completely elliminate any dependency on TEXT_BASE like a relocatable linux kernel (perfect world) Signed-off-by: Graeme Russ --- board/eNET/config.mk | 2 +- board/eNET/u-boot.lds | 9 ++++----- 2 files changed, 5 insertions(+), 6 deletions(-) (limited to 'board/eNET') diff --git a/board/eNET/config.mk b/board/eNET/config.mk index dcde7fcedb..63a58fdc50 100644 --- a/board/eNET/config.mk +++ b/board/eNET/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -TEXT_BASE = 0x38040000 +TEXT_BASE = 0x06000000 CFLAGS_common/dlmalloc.o += -Wa,--no-warn -fno-strict-aliasing PLATFORM_RELFLAGS += -fvisibility=hidden PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm diff --git a/board/eNET/u-boot.lds b/board/eNET/u-boot.lds index 0d740215ce..7b0ffaa6cc 100644 --- a/board/eNET/u-boot.lds +++ b/board/eNET/u-boot.lds @@ -27,7 +27,7 @@ ENTRY(_start) SECTIONS { - . = 0x38040000; /* Location of bootcode in flash */ + . = 0x06000000; /* Location of bootcode in flash */ _i386boot_text_start = .; .text : { *(.text); } @@ -97,14 +97,13 @@ SECTIONS * at reset and the code have to fit. * The fff0 offset of resetvec is important, however. */ - . = 0xfffffe00; - .start32 : AT (0x3807fe00) { *(.start32); } + .start32 : AT (0x0603fe00) { *(.start32); } . = 0xf800; - .start16 : AT (0x3807f800) { *(.start16); } + .start16 : AT (0x0603f800) { *(.start16); } . = 0xfff0; - .resetvec : AT (0x3807fff0) { *(.resetvec); } + .resetvec : AT (0x0603fff0) { *(.resetvec); } _i386boot_end = (LOADADDR(.resetvec) + SIZEOF(.resetvec) ); } -- cgit From bf16500f79fdf2653a286b40bb601cb185ac4675 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sat, 24 Apr 2010 00:05:47 +1000 Subject: x86: Use CONFIG_SERIAL_MULTI Signed-off-by: Graeme Russ --- board/eNET/eNET.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'board/eNET') diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index f794bebc25..52ea1407b5 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -111,8 +111,9 @@ int board_early_init_f(void) writew(0x0615, &sc520_mmcr->romcs1ctl); writew(0x0615, &sc520_mmcr->romcs2ctl); - writeb(0x02, &sc520_mmcr->adddecctl); + writeb(0x00, &sc520_mmcr->adddecctl); writeb(0x07, &sc520_mmcr->uart1ctl); + writeb(0x07, &sc520_mmcr->uart2ctl); writeb(0x06, &sc520_mmcr->sysarbctl); writew(0x0003, &sc520_mmcr->sysarbmenb); -- cgit From 21e67e796bb1d59a484dce2b4203d61bf1fd5be8 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sat, 24 Apr 2010 00:05:54 +1000 Subject: sc520: Board Specific PCI Init Signed-off-by: Graeme Russ --- board/eNET/eNET_pci.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'board/eNET') diff --git a/board/eNET/eNET_pci.c b/board/eNET/eNET_pci.c index e80a8feb16..fefb1a4fbe 100644 --- a/board/eNET/eNET_pci.c +++ b/board/eNET/eNET_pci.c @@ -93,3 +93,36 @@ void pci_init_board(void) { pci_sc520_init(&enet_hose); } + +int pci_set_regions(struct pci_controller *hose) +{ + /* System memory space */ + pci_set_region(hose->regions + 0, + SC520_PCI_MEMORY_BUS, + SC520_PCI_MEMORY_PHYS, + SC520_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + + /* ISA/PCI memory space */ + pci_set_region(hose->regions + 1, + SC520_ISA_MEM_BUS, + SC520_ISA_MEM_PHYS, + SC520_ISA_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region(hose->regions + 2, + SC520_PCI_IO_BUS, + SC520_PCI_IO_PHYS, + SC520_PCI_IO_SIZE, + PCI_REGION_IO); + + /* ISA/PCI I/O space */ + pci_set_region(hose->regions + 3, + SC520_ISA_IO_BUS, + SC520_ISA_IO_PHYS, + SC520_ISA_IO_SIZE, + PCI_REGION_IO); + + return 4; +} -- cgit From 8fd805632f95e5e834f312a51aa969bf1d99c41b Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sat, 24 Apr 2010 00:05:55 +1000 Subject: eNET: Add support for onboard RTL8100B (RTL8139) chips Signed-off-by: Graeme Russ --- board/eNET/eNET.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'board/eNET') diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index 52ea1407b5..62f99ce94d 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -24,6 +24,8 @@ #include #include #include +#include +#include #ifdef CONFIG_HW_WATCHDOG #include @@ -173,3 +175,8 @@ ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) } else return 0; } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} -- cgit From 4a4c31ae08d4dcabe348013e135de28b01c29bf0 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sat, 24 Apr 2010 00:05:56 +1000 Subject: eNET: Add PC/AT compatibility setup function The eNET uses the sc520 software timers rather than the PC/AT clones Set all interrupts and timers up to be PC/AT compatible Signed-off-by: Graeme Russ --- board/eNET/eNET.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'board/eNET') diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index 62f99ce94d..ad71f7e5dc 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -180,3 +180,41 @@ int board_eth_init(bd_t *bis) { return pci_eth_init(bis); } + +void setup_pcat_compatibility() +{ + /* disable global interrupt mode */ + writeb(0x40, &sc520_mmcr->picicr); + + /* set all irqs to edge */ + writeb(0x00, &sc520_mmcr->pic_mode[0]); + writeb(0x00, &sc520_mmcr->pic_mode[1]); + writeb(0x00, &sc520_mmcr->pic_mode[2]); + + /* + * active low polarity on PIC interrupt pins, + * active high polarity on all other irq pins + */ + writew(0x0000,&sc520_mmcr->intpinpol); + + /* Set PIT 0 -> IRQ0, RTC -> IRQ8, FP error -> IRQ13 */ + writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]); + writeb(SC520_IRQ8, &sc520_mmcr->rtcmap); + writeb(SC520_IRQ13, &sc520_mmcr->ferrmap); + + /* Disable all other interrupt sources */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[1]); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[0]); /* disable PCI INT A */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[1]); /* disable PCI INT B */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[2]); /* disable PCI INT C */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[3]); /* disable PCI INT D */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->dmabcintmap); /* disable DMA INT */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap); +} -- cgit From 880c59e5add3681bd4dca14d2fd20152bee7ad14 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sat, 24 Apr 2010 00:05:58 +1000 Subject: eNET: Implement eNET Watchdog Signed-off-by: Graeme Russ --- board/eNET/eNET.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ board/eNET/hardware.h | 1 + 2 files changed, 46 insertions(+) (limited to 'board/eNET') diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index ad71f7e5dc..7f0e2577f1 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -45,6 +45,9 @@ DECLARE_GLOBAL_DATA_PTR; unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN; +static void enet_timer_isr(void); +static void enet_toggle_run_led(void); + void init_sc520_enet (void) { /* Set CPU Speed to 100MHz */ @@ -160,6 +163,10 @@ int last_stage_init(void) major = minor = 0; + outb(0x00, LED_LATCH_ADDRESS); + + register_timer_isr (enet_timer_isr); + printf("Serck Controls eNET\n"); return 0; @@ -218,3 +225,41 @@ void setup_pcat_compatibility() writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap); writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap); } + +void enet_timer_isr(void) +{ + static long enet_ticks = 0; + + enet_ticks++; + + /* Toggle Watchdog every 100ms */ + if ((enet_ticks % 100) == 0) + hw_watchdog_reset(); + + /* Toggle Run LED every 500ms */ + if ((enet_ticks % 500) == 0) + enet_toggle_run_led(); +} + +void hw_watchdog_reset(void) +{ + /* Watchdog Reset must be atomic */ + long flag = disable_interrupts(); + + if (sc520_mmcr->piodata15_0 & WATCHDOG_PIO_BIT) + sc520_mmcr->pioclr15_0 = WATCHDOG_PIO_BIT; + else + sc520_mmcr->pioset15_0 = WATCHDOG_PIO_BIT; + + if (flag) + enable_interrupts(); +} + +void enet_toggle_run_led(void) +{ + unsigned char leds_state= inb(LED_LATCH_ADDRESS); + if (leds_state & LED_RUN_BITMASK) + outb(leds_state &~ LED_RUN_BITMASK, LED_LATCH_ADDRESS); + else + outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS); +} diff --git a/board/eNET/hardware.h b/board/eNET/hardware.h index 42474a62fa..dec2cd8040 100644 --- a/board/eNET/hardware.h +++ b/board/eNET/hardware.h @@ -31,5 +31,6 @@ #define LED_RX_BITMASK 0x08 #define LED_TX_BITMASK 0x10 #define LED_ERR_BITMASK 0x20 +#define WATCHDOG_PIO_BIT 0x8000 #endif /* HARDWARE_H_ */ -- cgit