From 96f599009a5b3bf6cd92007204e06fa53f9a1dfb Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 20 Feb 2021 20:05:58 -0500 Subject: arm: Remove platinum_picon board This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. Cc: Stefan Roese Signed-off-by: Tom Rini --- board/barco/platinum/platinum.c | 219 ---------------------------------------- 1 file changed, 219 deletions(-) delete mode 100644 board/barco/platinum/platinum.c (limited to 'board/barco/platinum/platinum.c') diff --git a/board/barco/platinum/platinum.c b/board/barco/platinum/platinum.c deleted file mode 100644 index ec8d552888..0000000000 --- a/board/barco/platinum/platinum.c +++ /dev/null @@ -1,219 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014, Barco (www.barco.com) - * Copyright (C) 2014 Stefan Roese - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "platinum.h" - -DECLARE_GLOBAL_DATA_PTR; - -iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ -}; - -iomux_v3_cfg_t nfc_pads[] = { - MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -struct fsl_esdhc_cfg usdhc_cfg[] = { - { USDHC3_BASE_ADDR }, -}; - -void setup_gpmi_nand(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - /* config gpmi nand iomux */ - imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); - - /* config gpmi and bch clock to 100 MHz */ - clrsetbits_le32(&mxc_ccm->cs2cdr, - MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, - MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | - MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | - MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); - - /* enable gpmi and bch clock gating */ - setbits_le32(&mxc_ccm->CCGR4, - MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); - - /* enable apbh clock gating */ - setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); - - return 0; -} - -int board_ehci_hcd_init(int port) -{ - return 0; -} - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - - if (cfg->esdhc_base == usdhc_cfg[0].esdhc_base) { - unsigned sd3_cd = IMX_GPIO_NR(7, 0); - gpio_direction_input(sd3_cd); - return !gpio_get_value(sd3_cd); - } - - return 0; -} - -int board_mmc_init(struct bd_info *bis) -{ - imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -} - -void board_init_gpio(void) -{ - platinum_init_gpio(); -} - -void board_init_gpmi_nand(void) -{ - setup_gpmi_nand(); -} - -void board_init_i2c(void) -{ - platinum_setup_i2c(); -} - -void board_init_spi(void) -{ - platinum_setup_spi(); -} - -void board_init_uart(void) -{ - platinum_setup_uart(); -} - -void board_init_usb(void) -{ - platinum_init_usb(); -} - -void board_init_finished(void) -{ - platinum_init_finished(); -} - -int board_phy_config(struct phy_device *phydev) -{ - return platinum_phy_config(phydev); -} - -int board_eth_init(struct bd_info *bis) -{ - return cpu_eth_init(bis); -} - -int board_early_init_f(void) -{ - board_init_uart(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - board_init_spi(); - - board_init_i2c(); - - board_init_gpmi_nand(); - - board_init_gpio(); - - board_init_usb(); - - board_init_finished(); - - return 0; -} - -int checkboard(void) -{ - puts("Board: " CONFIG_PLATINUM_BOARD "\n"); - return 0; -} - -static const struct boot_mode board_boot_modes[] = { - /* NAND */ - { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, - /* 4 bit bus width */ - { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) }, - { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) }, - { NULL, 0 }, -}; - -int misc_init_r(void) -{ - add_board_boot_modes(board_boot_modes); - - return 0; -} -- cgit