From 58067b0de1e5d8a07ccb8c3a5497beaa0e043c6b Mon Sep 17 00:00:00 2001 From: Weijie Gao Date: Thu, 11 Jul 2019 14:26:24 +0800 Subject: arm: dts: MediaTek: fix clock order for timer0 node of mt7629.dtsi The timer0 node has its two clocks written in reversed order. The timer0 is used as the tick timer which causes a problem that the time a delay function used is 4 times longer. This patch reverses these two clocks to solve this issue. Signed-off-by: Weijie Gao --- arch/arm/dts/mt7629.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi index c87115e0fe..ecbd29d7ae 100644 --- a/arch/arm/dts/mt7629.dtsi +++ b/arch/arm/dts/mt7629.dtsi @@ -82,8 +82,8 @@ compatible = "mediatek,timer"; reg = <0x10004000 0x80>; interrupts = ; - clocks = <&topckgen CLK_TOP_10M_SEL>, - <&topckgen CLK_TOP_CLKXTAL_D4>; + clocks = <&topckgen CLK_TOP_CLKXTAL_D4>, + <&topckgen CLK_TOP_10M_SEL>; clock-names = "mux", "src"; u-boot,dm-pre-reloc; }; -- cgit