From 5c606ca35c421faf42499f78ce4a4e7745d53df6 Mon Sep 17 00:00:00 2001 From: Deepak Das Date: Wed, 15 Apr 2020 08:55:24 +0530 Subject: rockchip: rk3399: enable spl-fifo-mode for sdmmc adapting commit fa2047c47310 ("rockchip: rk3328: enable spl-fifo-mode for emmc and sdmmc") for rk3399. Since mmc to sram can't do dma, add patch to prevent aborts transferring TF-A parts. Signed-off-by: Deepak Das --- arch/arm/dts/rk3399-u-boot.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 9bb130a92a..22017ecd60 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -91,6 +91,9 @@ &sdmmc { u-boot,dm-pre-reloc; + + /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ + u-boot,spl-fifo-mode; }; &spi1 { -- cgit From 765a12d6a39ee2151421c5fc0250d9eefdf0e085 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sat, 9 May 2020 22:26:23 +0530 Subject: rockchip: Enable PCIe/M.2 on rk3399 board w/ M.2 Enable PCIe/M.2 support on - NanoPC-T4 - ROC-RK3399-PC Mezzanine boards. Signed-off-by: Jagan Teki Tested-by: Suniel Mahesh #roc-rk3399-pc Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-u-boot.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 22017ecd60..8237782408 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -8,6 +8,7 @@ aliases { mmc0 = &sdhci; mmc1 = &sdmmc; + pci0 = &pcie0; }; cic: syscon@ff620000 { -- cgit From 353ad95aa6562654726a91cb457f30d5f2a85f4c Mon Sep 17 00:00:00 2001 From: Urja Rannikko Date: Wed, 13 May 2020 19:15:20 +0000 Subject: rockchip: spl: veyron speedy boots from SPI Apparently speedy was forgotten from this list of veyron devices. Fixes: 49105fb7ed ("rockchip: add common spl board file") Signed-off-by: Urja Rannikko Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/spl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index ec2f66d188..46b32eb345 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -53,7 +53,8 @@ u32 spl_boot_device(void) #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ - defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) + defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \ + defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY) return BOOT_DEVICE_SPI; #endif if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)) -- cgit From e68a84360173f90fa37df875e6aa2c83f2858b80 Mon Sep 17 00:00:00 2001 From: Urja Rannikko Date: Wed, 13 May 2020 19:15:22 +0000 Subject: rockchip: spl-boot-order: do not attempt to access fdt if OF_PLATDATA gd->fdt_blob is null if using OF_PLATDATA in SPL, which causes a hang after f0921f5098 ("fdt: Sync up to the latest libfdt"). We use the same test that is used in spl_common_init on whether to call fdtdec_setup to unconditionally avoid linking in the fdt-using code when not necessary and thus reduce SPL size. Signed-off-by: Urja Rannikko Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/spl-boot-order.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c index c2e4023007..94673f34c9 100644 --- a/arch/arm/mach-rockchip/spl-boot-order.c +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -99,6 +99,12 @@ __weak const char *board_spl_was_booted_from(void) void board_boot_order(u32 *spl_boot_list) { + /* In case of no fdt (or only platdata), use spl_boot_device() */ + if (!CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_PLATDATA)) { + spl_boot_list[0] = spl_boot_device(); + return; + } + const void *blob = gd->fdt_blob; int chosen_node = fdt_path_offset(blob, "/chosen"); int idx = 0; -- cgit From 33863f744d513f5c16a254870e7b3cef8580bbc9 Mon Sep 17 00:00:00 2001 From: Kurt Miller Date: Wed, 13 May 2020 15:55:20 -0400 Subject: rockchip: rk3328: rock64 - fix gen3 SPL hang Use the same approach as ROC-RK3328-CC which enables SPL GPIO, pinctl and regulator support. This allows the gen3 board to boot through SPL and does not break gen2 in the process. Signed-off-by: Kurt Miller Acked-by: Matwey V. Kornilov Reviewed-by: Kever Yang --- arch/arm/dts/rk3328-rock64-u-boot.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index 8318bf4e60..f076075076 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -11,6 +11,22 @@ }; }; +&gpio0 { + u-boot,dm-spl; +}; + +&pinctrl { + u-boot,dm-spl; +}; + +&sdmmc0m1_gpio { + u-boot,dm-spl; +}; + +&pcfg_pull_up_4ma { + u-boot,dm-spl; +}; + &usb_host0_xhci { vbus-supply = <&vcc_host_5v>; status = "okay"; @@ -25,3 +41,8 @@ /delete-property/ regulator-always-on; /delete-property/ regulator-boot-on; }; + +/* Need this and all the pinctrl/gpio stuff above to set pinmux */ +&vcc_sd { + u-boot,dm-spl; +}; -- cgit