From 16c78cba92f0cb24d56eaa87356beaca4a2d7f56 Mon Sep 17 00:00:00 2001 From: Michael Tretter Date: Mon, 3 Dec 2018 16:37:53 +0100 Subject: tools: zynqmpimage: round up partition size The FSBL copies "Total Partition Word Length" * 4 bytes from the boot.bin, which implies that the partition size is 4 byte aligned. When writing the partition, mkimage calculates "Total Partition Word Length" by dividing the size by 4. This implicitly cuts unaligned bytes at the end of the added binary. Instead of rounding down, the size must be round up to 4 bytes and the binary padded accordingly. Signed-off-by: Michael Tretter Reviewed-by: Alexander Graf Signed-off-by: Michal Simek --- tools/zynqmpbif.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/tools/zynqmpbif.c b/tools/zynqmpbif.c index 6c8f66055d..a33c15e1f0 100644 --- a/tools/zynqmpbif.c +++ b/tools/zynqmpbif.c @@ -319,16 +319,25 @@ static int bif_add_pmufw(struct bif_entry *bf, const char *data, size_t len) static int bif_add_part(struct bif_entry *bf, const char *data, size_t len) { size_t parthdr_offset = 0; + size_t len_padded = ROUND(len, 4); + struct partition_header parthdr = { - .len_enc = cpu_to_le32(len / 4), - .len_unenc = cpu_to_le32(len / 4), - .len = cpu_to_le32(len / 4), + .len_enc = cpu_to_le32(len_padded / 4), + .len_unenc = cpu_to_le32(len_padded / 4), + .len = cpu_to_le32(len_padded / 4), .entry_point = cpu_to_le64(bf->entry), .load_address = cpu_to_le64(bf->load), }; int r; uint32_t csum; + if (len < len_padded) { + char *newdata = malloc(len_padded); + memcpy(newdata, data, len); + memset(newdata + len, 0, len_padded - len); + data = newdata; + } + if (bf->flags & (1ULL << BIF_FLAG_PMUFW_IMAGE)) return bif_add_pmufw(bf, data, len); -- cgit From 97fca6a146390e1c4a5fe4c29b68f7730229db56 Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Mon, 3 Dec 2018 16:11:58 +0530 Subject: mtd: nand: arasan_nfc: Add support for nand multi chip select This patch adds support for nand multi chip select. Also adding CONFIG_SYS_NAND_MAX_CHIPS to Kconfig to specify maximum number of nand chips. Signed-off-by: Tummala Karthik Reddy Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- drivers/mtd/nand/raw/Kconfig | 7 +++++++ drivers/mtd/nand/raw/arasan_nfc.c | 27 +++++++++++++-------------- 2 files changed, 20 insertions(+), 14 deletions(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 6d466603d8..7f76e5ecef 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -299,6 +299,13 @@ config SYS_NAND_BUSWIDTH_16BIT not available while configuring controller. So a static CONFIG_NAND_xx is needed to know the device's bus-width in advance. +config SYS_NAND_MAX_CHIPS + int "NAND max chips" + default 1 + depends on NAND_ARASAN + help + The maximum number of NAND chips per device to be supported. + if SPL config SYS_NAND_U_BOOT_LOCATIONS diff --git a/drivers/mtd/nand/raw/arasan_nfc.c b/drivers/mtd/nand/raw/arasan_nfc.c index dc531ccb68..2cd3f64dc6 100644 --- a/drivers/mtd/nand/raw/arasan_nfc.c +++ b/drivers/mtd/nand/raw/arasan_nfc.c @@ -90,6 +90,8 @@ struct arasan_nand_command_format { #define ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT 16 #define ARASAN_NAND_MEM_ADDR2_PAGE_MASK 0xFF #define ARASAN_NAND_MEM_ADDR2_CS_MASK 0xC0000000 +#define ARASAN_NAND_MEM_ADDR2_CS0_MASK (0x3 << 30) +#define ARASAN_NAND_MEM_ADDR2_CS1_MASK (0x1 << 30) #define ARASAN_NAND_MEM_ADDR2_BCH_MASK 0xE000000 #define ARASAN_NAND_MEM_ADDR2_BCH_SHIFT 25 @@ -261,6 +263,16 @@ static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; static void arasan_nand_select_chip(struct mtd_info *mtd, int chip) { + u32 reg_val; + + reg_val = readl(&arasan_nand_base->memadr_reg2); + if (chip == 0) { + reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS0_MASK; + writel(reg_val, &arasan_nand_base->memadr_reg2); + } else if (chip == 1) { + reg_val |= ARASAN_NAND_MEM_ADDR2_CS1_MASK; + writel(reg_val, &arasan_nand_base->memadr_reg2); + } } static void arasan_nand_enable_ecc(void) @@ -713,9 +725,6 @@ static int arasan_nand_send_wrcmd(struct arasan_nand_command_format *curr_cmd, reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK; reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT); writel(reg_val, &arasan_nand_base->memadr_reg2); - reg_val = readl(&arasan_nand_base->memadr_reg2); - reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK; - writel(reg_val, &arasan_nand_base->memadr_reg2); return 0; } @@ -804,9 +813,6 @@ static int arasan_nand_erase(struct arasan_nand_command_format *curr_cmd, reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK; reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT); writel(reg_val, &arasan_nand_base->memadr_reg2); - reg_val = readl(&arasan_nand_base->memadr_reg2); - reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK; - writel(reg_val, &arasan_nand_base->memadr_reg2); writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); while (!(readl(&arasan_nand_base->intsts_reg) & @@ -859,10 +865,6 @@ static int arasan_nand_read_status(struct arasan_nand_command_format *curr_cmd, reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | 1; writel(reg_val, &arasan_nand_base->pkt_reg); - reg_val = readl(&arasan_nand_base->memadr_reg2); - reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK; - writel(reg_val, &arasan_nand_base->memadr_reg2); - writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); while (!(readl(&arasan_nand_base->intsts_reg) & ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { @@ -932,9 +934,6 @@ static int arasan_nand_send_rdcmd(struct arasan_nand_command_format *curr_cmd, reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT); writel(reg_val, &arasan_nand_base->memadr_reg2); - reg_val = readl(&arasan_nand_base->memadr_reg2); - reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK; - writel(reg_val, &arasan_nand_base->memadr_reg2); buf_index = 0; return 0; @@ -1219,7 +1218,7 @@ static int arasan_nand_init(struct nand_chip *nand_chip, int devnum) writel(0x0, &arasan_nand_base->pgm_reg); /* first scan to find the device and get the page size */ - if (nand_scan_ident(mtd, 1, NULL)) { + if (nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL)) { printf("%s: nand_scan_ident failed\n", __func__); goto fail; } -- cgit From a19eb356cccce644be0fff849cd13258a90fe146 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 3 Dec 2018 16:24:45 +0100 Subject: arm64: zynqmp: Enable 2 NAND chips for zc1751 dc2 This board contains 2 nand chips that's why enable this feature. Signed-off-by: Michal Simek --- configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index f9e56055b1..052e266fd7 100644 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -57,6 +57,7 @@ CONFIG_DM_MMC=y CONFIG_MTD_DEVICE=y CONFIG_NAND=y CONFIG_NAND_ARASAN=y +CONFIG_SYS_NAND_MAX_CHIPS=2 CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SST=y -- cgit From 25aed77f5188fef0ff5141569962e2919dd48020 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 5 Dec 2018 12:40:55 +0100 Subject: mmc: zynq: Remove unused pwrseq variable This variable was incorrectly added by: "mmc: zynq_sdhci: Add support for SD3.0" (sha1: d1f4e39d58db32a4fd1a1b4085e0ede498bd773f) which had nothing to do with MMC power sequence provider. Signed-off-by: Michal Simek --- drivers/mmc/zynq_sdhci.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index b05334dfc8..08023783de 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -28,7 +28,6 @@ struct arasan_sdhci_priv { u8 deviceid; u8 bank; u8 no_1p8; - bool pwrseq; }; #if defined(CONFIG_ARCH_ZYNQMP) -- cgit From f11d4ab0b37ede1eed45540ac4e2384b3d19ce98 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 20 Dec 2018 09:41:12 +0100 Subject: arm64: zynqmp: Do not protect zynqmp_pmufw_version() There is hard dependency for CLK_ZYNQMP to have zynqmp_pmufw_version() but also FPGA code is calling this function which is possible to use without actual CLK_ZYNQMP firmware driver to be enabled. This patch enables the case where only fixed-clock CLK setup is used. Signed-off-by: Michal Simek --- arch/arm/cpu/armv8/zynqmp/cpu.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index 4ee8e3f627..5ef1a52862 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -179,8 +179,7 @@ int __maybe_unused invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, return regs.regs[0]; } -#if defined(CONFIG_CLK_ZYNQMP) -unsigned int zynqmp_pmufw_version(void) +unsigned int __maybe_unused zynqmp_pmufw_version(void) { int ret; u32 ret_payload[PAYLOAD_ARG_CNT]; @@ -202,7 +201,6 @@ unsigned int zynqmp_pmufw_version(void) return pm_api_version; } -#endif static int zynqmp_mmio_rawwrite(const u32 address, const u32 mask, -- cgit From 0bf3f9cb2722e57a0afb37cb61af5ceaefcf70e0 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 20 Dec 2018 09:33:38 +0100 Subject: arm64: zynqmp: Protect board_late_init function Function should be compiled only when CONFIG_BOARD_LATE_INIT is defined. Signed-off-by: Michal Simek --- board/xilinx/zynqmp/zynqmp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 13c404b6ef..1dcb26db95 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -489,6 +489,7 @@ void reset_cpu(ulong addr) { } +#if defined(CONFIG_BOARD_LATE_INIT) static const struct { u32 bit; const char *name; @@ -655,6 +656,7 @@ int board_late_init(void) return 0; } +#endif int checkboard(void) { -- cgit From 10598580612cbaee2298bddd77e9a51df5a2943d Mon Sep 17 00:00:00 2001 From: Stefan Theil Date: Mon, 17 Dec 2018 09:12:30 +0100 Subject: zynq-gem: Use appropriate cache flush/invalidate for RX and TX The cache was only flushed before *transmitting* packets, but not when receiving them, leading to an issue where new packets were handed to the receive handler with old contents in cache. This only happens when a lot of packets are received without sending packages every now and then. Also flushing the receive buffers in the transmit function makes no sense and can be removed. Signed-off-by: Stefan Theil Reviewed-by: Bin Meng Signed-off-by: Michal Simek --- drivers/net/zynq_gem.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 9bd79b198a..3bd0093b7a 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -570,11 +570,6 @@ static int zynq_gem_send(struct udevice *dev, void *ptr, int len) addr &= ~(ARCH_DMA_MINALIGN - 1); size = roundup(len, ARCH_DMA_MINALIGN); flush_dcache_range(addr, addr + size); - - addr = (ulong)priv->rxbuffers; - addr &= ~(ARCH_DMA_MINALIGN - 1); - size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); - flush_dcache_range(addr, addr + size); barrier(); /* Start transmit */ @@ -621,6 +616,9 @@ static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp) *packetp = (uchar *)(uintptr_t)addr; + invalidate_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, ARCH_DMA_MINALIGN)); + barrier(); + return frame_len; } @@ -706,6 +704,9 @@ static int zynq_gem_probe(struct udevice *dev) return -ENOMEM; memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); + u32 addr = (ulong)priv->rxbuffers; + flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN)); + barrier(); /* Align bd_space to MMU_SECTION_SHIFT */ bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); -- cgit From e7c9de6617e6a51e6502920c5b3e5a41a0bf6973 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Thu, 3 Jan 2019 15:44:24 +0530 Subject: arm64: zynqmp: Fix mmc node names to be in sync with kernel This patches renames sd nodes in dts to be in line with kernel. This patch also modifies the references for the same in code. It checks mmc first to have no time penalty for new DT node names based on left-to-right expression evaluation. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp.dtsi | 4 ++-- board/xilinx/zynqmp/zynqmp.c | 4 ++++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 80ac9a6ac7..831d6e1ecc 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -700,7 +700,7 @@ /* dma-coherent; */ }; - sdhci0: sdhci@ff160000 { + sdhci0: mmc@ff160000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; @@ -715,7 +715,7 @@ nvmem-cell-names = "soc_revision"; }; - sdhci1: sdhci@ff170000 { + sdhci1: mmc@ff170000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 1dcb26db95..41e88b03f9 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -588,6 +588,8 @@ int board_late_init(void) case SD_MODE: puts("SD_MODE\n"); if (uclass_get_device_by_name(UCLASS_MMC, + "mmc@ff160000", &dev) && + uclass_get_device_by_name(UCLASS_MMC, "sdhci@ff160000", &dev)) { puts("Boot from SD0 but without SD0 enabled!\n"); return -1; @@ -604,6 +606,8 @@ int board_late_init(void) case SD_MODE1: puts("SD_MODE1\n"); if (uclass_get_device_by_name(UCLASS_MMC, + "mmc@ff170000", &dev) && + uclass_get_device_by_name(UCLASS_MMC, "sdhci@ff170000", &dev)) { puts("Boot from SD1 but without SD1 enabled!\n"); return -1; -- cgit From c256d3f7c591d6dbde0dedd9dfac696bd9c8376e Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 27 Nov 2018 11:49:10 +0530 Subject: net: phy: Move fixed link code to separate routine This patch moves fixed-link functionality code to a separate routine inorder to make it more modular and cleaner. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek Acked-by: Joe Hershberger --- drivers/net/phy/phy.c | 34 +++++++++++++++++++++++++++------- 1 file changed, 27 insertions(+), 7 deletions(-) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index cda4caa803..236913a154 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -876,18 +876,18 @@ void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev) debug("%s connected to %s\n", dev->name, phydev->drv->name); } +#ifdef CONFIG_PHY_FIXED #ifdef CONFIG_DM_ETH -struct phy_device *phy_connect(struct mii_dev *bus, int addr, - struct udevice *dev, - phy_interface_t interface) +static struct phy_device *phy_connect_fixed(struct mii_dev *bus, + struct udevice *dev, + phy_interface_t interface) #else -struct phy_device *phy_connect(struct mii_dev *bus, int addr, - struct eth_device *dev, - phy_interface_t interface) +static struct phy_device *phy_connect_fixed(struct mii_dev *bus, + struct eth_device *dev, + phy_interface_t interface) #endif { struct phy_device *phydev = NULL; -#ifdef CONFIG_PHY_FIXED int sn; const char *name; @@ -901,7 +901,27 @@ struct phy_device *phy_connect(struct mii_dev *bus, int addr, } sn = fdt_next_subnode(gd->fdt_blob, sn); } + + return phydev; +} #endif + +#ifdef CONFIG_DM_ETH +struct phy_device *phy_connect(struct mii_dev *bus, int addr, + struct udevice *dev, + phy_interface_t interface) +#else +struct phy_device *phy_connect(struct mii_dev *bus, int addr, + struct eth_device *dev, + phy_interface_t interface) +#endif +{ + struct phy_device *phydev = NULL; + +#ifdef CONFIG_PHY_FIXED + phydev = phy_connect_fixed(bus, dev, interface); +#endif + if (!phydev) phydev = phy_find_by_mask(bus, 1 << addr, interface); -- cgit From 4c84844715c645db9968d2f5cbeefe910268f57f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 21 Nov 2018 07:49:18 +0100 Subject: arm64: zynqmp: Fix tcminit help text alignment Trivial patch. Signed-off-by: Michal Simek --- board/xilinx/zynqmp/cmds.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c index 3e039ccb13..321670d4e3 100644 --- a/board/xilinx/zynqmp/cmds.c +++ b/board/xilinx/zynqmp/cmds.c @@ -174,11 +174,11 @@ static char zynqmp_help_text[] = "zynqmp mmio_write address mask value - write value after masking to\n" " address\n" #ifdef CONFIG_DEFINE_TCM_OCM_MMAP - "zynqmp tcminit mode - Initialize the TCM with zeros. TCM needs to be\n" - " initialized before accessing to avoid ECC\n" - " errors. mode specifies in which mode TCM has\n" - " to be initialized. Supported modes will be\n" - " lock(0)/split(1)\n" + "zynqmp tcminit mode - Initialize the TCM with zeros. TCM needs to be\n" + " initialized before accessing to avoid ECC\n" + " errors. mode specifies in which mode TCM has\n" + " to be initialized. Supported modes will be\n" + " lock(0)/split(1)\n" #endif ; #endif -- cgit From 8df324a20b45f3a15a166797a2d5a5d447337891 Mon Sep 17 00:00:00 2001 From: Luca Ceresoli Date: Fri, 11 Jan 2019 17:09:45 +0100 Subject: fpga: zynqmp: show an error message when FPGA programming fails When FPGA programming fails, it does so silently, unless debugging code is enabled. This makes it hard to detect problems in production environments. Print the error message unconditionally so the error doesn't go unnoticed. Signed-off-by: Luca Ceresoli Signed-off-by: Michal Simek --- drivers/fpga/zynqmppl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index c095d5ecaa..22bfdd8dce 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -233,7 +233,7 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, (u32)bsize, 0, ret_payload); if (ret) - debug("PL FPGA LOAD fail\n"); + puts("PL FPGA LOAD fail\n"); return ret; } -- cgit From fa7971574cfa6b4dc5ca72501b2f2b01159884f2 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 15 Jan 2019 08:52:46 +0100 Subject: arm64: versal: Setup DM_ETH/MMC if NET/MMC is enabled Setup proper ETH/MMC dependency for the whole platform. Signed-off-by: Michal Simek --- arch/arm/Kconfig | 2 ++ configs/xilinx_versal_virt_defconfig | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d6b1629a00..d69958b5a2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -886,6 +886,8 @@ config ARCH_VERSAL select ARM64 select CLK select DM + select DM_ETH if NET + select DM_MMC if MMC select DM_SERIAL select OF_CONTROL diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 668c313a29..e1797db982 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -42,7 +42,6 @@ CONFIG_OF_BOARD=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DM_GPIO=y -CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_DM_SPI_FLASH=y @@ -55,7 +54,6 @@ CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHY_FIXED=y -CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_ZYNQ_GEM=y -- cgit From fb69310850b69d7d13085e243fea52079f406340 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 15 Jan 2019 08:52:51 +0100 Subject: arm64: zynqmp: Setup DM_ETH/MMC if NET/MMC is enabled Setup proper ETH/MMC dependency for the whole platform. Signed-off-by: Michal Simek --- arch/arm/Kconfig | 2 ++ configs/avnet_ultra96_rev1_defconfig | 2 -- configs/xilinx_zynqmp_mini_emmc0_defconfig | 1 - configs/xilinx_zynqmp_mini_emmc1_defconfig | 1 - configs/xilinx_zynqmp_zc1232_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1254_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1275_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1275_revB_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 2 -- configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig | 2 -- configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 2 -- configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 2 -- configs/xilinx_zynqmp_zcu100_revC_defconfig | 2 -- configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 2 -- configs/xilinx_zynqmp_zcu102_revA_defconfig | 2 -- configs/xilinx_zynqmp_zcu102_revB_defconfig | 2 -- configs/xilinx_zynqmp_zcu104_revA_defconfig | 2 -- configs/xilinx_zynqmp_zcu104_revC_defconfig | 2 -- configs/xilinx_zynqmp_zcu106_revA_defconfig | 2 -- configs/xilinx_zynqmp_zcu111_revA_defconfig | 2 -- 21 files changed, 2 insertions(+), 33 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d69958b5a2..271d883d99 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -941,6 +941,8 @@ config ARCH_ZYNQMP select ARM64 select CLK select DM + select DM_ETH if NET + select DM_MMC if MMC select DM_SERIAL select DM_USB if USB select OF_CONTROL diff --git a/configs/avnet_ultra96_rev1_defconfig b/configs/avnet_ultra96_rev1_defconfig index 5b5af16df5..749f5a124c 100644 --- a/configs/avnet_ultra96_rev1_defconfig +++ b/configs/avnet_ultra96_rev1_defconfig @@ -55,7 +55,6 @@ CONFIG_ZYNQ_I2C1=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MISC=y -CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_DM_SPI_FLASH=y @@ -66,7 +65,6 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_DM_ETH=y # CONFIG_NETDEVICES is not set CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig index 9cdc944f0c..a49fb84c11 100644 --- a/configs/xilinx_zynqmp_mini_emmc0_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig @@ -52,7 +52,6 @@ CONFIG_SPL_DM=y # CONFIG_DM_WARN is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y # CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig index 74ea3a864e..658ea6ddcd 100644 --- a/configs/xilinx_zynqmp_mini_emmc1_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig @@ -52,7 +52,6 @@ CONFIG_SPL_DM=y # CONFIG_DM_WARN is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y # CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_zc1232_revA_defconfig b/configs/xilinx_zynqmp_zc1232_revA_defconfig index 7521fc4e34..b8d91b9a4e 100644 --- a/configs/xilinx_zynqmp_zc1232_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1232_revA_defconfig @@ -35,7 +35,6 @@ CONFIG_CLK_ZYNQMP=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y CONFIG_MISC=y -CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y diff --git a/configs/xilinx_zynqmp_zc1254_revA_defconfig b/configs/xilinx_zynqmp_zc1254_revA_defconfig index e0822b931e..6cfb4c4a76 100644 --- a/configs/xilinx_zynqmp_zc1254_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1254_revA_defconfig @@ -35,7 +35,6 @@ CONFIG_CLK_ZYNQMP=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y CONFIG_MISC=y -CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y diff --git a/configs/xilinx_zynqmp_zc1275_revA_defconfig b/configs/xilinx_zynqmp_zc1275_revA_defconfig index 3afed69737..17fa87e166 100644 --- a/configs/xilinx_zynqmp_zc1275_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1275_revA_defconfig @@ -35,7 +35,6 @@ CONFIG_CLK_ZYNQMP=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y CONFIG_MISC=y -CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y diff --git a/configs/xilinx_zynqmp_zc1275_revB_defconfig b/configs/xilinx_zynqmp_zc1275_revB_defconfig index 7e31b1112f..0a66ec3dc8 100644 --- a/configs/xilinx_zynqmp_zc1275_revB_defconfig +++ b/configs/xilinx_zynqmp_zc1275_revB_defconfig @@ -36,7 +36,6 @@ CONFIG_CLK_ZYNQMP=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y CONFIG_MISC=y -CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index efd933fbc6..3c8972a0d5 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -56,7 +56,6 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_MISC=y -CONFIG_DM_MMC=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y @@ -73,7 +72,6 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_TI=y CONFIG_PHY_VITESSE=y CONFIG_PHY_FIXED=y -CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_ZYNQ_GEM=y diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index 052e266fd7..b27c29038b 100644 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -67,7 +67,6 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_TI=y CONFIG_PHY_VITESSE=y CONFIG_PHY_FIXED=y -CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_ZYNQ_GEM=y diff --git a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig index 4d94a216c8..73f214e25e 100644 --- a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig @@ -50,7 +50,6 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_MISC=y -CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_MTD_DEVICE=y @@ -62,7 +61,6 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_TI=y CONFIG_PHY_VITESSE=y CONFIG_PHY_FIXED=y -CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_ZYNQ_GEM=y diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig index a0bbc0fbde..417e0e3b07 100644 --- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig @@ -43,7 +43,6 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_MISC=y -CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y @@ -59,7 +58,6 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_TI=y CONFIG_PHY_VITESSE=y CONFIG_PHY_FIXED=y -CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_ZYNQ_GEM=y diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig index 0625d195c9..4d51bfaaf5 100644 --- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig @@ -44,7 +44,6 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_MISC=y -CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_PHY_MARVELL=y @@ -53,7 +52,6 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_TI=y CONFIG_PHY_VITESSE=y CONFIG_PHY_FIXED=y -CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_ZYNQ_GEM=y diff --git a/configs/xilinx_zynqmp_zcu100_revC_defconfig b/configs/xilinx_zynqmp_zcu100_revC_defconfig index 53bca780af..1c9d6cca7d 100644 --- a/configs/xilinx_zynqmp_zcu100_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu100_revC_defconfig @@ -55,7 +55,6 @@ CONFIG_ZYNQ_I2C1=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MISC=y -CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_DM_SPI_FLASH=y @@ -66,7 +65,6 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_DM_ETH=y # CONFIG_NETDEVICES is not set CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig index 905d4672dc..860ac70126 100644 --- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig +++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig @@ -68,7 +68,6 @@ CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MISC=y CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 -CONFIG_DM_MMC=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_SDHCI=y @@ -87,7 +86,6 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_TI=y CONFIG_PHY_VITESSE=y CONFIG_PHY_FIXED=y -CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_ZYNQ_GEM=y diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig index 5e4bbf8e8f..1a226ba280 100644 --- a/configs/xilinx_zynqmp_zcu102_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig @@ -67,7 +67,6 @@ CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MISC=y CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 -CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_DM_SPI_FLASH=y @@ -84,7 +83,6 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_TI=y CONFIG_PHY_VITESSE=y CONFIG_PHY_FIXED=y -CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_ZYNQ_GEM=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index 29aa07695a..08a2cf161c 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -67,7 +67,6 @@ CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MISC=y CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 -CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_DM_SPI_FLASH=y @@ -84,7 +83,6 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_TI=y CONFIG_PHY_VITESSE=y CONFIG_PHY_FIXED=y -CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_ZYNQ_GEM=y diff --git a/configs/xilinx_zynqmp_zcu104_revA_defconfig b/configs/xilinx_zynqmp_zcu104_revA_defconfig index 8fe30f931c..92a8252cad 100644 --- a/configs/xilinx_zynqmp_zcu104_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revA_defconfig @@ -53,7 +53,6 @@ CONFIG_CMD_PCA953X=y CONFIG_SYS_I2C_ZYNQ=y CONFIG_ZYNQ_I2C1=y CONFIG_MISC=y -CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y @@ -70,7 +69,6 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_TI=y CONFIG_PHY_VITESSE=y CONFIG_PHY_FIXED=y -CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_ZYNQ_GEM=y diff --git a/configs/xilinx_zynqmp_zcu104_revC_defconfig b/configs/xilinx_zynqmp_zcu104_revC_defconfig index a3d8ea0bff..40e740d8dc 100644 --- a/configs/xilinx_zynqmp_zcu104_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revC_defconfig @@ -54,7 +54,6 @@ CONFIG_SYS_I2C_ZYNQ=y CONFIG_ZYNQ_I2C1=y CONFIG_MISC=y CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 -CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y @@ -71,7 +70,6 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_TI=y CONFIG_PHY_VITESSE=y CONFIG_PHY_FIXED=y -CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_ZYNQ_GEM=y diff --git a/configs/xilinx_zynqmp_zcu106_revA_defconfig b/configs/xilinx_zynqmp_zcu106_revA_defconfig index 6a659f00bf..d37aa4d347 100644 --- a/configs/xilinx_zynqmp_zcu106_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu106_revA_defconfig @@ -62,7 +62,6 @@ CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MISC=y CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 -CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y @@ -79,7 +78,6 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_TI=y CONFIG_PHY_VITESSE=y CONFIG_PHY_FIXED=y -CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_ZYNQ_GEM=y diff --git a/configs/xilinx_zynqmp_zcu111_revA_defconfig b/configs/xilinx_zynqmp_zcu111_revA_defconfig index fc544381de..5c8daf508e 100644 --- a/configs/xilinx_zynqmp_zcu111_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu111_revA_defconfig @@ -56,7 +56,6 @@ CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MISC=y CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 -CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y @@ -72,7 +71,6 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_TI=y CONFIG_PHY_VITESSE=y CONFIG_PHY_FIXED=y -CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_ZYNQ_GEM=y -- cgit From 2ae587b86fe255fbc2de3f49be216284d5bfe88d Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Fri, 12 Oct 2018 16:55:37 +0530 Subject: arm64: zynqmp: Enable net configs for zc1275 This patch enable net configs for zc1275 board. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- configs/xilinx_zynqmp_zc1275_revB_defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/configs/xilinx_zynqmp_zc1275_revB_defconfig b/configs/xilinx_zynqmp_zc1275_revB_defconfig index 0a66ec3dc8..6a80ae8d07 100644 --- a/configs/xilinx_zynqmp_zc1275_revB_defconfig +++ b/configs/xilinx_zynqmp_zc1275_revB_defconfig @@ -31,6 +31,7 @@ CONFIG_CMD_TIMER=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revB" +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_CLK_ZYNQMP=y CONFIG_FPGA_XILINX=y @@ -46,6 +47,9 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_MARVELL=y +CONFIG_PHY_XILINX_GMII2RGMII=y +CONFIG_ZYNQ_GEM=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y -- cgit From 6f96fb508df5c23c34fb801f75e7b7166833e435 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 15 Jan 2019 09:06:46 +0100 Subject: ARM: zynqmp_r5: Setup DM_ETH/MMC if NET/MMC is enabled Setup proper ETH/MMC dependency for the whole platform. Signed-off-by: Michal Simek --- arch/arm/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 271d883d99..8346b172ac 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -931,6 +931,8 @@ config ARCH_ZYNQMP_R5 select CLK select CPU_V7R select DM + select DM_ETH if NET + select DM_MMC if MMC select DM_SERIAL select OF_CONTROL imply CMD_DM -- cgit From 088f83ee3a194af798adb56e27c20b37c49b034a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 15 Jan 2019 10:50:39 +0100 Subject: arm64: zynqmp: Setup proper SPI dependency Select DM_SPI/DM_SPI_FLASH for the whole SoC. Signed-off-by: Michal Simek --- arch/arm/Kconfig | 2 ++ configs/avnet_ultra96_rev1_defconfig | 2 -- configs/xilinx_zynqmp_mini_qspi_defconfig | 2 -- configs/xilinx_zynqmp_zcu100_revC_defconfig | 2 -- configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 2 -- configs/xilinx_zynqmp_zcu102_revA_defconfig | 2 -- configs/xilinx_zynqmp_zcu102_revB_defconfig | 2 -- 7 files changed, 2 insertions(+), 12 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8346b172ac..a65e0c5211 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -946,6 +946,8 @@ config ARCH_ZYNQMP select DM_ETH if NET select DM_MMC if MMC select DM_SERIAL + select DM_SPI if SPI + select DM_SPI_FLASH if DM_SPI select DM_USB if USB select OF_CONTROL select SPL_BOARD_INIT if SPL diff --git a/configs/avnet_ultra96_rev1_defconfig b/configs/avnet_ultra96_rev1_defconfig index 749f5a124c..12b49daa75 100644 --- a/configs/avnet_ultra96_rev1_defconfig +++ b/configs/avnet_ultra96_rev1_defconfig @@ -57,7 +57,6 @@ CONFIG_LED_GPIO=y CONFIG_MISC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y @@ -70,7 +69,6 @@ CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y CONFIG_SPI=y -CONFIG_DM_SPI=y CONFIG_ZYNQ_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index d037da75b0..dd487320e3 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -52,7 +52,6 @@ CONFIG_SPL_DM=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_SPL_DM_SEQ_ALIAS=y # CONFIG_MMC is not set -CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y @@ -61,6 +60,5 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI=y -CONFIG_DM_SPI=y CONFIG_ZYNQMP_GQSPI=y # CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_zcu100_revC_defconfig b/configs/xilinx_zynqmp_zcu100_revC_defconfig index 1c9d6cca7d..a33680fa9f 100644 --- a/configs/xilinx_zynqmp_zcu100_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu100_revC_defconfig @@ -57,7 +57,6 @@ CONFIG_LED_GPIO=y CONFIG_MISC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y @@ -70,7 +69,6 @@ CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y CONFIG_SPI=y -CONFIG_DM_SPI=y CONFIG_ZYNQ_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig index 860ac70126..a30c96eda8 100644 --- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig +++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig @@ -72,7 +72,6 @@ CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y @@ -95,7 +94,6 @@ CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y CONFIG_SPI=y -CONFIG_DM_SPI=y CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig index 1a226ba280..d3c4df017c 100644 --- a/configs/xilinx_zynqmp_zcu102_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig @@ -69,7 +69,6 @@ CONFIG_MISC=y CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y @@ -92,7 +91,6 @@ CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y CONFIG_SPI=y -CONFIG_DM_SPI=y CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index 08a2cf161c..c0ce47628e 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -69,7 +69,6 @@ CONFIG_MISC=y CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y @@ -92,7 +91,6 @@ CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y CONFIG_SPI=y -CONFIG_DM_SPI=y CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y -- cgit From 8ae3fd66093945f9ea6b96261d99e0a874e46f1b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 15 Jan 2019 09:30:38 +0100 Subject: arm64: zynqmp: Enable SPI on several boards Enable GQSPI driver, SF command and SPL support for some platforms. Signed-off-by: Michal Simek --- configs/xilinx_zynqmp_zc1232_revA_defconfig | 3 +++ configs/xilinx_zynqmp_zc1254_revA_defconfig | 3 +++ configs/xilinx_zynqmp_zc1275_revA_defconfig | 3 +++ configs/xilinx_zynqmp_zc1275_revB_defconfig | 3 +++ configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 4 ++++ configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 4 ++++ configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 1 + configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 3 +++ configs/xilinx_zynqmp_zcu102_revA_defconfig | 3 +++ configs/xilinx_zynqmp_zcu102_revB_defconfig | 3 +++ configs/xilinx_zynqmp_zcu104_revA_defconfig | 3 +++ configs/xilinx_zynqmp_zcu104_revC_defconfig | 3 +++ configs/xilinx_zynqmp_zcu106_revA_defconfig | 5 +++++ configs/xilinx_zynqmp_zcu111_revA_defconfig | 3 +++ 16 files changed, 46 insertions(+) diff --git a/configs/xilinx_zynqmp_zc1232_revA_defconfig b/configs/xilinx_zynqmp_zc1232_revA_defconfig index b8d91b9a4e..8f6abe6ad5 100644 --- a/configs/xilinx_zynqmp_zc1232_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1232_revA_defconfig @@ -23,6 +23,7 @@ CONFIG_CMD_CLK=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_SF=y # CONFIG_CMD_NET is not set CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y @@ -46,4 +47,6 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_ZYNQMP_GQSPI=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zc1254_revA_defconfig b/configs/xilinx_zynqmp_zc1254_revA_defconfig index 6cfb4c4a76..83c6f902e2 100644 --- a/configs/xilinx_zynqmp_zc1254_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1254_revA_defconfig @@ -23,6 +23,7 @@ CONFIG_CMD_CLK=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_SF=y # CONFIG_CMD_NET is not set CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y @@ -46,4 +47,6 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_ZYNQMP_GQSPI=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zc1275_revA_defconfig b/configs/xilinx_zynqmp_zc1275_revA_defconfig index 17fa87e166..ef30979c28 100644 --- a/configs/xilinx_zynqmp_zc1275_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1275_revA_defconfig @@ -23,6 +23,7 @@ CONFIG_CMD_CLK=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_SF=y # CONFIG_CMD_NET is not set CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y @@ -46,4 +47,6 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_ZYNQMP_GQSPI=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zc1275_revB_defconfig b/configs/xilinx_zynqmp_zc1275_revB_defconfig index 6a80ae8d07..1910d21420 100644 --- a/configs/xilinx_zynqmp_zc1275_revB_defconfig +++ b/configs/xilinx_zynqmp_zc1275_revB_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_CLK=y CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y # CONFIG_CMD_NET is not set CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y @@ -53,4 +54,6 @@ CONFIG_ZYNQ_GEM=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_ZYNQMP_GQSPI=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index 3c8972a0d5..36093e9f2c 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -32,6 +32,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y @@ -61,6 +62,7 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y @@ -78,6 +80,8 @@ CONFIG_ZYNQ_GEM=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index b27c29038b..69ffa8e826 100644 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -73,6 +73,7 @@ CONFIG_ZYNQ_GEM=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig index 73f214e25e..c5c416b842 100644 --- a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig @@ -69,6 +69,7 @@ CONFIG_DM_SCSI=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig index 417e0e3b07..82dc2cb311 100644 --- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y @@ -47,6 +48,7 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y @@ -64,3 +66,5 @@ CONFIG_ZYNQ_GEM=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_ZYNQMP_GQSPI=y diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig index 4d51bfaaf5..960cd18f12 100644 --- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig @@ -58,4 +58,5 @@ CONFIG_ZYNQ_GEM=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig index a30c96eda8..0fb634ff1a 100644 --- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig +++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig @@ -6,6 +6,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xff000000 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y CONFIG_ZYNQMP_USB=y CONFIG_DEBUG_UART=y CONFIG_AHCI=y @@ -74,6 +76,7 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig index d3c4df017c..62982b8204 100644 --- a/configs/xilinx_zynqmp_zcu102_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig @@ -6,6 +6,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xff000000 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y CONFIG_ZYNQMP_USB=y CONFIG_DEBUG_UART=y CONFIG_AHCI=y @@ -71,6 +73,7 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index c0ce47628e..7320f0776b 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -6,6 +6,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xff000000 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y CONFIG_ZYNQMP_USB=y CONFIG_DEBUG_UART=y CONFIG_AHCI=y @@ -71,6 +73,7 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/xilinx_zynqmp_zcu104_revA_defconfig b/configs/xilinx_zynqmp_zcu104_revA_defconfig index 92a8252cad..c887bd6827 100644 --- a/configs/xilinx_zynqmp_zcu104_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revA_defconfig @@ -30,6 +30,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y @@ -77,6 +78,8 @@ CONFIG_DM_SCSI=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/xilinx_zynqmp_zcu104_revC_defconfig b/configs/xilinx_zynqmp_zcu104_revC_defconfig index 40e740d8dc..cd2e9b387b 100644 --- a/configs/xilinx_zynqmp_zcu104_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revC_defconfig @@ -30,6 +30,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y @@ -78,6 +79,8 @@ CONFIG_DM_SCSI=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/xilinx_zynqmp_zcu106_revA_defconfig b/configs/xilinx_zynqmp_zcu106_revA_defconfig index d37aa4d347..b7b0762966 100644 --- a/configs/xilinx_zynqmp_zcu106_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu106_revA_defconfig @@ -6,6 +6,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xff000000 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y CONFIG_ZYNQMP_USB=y CONFIG_DEBUG_UART=y CONFIG_AHCI=y @@ -31,6 +33,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y @@ -86,6 +89,8 @@ CONFIG_DM_SCSI=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/xilinx_zynqmp_zcu111_revA_defconfig b/configs/xilinx_zynqmp_zcu111_revA_defconfig index 5c8daf508e..b5f0e6bbe9 100644 --- a/configs/xilinx_zynqmp_zcu111_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu111_revA_defconfig @@ -29,6 +29,7 @@ CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y @@ -79,6 +80,8 @@ CONFIG_DM_SCSI=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -- cgit From f854004f95570440c546f72524f8c5634342403b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 15 Jan 2019 10:45:41 +0100 Subject: arm64: zynqmp: Enable ISSI flash for some platforms Enable ISSI flash for platforms. Xilinx reference boards are also used internally with different flash part to increase coverage that's why enable also ISSI parts for all these boards even if that board is released only with one part. Signed-off-by: Michal Simek --- configs/avnet_ultra96_rev1_defconfig | 1 + configs/xilinx_zynqmp_mini_qspi_defconfig | 1 + configs/xilinx_zynqmp_zc1232_revA_defconfig | 1 + configs/xilinx_zynqmp_zc1254_revA_defconfig | 1 + configs/xilinx_zynqmp_zc1275_revA_defconfig | 1 + configs/xilinx_zynqmp_zc1275_revB_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 + configs/xilinx_zynqmp_zcu100_revC_defconfig | 1 + configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 + configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 + configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 + configs/xilinx_zynqmp_zcu104_revA_defconfig | 1 + configs/xilinx_zynqmp_zcu104_revC_defconfig | 1 + configs/xilinx_zynqmp_zcu106_revA_defconfig | 1 + configs/xilinx_zynqmp_zcu111_revA_defconfig | 1 + 16 files changed, 16 insertions(+) diff --git a/configs/avnet_ultra96_rev1_defconfig b/configs/avnet_ultra96_rev1_defconfig index 12b49daa75..77389732a6 100644 --- a/configs/avnet_ultra96_rev1_defconfig +++ b/configs/avnet_ultra96_rev1_defconfig @@ -59,6 +59,7 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index dd487320e3..3ec435e7ff 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -55,6 +55,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/xilinx_zynqmp_zc1232_revA_defconfig b/configs/xilinx_zynqmp_zc1232_revA_defconfig index 8f6abe6ad5..8c623130d9 100644 --- a/configs/xilinx_zynqmp_zc1232_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1232_revA_defconfig @@ -39,6 +39,7 @@ CONFIG_MISC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/xilinx_zynqmp_zc1254_revA_defconfig b/configs/xilinx_zynqmp_zc1254_revA_defconfig index 83c6f902e2..cbb167a57e 100644 --- a/configs/xilinx_zynqmp_zc1254_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1254_revA_defconfig @@ -39,6 +39,7 @@ CONFIG_MISC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/xilinx_zynqmp_zc1275_revA_defconfig b/configs/xilinx_zynqmp_zc1275_revA_defconfig index ef30979c28..75f940ed2a 100644 --- a/configs/xilinx_zynqmp_zc1275_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1275_revA_defconfig @@ -39,6 +39,7 @@ CONFIG_MISC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/xilinx_zynqmp_zc1275_revB_defconfig b/configs/xilinx_zynqmp_zc1275_revB_defconfig index 1910d21420..179b9e1a83 100644 --- a/configs/xilinx_zynqmp_zc1275_revB_defconfig +++ b/configs/xilinx_zynqmp_zc1275_revB_defconfig @@ -43,6 +43,7 @@ CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index 36093e9f2c..f4ece0ccc8 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -63,6 +63,7 @@ CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig index 82dc2cb311..c5dcf2e2dc 100644 --- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig @@ -49,6 +49,7 @@ CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/xilinx_zynqmp_zcu100_revC_defconfig b/configs/xilinx_zynqmp_zcu100_revC_defconfig index a33680fa9f..2fe5573e35 100644 --- a/configs/xilinx_zynqmp_zcu100_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu100_revC_defconfig @@ -59,6 +59,7 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig index 0fb634ff1a..ef61496407 100644 --- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig +++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig @@ -77,6 +77,7 @@ CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig index 62982b8204..8bf2697f7c 100644 --- a/configs/xilinx_zynqmp_zcu102_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig @@ -74,6 +74,7 @@ CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index 7320f0776b..bfb967767f 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -74,6 +74,7 @@ CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/xilinx_zynqmp_zcu104_revA_defconfig b/configs/xilinx_zynqmp_zcu104_revA_defconfig index c887bd6827..c981130c6d 100644 --- a/configs/xilinx_zynqmp_zcu104_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revA_defconfig @@ -59,6 +59,7 @@ CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/xilinx_zynqmp_zcu104_revC_defconfig b/configs/xilinx_zynqmp_zcu104_revC_defconfig index cd2e9b387b..4066868033 100644 --- a/configs/xilinx_zynqmp_zcu104_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revC_defconfig @@ -60,6 +60,7 @@ CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/xilinx_zynqmp_zcu106_revA_defconfig b/configs/xilinx_zynqmp_zcu106_revA_defconfig index b7b0762966..4df75f08db 100644 --- a/configs/xilinx_zynqmp_zcu106_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu106_revA_defconfig @@ -70,6 +70,7 @@ CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/xilinx_zynqmp_zcu111_revA_defconfig b/configs/xilinx_zynqmp_zcu111_revA_defconfig index b5f0e6bbe9..6654506a91 100644 --- a/configs/xilinx_zynqmp_zcu111_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu111_revA_defconfig @@ -61,6 +61,7 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y -- cgit From 871ad9253f95b95c98632887a18374009c5c3e67 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 15 Jan 2019 11:01:54 +0100 Subject: arm64: zynqmp: Enable FPGA_LOAD_SECURE command Enable fpga load secure feature for xilinx platforms. Signed-off-by: Michal Simek --- configs/xilinx_zynqmp_zc1232_revA_defconfig | 1 + configs/xilinx_zynqmp_zc1254_revA_defconfig | 1 + configs/xilinx_zynqmp_zc1275_revA_defconfig | 1 + configs/xilinx_zynqmp_zc1275_revB_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 1 + configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 + configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 + configs/xilinx_zynqmp_zcu104_revA_defconfig | 1 + configs/xilinx_zynqmp_zcu104_revC_defconfig | 1 + configs/xilinx_zynqmp_zcu106_revA_defconfig | 1 + configs/xilinx_zynqmp_zcu111_revA_defconfig | 1 + 15 files changed, 15 insertions(+) diff --git a/configs/xilinx_zynqmp_zc1232_revA_defconfig b/configs/xilinx_zynqmp_zc1232_revA_defconfig index 8c623130d9..b0d909cfde 100644 --- a/configs/xilinx_zynqmp_zc1232_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1232_revA_defconfig @@ -23,6 +23,7 @@ CONFIG_CMD_CLK=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_CMD_SF=y # CONFIG_CMD_NET is not set CONFIG_CMD_TIME=y diff --git a/configs/xilinx_zynqmp_zc1254_revA_defconfig b/configs/xilinx_zynqmp_zc1254_revA_defconfig index cbb167a57e..3049c97428 100644 --- a/configs/xilinx_zynqmp_zc1254_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1254_revA_defconfig @@ -23,6 +23,7 @@ CONFIG_CMD_CLK=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_CMD_SF=y # CONFIG_CMD_NET is not set CONFIG_CMD_TIME=y diff --git a/configs/xilinx_zynqmp_zc1275_revA_defconfig b/configs/xilinx_zynqmp_zc1275_revA_defconfig index 75f940ed2a..f76d580890 100644 --- a/configs/xilinx_zynqmp_zc1275_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1275_revA_defconfig @@ -23,6 +23,7 @@ CONFIG_CMD_CLK=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_CMD_SF=y # CONFIG_CMD_NET is not set CONFIG_CMD_TIME=y diff --git a/configs/xilinx_zynqmp_zc1275_revB_defconfig b/configs/xilinx_zynqmp_zc1275_revB_defconfig index 179b9e1a83..e8e32cbba1 100644 --- a/configs/xilinx_zynqmp_zc1275_revB_defconfig +++ b/configs/xilinx_zynqmp_zc1275_revB_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_CLK=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y # CONFIG_CMD_NET is not set diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index f4ece0ccc8..14c051a19e 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index 69ffa8e826..4fd4959970 100644 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig index c5c416b842..dab36e276a 100644 --- a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig index c5dcf2e2dc..2225a47487 100644 --- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig @@ -23,6 +23,7 @@ CONFIG_CMD_CLK=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig index 960cd18f12..b95db94d6c 100644 --- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_CLK=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_TFTPPUT=y diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig index 8bf2697f7c..26d2bdcddf 100644 --- a/configs/xilinx_zynqmp_zcu102_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig @@ -31,6 +31,7 @@ CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index bfb967767f..265fdda6ac 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -31,6 +31,7 @@ CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/xilinx_zynqmp_zcu104_revA_defconfig b/configs/xilinx_zynqmp_zcu104_revA_defconfig index c981130c6d..b4030a627b 100644 --- a/configs/xilinx_zynqmp_zcu104_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revA_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/xilinx_zynqmp_zcu104_revC_defconfig b/configs/xilinx_zynqmp_zcu104_revC_defconfig index 4066868033..ebf2bba746 100644 --- a/configs/xilinx_zynqmp_zcu104_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revC_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/xilinx_zynqmp_zcu106_revA_defconfig b/configs/xilinx_zynqmp_zcu106_revA_defconfig index 4df75f08db..3ad1f60e7c 100644 --- a/configs/xilinx_zynqmp_zcu106_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu106_revA_defconfig @@ -29,6 +29,7 @@ CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/xilinx_zynqmp_zcu111_revA_defconfig b/configs/xilinx_zynqmp_zcu111_revA_defconfig index 6654506a91..7ddb0c31c2 100644 --- a/configs/xilinx_zynqmp_zcu111_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu111_revA_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -- cgit From 5d93e886f85810cb758f685361e0755779488663 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 15 Jan 2019 12:00:52 +0100 Subject: arm64: zynqmp: Disable MMC for for zc12xx_revA boards All these boards have no SD enabled. Signed-off-by: Michal Simek --- configs/xilinx_zynqmp_zc1232_revA_defconfig | 2 +- configs/xilinx_zynqmp_zc1254_revA_defconfig | 2 +- configs/xilinx_zynqmp_zc1275_revA_defconfig | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/configs/xilinx_zynqmp_zc1232_revA_defconfig b/configs/xilinx_zynqmp_zc1232_revA_defconfig index b0d909cfde..0acf672a93 100644 --- a/configs/xilinx_zynqmp_zc1232_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1232_revA_defconfig @@ -32,11 +32,11 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1232-revA" CONFIG_SPL_DM=y -# CONFIG_BLK is not set CONFIG_CLK_ZYNQMP=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y CONFIG_MISC=y +# CONFIG_MMC is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y diff --git a/configs/xilinx_zynqmp_zc1254_revA_defconfig b/configs/xilinx_zynqmp_zc1254_revA_defconfig index 3049c97428..90985d6c92 100644 --- a/configs/xilinx_zynqmp_zc1254_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1254_revA_defconfig @@ -32,11 +32,11 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1254-revA" CONFIG_SPL_DM=y -# CONFIG_BLK is not set CONFIG_CLK_ZYNQMP=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y CONFIG_MISC=y +# CONFIG_MMC is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y diff --git a/configs/xilinx_zynqmp_zc1275_revA_defconfig b/configs/xilinx_zynqmp_zc1275_revA_defconfig index f76d580890..7d2bd2e53f 100644 --- a/configs/xilinx_zynqmp_zc1275_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1275_revA_defconfig @@ -32,11 +32,11 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revA" CONFIG_SPL_DM=y -# CONFIG_BLK is not set CONFIG_CLK_ZYNQMP=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y CONFIG_MISC=y +# CONFIG_MMC is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SF_DUAL_FLASH=y -- cgit From d9eaae3bae99cf79fd1453f4980b2624a6be9501 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 20 Dec 2018 08:40:25 +0100 Subject: travis: Wire Xilinx Versal Virt platform Test Xilinx Versal Virt platform running on the v3.1.0 Qemu. Signed-off-by: Michal Simek --- .travis.yml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/.travis.yml b/.travis.yml index 59e615abb2..49a7fa94f3 100644 --- a/.travis.yml +++ b/.travis.yml @@ -463,6 +463,13 @@ matrix: QEMU_TARGET="arm-softmmu" TEST_PY_ID="--id qemu" BUILDMAN="^zynq_zc702$" + - name: "test/py xilinx_versal_virt" + env: + - TEST_PY_BD="xilinx_versal_virt" + TEST_PY_TEST_SPEC="not sleep" + QEMU_TARGET="aarch64-softmmu" + TEST_PY_ID="--id qemu" + BUILDMAN="^xilinx_versal_virt$" - name: "test/py xtfpga" env: - TEST_PY_BD="xtfpga" -- cgit From 775ed87ac4015c8b17bc9d828e3bafe4a0f7ed03 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 14 Dec 2018 10:53:54 +0100 Subject: tools: zynqmpimage: Align image_size/image_stored_size Bootrom is not capable to work with non aligned bootloader sizes. SPL with OF_SEPARATE generates non-align images quite often that's why this change is required before OF_SEPARATE enableding. Signed-off-by: Michal Simek --- tools/zynqmpbif.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/zynqmpbif.c b/tools/zynqmpbif.c index a33c15e1f0..8c47107c7b 100644 --- a/tools/zynqmpbif.c +++ b/tools/zynqmpbif.c @@ -425,8 +425,8 @@ static int bif_add_part(struct bif_entry *bf, const char *data, size_t len) if (!bif_output.header->image_offset) bif_output.header->image_offset = cpu_to_le32(bf->offset); - bif_output.header->image_size = cpu_to_le32(len); - bif_output.header->image_stored_size = cpu_to_le32(len); + bif_output.header->image_size = cpu_to_le32(len_padded); + bif_output.header->image_stored_size = cpu_to_le32(len_padded); bif_output.header->image_attributes &= ~HEADER_CPU_SELECT_MASK; switch (bf->dest_cpu) { -- cgit From a903dcf7dee787320d7cfee969de322ac7a30ee1 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 16 Jan 2019 12:14:00 +0100 Subject: arm64: zynqmp: Align u-boot-spl.bin for boot.bin creation Bootrom is not capable to work with non align bootloader partition that's why it is necessary to align it before boot.bin creation. The patch is creating new spl/u-boot-spl-align.bin which is used only for boot.bin. Signed-off-by: Michal Simek Reviewed-by: Simon Glass --- scripts/Makefile.spl | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 29626e0025..e5b604e2d2 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -190,7 +190,10 @@ MKIMAGEFLAGS_boot.bin = -T zynqmpimage -R $(srctree)/$(CONFIG_BOOT_INIT_FILE) \ -n "$(shell cd $(srctree); readlink -f $(CONFIG_PMUFW_INIT_FILE))" endif -spl/boot.bin: $(obj)/u-boot-spl.bin FORCE +$(obj)/$(SPL_BIN)-align.bin: $(obj)/$(SPL_BIN).bin + @dd if=$< of=$@ conv=block,sync bs=4 2>/dev/null; + +spl/boot.bin: $(obj)/$(SPL_BIN)-align.bin FORCE $(call if_changed,mkimage) endif -- cgit From e9dc39915a5d20782f41ed49d0040e0cbf6db07c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 14 Dec 2018 11:13:11 +0100 Subject: arm64: zynqmp: Convert all reference boards to OF_SEPARATE Build warning was added by: "fdt: Add warning about CONFIG_OF_EMBED" (sha1: 841d5fbae4e993476fa87d8933db0cd58d3c2d41) ZynqMP mini configurations are not moved yet and it is questionable if make sense to move them too. Signed-off-by: Michal Simek --- configs/avnet_ultra96_rev1_defconfig | 1 - configs/xilinx_zynqmp_zc1232_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1254_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1275_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1275_revB_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 1 - configs/xilinx_zynqmp_zcu100_revC_defconfig | 1 - configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 - configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revC_defconfig | 1 - configs/xilinx_zynqmp_zcu106_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu111_revA_defconfig | 1 - 18 files changed, 18 deletions(-) diff --git a/configs/avnet_ultra96_rev1_defconfig b/configs/avnet_ultra96_rev1_defconfig index 77389732a6..896de78b34 100644 --- a/configs/avnet_ultra96_rev1_defconfig +++ b/configs/avnet_ultra96_rev1_defconfig @@ -39,7 +39,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="avnet-ultra96-rev1" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/xilinx_zynqmp_zc1232_revA_defconfig b/configs/xilinx_zynqmp_zc1232_revA_defconfig index 0acf672a93..983e61e48e 100644 --- a/configs/xilinx_zynqmp_zc1232_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1232_revA_defconfig @@ -29,7 +29,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1232-revA" CONFIG_SPL_DM=y CONFIG_CLK_ZYNQMP=y diff --git a/configs/xilinx_zynqmp_zc1254_revA_defconfig b/configs/xilinx_zynqmp_zc1254_revA_defconfig index 90985d6c92..10d3489b69 100644 --- a/configs/xilinx_zynqmp_zc1254_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1254_revA_defconfig @@ -29,7 +29,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1254-revA" CONFIG_SPL_DM=y CONFIG_CLK_ZYNQMP=y diff --git a/configs/xilinx_zynqmp_zc1275_revA_defconfig b/configs/xilinx_zynqmp_zc1275_revA_defconfig index 7d2bd2e53f..9ac3dd85f1 100644 --- a/configs/xilinx_zynqmp_zc1275_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1275_revA_defconfig @@ -29,7 +29,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revA" CONFIG_SPL_DM=y CONFIG_CLK_ZYNQMP=y diff --git a/configs/xilinx_zynqmp_zc1275_revB_defconfig b/configs/xilinx_zynqmp_zc1275_revB_defconfig index e8e32cbba1..c154b15871 100644 --- a/configs/xilinx_zynqmp_zc1275_revB_defconfig +++ b/configs/xilinx_zynqmp_zc1275_revB_defconfig @@ -31,7 +31,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revB" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index 14c051a19e..f2caac790a 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -40,7 +40,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1" CONFIG_ENV_IS_IN_FAT=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index 4fd4959970..bbbbb8ef4d 100644 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -39,7 +39,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig index dab36e276a..d91d511a3a 100644 --- a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig @@ -36,7 +36,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm017-dc3" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig index 2225a47487..10e0fca655 100644 --- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig @@ -32,7 +32,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4" CONFIG_ENV_IS_IN_FAT=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig index b95db94d6c..d14d6c4972 100644 --- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig @@ -32,7 +32,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5" CONFIG_ENV_IS_IN_FAT=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/xilinx_zynqmp_zcu100_revC_defconfig b/configs/xilinx_zynqmp_zcu100_revC_defconfig index 2fe5573e35..ca96b9ee2a 100644 --- a/configs/xilinx_zynqmp_zcu100_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu100_revC_defconfig @@ -39,7 +39,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig index ef61496407..30d3147a7a 100644 --- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig +++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig @@ -44,7 +44,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-rev1.0" CONFIG_ENV_IS_IN_FAT=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig index 26d2bdcddf..bada5e1173 100644 --- a/configs/xilinx_zynqmp_zcu102_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig @@ -44,7 +44,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revA" CONFIG_ENV_IS_IN_FAT=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index 265fdda6ac..3c4ac01b22 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -44,7 +44,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB" CONFIG_ENV_IS_IN_FAT=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/xilinx_zynqmp_zcu104_revA_defconfig b/configs/xilinx_zynqmp_zcu104_revA_defconfig index b4030a627b..90fd431df3 100644 --- a/configs/xilinx_zynqmp_zcu104_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revA_defconfig @@ -38,7 +38,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu104-revA" CONFIG_ENV_IS_IN_FAT=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/xilinx_zynqmp_zcu104_revC_defconfig b/configs/xilinx_zynqmp_zcu104_revC_defconfig index ebf2bba746..eb30e2398f 100644 --- a/configs/xilinx_zynqmp_zcu104_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revC_defconfig @@ -38,7 +38,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu104-revC" CONFIG_ENV_IS_IN_FAT=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/xilinx_zynqmp_zcu106_revA_defconfig b/configs/xilinx_zynqmp_zcu106_revA_defconfig index 3ad1f60e7c..9e8eb5f483 100644 --- a/configs/xilinx_zynqmp_zcu106_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu106_revA_defconfig @@ -41,7 +41,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu106-revA" CONFIG_ENV_IS_IN_FAT=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/xilinx_zynqmp_zcu111_revA_defconfig b/configs/xilinx_zynqmp_zcu111_revA_defconfig index 7ddb0c31c2..b8e96042da 100644 --- a/configs/xilinx_zynqmp_zcu111_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu111_revA_defconfig @@ -37,7 +37,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu111-revA" CONFIG_ENV_IS_IN_FAT=y CONFIG_NET_RANDOM_ETHADDR=y -- cgit From e2321f0b3c7832616def7b27e10032951e005307 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 22 Jan 2019 14:34:12 +0530 Subject: arm: zynq: Enable CONFIG_REMAKE_ELF This patch enables CONFIG_REMAKE_ELF for Zynq platform so that it generates u-boot.elf from binary which works for all Zynq boards with OF_SEPARATE option enabled. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- include/configs/zynq-common.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 864f3220f3..1710feda91 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -14,6 +14,8 @@ # define CONFIG_CPU_FREQ_HZ 800000000 #endif +#define CONFIG_REMAKE_ELF + /* Cache options */ #define CONFIG_SYS_L2CACHE_OFF #ifndef CONFIG_SYS_L2CACHE_OFF -- cgit From 495c7303a9c3d6a1803cece87978dc99302701da Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 15 Jan 2019 14:02:32 +0100 Subject: ARM: zynq: Convert all boards to OF_SEPARATE Build warning was added by: "fdt: Add warning about CONFIG_OF_EMBED" (sha1: 841d5fbae4e993476fa87d8933db0cd58d3c2d41) Zynq mini configurations are not moved yet and it is questionable if make sense to move them too. Signed-off-by: Michal Simek --- configs/syzygy_hub_defconfig | 1 - configs/zynq_dlc20_rev1_0_defconfig | 1 - 2 files changed, 2 deletions(-) diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig index c4bca0636f..75139d93b3 100644 --- a/configs/syzygy_hub_defconfig +++ b/configs/syzygy_hub_defconfig @@ -31,7 +31,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynq-syzygy-hub" CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_FPGA_XILINX=y diff --git a/configs/zynq_dlc20_rev1_0_defconfig b/configs/zynq_dlc20_rev1_0_defconfig index e39bd131ff..7ead19208f 100644 --- a/configs/zynq_dlc20_rev1_0_defconfig +++ b/configs/zynq_dlc20_rev1_0_defconfig @@ -35,7 +35,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynq-dlc20-rev1.0" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y -- cgit From 274ccb5b1175e1d87a5b2eaf2f82826b079382b5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 17 Jan 2019 08:22:43 +0100 Subject: arm64: zynqmp: Move SoC sources to mach-zynqmp Similar changes was done for Zynq in past and this patch just follow this pattern to separate cpu code from SoC code. Move arch/arm/cpu/armv8/zynqmp/* -> arch/arm/mach-zynqmp/* And also fix references to these files. Based on "ARM: zynq: move SoC sources to mach-zynq" (sha1: 0107f2403669f764ab726d0d404e35bb9447bbcc) Signed-off-by: Michal Simek --- MAINTAINERS | 2 +- arch/arm/Kconfig | 4 +- arch/arm/Makefile | 1 + arch/arm/cpu/armv8/Makefile | 1 - arch/arm/cpu/armv8/zynqmp/Kconfig | 156 ------------ arch/arm/cpu/armv8/zynqmp/Makefile | 10 - arch/arm/cpu/armv8/zynqmp/clk.c | 45 ---- arch/arm/cpu/armv8/zynqmp/cpu.c | 260 -------------------- arch/arm/cpu/armv8/zynqmp/handoff.c | 86 ------- arch/arm/cpu/armv8/zynqmp/mp.c | 297 ----------------------- arch/arm/cpu/armv8/zynqmp/psu_spl_init.c | 79 ------ arch/arm/cpu/armv8/zynqmp/spl.c | 134 ---------- arch/arm/include/asm/arch-zynqmp/clk.h | 12 - arch/arm/include/asm/arch-zynqmp/gpio.h | 11 - arch/arm/include/asm/arch-zynqmp/hardware.h | 159 ------------ arch/arm/include/asm/arch-zynqmp/psu_init_gpl.h | 25 -- arch/arm/include/asm/arch-zynqmp/sys_proto.h | 75 ------ arch/arm/mach-k3/arm64-mmu.c | 2 +- arch/arm/mach-tegra/arm64-mmu.c | 2 +- arch/arm/mach-zynqmp/Kconfig | 156 ++++++++++++ arch/arm/mach-zynqmp/Makefile | 10 + arch/arm/mach-zynqmp/clk.c | 45 ++++ arch/arm/mach-zynqmp/cpu.c | 260 ++++++++++++++++++++ arch/arm/mach-zynqmp/handoff.c | 86 +++++++ arch/arm/mach-zynqmp/include/mach/clk.h | 12 + arch/arm/mach-zynqmp/include/mach/gpio.h | 11 + arch/arm/mach-zynqmp/include/mach/hardware.h | 159 ++++++++++++ arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h | 25 ++ arch/arm/mach-zynqmp/include/mach/sys_proto.h | 75 ++++++ arch/arm/mach-zynqmp/mp.c | 297 +++++++++++++++++++++++ arch/arm/mach-zynqmp/psu_spl_init.c | 79 ++++++ arch/arm/mach-zynqmp/spl.c | 134 ++++++++++ 32 files changed, 1355 insertions(+), 1355 deletions(-) delete mode 100644 arch/arm/cpu/armv8/zynqmp/Kconfig delete mode 100644 arch/arm/cpu/armv8/zynqmp/Makefile delete mode 100644 arch/arm/cpu/armv8/zynqmp/clk.c delete mode 100644 arch/arm/cpu/armv8/zynqmp/cpu.c delete mode 100644 arch/arm/cpu/armv8/zynqmp/handoff.c delete mode 100644 arch/arm/cpu/armv8/zynqmp/mp.c delete mode 100644 arch/arm/cpu/armv8/zynqmp/psu_spl_init.c delete mode 100644 arch/arm/cpu/armv8/zynqmp/spl.c delete mode 100644 arch/arm/include/asm/arch-zynqmp/clk.h delete mode 100644 arch/arm/include/asm/arch-zynqmp/gpio.h delete mode 100644 arch/arm/include/asm/arch-zynqmp/hardware.h delete mode 100644 arch/arm/include/asm/arch-zynqmp/psu_init_gpl.h delete mode 100644 arch/arm/include/asm/arch-zynqmp/sys_proto.h create mode 100644 arch/arm/mach-zynqmp/Kconfig create mode 100644 arch/arm/mach-zynqmp/Makefile create mode 100644 arch/arm/mach-zynqmp/clk.c create mode 100644 arch/arm/mach-zynqmp/cpu.c create mode 100644 arch/arm/mach-zynqmp/handoff.c create mode 100644 arch/arm/mach-zynqmp/include/mach/clk.h create mode 100644 arch/arm/mach-zynqmp/include/mach/gpio.h create mode 100644 arch/arm/mach-zynqmp/include/mach/hardware.h create mode 100644 arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h create mode 100644 arch/arm/mach-zynqmp/include/mach/sys_proto.h create mode 100644 arch/arm/mach-zynqmp/mp.c create mode 100644 arch/arm/mach-zynqmp/psu_spl_init.c create mode 100644 arch/arm/mach-zynqmp/spl.c diff --git a/MAINTAINERS b/MAINTAINERS index 1cb092e539..ecac867950 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -362,7 +362,7 @@ ARM ZYNQMP M: Michal Simek S: Maintained T: git git://git.denx.de/u-boot-microblaze.git -F: arch/arm/cpu/armv8/zynqmp/ +F: arch/arm/mach-zynqmp/ F: drivers/clk/clk_zynqmp.c F: drivers/fpga/zynqpl.c F: drivers/gpio/zynq_gpio.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a65e0c5211..2298e6e7d7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1503,14 +1503,14 @@ source "arch/arm/cpu/armv7/vf610/Kconfig" source "arch/arm/mach-zynq/Kconfig" +source "arch/arm/mach-zynqmp/Kconfig" + source "arch/arm/mach-versal/Kconfig" source "arch/arm/mach-zynqmp-r5/Kconfig" source "arch/arm/cpu/armv7/Kconfig" -source "arch/arm/cpu/armv8/zynqmp/Kconfig" - source "arch/arm/cpu/armv8/Kconfig" source "arch/arm/mach-imx/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 87d9d4b9f7..817302523a 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -81,6 +81,7 @@ machine-$(CONFIG_ARCH_STM32MP) += stm32mp machine-$(CONFIG_TEGRA) += tegra machine-$(CONFIG_ARCH_UNIPHIER) += uniphier machine-$(CONFIG_ARCH_ZYNQ) += zynq +machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp machine-$(CONFIG_ARCH_VERSAL) += versal machine-$(CONFIG_ARCH_ZYNQMP_R5) += zynqmp-r5 diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index 52c8daa049..4c4b13c9e7 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -29,7 +29,6 @@ obj-$(CONFIG_$(SPL_)ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_a obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/ obj-$(CONFIG_S32V234) += s32v234/ -obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/ obj-$(CONFIG_TARGET_HIKEY) += hisilicon/ obj-$(CONFIG_ARMV8_PSCI) += psci.o obj-$(CONFIG_ARCH_SUNXI) += lowlevel_init.o diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig deleted file mode 100644 index 8a311e1c89..0000000000 --- a/arch/arm/cpu/armv8/zynqmp/Kconfig +++ /dev/null @@ -1,156 +0,0 @@ -if ARCH_ZYNQMP - -config SPL_FAT_SUPPORT - default y - -config SPL_LIBCOMMON_SUPPORT - default y - -config SPL_LIBDISK_SUPPORT - default y - -config SPL_LIBGENERIC_SUPPORT - default y - -config SPL_MMC_SUPPORT - default y if MMC_SDHCI_ZYNQ - -config SPL_SERIAL_SUPPORT - default y - -config SPL_SPI_FLASH_SUPPORT - default y if ZYNQ_QSPI - -config SPL_SPI_SUPPORT - default y if ZYNQ_QSPI - -config SYS_BOARD - default "zynqmp" - -config SYS_VENDOR - string "Vendor name" - default "xilinx" - -config SYS_SOC - default "zynqmp" - -config SYS_CONFIG_NAME - string "Board configuration name" - default "xilinx_zynqmp" - help - This option contains information about board configuration name. - Based on this option include/configs/.h header - will be used for board configuration. - -config SYS_MEM_RSVD_FOR_MMU - bool "Reserve memory for MMU Table" - help - If defined this option is used to setup different space for - MMU table than the one which will be allocated during - relocation. - -config BOOT_INIT_FILE - string "boot.bin init register filename" - depends on SPL - default "" - help - Add register writes to boot.bin format (max 256 pairs). - Expect a table of register-value pairs, e.g. "0x12345678 0x4321" - -config PMUFW_INIT_FILE - string "PMU firmware" - depends on SPL - default "" - help - Include external PMUFW (Platform Management Unit FirmWare) to - a Xilinx bootable image (boot.bin). - -config ZYNQMP_USB - bool "Configure ZynqMP USB" - -config ZYNQMP_NO_DDR - bool "Disable DDR MMU mapping" - help - This option configures MMU with no DDR to avoid speculative - access to DDR memory where DDR is not present. - -config SYS_MALLOC_F_LEN - default 0x600 - -config DEFINE_TCM_OCM_MMAP - bool "Define TCM and OCM memory in MMU Table" - default y if MP - help - This option if enabled defines the TCM and OCM memory and its - memory attributes in MMU table entry. - -config ZYNQMP_PSU_INIT_ENABLED - bool "Include psu_init" - help - Include psu_init to full u-boot. SPL include psu_init by default. - -config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED - bool "Overwrite SPL bootmode" - depends on SPL - help - Overwrite bootmode selected via boot mode pins to tell SPL what should - be the next boot device. - -config ZYNQ_SDHCI_MAX_FREQ - default 200000000 - -config SPL_ZYNQMP_ALT_BOOTMODE - hex - default 0x0 if JTAG_MODE - default 0x1 if QSPI_MODE_24BIT - default 0x2 if QSPI_MODE_32BIT - default 0x3 if SD_MODE - default 0x4 if NAND_MODE - default 0x5 if SD_MODE1 - default 0x6 if EMMC_MODE - default 0x7 if USB_MODE - default 0xa if SW_USBHOST_MODE - default 0xb if SW_SATA_MODE - default 0xe if SD1_LSHFT_MODE - -choice - prompt "Boot mode" - depends on SPL_ZYNQMP_ALT_BOOTMODE_ENABLED - default JTAG_MODE - -config JTAG_MODE - bool "JTAG_MODE" - -config QSPI_MODE_24BIT - bool "QSPI_MODE_24BIT" - -config QSPI_MODE_32BIT - bool "QSPI_MODE_32BIT" - -config SD_MODE - bool "SD_MODE" - -config SD_MODE1 - bool "SD_MODE1" - -config NAND_MODE - bool "NAND_MODE" - -config EMMC_MODE - bool "EMMC_MODE" - -config USB_MODE - bool "USB" - -config SW_USBHOST_MODE - bool "SW USBHOST_MODE" - -config SW_SATA_MODE - bool "SW SATA_MODE" - -config SD1_LSHFT_MODE - bool "SD1_LSHFT_MODE" - -endchoice - -endif diff --git a/arch/arm/cpu/armv8/zynqmp/Makefile b/arch/arm/cpu/armv8/zynqmp/Makefile deleted file mode 100644 index 8a3b074724..0000000000 --- a/arch/arm/cpu/armv8/zynqmp/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2014 - 2015 Xilinx, Inc. -# Michal Simek - -obj-y += clk.o -obj-y += cpu.o -obj-$(CONFIG_MP) += mp.o -obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o -obj-$(CONFIG_ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o diff --git a/arch/arm/cpu/armv8/zynqmp/clk.c b/arch/arm/cpu/armv8/zynqmp/clk.c deleted file mode 100644 index 0593b6310f..0000000000 --- a/arch/arm/cpu/armv8/zynqmp/clk.c +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -unsigned long zynqmp_get_system_timer_freq(void) -{ - u32 ver = zynqmp_get_silicon_version(); - - switch (ver) { - case ZYNQMP_CSU_VERSION_QEMU: - return 50000000; - } - - return 100000000; -} - -#ifdef CONFIG_CLOCKS -/** - * set_cpu_clk_info() - Initialize clock framework - * Always returns zero. - * - * This function is called from common code after relocation and sets up the - * clock framework. The framework must not be used before this function had been - * called. - */ -int set_cpu_clk_info(void) -{ - gd->cpu_clk = get_tbclk(); - - gd->bd->bi_arm_freq = gd->cpu_clk / 1000000; - - gd->bd->bi_dsp_freq = 0; - - return 0; -} -#endif diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c deleted file mode 100644 index 5ef1a52862..0000000000 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ /dev/null @@ -1,260 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek - */ - -#include -#include -#include -#include -#include - -#define ZYNQ_SILICON_VER_MASK 0xF000 -#define ZYNQ_SILICON_VER_SHIFT 12 - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Number of filled static entries and also the first empty - * slot in zynqmp_mem_map. - */ -#define ZYNQMP_MEM_MAP_USED 4 - -#if !defined(CONFIG_ZYNQMP_NO_DDR) -#define DRAM_BANKS CONFIG_NR_DRAM_BANKS -#else -#define DRAM_BANKS 0 -#endif - -#if defined(CONFIG_DEFINE_TCM_OCM_MMAP) -#define TCM_MAP 1 -#else -#define TCM_MAP 0 -#endif - -/* +1 is end of list which needs to be empty */ -#define ZYNQMP_MEM_MAP_MAX (ZYNQMP_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1) - -static struct mm_region zynqmp_mem_map[ZYNQMP_MEM_MAP_MAX] = { - { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x70000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0xf8000000UL, - .phys = 0xf8000000UL, - .size = 0x07e00000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x400000000UL, - .phys = 0x400000000UL, - .size = 0x400000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x1000000000UL, - .phys = 0x1000000000UL, - .size = 0xf000000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - } -}; - -void mem_map_fill(void) -{ - int banks = ZYNQMP_MEM_MAP_USED; - -#if defined(CONFIG_DEFINE_TCM_OCM_MMAP) - zynqmp_mem_map[banks].virt = 0xffe00000UL; - zynqmp_mem_map[banks].phys = 0xffe00000UL; - zynqmp_mem_map[banks].size = 0x00200000UL; - zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE; - banks = banks + 1; -#endif - -#if !defined(CONFIG_ZYNQMP_NO_DDR) - for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - /* Zero size means no more DDR that's this is end */ - if (!gd->bd->bi_dram[i].size) - break; - - zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start; - zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start; - zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size; - zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE; - banks = banks + 1; - } -#endif -} - -struct mm_region *mem_map = zynqmp_mem_map; - -u64 get_page_table_size(void) -{ - return 0x14000; -} - -#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP) -void tcm_init(u8 mode) -{ - puts("WARNING: Initializing TCM overwrites TCM content\n"); - initialize_tcm(mode); - memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE); -} -#endif - -#ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU -int reserve_mmu(void) -{ - tcm_init(TCM_LOCK); - gd->arch.tlb_size = PGTABLE_SIZE; - gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR; - - return 0; -} -#endif - -static unsigned int zynqmp_get_silicon_version_secure(void) -{ - u32 ver; - - ver = readl(&csu_base->version); - ver &= ZYNQMP_SILICON_VER_MASK; - ver >>= ZYNQMP_SILICON_VER_SHIFT; - - return ver; -} - -unsigned int zynqmp_get_silicon_version(void) -{ - if (current_el() == 3) - return zynqmp_get_silicon_version_secure(); - - gd->cpu_clk = get_tbclk(); - - switch (gd->cpu_clk) { - case 50000000: - return ZYNQMP_CSU_VERSION_QEMU; - } - - return ZYNQMP_CSU_VERSION_SILICON; -} - -#define ZYNQMP_MMIO_READ 0xC2000014 -#define ZYNQMP_MMIO_WRITE 0xC2000013 - -int __maybe_unused invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, - u32 arg3, u32 *ret_payload) -{ - /* - * Added SIP service call Function Identifier - * Make sure to stay in x0 register - */ - struct pt_regs regs; - - regs.regs[0] = pm_api_id; - regs.regs[1] = ((u64)arg1 << 32) | arg0; - regs.regs[2] = ((u64)arg3 << 32) | arg2; - - smc_call(®s); - - if (ret_payload != NULL) { - ret_payload[0] = (u32)regs.regs[0]; - ret_payload[1] = upper_32_bits(regs.regs[0]); - ret_payload[2] = (u32)regs.regs[1]; - ret_payload[3] = upper_32_bits(regs.regs[1]); - ret_payload[4] = (u32)regs.regs[2]; - } - - return regs.regs[0]; -} - -unsigned int __maybe_unused zynqmp_pmufw_version(void) -{ - int ret; - u32 ret_payload[PAYLOAD_ARG_CNT]; - static u32 pm_api_version = ZYNQMP_PM_VERSION_INVALID; - - /* - * Get PMU version only once and later - * just return stored values instead of - * asking PMUFW again. - */ - if (pm_api_version == ZYNQMP_PM_VERSION_INVALID) { - ret = invoke_smc(ZYNQMP_SIP_SVC_GET_API_VERSION, 0, 0, 0, 0, - ret_payload); - pm_api_version = ret_payload[1]; - - if (ret) - panic("PMUFW is not found - Please load it!\n"); - } - - return pm_api_version; -} - -static int zynqmp_mmio_rawwrite(const u32 address, - const u32 mask, - const u32 value) -{ - u32 data; - u32 value_local = value; - int ret; - - ret = zynqmp_mmio_read(address, &data); - if (ret) - return ret; - - data &= ~mask; - value_local &= mask; - value_local |= data; - writel(value_local, (ulong)address); - return 0; -} - -static int zynqmp_mmio_rawread(const u32 address, u32 *value) -{ - *value = readl((ulong)address); - return 0; -} - -int zynqmp_mmio_write(const u32 address, - const u32 mask, - const u32 value) -{ - if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) - return zynqmp_mmio_rawwrite(address, mask, value); - else - return invoke_smc(ZYNQMP_MMIO_WRITE, address, mask, - value, 0, NULL); - - return -EINVAL; -} - -int zynqmp_mmio_read(const u32 address, u32 *value) -{ - u32 ret_payload[PAYLOAD_ARG_CNT]; - u32 ret; - - if (!value) - return -EINVAL; - - if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) { - ret = zynqmp_mmio_rawread(address, value); - } else { - ret = invoke_smc(ZYNQMP_MMIO_READ, address, 0, 0, - 0, ret_payload); - *value = ret_payload[1]; - } - - return ret; -} diff --git a/arch/arm/cpu/armv8/zynqmp/handoff.c b/arch/arm/cpu/armv8/zynqmp/handoff.c deleted file mode 100644 index f71ff7b3d2..0000000000 --- a/arch/arm/cpu/armv8/zynqmp/handoff.c +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2016 - 2017 Xilinx, Inc. - * - * Michal Simek - */ - -#include -#include -#include -#include - -/* - * atfhandoffparams - * Parameter bitfield encoding - * ----------------------------------------------------------------------------- - * Exec State 0 0 -> Aarch64, 1-> Aarch32 - * endianness 1 0 -> LE, 1 -> BE - * secure (TZ) 2 0 -> Non secure, 1 -> secure - * EL 3:4 00 -> EL0, 01 -> EL1, 10 -> EL2, 11 -> EL3 - * CPU# 5:6 00 -> A53_0, 01 -> A53_1, 10 -> A53_2, 11 -> A53_3 - */ - -#define FSBL_FLAGS_ESTATE_SHIFT 0 -#define FSBL_FLAGS_ESTATE_MASK (1 << FSBL_FLAGS_ESTATE_SHIFT) -#define FSBL_FLAGS_ESTATE_A64 0 -#define FSBL_FLAGS_ESTATE_A32 1 - -#define FSBL_FLAGS_ENDIAN_SHIFT 1 -#define FSBL_FLAGS_ENDIAN_MASK (1 << FSBL_FLAGS_ENDIAN_SHIFT) -#define FSBL_FLAGS_ENDIAN_LE 0 -#define FSBL_FLAGS_ENDIAN_BE 1 - -#define FSBL_FLAGS_TZ_SHIFT 2 -#define FSBL_FLAGS_TZ_MASK (1 << FSBL_FLAGS_TZ_SHIFT) -#define FSBL_FLAGS_NON_SECURE 0 -#define FSBL_FLAGS_SECURE 1 - -#define FSBL_FLAGS_EL_SHIFT 3 -#define FSBL_FLAGS_EL_MASK (3 << FSBL_FLAGS_EL_SHIFT) -#define FSBL_FLAGS_EL0 0 -#define FSBL_FLAGS_EL1 1 -#define FSBL_FLAGS_EL2 2 -#define FSBL_FLAGS_EL3 3 - -#define FSBL_FLAGS_CPU_SHIFT 5 -#define FSBL_FLAGS_CPU_MASK (3 << FSBL_FLAGS_CPU_SHIFT) -#define FSBL_FLAGS_A53_0 0 -#define FSBL_FLAGS_A53_1 1 -#define FSBL_FLAGS_A53_2 2 -#define FSBL_FLAGS_A53_3 3 - -#define FSBL_MAX_PARTITIONS 8 - -/* Structure corresponding to each partition entry */ -struct xfsbl_partition { - uint64_t entry_point; - uint64_t flags; -}; - -/* Structure for handoff parameters to ARM Trusted Firmware (ATF) */ -struct xfsbl_atf_handoff_params { - uint8_t magic[4]; - uint32_t num_entries; - struct xfsbl_partition partition[FSBL_MAX_PARTITIONS]; -}; - -#ifdef CONFIG_SPL_OS_BOOT -void handoff_setup(void) -{ - struct xfsbl_atf_handoff_params *atfhandoffparams; - - atfhandoffparams = (void *)CONFIG_SPL_TEXT_BASE; - atfhandoffparams->magic[0] = 'X'; - atfhandoffparams->magic[1] = 'L'; - atfhandoffparams->magic[2] = 'N'; - atfhandoffparams->magic[3] = 'X'; - - atfhandoffparams->num_entries = 1; - atfhandoffparams->partition[0].entry_point = CONFIG_SYS_TEXT_BASE; - atfhandoffparams->partition[0].flags = FSBL_FLAGS_EL2 << - FSBL_FLAGS_EL_SHIFT; - - writel(CONFIG_SPL_TEXT_BASE, &pmu_base->gen_storage6); -} -#endif diff --git a/arch/arm/cpu/armv8/zynqmp/mp.c b/arch/arm/cpu/armv8/zynqmp/mp.c deleted file mode 100644 index 2a71870ae7..0000000000 --- a/arch/arm/cpu/armv8/zynqmp/mp.c +++ /dev/null @@ -1,297 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek - */ - -#include -#include -#include -#include - -#define LOCK 0 -#define SPLIT 1 - -#define HALT 0 -#define RELEASE 1 - -#define ZYNQMP_BOOTADDR_HIGH_MASK 0xFFFFFFFF -#define ZYNQMP_R5_HIVEC_ADDR 0xFFFF0000 -#define ZYNQMP_R5_LOVEC_ADDR 0x0 -#define ZYNQMP_RPU_CFG_CPU_HALT_MASK 0x01 -#define ZYNQMP_RPU_CFG_HIVEC_MASK 0x04 -#define ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK 0x08 -#define ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK 0x40 -#define ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK 0x10 - -#define ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK 0x04 -#define ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK 0x01 -#define ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK 0x02 -#define ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK 0x1000000 - -#define ZYNQMP_TCM_START_ADDRESS 0xFFE00000 -#define ZYNQMP_TCM_BOTH_SIZE 0x40000 - -#define ZYNQMP_CORE_APU0 0 -#define ZYNQMP_CORE_APU3 3 - -#define ZYNQMP_MAX_CORES 6 - -int is_core_valid(unsigned int core) -{ - if (core < ZYNQMP_MAX_CORES) - return 1; - - return 0; -} - -int cpu_reset(u32 nr) -{ - puts("Feature is not implemented.\n"); - return 0; -} - -static void set_r5_halt_mode(u8 halt, u8 mode) -{ - u32 tmp; - - tmp = readl(&rpu_base->rpu0_cfg); - if (halt == HALT) - tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK; - else - tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK; - writel(tmp, &rpu_base->rpu0_cfg); - - if (mode == LOCK) { - tmp = readl(&rpu_base->rpu1_cfg); - if (halt == HALT) - tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK; - else - tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK; - writel(tmp, &rpu_base->rpu1_cfg); - } -} - -static void set_r5_tcm_mode(u8 mode) -{ - u32 tmp; - - tmp = readl(&rpu_base->rpu_glbl_ctrl); - if (mode == LOCK) { - tmp &= ~ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK; - tmp |= ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK | - ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK; - } else { - tmp |= ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK; - tmp &= ~(ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK | - ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK); - } - - writel(tmp, &rpu_base->rpu_glbl_ctrl); -} - -static void set_r5_reset(u8 mode) -{ - u32 tmp; - - tmp = readl(&crlapb_base->rst_lpd_top); - tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | - ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK); - - if (mode == LOCK) - tmp |= ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK; - - writel(tmp, &crlapb_base->rst_lpd_top); -} - -static void release_r5_reset(u8 mode) -{ - u32 tmp; - - tmp = readl(&crlapb_base->rst_lpd_top); - tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | - ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK); - - if (mode == LOCK) - tmp &= ~ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK; - - writel(tmp, &crlapb_base->rst_lpd_top); -} - -static void enable_clock_r5(void) -{ - u32 tmp; - - tmp = readl(&crlapb_base->cpu_r5_ctrl); - tmp |= ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK; - writel(tmp, &crlapb_base->cpu_r5_ctrl); - - /* Give some delay for clock - * to propagate */ - udelay(0x500); -} - -int cpu_disable(u32 nr) -{ - if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) { - u32 val = readl(&crfapb_base->rst_fpd_apu); - val |= 1 << nr; - writel(val, &crfapb_base->rst_fpd_apu); - } else { - set_r5_reset(LOCK); - } - - return 0; -} - -int cpu_status(u32 nr) -{ - if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) { - u32 addr_low = readl(((u8 *)&apu_base->rvbar_addr0_l) + nr * 8); - u32 addr_high = readl(((u8 *)&apu_base->rvbar_addr0_h) + - nr * 8); - u32 val = readl(&crfapb_base->rst_fpd_apu); - val &= 1 << nr; - printf("APU CPU%d %s - starting address HI: %x, LOW: %x\n", - nr, val ? "OFF" : "ON" , addr_high, addr_low); - } else { - u32 val = readl(&crlapb_base->rst_lpd_top); - val &= 1 << (nr - 4); - printf("RPU CPU%d %s\n", nr - 4, val ? "OFF" : "ON"); - } - - return 0; -} - -static void set_r5_start(u8 high) -{ - u32 tmp; - - tmp = readl(&rpu_base->rpu0_cfg); - if (high) - tmp |= ZYNQMP_RPU_CFG_HIVEC_MASK; - else - tmp &= ~ZYNQMP_RPU_CFG_HIVEC_MASK; - writel(tmp, &rpu_base->rpu0_cfg); - - tmp = readl(&rpu_base->rpu1_cfg); - if (high) - tmp |= ZYNQMP_RPU_CFG_HIVEC_MASK; - else - tmp &= ~ZYNQMP_RPU_CFG_HIVEC_MASK; - writel(tmp, &rpu_base->rpu1_cfg); -} - -static void write_tcm_boot_trampoline(u32 boot_addr) -{ - if (boot_addr) { - /* - * Boot trampoline is simple ASM code below. - * - * b over; - * label: - * .word 0 - * over: ldr r0, =label - * ldr r1, [r0] - * bx r1 - */ - debug("Write boot trampoline for %x\n", boot_addr); - writel(0xea000000, ZYNQMP_TCM_START_ADDRESS); - writel(boot_addr, ZYNQMP_TCM_START_ADDRESS + 0x4); - writel(0xe59f0004, ZYNQMP_TCM_START_ADDRESS + 0x8); - writel(0xe5901000, ZYNQMP_TCM_START_ADDRESS + 0xc); - writel(0xe12fff11, ZYNQMP_TCM_START_ADDRESS + 0x10); - writel(0x00000004, ZYNQMP_TCM_START_ADDRESS + 0x14); // address for - } -} - -void initialize_tcm(bool mode) -{ - if (!mode) { - set_r5_tcm_mode(LOCK); - set_r5_halt_mode(HALT, LOCK); - enable_clock_r5(); - release_r5_reset(LOCK); - } else { - set_r5_tcm_mode(SPLIT); - set_r5_halt_mode(HALT, SPLIT); - enable_clock_r5(); - release_r5_reset(SPLIT); - } -} - -int cpu_release(u32 nr, int argc, char * const argv[]) -{ - if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) { - u64 boot_addr = simple_strtoull(argv[0], NULL, 16); - /* HIGH */ - writel((u32)(boot_addr >> 32), - ((u8 *)&apu_base->rvbar_addr0_h) + nr * 8); - /* LOW */ - writel((u32)(boot_addr & ZYNQMP_BOOTADDR_HIGH_MASK), - ((u8 *)&apu_base->rvbar_addr0_l) + nr * 8); - - u32 val = readl(&crfapb_base->rst_fpd_apu); - val &= ~(1 << nr); - writel(val, &crfapb_base->rst_fpd_apu); - } else { - if (argc != 2) { - printf("Invalid number of arguments to release.\n"); - printf(" -Start addr lockstep or split\n"); - return 1; - } - - u32 boot_addr = simple_strtoul(argv[0], NULL, 16); - u32 boot_addr_uniq = 0; - if (!(boot_addr == ZYNQMP_R5_LOVEC_ADDR || - boot_addr == ZYNQMP_R5_HIVEC_ADDR)) { - printf("Using TCM jump trampoline for address 0x%x\n", - boot_addr); - /* Save boot address for later usage */ - boot_addr_uniq = boot_addr; - /* - * R5 needs to start from LOVEC at TCM - * OCM will be probably occupied by ATF - */ - boot_addr = ZYNQMP_R5_LOVEC_ADDR; - } - - /* - * Since we don't know where the user may have loaded the image - * for an R5 we have to flush all the data cache to ensure - * the R5 sees it. - */ - flush_dcache_all(); - - if (!strncmp(argv[1], "lockstep", 8)) { - printf("R5 lockstep mode\n"); - set_r5_reset(LOCK); - set_r5_tcm_mode(LOCK); - set_r5_halt_mode(HALT, LOCK); - set_r5_start(boot_addr); - enable_clock_r5(); - release_r5_reset(LOCK); - dcache_disable(); - write_tcm_boot_trampoline(boot_addr_uniq); - dcache_enable(); - set_r5_halt_mode(RELEASE, LOCK); - } else if (!strncmp(argv[1], "split", 5)) { - printf("R5 split mode\n"); - set_r5_reset(SPLIT); - set_r5_tcm_mode(SPLIT); - set_r5_halt_mode(HALT, SPLIT); - set_r5_start(boot_addr); - enable_clock_r5(); - release_r5_reset(SPLIT); - dcache_disable(); - write_tcm_boot_trampoline(boot_addr_uniq); - dcache_enable(); - set_r5_halt_mode(RELEASE, SPLIT); - } else { - printf("Unsupported mode\n"); - return 1; - } - } - - return 0; -} diff --git a/arch/arm/cpu/armv8/zynqmp/psu_spl_init.c b/arch/arm/cpu/armv8/zynqmp/psu_spl_init.c deleted file mode 100644 index b357de3235..0000000000 --- a/arch/arm/cpu/armv8/zynqmp/psu_spl_init.c +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018 Xilinx, Inc. - * - * Michal Simek - */ -#include -#include -#include - -#define PSU_MASK_POLL_TIME 1100000 - -int __maybe_unused mask_pollonvalue(unsigned long add, u32 mask, u32 value) -{ - int i = 0; - - while ((__raw_readl(add) & mask) != value) { - if (i == PSU_MASK_POLL_TIME) - return 0; - i++; - } - return 1; -} - -__weak int mask_poll(u32 add, u32 mask) -{ - int i = 0; - unsigned long addr = add; - - while (!(__raw_readl(addr) & mask)) { - if (i == PSU_MASK_POLL_TIME) - return 0; - i++; - } - return 1; -} - -__weak u32 mask_read(u32 add, u32 mask) -{ - unsigned long addr = add; - - return __raw_readl(addr) & mask; -} - -__weak void mask_delay(u32 delay) -{ - udelay(delay); -} - -__weak void psu_mask_write(unsigned long offset, unsigned long mask, - unsigned long val) -{ - unsigned long regval = 0; - - regval = readl(offset); - regval &= ~(mask); - regval |= (val & mask); - writel(regval, offset); -} - -__weak void prog_reg(unsigned long addr, unsigned long mask, - unsigned long shift, unsigned long value) -{ - int rdata = 0; - - rdata = readl(addr); - rdata = rdata & (~mask); - rdata = rdata | (value << shift); - writel(rdata, addr); -} - -__weak int psu_init(void) -{ - /* - * This function is overridden by the one in - * board/xilinx/zynqmp/(platform)/psu_init_gpl.c, if it exists. - */ - return -1; -} diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c deleted file mode 100644 index 01f31d0f0e..0000000000 --- a/arch/arm/cpu/armv8/zynqmp/spl.c +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 - 2016 Xilinx, Inc. - * - * Michal Simek - */ - -#include -#include -#include - -#include -#include -#include -#include - -void board_init_f(ulong dummy) -{ - board_early_init_f(); - board_early_init_r(); - -#ifdef CONFIG_DEBUG_UART - /* Uart debug for sure */ - debug_uart_init(); - puts("Debug uart enabled\n"); /* or printch() */ -#endif - /* Delay is required for clocks to be propagated */ - udelay(1000000); - - /* Clear the BSS */ - memset(__bss_start, 0, __bss_end - __bss_start); - - /* No need to call timer init - it is empty for ZynqMP */ - board_init_r(NULL, 0); -} - -static void ps_mode_reset(ulong mode) -{ - writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT, - &crlapb_base->boot_pin_ctrl); - udelay(5); - writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT | - mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT, - &crlapb_base->boot_pin_ctrl); -} - -/* - * Set default PS_MODE1 which is used for USB ULPI phy reset - * Also other resets can be connected to this certain pin - */ -#ifndef MODE_RESET -# define MODE_RESET PS_MODE1 -#endif - -#ifdef CONFIG_SPL_BOARD_INIT -void spl_board_init(void) -{ - preloader_console_init(); - ps_mode_reset(MODE_RESET); - board_init(); -} -#endif - -u32 spl_boot_device(void) -{ - u32 reg = 0; - u8 bootmode; - -#if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED) - /* Change default boot mode at run-time */ - writel(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT, - &crlapb_base->boot_mode); -#endif - - reg = readl(&crlapb_base->boot_mode); - if (reg >> BOOT_MODE_ALT_SHIFT) - reg >>= BOOT_MODE_ALT_SHIFT; - - bootmode = reg & BOOT_MODES_MASK; - - switch (bootmode) { - case JTAG_MODE: - return BOOT_DEVICE_RAM; -#ifdef CONFIG_SPL_MMC_SUPPORT - case SD_MODE1: - case SD1_LSHFT_MODE: /* not working on silicon v1 */ -/* if both controllers enabled, then these two are the second controller */ -#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1) - return BOOT_DEVICE_MMC2; -/* else, fall through, the one SDHCI controller that is enabled is number 1 */ -#endif - case SD_MODE: - case EMMC_MODE: - return BOOT_DEVICE_MMC1; -#endif -#ifdef CONFIG_SPL_DFU_SUPPORT - case USB_MODE: - return BOOT_DEVICE_DFU; -#endif -#ifdef CONFIG_SPL_SATA_SUPPORT - case SW_SATA_MODE: - return BOOT_DEVICE_SATA; -#endif -#ifdef CONFIG_SPL_SPI_SUPPORT - case QSPI_MODE_24BIT: - case QSPI_MODE_32BIT: - return BOOT_DEVICE_SPI; -#endif - default: - printf("Invalid Boot Mode:0x%x\n", bootmode); - break; - } - - return 0; -} - -#ifdef CONFIG_SPL_OS_BOOT -int spl_start_uboot(void) -{ - handoff_setup(); - - return 0; -} -#endif - -#ifdef CONFIG_SPL_LOAD_FIT -int board_fit_config_name_match(const char *name) -{ - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); - - return 0; -} -#endif diff --git a/arch/arm/include/asm/arch-zynqmp/clk.h b/arch/arm/include/asm/arch-zynqmp/clk.h deleted file mode 100644 index cfd44c8e0f..0000000000 --- a/arch/arm/include/asm/arch-zynqmp/clk.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek - */ - -#ifndef _ASM_ARCH_CLK_H_ -#define _ASM_ARCH_CLK_H_ - -unsigned long zynqmp_get_system_timer_freq(void); - -#endif /* _ASM_ARCH_CLK_H_ */ diff --git a/arch/arm/include/asm/arch-zynqmp/gpio.h b/arch/arm/include/asm/arch-zynqmp/gpio.h deleted file mode 100644 index 542a5fc3e9..0000000000 --- a/arch/arm/include/asm/arch-zynqmp/gpio.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Xilinx, Inc. - */ - -#ifndef __ARCH_ZYNQMP_GPIO_H -#define __ARCH_ZYNQMP_GPIO_H - -/* Empty file - sdhci requires this. */ - -#endif diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h deleted file mode 100644 index 8a505edab3..0000000000 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ /dev/null @@ -1,159 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek - */ - -#ifndef _ASM_ARCH_HARDWARE_H -#define _ASM_ARCH_HARDWARE_H - -#define ZYNQ_GEM_BASEADDR0 0xFF0B0000 -#define ZYNQ_GEM_BASEADDR1 0xFF0C0000 -#define ZYNQ_GEM_BASEADDR2 0xFF0D0000 -#define ZYNQ_GEM_BASEADDR3 0xFF0E0000 - -#define ZYNQ_I2C_BASEADDR0 0xFF020000 -#define ZYNQ_I2C_BASEADDR1 0xFF030000 - -#define ARASAN_NAND_BASEADDR 0xFF100000 - -#define ZYNQMP_TCM_BASE_ADDR 0xFFE00000 -#define ZYNQMP_TCM_SIZE 0x40000 - -#define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000 -#define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 -#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0 -#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8 - -#define PS_MODE0 BIT(0) -#define PS_MODE1 BIT(1) -#define PS_MODE2 BIT(2) -#define PS_MODE3 BIT(3) - -#define RESET_REASON_DEBUG_SYS BIT(6) -#define RESET_REASON_SOFT BIT(5) -#define RESET_REASON_SRST BIT(4) -#define RESET_REASON_PSONLY BIT(3) -#define RESET_REASON_PMU BIT(2) -#define RESET_REASON_INTERNAL BIT(1) -#define RESET_REASON_EXTERNAL BIT(0) - -struct crlapb_regs { - u32 reserved0[36]; - u32 cpu_r5_ctrl; /* 0x90 */ - u32 reserved1[37]; - u32 timestamp_ref_ctrl; /* 0x128 */ - u32 reserved2[53]; - u32 boot_mode; /* 0x200 */ - u32 reserved3_0[7]; - u32 reset_reason; /* 0x220 */ - u32 reserved3_1[6]; - u32 rst_lpd_top; /* 0x23C */ - u32 reserved4[4]; - u32 boot_pin_ctrl; /* 0x250 */ - u32 reserved5[21]; -}; - -#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) - -#define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000 -#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1 -#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2 - -struct iou_scntr_secure { - u32 counter_control_register; - u32 reserved0[7]; - u32 base_frequency_id_register; -}; - -#define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE) - -/* Bootmode setting values */ -#define BOOT_MODES_MASK 0x0000000F -#define QSPI_MODE_24BIT 0x00000001 -#define QSPI_MODE_32BIT 0x00000002 -#define SD_MODE 0x00000003 /* sd 0 */ -#define SD_MODE1 0x00000005 /* sd 1 */ -#define NAND_MODE 0x00000004 -#define EMMC_MODE 0x00000006 -#define USB_MODE 0x00000007 -#define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */ -#define JTAG_MODE 0x00000000 -#define BOOT_MODE_USE_ALT 0x100 -#define BOOT_MODE_ALT_SHIFT 12 -/* SW secondary boot modes 0xa - 0xd */ -#define SW_USBHOST_MODE 0x0000000A -#define SW_SATA_MODE 0x0000000B - -#define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000 - -struct iou_slcr_regs { - u32 mio_pin[78]; - u32 reserved[442]; -}; - -#define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR) - -#define ZYNQMP_RPU_BASEADDR 0xFF9A0000 - -struct rpu_regs { - u32 rpu_glbl_ctrl; - u32 reserved0[63]; - u32 rpu0_cfg; /* 0x100 */ - u32 reserved1[63]; - u32 rpu1_cfg; /* 0x200 */ -}; - -#define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR) - -#define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000 - -struct crfapb_regs { - u32 reserved0[65]; - u32 rst_fpd_apu; /* 0x104 */ - u32 reserved1; -}; - -#define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR) - -#define ZYNQMP_APU_BASEADDR 0xFD5C0000 - -struct apu_regs { - u32 reserved0[16]; - u32 rvbar_addr0_l; /* 0x40 */ - u32 rvbar_addr0_h; /* 0x44 */ - u32 reserved1[20]; -}; - -#define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR) - -/* Board version value */ -#define ZYNQMP_CSU_BASEADDR 0xFFCA0000 -#define ZYNQMP_CSU_VERSION_SILICON 0x0 -#define ZYNQMP_CSU_VERSION_QEMU 0x3 - -#define ZYNQMP_CSU_VERSION_EMPTY_SHIFT 20 - -#define ZYNQMP_SILICON_VER_MASK 0xF000 -#define ZYNQMP_SILICON_VER_SHIFT 12 - -struct csu_regs { - u32 reserved0[17]; - u32 version; -}; - -#define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR) - -#define ZYNQMP_PMU_BASEADDR 0xFFD80000 - -struct pmu_regs { - u32 reserved[18]; - u32 gen_storage6; /* 0x48 */ -}; - -#define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR) - -#define ZYNQMP_CSU_IDCODE_ADDR 0xFFCA0040 -#define ZYNQMP_CSU_VER_ADDR 0xFFCA0044 - -#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-zynqmp/psu_init_gpl.h b/arch/arm/include/asm/arch-zynqmp/psu_init_gpl.h deleted file mode 100644 index 15e54c0493..0000000000 --- a/arch/arm/include/asm/arch-zynqmp/psu_init_gpl.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ - -#ifndef _PSU_INIT_GPL_H_ /* prevent circular inclusions */ -#define _PSU_INIT_GPL_H_ - -#include -#include - -int mask_pollonvalue(unsigned long add, u32 mask, u32 value); - -int mask_poll(u32 add, u32 mask); - -u32 mask_read(u32 add, u32 mask); - -void mask_delay(u32 delay); - -void psu_mask_write(unsigned long offset, unsigned long mask, - unsigned long val); - -void prog_reg(unsigned long addr, unsigned long mask, - unsigned long shift, unsigned long value); - -int psu_init(void); - -#endif /* _PSU_INIT_GPL_H_ */ diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h deleted file mode 100644 index 385c8825f2..0000000000 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ /dev/null @@ -1,75 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek - */ - -#ifndef _ASM_ARCH_SYS_PROTO_H -#define _ASM_ARCH_SYS_PROTO_H - -#define PAYLOAD_ARG_CNT 5 - -#define ZYNQMP_CSU_SILICON_VER_MASK 0xF -#define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD 0xC200002D -#define KEY_PTR_LEN 32 - -#define ZYNQMP_FPGA_BIT_AUTH_DDR 1 -#define ZYNQMP_FPGA_BIT_AUTH_OCM 2 -#define ZYNQMP_FPGA_BIT_ENC_USR_KEY 3 -#define ZYNQMP_FPGA_BIT_ENC_DEV_KEY 4 -#define ZYNQMP_FPGA_BIT_NS 5 - -#define ZYNQMP_FPGA_AUTH_DDR 1 - -#define ZYNQMP_SIP_SVC_GET_API_VERSION 0xC2000001 - -#define ZYNQMP_PM_VERSION_MAJOR 1 -#define ZYNQMP_PM_VERSION_MINOR 0 -#define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16 -#define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF - -#define ZYNQMP_PM_VERSION \ - ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \ - ZYNQMP_PM_VERSION_MINOR) - -#define ZYNQMP_PM_VERSION_INVALID ~0 - -#define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0) - -enum { - IDCODE, - VERSION, - IDCODE2, -}; - -enum { - ZYNQMP_SILICON_V1, - ZYNQMP_SILICON_V2, - ZYNQMP_SILICON_V3, - ZYNQMP_SILICON_V4, -}; - -enum { - TCM_LOCK, - TCM_SPLIT, -}; - -int zynq_board_read_rom_ethaddr(unsigned char *ethaddr); -unsigned int zynqmp_get_silicon_version(void); - -void handoff_setup(void); - -unsigned int zynqmp_pmufw_version(void); -int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); -int zynqmp_mmio_read(const u32 address, u32 *value); -int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, - u32 *ret_payload); - -void initialize_tcm(bool mode); -void mem_map_fill(void); -int chip_id(unsigned char id); -#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP) -void tcm_init(u8 mode); -#endif - -#endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index f8b93fe458..a75ba1ffdb 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -4,7 +4,7 @@ * * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ * Lokesh Vutla - * (This file is derived from arch/arm/cpu/armv8/zynqmp/cpu.c) + * (This file is derived from arch/arm/mach-zynqmp/cpu.c) * */ diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c index 702fde1dea..d45b1faaa2 100644 --- a/arch/arm/mach-tegra/arm64-mmu.c +++ b/arch/arm/mach-tegra/arm64-mmu.c @@ -2,7 +2,7 @@ /* * (C) Copyright 2014 - 2015 Xilinx, Inc. * Michal Simek - * (This file derived from arch/arm/cpu/armv8/zynqmp/cpu.c) + * (This file derived from arch/arm/mach-zynqmp/cpu.c) * * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. */ diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig new file mode 100644 index 0000000000..8a311e1c89 --- /dev/null +++ b/arch/arm/mach-zynqmp/Kconfig @@ -0,0 +1,156 @@ +if ARCH_ZYNQMP + +config SPL_FAT_SUPPORT + default y + +config SPL_LIBCOMMON_SUPPORT + default y + +config SPL_LIBDISK_SUPPORT + default y + +config SPL_LIBGENERIC_SUPPORT + default y + +config SPL_MMC_SUPPORT + default y if MMC_SDHCI_ZYNQ + +config SPL_SERIAL_SUPPORT + default y + +config SPL_SPI_FLASH_SUPPORT + default y if ZYNQ_QSPI + +config SPL_SPI_SUPPORT + default y if ZYNQ_QSPI + +config SYS_BOARD + default "zynqmp" + +config SYS_VENDOR + string "Vendor name" + default "xilinx" + +config SYS_SOC + default "zynqmp" + +config SYS_CONFIG_NAME + string "Board configuration name" + default "xilinx_zynqmp" + help + This option contains information about board configuration name. + Based on this option include/configs/.h header + will be used for board configuration. + +config SYS_MEM_RSVD_FOR_MMU + bool "Reserve memory for MMU Table" + help + If defined this option is used to setup different space for + MMU table than the one which will be allocated during + relocation. + +config BOOT_INIT_FILE + string "boot.bin init register filename" + depends on SPL + default "" + help + Add register writes to boot.bin format (max 256 pairs). + Expect a table of register-value pairs, e.g. "0x12345678 0x4321" + +config PMUFW_INIT_FILE + string "PMU firmware" + depends on SPL + default "" + help + Include external PMUFW (Platform Management Unit FirmWare) to + a Xilinx bootable image (boot.bin). + +config ZYNQMP_USB + bool "Configure ZynqMP USB" + +config ZYNQMP_NO_DDR + bool "Disable DDR MMU mapping" + help + This option configures MMU with no DDR to avoid speculative + access to DDR memory where DDR is not present. + +config SYS_MALLOC_F_LEN + default 0x600 + +config DEFINE_TCM_OCM_MMAP + bool "Define TCM and OCM memory in MMU Table" + default y if MP + help + This option if enabled defines the TCM and OCM memory and its + memory attributes in MMU table entry. + +config ZYNQMP_PSU_INIT_ENABLED + bool "Include psu_init" + help + Include psu_init to full u-boot. SPL include psu_init by default. + +config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED + bool "Overwrite SPL bootmode" + depends on SPL + help + Overwrite bootmode selected via boot mode pins to tell SPL what should + be the next boot device. + +config ZYNQ_SDHCI_MAX_FREQ + default 200000000 + +config SPL_ZYNQMP_ALT_BOOTMODE + hex + default 0x0 if JTAG_MODE + default 0x1 if QSPI_MODE_24BIT + default 0x2 if QSPI_MODE_32BIT + default 0x3 if SD_MODE + default 0x4 if NAND_MODE + default 0x5 if SD_MODE1 + default 0x6 if EMMC_MODE + default 0x7 if USB_MODE + default 0xa if SW_USBHOST_MODE + default 0xb if SW_SATA_MODE + default 0xe if SD1_LSHFT_MODE + +choice + prompt "Boot mode" + depends on SPL_ZYNQMP_ALT_BOOTMODE_ENABLED + default JTAG_MODE + +config JTAG_MODE + bool "JTAG_MODE" + +config QSPI_MODE_24BIT + bool "QSPI_MODE_24BIT" + +config QSPI_MODE_32BIT + bool "QSPI_MODE_32BIT" + +config SD_MODE + bool "SD_MODE" + +config SD_MODE1 + bool "SD_MODE1" + +config NAND_MODE + bool "NAND_MODE" + +config EMMC_MODE + bool "EMMC_MODE" + +config USB_MODE + bool "USB" + +config SW_USBHOST_MODE + bool "SW USBHOST_MODE" + +config SW_SATA_MODE + bool "SW SATA_MODE" + +config SD1_LSHFT_MODE + bool "SD1_LSHFT_MODE" + +endchoice + +endif diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile new file mode 100644 index 0000000000..8a3b074724 --- /dev/null +++ b/arch/arm/mach-zynqmp/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2014 - 2015 Xilinx, Inc. +# Michal Simek + +obj-y += clk.o +obj-y += cpu.o +obj-$(CONFIG_MP) += mp.o +obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o +obj-$(CONFIG_ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o diff --git a/arch/arm/mach-zynqmp/clk.c b/arch/arm/mach-zynqmp/clk.c new file mode 100644 index 0000000000..0593b6310f --- /dev/null +++ b/arch/arm/mach-zynqmp/clk.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2014 - 2015 Xilinx, Inc. + * Michal Simek + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +unsigned long zynqmp_get_system_timer_freq(void) +{ + u32 ver = zynqmp_get_silicon_version(); + + switch (ver) { + case ZYNQMP_CSU_VERSION_QEMU: + return 50000000; + } + + return 100000000; +} + +#ifdef CONFIG_CLOCKS +/** + * set_cpu_clk_info() - Initialize clock framework + * Always returns zero. + * + * This function is called from common code after relocation and sets up the + * clock framework. The framework must not be used before this function had been + * called. + */ +int set_cpu_clk_info(void) +{ + gd->cpu_clk = get_tbclk(); + + gd->bd->bi_arm_freq = gd->cpu_clk / 1000000; + + gd->bd->bi_dsp_freq = 0; + + return 0; +} +#endif diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c new file mode 100644 index 0000000000..5ef1a52862 --- /dev/null +++ b/arch/arm/mach-zynqmp/cpu.c @@ -0,0 +1,260 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2014 - 2015 Xilinx, Inc. + * Michal Simek + */ + +#include +#include +#include +#include +#include + +#define ZYNQ_SILICON_VER_MASK 0xF000 +#define ZYNQ_SILICON_VER_SHIFT 12 + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Number of filled static entries and also the first empty + * slot in zynqmp_mem_map. + */ +#define ZYNQMP_MEM_MAP_USED 4 + +#if !defined(CONFIG_ZYNQMP_NO_DDR) +#define DRAM_BANKS CONFIG_NR_DRAM_BANKS +#else +#define DRAM_BANKS 0 +#endif + +#if defined(CONFIG_DEFINE_TCM_OCM_MMAP) +#define TCM_MAP 1 +#else +#define TCM_MAP 0 +#endif + +/* +1 is end of list which needs to be empty */ +#define ZYNQMP_MEM_MAP_MAX (ZYNQMP_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1) + +static struct mm_region zynqmp_mem_map[ZYNQMP_MEM_MAP_MAX] = { + { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x70000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0xf8000000UL, + .phys = 0xf8000000UL, + .size = 0x07e00000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x400000000UL, + .phys = 0x400000000UL, + .size = 0x400000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x1000000000UL, + .phys = 0x1000000000UL, + .size = 0xf000000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + } +}; + +void mem_map_fill(void) +{ + int banks = ZYNQMP_MEM_MAP_USED; + +#if defined(CONFIG_DEFINE_TCM_OCM_MMAP) + zynqmp_mem_map[banks].virt = 0xffe00000UL; + zynqmp_mem_map[banks].phys = 0xffe00000UL; + zynqmp_mem_map[banks].size = 0x00200000UL; + zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE; + banks = banks + 1; +#endif + +#if !defined(CONFIG_ZYNQMP_NO_DDR) + for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + /* Zero size means no more DDR that's this is end */ + if (!gd->bd->bi_dram[i].size) + break; + + zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start; + zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start; + zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size; + zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE; + banks = banks + 1; + } +#endif +} + +struct mm_region *mem_map = zynqmp_mem_map; + +u64 get_page_table_size(void) +{ + return 0x14000; +} + +#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP) +void tcm_init(u8 mode) +{ + puts("WARNING: Initializing TCM overwrites TCM content\n"); + initialize_tcm(mode); + memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE); +} +#endif + +#ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU +int reserve_mmu(void) +{ + tcm_init(TCM_LOCK); + gd->arch.tlb_size = PGTABLE_SIZE; + gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR; + + return 0; +} +#endif + +static unsigned int zynqmp_get_silicon_version_secure(void) +{ + u32 ver; + + ver = readl(&csu_base->version); + ver &= ZYNQMP_SILICON_VER_MASK; + ver >>= ZYNQMP_SILICON_VER_SHIFT; + + return ver; +} + +unsigned int zynqmp_get_silicon_version(void) +{ + if (current_el() == 3) + return zynqmp_get_silicon_version_secure(); + + gd->cpu_clk = get_tbclk(); + + switch (gd->cpu_clk) { + case 50000000: + return ZYNQMP_CSU_VERSION_QEMU; + } + + return ZYNQMP_CSU_VERSION_SILICON; +} + +#define ZYNQMP_MMIO_READ 0xC2000014 +#define ZYNQMP_MMIO_WRITE 0xC2000013 + +int __maybe_unused invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, + u32 arg3, u32 *ret_payload) +{ + /* + * Added SIP service call Function Identifier + * Make sure to stay in x0 register + */ + struct pt_regs regs; + + regs.regs[0] = pm_api_id; + regs.regs[1] = ((u64)arg1 << 32) | arg0; + regs.regs[2] = ((u64)arg3 << 32) | arg2; + + smc_call(®s); + + if (ret_payload != NULL) { + ret_payload[0] = (u32)regs.regs[0]; + ret_payload[1] = upper_32_bits(regs.regs[0]); + ret_payload[2] = (u32)regs.regs[1]; + ret_payload[3] = upper_32_bits(regs.regs[1]); + ret_payload[4] = (u32)regs.regs[2]; + } + + return regs.regs[0]; +} + +unsigned int __maybe_unused zynqmp_pmufw_version(void) +{ + int ret; + u32 ret_payload[PAYLOAD_ARG_CNT]; + static u32 pm_api_version = ZYNQMP_PM_VERSION_INVALID; + + /* + * Get PMU version only once and later + * just return stored values instead of + * asking PMUFW again. + */ + if (pm_api_version == ZYNQMP_PM_VERSION_INVALID) { + ret = invoke_smc(ZYNQMP_SIP_SVC_GET_API_VERSION, 0, 0, 0, 0, + ret_payload); + pm_api_version = ret_payload[1]; + + if (ret) + panic("PMUFW is not found - Please load it!\n"); + } + + return pm_api_version; +} + +static int zynqmp_mmio_rawwrite(const u32 address, + const u32 mask, + const u32 value) +{ + u32 data; + u32 value_local = value; + int ret; + + ret = zynqmp_mmio_read(address, &data); + if (ret) + return ret; + + data &= ~mask; + value_local &= mask; + value_local |= data; + writel(value_local, (ulong)address); + return 0; +} + +static int zynqmp_mmio_rawread(const u32 address, u32 *value) +{ + *value = readl((ulong)address); + return 0; +} + +int zynqmp_mmio_write(const u32 address, + const u32 mask, + const u32 value) +{ + if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) + return zynqmp_mmio_rawwrite(address, mask, value); + else + return invoke_smc(ZYNQMP_MMIO_WRITE, address, mask, + value, 0, NULL); + + return -EINVAL; +} + +int zynqmp_mmio_read(const u32 address, u32 *value) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + u32 ret; + + if (!value) + return -EINVAL; + + if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) { + ret = zynqmp_mmio_rawread(address, value); + } else { + ret = invoke_smc(ZYNQMP_MMIO_READ, address, 0, 0, + 0, ret_payload); + *value = ret_payload[1]; + } + + return ret; +} diff --git a/arch/arm/mach-zynqmp/handoff.c b/arch/arm/mach-zynqmp/handoff.c new file mode 100644 index 0000000000..f71ff7b3d2 --- /dev/null +++ b/arch/arm/mach-zynqmp/handoff.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2016 - 2017 Xilinx, Inc. + * + * Michal Simek + */ + +#include +#include +#include +#include + +/* + * atfhandoffparams + * Parameter bitfield encoding + * ----------------------------------------------------------------------------- + * Exec State 0 0 -> Aarch64, 1-> Aarch32 + * endianness 1 0 -> LE, 1 -> BE + * secure (TZ) 2 0 -> Non secure, 1 -> secure + * EL 3:4 00 -> EL0, 01 -> EL1, 10 -> EL2, 11 -> EL3 + * CPU# 5:6 00 -> A53_0, 01 -> A53_1, 10 -> A53_2, 11 -> A53_3 + */ + +#define FSBL_FLAGS_ESTATE_SHIFT 0 +#define FSBL_FLAGS_ESTATE_MASK (1 << FSBL_FLAGS_ESTATE_SHIFT) +#define FSBL_FLAGS_ESTATE_A64 0 +#define FSBL_FLAGS_ESTATE_A32 1 + +#define FSBL_FLAGS_ENDIAN_SHIFT 1 +#define FSBL_FLAGS_ENDIAN_MASK (1 << FSBL_FLAGS_ENDIAN_SHIFT) +#define FSBL_FLAGS_ENDIAN_LE 0 +#define FSBL_FLAGS_ENDIAN_BE 1 + +#define FSBL_FLAGS_TZ_SHIFT 2 +#define FSBL_FLAGS_TZ_MASK (1 << FSBL_FLAGS_TZ_SHIFT) +#define FSBL_FLAGS_NON_SECURE 0 +#define FSBL_FLAGS_SECURE 1 + +#define FSBL_FLAGS_EL_SHIFT 3 +#define FSBL_FLAGS_EL_MASK (3 << FSBL_FLAGS_EL_SHIFT) +#define FSBL_FLAGS_EL0 0 +#define FSBL_FLAGS_EL1 1 +#define FSBL_FLAGS_EL2 2 +#define FSBL_FLAGS_EL3 3 + +#define FSBL_FLAGS_CPU_SHIFT 5 +#define FSBL_FLAGS_CPU_MASK (3 << FSBL_FLAGS_CPU_SHIFT) +#define FSBL_FLAGS_A53_0 0 +#define FSBL_FLAGS_A53_1 1 +#define FSBL_FLAGS_A53_2 2 +#define FSBL_FLAGS_A53_3 3 + +#define FSBL_MAX_PARTITIONS 8 + +/* Structure corresponding to each partition entry */ +struct xfsbl_partition { + uint64_t entry_point; + uint64_t flags; +}; + +/* Structure for handoff parameters to ARM Trusted Firmware (ATF) */ +struct xfsbl_atf_handoff_params { + uint8_t magic[4]; + uint32_t num_entries; + struct xfsbl_partition partition[FSBL_MAX_PARTITIONS]; +}; + +#ifdef CONFIG_SPL_OS_BOOT +void handoff_setup(void) +{ + struct xfsbl_atf_handoff_params *atfhandoffparams; + + atfhandoffparams = (void *)CONFIG_SPL_TEXT_BASE; + atfhandoffparams->magic[0] = 'X'; + atfhandoffparams->magic[1] = 'L'; + atfhandoffparams->magic[2] = 'N'; + atfhandoffparams->magic[3] = 'X'; + + atfhandoffparams->num_entries = 1; + atfhandoffparams->partition[0].entry_point = CONFIG_SYS_TEXT_BASE; + atfhandoffparams->partition[0].flags = FSBL_FLAGS_EL2 << + FSBL_FLAGS_EL_SHIFT; + + writel(CONFIG_SPL_TEXT_BASE, &pmu_base->gen_storage6); +} +#endif diff --git a/arch/arm/mach-zynqmp/include/mach/clk.h b/arch/arm/mach-zynqmp/include/mach/clk.h new file mode 100644 index 0000000000..cfd44c8e0f --- /dev/null +++ b/arch/arm/mach-zynqmp/include/mach/clk.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2014 - 2015 Xilinx, Inc. + * Michal Simek + */ + +#ifndef _ASM_ARCH_CLK_H_ +#define _ASM_ARCH_CLK_H_ + +unsigned long zynqmp_get_system_timer_freq(void); + +#endif /* _ASM_ARCH_CLK_H_ */ diff --git a/arch/arm/mach-zynqmp/include/mach/gpio.h b/arch/arm/mach-zynqmp/include/mach/gpio.h new file mode 100644 index 0000000000..542a5fc3e9 --- /dev/null +++ b/arch/arm/mach-zynqmp/include/mach/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Xilinx, Inc. + */ + +#ifndef __ARCH_ZYNQMP_GPIO_H +#define __ARCH_ZYNQMP_GPIO_H + +/* Empty file - sdhci requires this. */ + +#endif diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h new file mode 100644 index 0000000000..8a505edab3 --- /dev/null +++ b/arch/arm/mach-zynqmp/include/mach/hardware.h @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2014 - 2015 Xilinx, Inc. + * Michal Simek + */ + +#ifndef _ASM_ARCH_HARDWARE_H +#define _ASM_ARCH_HARDWARE_H + +#define ZYNQ_GEM_BASEADDR0 0xFF0B0000 +#define ZYNQ_GEM_BASEADDR1 0xFF0C0000 +#define ZYNQ_GEM_BASEADDR2 0xFF0D0000 +#define ZYNQ_GEM_BASEADDR3 0xFF0E0000 + +#define ZYNQ_I2C_BASEADDR0 0xFF020000 +#define ZYNQ_I2C_BASEADDR1 0xFF030000 + +#define ARASAN_NAND_BASEADDR 0xFF100000 + +#define ZYNQMP_TCM_BASE_ADDR 0xFFE00000 +#define ZYNQMP_TCM_SIZE 0x40000 + +#define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000 +#define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 +#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0 +#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8 + +#define PS_MODE0 BIT(0) +#define PS_MODE1 BIT(1) +#define PS_MODE2 BIT(2) +#define PS_MODE3 BIT(3) + +#define RESET_REASON_DEBUG_SYS BIT(6) +#define RESET_REASON_SOFT BIT(5) +#define RESET_REASON_SRST BIT(4) +#define RESET_REASON_PSONLY BIT(3) +#define RESET_REASON_PMU BIT(2) +#define RESET_REASON_INTERNAL BIT(1) +#define RESET_REASON_EXTERNAL BIT(0) + +struct crlapb_regs { + u32 reserved0[36]; + u32 cpu_r5_ctrl; /* 0x90 */ + u32 reserved1[37]; + u32 timestamp_ref_ctrl; /* 0x128 */ + u32 reserved2[53]; + u32 boot_mode; /* 0x200 */ + u32 reserved3_0[7]; + u32 reset_reason; /* 0x220 */ + u32 reserved3_1[6]; + u32 rst_lpd_top; /* 0x23C */ + u32 reserved4[4]; + u32 boot_pin_ctrl; /* 0x250 */ + u32 reserved5[21]; +}; + +#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) + +#define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000 +#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1 +#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2 + +struct iou_scntr_secure { + u32 counter_control_register; + u32 reserved0[7]; + u32 base_frequency_id_register; +}; + +#define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE) + +/* Bootmode setting values */ +#define BOOT_MODES_MASK 0x0000000F +#define QSPI_MODE_24BIT 0x00000001 +#define QSPI_MODE_32BIT 0x00000002 +#define SD_MODE 0x00000003 /* sd 0 */ +#define SD_MODE1 0x00000005 /* sd 1 */ +#define NAND_MODE 0x00000004 +#define EMMC_MODE 0x00000006 +#define USB_MODE 0x00000007 +#define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */ +#define JTAG_MODE 0x00000000 +#define BOOT_MODE_USE_ALT 0x100 +#define BOOT_MODE_ALT_SHIFT 12 +/* SW secondary boot modes 0xa - 0xd */ +#define SW_USBHOST_MODE 0x0000000A +#define SW_SATA_MODE 0x0000000B + +#define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000 + +struct iou_slcr_regs { + u32 mio_pin[78]; + u32 reserved[442]; +}; + +#define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR) + +#define ZYNQMP_RPU_BASEADDR 0xFF9A0000 + +struct rpu_regs { + u32 rpu_glbl_ctrl; + u32 reserved0[63]; + u32 rpu0_cfg; /* 0x100 */ + u32 reserved1[63]; + u32 rpu1_cfg; /* 0x200 */ +}; + +#define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR) + +#define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000 + +struct crfapb_regs { + u32 reserved0[65]; + u32 rst_fpd_apu; /* 0x104 */ + u32 reserved1; +}; + +#define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR) + +#define ZYNQMP_APU_BASEADDR 0xFD5C0000 + +struct apu_regs { + u32 reserved0[16]; + u32 rvbar_addr0_l; /* 0x40 */ + u32 rvbar_addr0_h; /* 0x44 */ + u32 reserved1[20]; +}; + +#define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR) + +/* Board version value */ +#define ZYNQMP_CSU_BASEADDR 0xFFCA0000 +#define ZYNQMP_CSU_VERSION_SILICON 0x0 +#define ZYNQMP_CSU_VERSION_QEMU 0x3 + +#define ZYNQMP_CSU_VERSION_EMPTY_SHIFT 20 + +#define ZYNQMP_SILICON_VER_MASK 0xF000 +#define ZYNQMP_SILICON_VER_SHIFT 12 + +struct csu_regs { + u32 reserved0[17]; + u32 version; +}; + +#define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR) + +#define ZYNQMP_PMU_BASEADDR 0xFFD80000 + +struct pmu_regs { + u32 reserved[18]; + u32 gen_storage6; /* 0x48 */ +}; + +#define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR) + +#define ZYNQMP_CSU_IDCODE_ADDR 0xFFCA0040 +#define ZYNQMP_CSU_VER_ADDR 0xFFCA0044 + +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h b/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h new file mode 100644 index 0000000000..15e54c0493 --- /dev/null +++ b/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _PSU_INIT_GPL_H_ /* prevent circular inclusions */ +#define _PSU_INIT_GPL_H_ + +#include +#include + +int mask_pollonvalue(unsigned long add, u32 mask, u32 value); + +int mask_poll(u32 add, u32 mask); + +u32 mask_read(u32 add, u32 mask); + +void mask_delay(u32 delay); + +void psu_mask_write(unsigned long offset, unsigned long mask, + unsigned long val); + +void prog_reg(unsigned long addr, unsigned long mask, + unsigned long shift, unsigned long value); + +int psu_init(void); + +#endif /* _PSU_INIT_GPL_H_ */ diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h new file mode 100644 index 0000000000..385c8825f2 --- /dev/null +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2014 - 2015 Xilinx, Inc. + * Michal Simek + */ + +#ifndef _ASM_ARCH_SYS_PROTO_H +#define _ASM_ARCH_SYS_PROTO_H + +#define PAYLOAD_ARG_CNT 5 + +#define ZYNQMP_CSU_SILICON_VER_MASK 0xF +#define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD 0xC200002D +#define KEY_PTR_LEN 32 + +#define ZYNQMP_FPGA_BIT_AUTH_DDR 1 +#define ZYNQMP_FPGA_BIT_AUTH_OCM 2 +#define ZYNQMP_FPGA_BIT_ENC_USR_KEY 3 +#define ZYNQMP_FPGA_BIT_ENC_DEV_KEY 4 +#define ZYNQMP_FPGA_BIT_NS 5 + +#define ZYNQMP_FPGA_AUTH_DDR 1 + +#define ZYNQMP_SIP_SVC_GET_API_VERSION 0xC2000001 + +#define ZYNQMP_PM_VERSION_MAJOR 1 +#define ZYNQMP_PM_VERSION_MINOR 0 +#define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16 +#define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF + +#define ZYNQMP_PM_VERSION \ + ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \ + ZYNQMP_PM_VERSION_MINOR) + +#define ZYNQMP_PM_VERSION_INVALID ~0 + +#define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0) + +enum { + IDCODE, + VERSION, + IDCODE2, +}; + +enum { + ZYNQMP_SILICON_V1, + ZYNQMP_SILICON_V2, + ZYNQMP_SILICON_V3, + ZYNQMP_SILICON_V4, +}; + +enum { + TCM_LOCK, + TCM_SPLIT, +}; + +int zynq_board_read_rom_ethaddr(unsigned char *ethaddr); +unsigned int zynqmp_get_silicon_version(void); + +void handoff_setup(void); + +unsigned int zynqmp_pmufw_version(void); +int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); +int zynqmp_mmio_read(const u32 address, u32 *value); +int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, + u32 *ret_payload); + +void initialize_tcm(bool mode); +void mem_map_fill(void); +int chip_id(unsigned char id); +#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP) +void tcm_init(u8 mode); +#endif + +#endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c new file mode 100644 index 0000000000..2a71870ae7 --- /dev/null +++ b/arch/arm/mach-zynqmp/mp.c @@ -0,0 +1,297 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2014 - 2015 Xilinx, Inc. + * Michal Simek + */ + +#include +#include +#include +#include + +#define LOCK 0 +#define SPLIT 1 + +#define HALT 0 +#define RELEASE 1 + +#define ZYNQMP_BOOTADDR_HIGH_MASK 0xFFFFFFFF +#define ZYNQMP_R5_HIVEC_ADDR 0xFFFF0000 +#define ZYNQMP_R5_LOVEC_ADDR 0x0 +#define ZYNQMP_RPU_CFG_CPU_HALT_MASK 0x01 +#define ZYNQMP_RPU_CFG_HIVEC_MASK 0x04 +#define ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK 0x08 +#define ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK 0x40 +#define ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK 0x10 + +#define ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK 0x04 +#define ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK 0x01 +#define ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK 0x02 +#define ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK 0x1000000 + +#define ZYNQMP_TCM_START_ADDRESS 0xFFE00000 +#define ZYNQMP_TCM_BOTH_SIZE 0x40000 + +#define ZYNQMP_CORE_APU0 0 +#define ZYNQMP_CORE_APU3 3 + +#define ZYNQMP_MAX_CORES 6 + +int is_core_valid(unsigned int core) +{ + if (core < ZYNQMP_MAX_CORES) + return 1; + + return 0; +} + +int cpu_reset(u32 nr) +{ + puts("Feature is not implemented.\n"); + return 0; +} + +static void set_r5_halt_mode(u8 halt, u8 mode) +{ + u32 tmp; + + tmp = readl(&rpu_base->rpu0_cfg); + if (halt == HALT) + tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK; + else + tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK; + writel(tmp, &rpu_base->rpu0_cfg); + + if (mode == LOCK) { + tmp = readl(&rpu_base->rpu1_cfg); + if (halt == HALT) + tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK; + else + tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK; + writel(tmp, &rpu_base->rpu1_cfg); + } +} + +static void set_r5_tcm_mode(u8 mode) +{ + u32 tmp; + + tmp = readl(&rpu_base->rpu_glbl_ctrl); + if (mode == LOCK) { + tmp &= ~ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK; + tmp |= ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK | + ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK; + } else { + tmp |= ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK; + tmp &= ~(ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK | + ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK); + } + + writel(tmp, &rpu_base->rpu_glbl_ctrl); +} + +static void set_r5_reset(u8 mode) +{ + u32 tmp; + + tmp = readl(&crlapb_base->rst_lpd_top); + tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | + ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK); + + if (mode == LOCK) + tmp |= ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK; + + writel(tmp, &crlapb_base->rst_lpd_top); +} + +static void release_r5_reset(u8 mode) +{ + u32 tmp; + + tmp = readl(&crlapb_base->rst_lpd_top); + tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | + ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK); + + if (mode == LOCK) + tmp &= ~ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK; + + writel(tmp, &crlapb_base->rst_lpd_top); +} + +static void enable_clock_r5(void) +{ + u32 tmp; + + tmp = readl(&crlapb_base->cpu_r5_ctrl); + tmp |= ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK; + writel(tmp, &crlapb_base->cpu_r5_ctrl); + + /* Give some delay for clock + * to propagate */ + udelay(0x500); +} + +int cpu_disable(u32 nr) +{ + if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) { + u32 val = readl(&crfapb_base->rst_fpd_apu); + val |= 1 << nr; + writel(val, &crfapb_base->rst_fpd_apu); + } else { + set_r5_reset(LOCK); + } + + return 0; +} + +int cpu_status(u32 nr) +{ + if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) { + u32 addr_low = readl(((u8 *)&apu_base->rvbar_addr0_l) + nr * 8); + u32 addr_high = readl(((u8 *)&apu_base->rvbar_addr0_h) + + nr * 8); + u32 val = readl(&crfapb_base->rst_fpd_apu); + val &= 1 << nr; + printf("APU CPU%d %s - starting address HI: %x, LOW: %x\n", + nr, val ? "OFF" : "ON" , addr_high, addr_low); + } else { + u32 val = readl(&crlapb_base->rst_lpd_top); + val &= 1 << (nr - 4); + printf("RPU CPU%d %s\n", nr - 4, val ? "OFF" : "ON"); + } + + return 0; +} + +static void set_r5_start(u8 high) +{ + u32 tmp; + + tmp = readl(&rpu_base->rpu0_cfg); + if (high) + tmp |= ZYNQMP_RPU_CFG_HIVEC_MASK; + else + tmp &= ~ZYNQMP_RPU_CFG_HIVEC_MASK; + writel(tmp, &rpu_base->rpu0_cfg); + + tmp = readl(&rpu_base->rpu1_cfg); + if (high) + tmp |= ZYNQMP_RPU_CFG_HIVEC_MASK; + else + tmp &= ~ZYNQMP_RPU_CFG_HIVEC_MASK; + writel(tmp, &rpu_base->rpu1_cfg); +} + +static void write_tcm_boot_trampoline(u32 boot_addr) +{ + if (boot_addr) { + /* + * Boot trampoline is simple ASM code below. + * + * b over; + * label: + * .word 0 + * over: ldr r0, =label + * ldr r1, [r0] + * bx r1 + */ + debug("Write boot trampoline for %x\n", boot_addr); + writel(0xea000000, ZYNQMP_TCM_START_ADDRESS); + writel(boot_addr, ZYNQMP_TCM_START_ADDRESS + 0x4); + writel(0xe59f0004, ZYNQMP_TCM_START_ADDRESS + 0x8); + writel(0xe5901000, ZYNQMP_TCM_START_ADDRESS + 0xc); + writel(0xe12fff11, ZYNQMP_TCM_START_ADDRESS + 0x10); + writel(0x00000004, ZYNQMP_TCM_START_ADDRESS + 0x14); // address for + } +} + +void initialize_tcm(bool mode) +{ + if (!mode) { + set_r5_tcm_mode(LOCK); + set_r5_halt_mode(HALT, LOCK); + enable_clock_r5(); + release_r5_reset(LOCK); + } else { + set_r5_tcm_mode(SPLIT); + set_r5_halt_mode(HALT, SPLIT); + enable_clock_r5(); + release_r5_reset(SPLIT); + } +} + +int cpu_release(u32 nr, int argc, char * const argv[]) +{ + if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) { + u64 boot_addr = simple_strtoull(argv[0], NULL, 16); + /* HIGH */ + writel((u32)(boot_addr >> 32), + ((u8 *)&apu_base->rvbar_addr0_h) + nr * 8); + /* LOW */ + writel((u32)(boot_addr & ZYNQMP_BOOTADDR_HIGH_MASK), + ((u8 *)&apu_base->rvbar_addr0_l) + nr * 8); + + u32 val = readl(&crfapb_base->rst_fpd_apu); + val &= ~(1 << nr); + writel(val, &crfapb_base->rst_fpd_apu); + } else { + if (argc != 2) { + printf("Invalid number of arguments to release.\n"); + printf(" -Start addr lockstep or split\n"); + return 1; + } + + u32 boot_addr = simple_strtoul(argv[0], NULL, 16); + u32 boot_addr_uniq = 0; + if (!(boot_addr == ZYNQMP_R5_LOVEC_ADDR || + boot_addr == ZYNQMP_R5_HIVEC_ADDR)) { + printf("Using TCM jump trampoline for address 0x%x\n", + boot_addr); + /* Save boot address for later usage */ + boot_addr_uniq = boot_addr; + /* + * R5 needs to start from LOVEC at TCM + * OCM will be probably occupied by ATF + */ + boot_addr = ZYNQMP_R5_LOVEC_ADDR; + } + + /* + * Since we don't know where the user may have loaded the image + * for an R5 we have to flush all the data cache to ensure + * the R5 sees it. + */ + flush_dcache_all(); + + if (!strncmp(argv[1], "lockstep", 8)) { + printf("R5 lockstep mode\n"); + set_r5_reset(LOCK); + set_r5_tcm_mode(LOCK); + set_r5_halt_mode(HALT, LOCK); + set_r5_start(boot_addr); + enable_clock_r5(); + release_r5_reset(LOCK); + dcache_disable(); + write_tcm_boot_trampoline(boot_addr_uniq); + dcache_enable(); + set_r5_halt_mode(RELEASE, LOCK); + } else if (!strncmp(argv[1], "split", 5)) { + printf("R5 split mode\n"); + set_r5_reset(SPLIT); + set_r5_tcm_mode(SPLIT); + set_r5_halt_mode(HALT, SPLIT); + set_r5_start(boot_addr); + enable_clock_r5(); + release_r5_reset(SPLIT); + dcache_disable(); + write_tcm_boot_trampoline(boot_addr_uniq); + dcache_enable(); + set_r5_halt_mode(RELEASE, SPLIT); + } else { + printf("Unsupported mode\n"); + return 1; + } + } + + return 0; +} diff --git a/arch/arm/mach-zynqmp/psu_spl_init.c b/arch/arm/mach-zynqmp/psu_spl_init.c new file mode 100644 index 0000000000..b357de3235 --- /dev/null +++ b/arch/arm/mach-zynqmp/psu_spl_init.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 Xilinx, Inc. + * + * Michal Simek + */ +#include +#include +#include + +#define PSU_MASK_POLL_TIME 1100000 + +int __maybe_unused mask_pollonvalue(unsigned long add, u32 mask, u32 value) +{ + int i = 0; + + while ((__raw_readl(add) & mask) != value) { + if (i == PSU_MASK_POLL_TIME) + return 0; + i++; + } + return 1; +} + +__weak int mask_poll(u32 add, u32 mask) +{ + int i = 0; + unsigned long addr = add; + + while (!(__raw_readl(addr) & mask)) { + if (i == PSU_MASK_POLL_TIME) + return 0; + i++; + } + return 1; +} + +__weak u32 mask_read(u32 add, u32 mask) +{ + unsigned long addr = add; + + return __raw_readl(addr) & mask; +} + +__weak void mask_delay(u32 delay) +{ + udelay(delay); +} + +__weak void psu_mask_write(unsigned long offset, unsigned long mask, + unsigned long val) +{ + unsigned long regval = 0; + + regval = readl(offset); + regval &= ~(mask); + regval |= (val & mask); + writel(regval, offset); +} + +__weak void prog_reg(unsigned long addr, unsigned long mask, + unsigned long shift, unsigned long value) +{ + int rdata = 0; + + rdata = readl(addr); + rdata = rdata & (~mask); + rdata = rdata | (value << shift); + writel(rdata, addr); +} + +__weak int psu_init(void) +{ + /* + * This function is overridden by the one in + * board/xilinx/zynqmp/(platform)/psu_init_gpl.c, if it exists. + */ + return -1; +} diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c new file mode 100644 index 0000000000..01f31d0f0e --- /dev/null +++ b/arch/arm/mach-zynqmp/spl.c @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015 - 2016 Xilinx, Inc. + * + * Michal Simek + */ + +#include +#include +#include + +#include +#include +#include +#include + +void board_init_f(ulong dummy) +{ + board_early_init_f(); + board_early_init_r(); + +#ifdef CONFIG_DEBUG_UART + /* Uart debug for sure */ + debug_uart_init(); + puts("Debug uart enabled\n"); /* or printch() */ +#endif + /* Delay is required for clocks to be propagated */ + udelay(1000000); + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* No need to call timer init - it is empty for ZynqMP */ + board_init_r(NULL, 0); +} + +static void ps_mode_reset(ulong mode) +{ + writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT, + &crlapb_base->boot_pin_ctrl); + udelay(5); + writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT | + mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT, + &crlapb_base->boot_pin_ctrl); +} + +/* + * Set default PS_MODE1 which is used for USB ULPI phy reset + * Also other resets can be connected to this certain pin + */ +#ifndef MODE_RESET +# define MODE_RESET PS_MODE1 +#endif + +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init(void) +{ + preloader_console_init(); + ps_mode_reset(MODE_RESET); + board_init(); +} +#endif + +u32 spl_boot_device(void) +{ + u32 reg = 0; + u8 bootmode; + +#if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED) + /* Change default boot mode at run-time */ + writel(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT, + &crlapb_base->boot_mode); +#endif + + reg = readl(&crlapb_base->boot_mode); + if (reg >> BOOT_MODE_ALT_SHIFT) + reg >>= BOOT_MODE_ALT_SHIFT; + + bootmode = reg & BOOT_MODES_MASK; + + switch (bootmode) { + case JTAG_MODE: + return BOOT_DEVICE_RAM; +#ifdef CONFIG_SPL_MMC_SUPPORT + case SD_MODE1: + case SD1_LSHFT_MODE: /* not working on silicon v1 */ +/* if both controllers enabled, then these two are the second controller */ +#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1) + return BOOT_DEVICE_MMC2; +/* else, fall through, the one SDHCI controller that is enabled is number 1 */ +#endif + case SD_MODE: + case EMMC_MODE: + return BOOT_DEVICE_MMC1; +#endif +#ifdef CONFIG_SPL_DFU_SUPPORT + case USB_MODE: + return BOOT_DEVICE_DFU; +#endif +#ifdef CONFIG_SPL_SATA_SUPPORT + case SW_SATA_MODE: + return BOOT_DEVICE_SATA; +#endif +#ifdef CONFIG_SPL_SPI_SUPPORT + case QSPI_MODE_24BIT: + case QSPI_MODE_32BIT: + return BOOT_DEVICE_SPI; +#endif + default: + printf("Invalid Boot Mode:0x%x\n", bootmode); + break; + } + + return 0; +} + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + handoff_setup(); + + return 0; +} +#endif + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif -- cgit From c447a17d9e94ddca3ae6c5c11a1a7bb6618950a5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 16 Jan 2019 16:50:17 +0100 Subject: arm64: versal: Enable i2c cadence controller and i2c command Enable communication over i2c. Signed-off-by: Michal Simek --- configs/xilinx_versal_virt_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index e1797db982..3f26163913 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -20,6 +20,7 @@ CONFIG_CMD_BOOTMENU=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y # CONFIG_CMD_FLASH is not set +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_DHCP=y @@ -42,6 +43,8 @@ CONFIG_OF_BOARD=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_DM_SPI_FLASH=y -- cgit From 89fe08bb88d89ba979e1e9d0766891ba8d26ed62 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 16 Jan 2019 16:52:19 +0100 Subject: arm64: versal: Enable dm command It is useful to have this command enable to see which devices are bind/probed. Signed-off-by: Michal Simek --- configs/xilinx_versal_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 3f26163913..57e497c922 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_PROMPT="Versal> " CONFIG_CMD_BOOTMENU=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -- cgit From 84de0f918844257013cb1f851bed3a10fc9a545d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 18 Jan 2019 10:43:39 +0100 Subject: i2c: cdns: Convert to livetree function Update cadence i2c driver to support livetree Similar changes were done by: "net: zynq_gem: convert to use livetree" (sha1: 26026e695afa794ac018a09e79a48120d322b60d) Signed-off-by: Michal Simek --- drivers/i2c/i2c-cdns.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c index f2c4b2073c..4330d28c2b 100644 --- a/drivers/i2c/i2c-cdns.c +++ b/drivers/i2c/i2c-cdns.c @@ -419,7 +419,7 @@ static int cdns_i2c_ofdata_to_platdata(struct udevice *dev) struct clk clk; int ret; - i2c_bus->regs = (struct cdns_i2c_regs *)devfdt_get_addr(dev); + i2c_bus->regs = (struct cdns_i2c_regs *)dev_read_addr(dev); if (!i2c_bus->regs) return -ENOMEM; -- cgit From 5820590309dff693115e6fb0800115067a1be46e Mon Sep 17 00:00:00 2001 From: Mike Looijmans Date: Fri, 18 Jan 2019 09:02:47 +0100 Subject: topic-miamiplus: Run CPU at 800MHz for speedgrade-2 The miamiplus contains a speedgrade-2 device, which may run the CPU at 800MHz. Change the PLL setting to 800MHz, and adapt the setpoints in the devicetree. Signed-off-by: Mike Looijmans Signed-off-by: Michal Simek --- arch/arm/dts/zynq-topic-miamiplus.dts | 9 +++++++++ board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c | 4 ++-- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynq-topic-miamiplus.dts b/arch/arm/dts/zynq-topic-miamiplus.dts index c0ccea90a1..df53886529 100644 --- a/arch/arm/dts/zynq-topic-miamiplus.dts +++ b/arch/arm/dts/zynq-topic-miamiplus.dts @@ -11,6 +11,15 @@ compatible = "topic,miamiplus", "xlnx,zynq-7000"; }; +/* The miamiplus contains a speedgrade-2 device and runs at 800MHz */ +&cpu0 { + operating-points = < + /* kHz uV */ + 800000 1000000 + 400000 1000000 + >; +}; + &qspi { is-dual = <1>; }; diff --git a/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c index c1cc1df23d..fd5846aa03 100644 --- a/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c +++ b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c @@ -8,8 +8,8 @@ static unsigned long ps7_pll_init_data_3_0[] = { EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U), - EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA240U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00030000U), EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), -- cgit From acc58a4aca6ff28aef3d3ba33d5f94c7bff9cc96 Mon Sep 17 00:00:00 2001 From: Mike Looijmans Date: Fri, 18 Jan 2019 09:02:48 +0100 Subject: board: topic-miamiplus: Run IO PLL at 1000 MHz The miamiplus can use GEM0 through MIO pins, which requires a 125 MHz TX clock to be generated. With the IO PLL at 1200 MHz this isn't possible, so change it to run at 1000 and adjust the divisors accordingly. Also set the GEM0 clock source to MIO instead of EMIO. Signed-off-by: Mike Looijmans Signed-off-by: Michal Simek --- .../topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c | 30 ++++++++++------------ 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c index fd5846aa03..d90a350d3f 100644 --- a/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c +++ b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c @@ -24,8 +24,8 @@ static unsigned long ps7_pll_init_data_3_0[] = { EMIT_MASKPOLL(0XF800010C, 0x00000002U), EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), - EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x00113220U), - EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00024000U), + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U), + EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U), EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), @@ -37,20 +37,18 @@ static unsigned long ps7_pll_init_data_3_0[] = { static unsigned long ps7_clock_init_data_3_0[] = { EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U), - EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000011U), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U), + EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U), EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U), - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100141U), - EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00100141U), - EMIT_MASKWRITE(0XF8000148, 0x00003F31U, 0x00000C01U), - EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000601U), - EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001803U), - EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000C03U), - EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000601U), - EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000601U), - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100C00U), - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100C00U), - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100600U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U), + EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A03U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000501U), + EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00200500U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U), + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U), EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101800U), EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01FC4C4DU), @@ -88,7 +86,7 @@ static unsigned long ps7_ddr_init_data_3_0[] = { EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U), EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U), EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB52U), EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U), -- cgit From 8a2607020c97095d39e260372b28ea5e13bbc977 Mon Sep 17 00:00:00 2001 From: Anton Gerasimov Date: Mon, 24 Dec 2018 02:29:04 +0100 Subject: zynq: Kconfig: extend the bootstrap malloc() pool Most of the memory is being consumed by device binding code, more space needed for other data structures. Z-turn board has already hit the limit, others may follow soon. Measuring only the memory consumed in device_bind_common, I've got the following results (in decimal): root_driver: 108 mod_exp_sw: 108 amba: 120 serial@e0000000 aka uart0: 112 serial@e0001000 aka uart1: 88 spi@e000d000 aka qspi: 120 sdhci@e0100000 aka mmc0: 455 sdhci@e0100000.blk: 208 slcr@f8000000: 96 clkc@100: 72 (total) 1487 = 0x5cf of 0x600 Signed-off-by: Anton Gerasimov Signed-off-by: Michal Simek --- arch/arm/mach-zynq/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index a599ed63ee..21dfebf5c0 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -55,7 +55,7 @@ config SYS_CONFIG_NAME will be used for board configuration. config SYS_MALLOC_F_LEN - default 0x600 + default 0x800 config SYS_MALLOC_LEN default 0x1400000 -- cgit From 73d52b066a806cebd451e09d46d73b45eb0035fd Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 22 Jan 2019 13:15:01 +0100 Subject: arm64: zynqmp: Remove unused GEM addresses With DM in place there is no need to have GEM addresses in headers. None is using them. Signed-off-by: Michal Simek --- arch/arm/mach-zynqmp/include/mach/hardware.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h index 8a505edab3..efb4bba4b8 100644 --- a/arch/arm/mach-zynqmp/include/mach/hardware.h +++ b/arch/arm/mach-zynqmp/include/mach/hardware.h @@ -7,11 +7,6 @@ #ifndef _ASM_ARCH_HARDWARE_H #define _ASM_ARCH_HARDWARE_H -#define ZYNQ_GEM_BASEADDR0 0xFF0B0000 -#define ZYNQ_GEM_BASEADDR1 0xFF0C0000 -#define ZYNQ_GEM_BASEADDR2 0xFF0D0000 -#define ZYNQ_GEM_BASEADDR3 0xFF0E0000 - #define ZYNQ_I2C_BASEADDR0 0xFF020000 #define ZYNQ_I2C_BASEADDR1 0xFF030000 -- cgit From 2e530511facd7b98834252a2f563421f3e626d1f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 22 Jan 2019 13:15:46 +0100 Subject: ARM: zynq: Remove unused GEM addresses With DM in place there is no need to have GEM addresses in headers. None is using them. Signed-off-by: Michal Simek --- arch/arm/mach-zynq/include/mach/hardware.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/mach-zynq/include/mach/hardware.h b/arch/arm/mach-zynq/include/mach/hardware.h index 3ff3c1073e..58b6f95395 100644 --- a/arch/arm/mach-zynq/include/mach/hardware.h +++ b/arch/arm/mach-zynq/include/mach/hardware.h @@ -9,8 +9,6 @@ #define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000 #define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000 #define ZYNQ_SCU_BASEADDR 0xF8F00000 -#define ZYNQ_GEM_BASEADDR0 0xE000B000 -#define ZYNQ_GEM_BASEADDR1 0xE000C000 #define ZYNQ_I2C_BASEADDR0 0xE0004000 #define ZYNQ_I2C_BASEADDR1 0xE0005000 #define ZYNQ_QSPI_BASEADDR 0xE000D000 -- cgit From 8d932736f5c2b6a28ad508442fc13c25dc2819b4 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 22 Jan 2019 14:04:20 +0100 Subject: ARM: zynq: Disable i2c for Zybo/Zybo Z7 There is no i2c connected in base DT that's why disable I2C commands. Also remove zynq_zybo which is not needed now. Signed-off-by: Michal Simek --- configs/zynq_zybo_defconfig | 6 ------ configs/zynq_zybo_z7_defconfig | 4 ---- include/configs/zynq_zybo.h | 18 ------------------ 3 files changed, 28 deletions(-) delete mode 100644 include/configs/zynq_zybo.h diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index 46b63003b3..9e44e82549 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="zynq_zybo" CONFIG_ARCH_ZYNQ=y CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_SPL=y @@ -18,7 +17,6 @@ CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_EEPROM=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y @@ -26,7 +24,6 @@ CONFIG_CMD_FPGA_LOADFS=y CONFIG_CMD_FPGA_LOADMK=y CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_USB=y @@ -43,9 +40,6 @@ CONFIG_DFU_RAM=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQPL=y CONFIG_DM_GPIO=y -CONFIG_SYS_I2C_ZYNQ=y -CONFIG_ZYNQ_I2C0=y -CONFIG_ZYNQ_I2C1=y CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y diff --git a/configs/zynq_zybo_z7_defconfig b/configs/zynq_zybo_z7_defconfig index 7985ad6c63..d729ca340c 100644 --- a/configs/zynq_zybo_z7_defconfig +++ b/configs/zynq_zybo_z7_defconfig @@ -24,7 +24,6 @@ CONFIG_CMD_FPGA_LOADFS=y CONFIG_CMD_FPGA_LOADMK=y CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_USB=y @@ -41,9 +40,6 @@ CONFIG_DFU_RAM=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQPL=y CONFIG_DM_GPIO=y -CONFIG_SYS_I2C_ZYNQ=y -CONFIG_ZYNQ_I2C0=y -CONFIG_ZYNQ_I2C1=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y diff --git a/include/configs/zynq_zybo.h b/include/configs/zynq_zybo.h deleted file mode 100644 index 7d00b412a7..0000000000 --- a/include/configs/zynq_zybo.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012 Xilinx - * (C) Copyright 2014 Digilent Inc. - * - * Configuration for Zynq Development Board - ZYBO - * See zynq-common.h for Zynq common configs - */ - -#ifndef __CONFIG_ZYNQ_ZYBO_H -#define __CONFIG_ZYNQ_ZYBO_H - -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x50 - -#include - -#endif /* __CONFIG_ZYNQ_ZYBO_H */ -- cgit From 4efdbc88b79bd8bd3e285cd238e1942d669a7088 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 22 Jan 2019 15:47:52 +0100 Subject: ARM: zynq: Convert Topic Miami to DM_I2C Both boards have only controllers enabled that's why move to DM_I2C is easy. Signed-off-by: Michal Simek --- configs/topic_miami_defconfig | 5 ++--- configs/topic_miamilite_defconfig | 5 ++--- configs/topic_miamiplus_defconfig | 5 ++--- 3 files changed, 6 insertions(+), 9 deletions(-) diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index 70d07ac041..927ce9ad28 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -34,9 +34,8 @@ CONFIG_DFU_RAM=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQPL=y CONFIG_DM_GPIO=y -CONFIG_SYS_I2C_ZYNQ=y -CONFIG_ZYNQ_I2C0=y -CONFIG_ZYNQ_I2C1=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig index 387f4cae08..e4d52f6a91 100644 --- a/configs/topic_miamilite_defconfig +++ b/configs/topic_miamilite_defconfig @@ -34,9 +34,8 @@ CONFIG_DFU_RAM=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQPL=y CONFIG_DM_GPIO=y -CONFIG_SYS_I2C_ZYNQ=y -CONFIG_ZYNQ_I2C0=y -CONFIG_ZYNQ_I2C1=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index d820fff501..f742838d7c 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -33,9 +33,8 @@ CONFIG_DFU_RAM=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQPL=y CONFIG_DM_GPIO=y -CONFIG_SYS_I2C_ZYNQ=y -CONFIG_ZYNQ_I2C0=y -CONFIG_ZYNQ_I2C1=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y -- cgit